AT17LV002-10SI [ATMEL]
FPGA Configuration EEPROM Memory; FPGA配置EEPROM存储器
| 型号： | AT17LV002-10SI |
| 厂家： | 
ATMEL |
| 描述： | FPGA Configuration EEPROM Memory |
| 文件： | 总24页 (文件大小：218K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• EE Programmable 65,536 x 1-, 131,072 x 1-, 262,144 x 1-, 524,288 x 1-, 1,048,576 x 1-,
2,097,152 x 1-, and 4,194,304 x 1-bit Serial Memories Designed to Store Configuration
Programs for Field Programmable Gate Arrays (FPGAs)
• Supports both 3.3V and 5.0V Operating Voltage Applications
• In-System Programmable (ISP) via Two-Wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera FLEX®, APEX™
Devices, Lucent ORCA®, Xilinx XC3000™, XC4000™, XC5200™, Spartan®, Virtex® FPGAs
• Cascadable Read-back to Support Additional Configurations or Higher-density Arrays
• Very Low-power CMOS EEPROM Process
FPGA
• Programmable Reset Polarity
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP (Pin-compatible with 8-lead SOIC/VOIC
Packages), 8-lead PDIP, 8-lead SOIC, 20-lead PLCC, 20-lead SOIC, 44-lead PLCC and
44-lead TQFP Packages
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Low-power Standby Mode
• High-reliability
Configuration
EEPROM
Memory
– Endurance: 100,000 Write Cycles
– Data Retention: 90 Years for Industrial Parts (at 85°C) and 190 Years for
Commercial Parts (at 70°C)
AT17LV65
Description
AT17LV128
AT17LV256
AT17LV512
AT17LV010
AT17LV002
AT17LV040
The AT17LV series FPGA Configuration EEPROMs (Configurators) provide an easy-
to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The
AT17LV series device is packaged in the 8-lead LAP, 8-lead PDIP, 8-lead SOIC, 20-
lead PLCC, 20-lead SOIC, 44-lead PLCC and 44-lead TQFP, see Table 1. The
AT17LV series Configurators uses a simple serial-access procedure to configure one
or more FPGA devices. The user can select the polarity of the reset function by pro-
gramming four EEPROM bytes. These devices also support a write-protection
mechanism within its programming mode.
The AT17LV series configurators can be programmed with industry-standard program-
mers, Atmel’s ATDH2200E Programming Kit or Atmel’s ATDH2225 ISP Cable.
Table 1. AT17LV Series Packages
3.3V and 5V
System Support
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
Package
AT17LV002
AT17LV040
(3)
8-lead LAP
Yes
Yes
Yes
Yes
Yes(2)
–
Yes
Yes
Yes
–
8-lead PDIP
8-lead SOIC
20-lead PLCC
20-lead SOIC
44-lead PLCC
44-lead TQFP
–
(1)
(1)
(3)
Use 8-lead LAP
Use 8-lead LAP
Yes
Yes(2)
–
Yes
Yes(2)
Yes
–
–
Yes
Yes
–
–
Yes
Notes: 1. The 8-lead LAP package has the same footprint as the 8-lead SOIC. Since an 8-
lead SOIC package is not available for the AT17LV512/010/002 devices, it is possi-
ble to use an 8-lead LAP package instead.
2. The pinout for the AT17LV65/128/256 devices is not pin-for-pin compatible with the
AT17LV512/010/002 devices.
Rev. 2321E–CNFG–06/03
3. Refer to the AT17Fxxx datasheet, available on the Atmel web site.
Pin Configuration
8-lead LAP
DATA 1
8 VCC
CLK 2
(WP(1)) RESET/OE 3
CE 4
7 SER_EN
6 CEO (A2)
5 GND
8-lead SOIC
DATA
1
8
VCC
CLK
(WP(1)) RESET/OE
CE
2
7
SER_EN
CEO (A2)
GND
3
4
6
5
8-lead PDIP
DATA
1
2
3
4
8
VCC
CLK
(WP(1)) RESET/OE
CE
7
6
5
SER_EN
CEO (A2)
GND
20-lead PLCC
CLK
(WP1(2)) NC
(WP(1)) RESET/OE
(WP2(2)) NC
CE
4
18 NC
5
17 SER_EN
6
7
8
16 NC
15 NC (READY(2))
14 CEO (A2)
Notes: 1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
2
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
20-lead SOIC(1)
NC
DATA
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
NC
NC
CLK
SER_EN
NC
NC
RESET/OE
NC
NC
CEO (A2)
NC
CE
NC
NC
GND
NC
Note:
1. This pinout only applies to AT17LV65/128/256 devices.
20-lead SOIC(1)
DATA
NC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
VCC
NC
CLK
NC
SER_EN
NC
NC
NC
NC
NC
NC
NC
RESET/OE
CEO
NC
NC
CE
GND
Note:
1. This pinout only applies to AT17LV512/010/002 devices.
3
2321E–CNFG–06/03
44 PLCC
(WP1(1)) NC
NC
7
39
38
37
36
35
34
33
32
31
30
29
NC
NC
8
NC
NC
9
NC
NC
10
11
12
13
14
15
16
17
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
READY
NC
44 TQFP
NC
NC
NC
NC
NC
NC
1
33
32
31
30
29
28
27
26
25
24
23
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
3
4
5
6
(WP1(1)) NC
7
NC
NC
NC
NC
8
9
10
11
READY
Note:
1. This pin is only available on AT17LV002 devices.
4
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
Block Diagram
SER_EN
WP1(2)
WP2(2)
POWER ON
RESET
READY(2)
(1)
Notes: 1. This pin is only available on AT17LV65/128/256 devices.
2. This pin is only available on AT17LV512/010/002 devices.
Device Description
The control signals for the configuration EEPROM (CE, RESET/OE and CCLK) inter-
face directly with the FPGA device control signals. All FPGA devices can control the
entire configuration process and retrieve data from the configuration EEPROM without
requiring an external intelligent controller.
The configuration EEPROM RESET/OE and CE pins control the tri-state buffer on the
DATA output pin and enable the address counter. When RESET/OE is driven High, the
configuration EEPROM resets its address counter and tri-states its DATA pin. The CE
pin also controls the output of the AT17LV series configurator. If CE is held High after
the RESET/OE reset pulse, the counter is disabled and the DATA output pin is tri-
stated. When OE is subsequently driven Low, the counter and the DATA output pin are
enabled. When RESET/OE is driven High again, the address counter is reset and the
DATA output pin is tri-stated, regardless of the state of CE.
When the configurator has driven out all of its data and CEO is driven Low, the device
tri-states the DATA pin to avoid contention with other configurators. Upon power-up, the
address counter is automatically reset.
This is the default setting for the device. Since almost all FPGAs use RESET Low and
OE High, this document will describe RESET/OE.
5
2321E–CNFG–06/03
Pin Description
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002
AT17LV040
8
8
DIP/
LAP/
SOIC
8
DIP/
LAP
DIP/
LAP/
SOIC
20
PLCC
20
SOIC
20
PLCC
20
SOIC
20
PLCC
20
SOIC
44
PLCC
44
TQFP
44
PLCC
44
TQFP
Name
I/O
I/
O
DATA
1
2
2
1
2
1
1
2
1
2
40
2
40
CLK
WP1
I
I
I
I
I
2
–
3
4
–
6
4
–
6
2
–
3
–
4
5
4
5
3
–
2
–
3
–
4
5
4
5
3
–
5
–
43
–
5
–
43
–
RESET/OE
WP2
6
8
6
8
19
–
13
–
19
–
13
–
7
–
7
–
CE
4
5
8
8
8
10
11
13
–
8
10
11
13
–
21
24
15
18
21
24
15
18
GND
10
10
10
10
CEO
O
I
6
14
14
6
14
6
14
27
21
27
21
A2
READY
SER_EN
VCC
O
I
–
7
8
–
–
–
7
8
15
17
20
–
–
7
8
15
17
20
–
29
41
44
23
35
38
29
41
44
23
35
38
17
20
17
20
18
20
18
20
DATA
Three-state DATA output for configuration. Open-collector bi-directional pin for
programming.
CLK
WP1
Clock input. Used to increment the internal address and bit counter for reading and
programming.
WRITE PROTECT (1). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations. This pin is only available on AT17LV512/010/002 devices.
RESET/OE
Output Enable (active High) and RESET (active Low) when SER_EN is High. A Low
level on RESET/OE resets both the address and bit counters. A High level (with CE
Low) enables the data output driver. The logic polarity of this input is programmable as
either RESET/OE or RESET/OE. For most applications, RESET should be programmed
active Low. This document describes the pin as RESET/OE.
WP
Write protect (WP) input (when CE is Low) during programming only (SER_EN Low).
When WP is Low, the entire memory can be written. When WP is enabled (High), the
lowest block of the memory cannot be written. This pin is only available on
AT17LV65/128/256 devices.
WP2
WRITE PROTECT (2). Used to protect portions of memory during programming. Dis-
abled by default due to internal pull-down resistor. This input pin is not used during
FPGA loading operations. This pin is only available on AT17LV512/010 devices.
6
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
CE
Chip Enable input (active Low). A Low level (with OE High) allows CLK to increment the
address counter and enables the data output driver. A High level on CE disables both
the address and bit counters and forces the device into a low-power standby mode.
Note that this pin will not enable/disable the device in the Two-Wire Serial Programming
mode (SER_EN Low).
GND
CEO
Ground pin. A 0.2 µF decoupling capacitor between VCC and GND is recommended.
Chip Enable Output (active Low). This output goes Low when the address counter has
reached its maximum value. In a daisy chain of AT17LV series devices, the CEO pin of
one device must be connected to the CE input of the next device in the chain. It will stay
Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
A2
Device selection input, A2. This is used to enable (or select) the device during program-
ming (i.e., when SER_EN is Low). A2 has an internal pull-down resistor.
READY
Open collector reset state indicator. Driven Low during power-up reset, released when
power-up is complete. It is recommended to use a 4.7 kΩ pull-up resistor when this pin
is used.
SER_EN
VCC
Serial enable must be held High during FPGA loading operations. Bringing SER_EN
Low enables the Two-Wire Serial Programming Mode. For non-ISP applications,
SER_EN should be tied to VCC
.
3.3V ( 10%) and 5.0V ( 5% Commercial, 10% Industrial) power supply pin.
7
2321E–CNFG–06/03
FPGA Master Serial
Mode Summary
The I/O and logic functions of any SRAM-based FPGA are established by a configura-
tion program. The program is loaded either automatically upon power-up, or on
command, depending on the state of the FPGA mode pins. In Master mode, the FPGA
automatically loads the configuration program from an external memory. The AT17LV
Serial Configuration EEPROM has been designed for compatibility with the Master
Serial mode.
This document discusses the Atmel AT40K, AT40KAL and AT94KAL applications as
well as Xilinx applications.
Control of
Configuration
Most connections between the FPGA device and the AT17LV Serial EEPROM are sim-
ple and self-explanatory.
•
•
The DATA output of the AT17LV series configurator drives DIN of the FPGA devices.
The master FPGA CCLK output drives the CLK input of the AT17LV series
configurator.
•
The CEO output of any AT17LV series configurator drives the CE input of the next
configurator in a cascaded chain of EEPROMs.
•
•
SER_EN must be connected to VCC (except during ISP).
The READY(1) pin is available as an open-collector indicator of the device’s reset
status; it is driven Low while the device is in its power-on reset cycle and released
(tri-stated) when the cycle is complete.
Note:
1. This pin is not available for the AT17LV65/128/256 devices.
Cascading Serial
Configuration
EEPROMs
For multiple FPGAs configured as a daisy-chain, or for FPGAs requiring larger configu-
ration memories, cascaded configurators provide additional memory.
After the last bit from the first configurator is read, the clock signal to the configurator
asserts its CEO output Low and disables its DATA line driver. The second configurator
recognizes the Low level on its CE input and enables its DATA output.
After configuration is complete, the address counters of all cascaded configurators are
reset if the RESET/OE on each configurator is driven to its active (Low) level.
If the address counters are not to be reset upon completion, then the RESET/OE input
can be tied to its inactive (High) level.
AT17LV Series Reset The AT17LV series configurator allows the user to program the reset polarity as either
RESET/OE or RESET/OE. This feature is supported by industry-standard programmer
algorithms.
Polarity
Programming Mode
Standby Mode
The programming mode is entered by bringing SER_EN Low. In this mode the chip can
be programmed by the Two-Wire serial bus. The programming is done at VCC supply
only. Programming super voltages are generated inside the chip.
The AT17LV series configurators enter a low-power standby mode whenever CE is
asserted High. In this mode, the AT17LV65/128/256 configurator consumes less than
50 µA of current at 3.3V (100 µA for the AT17LV512/010 and 200 µA for the
AT17LV002/040). The output remains in a high-impedance state regardless of the state
of the OE input.
8
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those listed under oper-
ating conditions is not implied. Exposure to Abso-
lute Maximum Rating conditions for extended
periods of time may affect device reliability.
Operating Temperature.................................... -40°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin
with Respect to Ground..............................-0.1V to VCC +0.5V
Supply Voltage (VCC) .........................................-0.5V to +7.0V
Maximum Soldering Temp. (10 sec. @ 1/16 in.).............260°C
ESD (RZAP = 1.5K, CZAP = 100 pF)................................. 2000V
Operating Conditions
3.3V
5V
Symbol
Description
Min
Max
Min
Max
Units
Supply voltage relative to GND
-0°C to +70°C
Commercial
3.0
3.6
4.75
5.25
V
VCC
Supply voltage relative to GND
-40°C to +85°C
Industrial
3.0
3.6
4.5
5.5
V
9
2321E–CNFG–06/03
DC Characteristics
VCC = 3.3V 10%
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002/
AT17LV040
Symbol
VIH
Description
Min
Max
Min
Max
Min
Max
Units
V
High-level Input Voltage
2.0
0
VCC
0.8
2.0
0
VCC
0.8
2.0
0
VCC
0.8
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
Supply Current, Active Mode
2.4
2.4
2.4
V
Commercial
Industrial
0.4
0.4
0.4
V
2.4
-10
2.4
-10
2.4
-10
V
0.4
5
0.4
5
0.4
5
V
mA
µA
µA
µA
Input or Output Leakage Current (VIN = VCC or GND)
Commercial
Industrial
10
50
100
10
10
100
100
150
150
ICCS
Supply Current, Standby Mode
DC Characteristics
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
AT17LV002/
AT17LV040
Symbol
VIH
Description
Min
Max
Min
Max
Min
Max
Units
V
High-level Input Voltage
2.0
0
VCC
0.8
2.0
0
VCC
0.8
2.0
0
VCC
0.8
VIL
Low-level Input Voltage
V
VOH
VOL
VOH
VOL
ICCA
IL
High-level Output Voltage (IOH = -2.5 mA)
Low-level Output Voltage (IOL = +3 mA)
High-level Output Voltage (IOH = -2 mA)
Low-level Output Voltage (IOL = +3 mA)
Supply Current, Active Mode
3.7
3.86
3.86
V
Commercial
Industrial
0.32
0.32
0.32
V
3.6
-10
3.76
-10
3.76
-10
V
0.37
10
0.37
10
0.37
10
V
mA
µA
µA
µA
Input or Output Leakage Current (VIN = VCC or GND)
Commercial
Industrial
10
10
10
75
200
200
350
350
ICCS
Supply Current, Standby Mode
150
10
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
AC Characteristics
CE
TSCE
THCE
TSCE
RESET/OE
CLK
THOE
TLC
THC
TOH
TOE
TCAC
TDF
TCE
DATA
TOH
AC Characteristics when Cascading
RESET/OE
CE
CLK
TCDF
FIRST BIT
LAST BIT
DATA
TOCK
TOCE
TOOE
CEO
TOCE
11
2321E–CNFG–06/03
AC Characteristics
VCC = 3.3V 10%
AT17LV65/128/256
Commercial Industrial
AT17LV512/010/002/040
Commercial Industrial
Symbol
Description
Min
Max
50
Min
Max
Min
Max
50
Min
Max
Units
ns
(1)
TOE
OE to Data Delay
55
60
80
55
60
60
(1)
TCE
CE to Data Delay
60
55
ns
(1)
TCAC
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
75
55
ns
TOH
0
0
0
0
ns
(2)
TDF
55
55
50
50
ns
TLC
THC
25
25
25
25
25
25
25
25
ns
CLK High Time
ns
CE Setup Time to CLK
(to guarantee proper counting)
TSCE
35
60
30
35
ns
ns
CE Hold Time from CLK
(to guarantee proper counting)
THCE
0
0
0
0
THOE
FMAX
OE High Time (guarantees counter is reset)
Maximum Clock Frequency
25
25
25
25
ns
10
10
15
10
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
AC Characteristics when Cascading
VCC = 3.3V 10%
AT17LV65/128/256
Commercial Industrial
Min Max
AT17LV512/010/002/040
Commercial Industrial
Min Max
Symbol
Description
Min
Max
60
Min
Max
50
Units
ns
(2)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
CE to CEO Delay
60
60
60
45
50
55
40
35
10
(1)
TOCK
55
50
ns
(1)
TOCE
55
35
ns
(1)
TOOE
RESET/OE to CEO Delay
40
35
ns
FMAX
Maximum Clock Frequency
8
8
12.5
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
12
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
AC Characteristics
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65/128/256
Commercial Industrial
AT17LV512/010/002/040
Commercial Industrial
Symbol
Description
Min
Max
30
Min
Max
Min
Max
30
Min
Max
Units
ns
(1)
TOE
OE to Data Delay
35
45
55
35
45
50
(1)
TCE
CE to Data Delay
45
45
ns
(1)
TCAC
CLK to Data Delay
Data Hold from CE, OE, or CLK
CE or OE to Data Float Delay
CLK Low Time
50
50
ns
TOH
0
0
0
0
ns
(2)
TDF
50
50
50
50
ns
TLC
THC
20
20
20
20
20
20
20
20
ns
CLK High Time
ns
CE Setup Time to CLK (to guarantee proper
counting)
TSCE
35
40
20
25
ns
ns
CE Hold Time from CLK (to guarantee proper
counting)
THCE
0
0
0
0
THOE
FMAX
OE High Time (guarantees counter is reset)
Maximum Clock Frequency
20
20
20
20
ns
12.5
12.5
15
15
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
AC Characteristics when Cascading
VCC = 5V 5% Commercial; VCC = 5V 10% Industrial
AT17LV65/128/256
Commercial Industrial
Min Max
AT17LV512/010/002/040
Commercial Industrial
Min Max
Symbol
Description
Min
Max
50
Min
Max
50
Units
ns
(2)
TCDF
CLK to Data Float Delay
CLK to CEO Delay
50
40
35
35
10
50
40
(1)
TOCK
35
35
ns
(1)
TOCE
CE to CEO Delay
35
35
35
ns
(1)
TOOE
RESET/OE to CEO Delay
Maximum Clock Frequency
30
30
30
ns
FMAX
10
12.5
12.5
MHz
Notes: 1. AC test lead = 50 pF.
2. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady-state active levels.
13
2321E–CNFG–06/03
Thermal Resistance Coefficients(1)
AT17LV65/
AT17LV128/
AT17LV256
AT17LV512/
AT17LV010
Package Type
AT17LV002
AT17LV040
θ
JC [°C/W]
JA [°C/W](2)
JC [°C/W]
JA [°C/W](2)
JC [°C/W]
JA [°C/W](2)
JC [°C/W]
JA [°C/W](2)
JC [°C/W]
JA [°C/W](2)
JC [°C/W]
JA [°C/W](2)
JC [°C/W]
JA [°C/W](2)
45
115.71
37
45
135.71
37
45
–
–
8CN4
8P3
8S1
20J
Leadless Array Package (LAP)
θ
159.60
θ
–
–
–
Plastic Dual Inline Package (PDIP)
θ
107
45
107
–
–
θ
–
–
Plastic Gull Wing Small Outline
(SOIC)
θ
150
35
–
–
–
θ
35
35
90
–
Plastic Leaded Chip Carrier
(PLCC)
θ
90
90
–
θ
–
Plastic Gull Wing Small Outline
(SOIC)
20S2
44A
44J
θ
–
θ
–
–
–
–
–
–
–
–
17
62
15
50
17
62
15
50
Thin Plastic Quad Flat Package
(TQFP)
θ
θ
Plastic Leaded Chip Carrier
(PLCC)
θ
Notes: 1. For more information refer to the “Thermal Characteristics of Atmel’s Packages”, available on the Atmel web site.
2. Airflow = 0 ft/min.
14
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
Figure 1. Ordering Code
AT17LV65A-10PC
Voltage
Size (Bits)
Special Pinouts
= Altera
Package
Temperature
C
P
N
J
3.0V to 5.5V
65
= 65K
A
= 8CN4 C = Commercial
128
256
512
010
002
040
= 128K
= 256K
= 512K
= 1M
Blank = Xilinx/Atmel/
Other
= 8P3
= 8S1
= 20J
I = Industrial
S
= 20S2
TQ = 44A
BJ = 44J
= 2M
= 4M
Package Type
8CN4
8P3
8S1
20J
8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package (LAP) – Pin-compatible with 8-lead SOIC/VOID Packages
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
20-lead, Plastic J-leaded Chip Carrier (PLCC)
20S2
44A
44J
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC)
44-lead, Thin (1.0 mm) Plastic Quad Flat Package Carrier (TQFP)
44-lead, Plastic J-leaded Chip Carrier (PLCC)
15
2321E–CNFG–06/03
Ordering Information
Memory Size
Ordering Code
Package
Operation Range
64-Kbit(1)
128-Kbit(1)
256-Kbit(1)
AT17LV65-10CC
AT17LV65-10PC
AT17LV65-10NC
AT17LV65-10JC
AT17LV65-10SC
8CN4
8P3
8S1
20J
20S2
Commercial
(0°C to 70°C)
AT17LV65-10CI
AT17LV65-10PI
AT17LV65-10NI
AT17LV65-10JI
AT17LV65-10SI
8CN4
8P3
8S1
20J
20S2
Industrial
(-40°C to 85°C)
AT17LV128-10CC
AT17LV128-10PC
AT17LV128-10NC
AT17LV128-10JC
AT17LV128-10SC
8CN4
8P3
8S1
20J
20S2
Commercial
(0°C to 70°C)
AT17LV128-10CI
AT17LV128-10PI
AT17LV128-10NI
AT17LV128-10JI
AT17LV128-10SI
8CN4
8P3
8S1
20J
20S2
Industrial
(-40°C to 85°C)
AT17LV256-10CC
AT17LV256-10PC
AT17LV256-10NC
AT17LV256-10JC
AT17LV256-10SC
8CN4
8P3
8S1
20J
20S2
Commercial
(0°C to 70°C)
AT17LV256-10CI
AT17LV256-10PI
AT17LV256-10NI
AT17LV256-10JI
AT17LV256-10SI
8CN4
8P3
8S1
20J
20S2
Industrial
(-40°C to 85°C)
512-Kbit(1)
1-Mbit(1)
2-Mbit(1)
AT17LV512-10CC
AT17LV512-10PC
AT17LV512-10JC
AT17LV512-10SC
8CN4
8P3
20J
Commercial
(0°C to 70°C)
20S2
AT17LV512-10CI
AT17LV512-10PI
AT17LV512-10JI
AT17LV512-10SI
8CN4
8P3
20J
Industrial
(-40°C to 85°C)
20S2
AT17LV010-10CC
AT17LV010-10PC
AT17LV010-10JC
AT17LV010-10SC
8CN4
8P3
20J
Commercial
(0°C to 70°C)
20S2
AT17LV010-10CI
AT17LV010-10PI
AT17LV010-10JI
AT17LV010-10SI
8CN4
8P3
20J
Industrial
(-40°C to 85°C)
20S2
AT17LV002-10CC
AT17LV002-10JC
AT17LV002-10SC
AT17LV002-10TQC
AT17LV002-10BJC
8CN4
20J
20S2
44A
Commercial
(0°C to 70°C)
44J
AT17LV002-10CI
AT17LV002-10JI
AT17LV002-10SI
AT17LV002-10TQI
AT17LV002-10BJI
8CN4
20J
20S2
44A
Industrial
(-40°C to 85°C)
44J
4-Mbit(1)
AT17LV040-10TQC
AT17LV040-10BJC
44A
44J
Commercial
(0°C to 70°C)
AT17LV040-10TQI
AT17LV040-10BJI
44A
44J
Industrial
(-40°C to 85°C)
Note:
1. For operating 5V operating voltage, please refer to the corresponding AC and DC Characteristics.
16
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
Packaging Information
8CN4 – LAP
Marked Pin1 Indentifier
E
A
D
A1
Top View
Side View
Pin1 Corner
L1
0.10 mm
TYP
8
7
1
e
COMMON DIMENSIONS
(Unit of Measure = mm)
2
3
MIN
0.94
0.30
0.45
5.89
4.89
MAX
1.14
0.38
0.55
6.09
6.09
NOM
1.04
NOTE
SYMBOL
A
6
5
A1
b
0.34
b
0.50
1
4
D
5.99
E
5.99
e1
L
e
1.27 BSC
1.10 REF
1.00
e1
L
Bottom View
0.95
1.25
1.05
1.35
1
1
L1
1.30
Note: 1. Metal Pad Dimensions.
11/14/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
8CN4, 8-lead (6 x 6 x 1.04 mm Body), Lead Pitch 1.27 mm,
Leadless Array Package (LAP)
A
8CN4
R
17
2321E–CNFG–06/03
8P3 – PDIP
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
18
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
8S1 – SOIC
1
3
2
H
N
Top View
e
B
A
D
COMMON DIMENSIONS
(Unit of Measure = mm)
Side View
MIN
–
MAX
1.75
0.51
0.25
5.00
4.00
NOM
NOTE
SYMBOL
A
B
C
D
E
e
–
A2
L
–
–
–
–
–
–
–
–
1.27 BSC
E
H
L
–
–
–
–
6.20
1.27
End View
Note:
This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.
10/10/01
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing
8S1
A
R
Small Outline (JEDEC SOIC)
19
2321E–CNFG–06/03
20J – PLCC
PIN NO. 1
1.14(0.045) X 45˚
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
IDENTIFIER
e
E1
E
D2/E2
B1
B
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
2.286
0.508
9.779
8.890
9.779
8.890
7.366
0.660
0.330
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
A1
A2
D
–
–
–
–
10.033
D1
E
–
9.042 Note 2
10.033
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AA.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
D2/E2
B
–
9.042 Note 2
8.382
–
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC)
20J
B
R
20
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
20S2 – SOIC
C
1
H
E
N
A1
Top View
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
MIN
MAX
NOM
NOTE
SYMBOL
e
b
A
A1
b
0.0926
0.0040
0.0130
0.0091
0.4961
0.2914
0.3940
0.0160
0.1043
0.0118
0.0200
0.0125
0.5118
0.2992
0.4190
0.050
A
4
C
D
E
H
L
D
1
2
Side View
3
e
0.050 BSC
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.
2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed
0.15 mm (0.006") per side.
3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm
(0.010") per side.
4. "L" is the length of the terminal for soldering to a substrate.
5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm
1/9/02
(0.024") per side.
TITLE
DRAWING NO.
REV.
20S2, 20-lead, 0.300" Wide Body, Plastic Gull
Wing Small Outline Package (SOIC)
2325 Orchard Parkway
San Jose, CA 95131
A
20S2
R
21
2321E–CNFG–06/03
44A – TQFP
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0˚~7˚
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
E1
B
10.10 Note 2
0.45
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
B
R
22
AT17LV65/128/256/512/010/002/040
2321E–CNFG–06/03
AT17LV65/128/256/512/010/002/040
44J – PLCC
1.14(0.045) X 45˚
0.318(0.0125)
0.191(0.0075)
PIN NO. 1
1.14(0.045) X 45˚
IDENTIFIER
D2/E2
E1
E
B1
B
e
A2
A1
D1
D
A
0.51(0.020)MAX
45˚ MAX (3X)
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
4.191
MAX
4.572
3.048
–
NOM
NOTE
SYMBOL
A
–
A1
A2
D
2.286
–
0.508
–
17.399
16.510
17.399
16.510
–
17.653
D1
E
–
16.662 Note 2
17.653
–
Notes:
1. This package conforms to JEDEC reference MS-018, Variation AC.
2. Dimensions D1 and E1 do not include mold protrusion.
Allowable protrusion is .010"(0.254 mm) per side. Dimension D1
and E1 include mold mismatch and are measured at the extreme
material condition at the upper or lower parting line.
E1
–
16.662 Note 2
16.002
D2/E2 14.986
–
B
0.660
0.330
–
–
0.813
3. Lead coplanarity is 0.004" (0.102 mm) maximum.
B1
e
0.533
1.270 TYP
10/04/01
DRAWING NO. REV.
44J
TITLE
2325 Orchard Parkway
San Jose, CA 95131
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
B
R
23
2321E–CNFG–06/03
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Regional Headquarters
Microcontrollers
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Tel: 1(408) 441-0311
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Tel: (44) 1355-803-000
Fax: (44) 1355-242-743
Atmel Configurator Hotline
e-mail
literature@atmel.com
(408) 436-4119
Atmel Configurator e-mail
Web Site
http://www.atmel.com
configurator@atmel.com
FAQ
Available on web site
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
© Atmel Corporation 2003. All rights reserved. Atmel® and combinations thereof are the registered trade-
mark of Atmel.
FLEX™ is the trademark of Altera Corporation; ORCA™ is the trademark of Lattice Semiconductors;
SPARTAN® and Virtex® are the registered trademarks of Xilinx, Inc.; XC3000™, XC4000™ and XC5200™ are
the trademarks of Xilinx, Inc.; APEX™ is the trademark of MIPS Technologies; Other terms and product names
Printed on recycled paper.
may be the trademarks of others.
2321E–CNFG–06/03
xM
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