AX88796L [ASIX]
3-in-1 Local Bus Fast Ethernet Controller; 3合1本地总线快速以太网控制器
| 型号： | AX88796L |
| 厂家： | 
ASIX ELECTRONICS CORPORATION |
| 描述： | 3-in-1 Local Bus Fast Ethernet Controller |
| 文件： | 总71页 (文件大小：918K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
10/100BASE 3-in-1 Local CPU Bus Fast Ethernet Controller
with Embedded SRAM
Document No.: AX796-17 / V1.7 / Jan. 25 ’02
Features
·
Highly integrated with embedded 10/100Mbps
MAC, PHY and Transceiver
Embedded 8K * 16 bit SRAM
·
·
External and internal loop-back capability
Support Standard Print Port for printer server
application
Support upto 3/1 General Purpose In/Out pins
128-pin LQFP low profile package
Low Power Consumption, typical under 100mA
0.25 Micron low power CMOS process. 25MHz
Operation, Pure 3.3V operation with 5V I/O
tolerance.
*IEEE is a registered trademark of the Institute of
Electrical and Electronic Engineers, Inc.
*All other trademarks and registered trademark are
the property of their respective holders.
·
·
Compliant
with
IEEE
802.3/802.3u
·
·
·
·
100BASE-TX/FX specification
·
·
NE2000 register level compatible instruction
Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
Support both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series and MC68K
series CPU
Support both 10Mbps and 100Mbps data rate
Support both full-duplex or half-duplex operation
Provides an extra MII port for supporting other
media. For example, Home LAN application
Support EEPROM interface to store MAC address
·
·
·
·
·
Product description
The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller
with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local
CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both
10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796 also provides
an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII
interface, Home LAN PHY type media can be supported.
As well as, the chip also provides optional Standard Print Port ( parallel port interface ), can be used for printer server
device or treat as simple general I/O port. The chip also support upto 3/1 additional General Purpose In/Out pins
System Block Diagram
AD BUS
Optional Print Port
Or General I/O Ports
Addr L
Optional
Home LAN
PHY
RJ11
AX88796
With
Addr H
10/100 Mbps
PHY/TxRx
Ctl BUS
RJ45
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
First Released Date : July/31/2000
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558
http://www.asix.com.tw
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 5
1.1 GENERAL DESCRIPTION:..................................................................................................................................... 5
1.2 AX88796 BLOCK DIAGRAM:.............................................................................................................................. 5
1.3A AX88796 PIN CONNECTION DIAGRAM.............................................................................................................. 6
1.3B AX88796 PIN CONNECTION DIAGRAM WITH SPP PORT OPTION ........................................................................ 7
1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode................................................................................ 8
1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode................................................................................... 9
1.3.3 AX88796 Pin Connection Diagram for MC68K Mode.............................................................................. 10
1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode ............................................................................. 11
2.0 SIGNAL DESCRIPTION................................................................................................................................. 12
2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP................................................................................................... 12
2.2 10/100MBPS TWISTED-PAIR INTERFACE PINS GROUP ......................................................................................... 13
2.3 BUILT-IN PHY LED INDICATOR PINS GROUP ..................................................................................................... 13
2.4 EEPROM SIGNALS GROUP .............................................................................................................................. 14
2.5 MII INTERFACE SIGNALS GROUP(OPTIONAL) ..................................................................................................... 14
2.6 STANDARD PRINTER PORT (SPP) INTERFACE PINS GROUP (OPTIONAL)................................................................ 15
2.7 GENERAL PURPOSE I/O PINS GROUP........................................................................................... 15
2.8 MISCELLANEOUS PINS GROUP............................................................................................................................ 16
2.9 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE..................... 17
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 18
3.1 EEPROM MEMORY MAPPING.......................................................................................................................... 18
3.2 I/O MAPPING................................................................................................................................................... 18
3.3 SRAM MEMORY MAPPING .............................................................................................................................. 18
4.0 BASIC OPERATION ...................................................................................................................................... 19
4.1 RECEIVER FILTERING ....................................................................................................................................... 19
4.1.1 Unicast Address Match Filter................................................................................................................... 19
4.1.2 Multicast Address Match Filter................................................................................................................ 19
4.1.3 Broadcast Address Match Filter............................................................................................................... 20
4.1.4 Aggregate Address Filter with Receive Configuration Setup..................................................................... 20
4.2 BUFFER MANAGEMENT OPERATION .................................................................................................................. 22
4.2.1 Packet Reception ..................................................................................................................................... 22
4.2.2 Packet Transmision.................................................................................................................................. 25
4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory).................................................................... 27
4.2.4 Removing Packets from the Ring (Host read data from memory).............................................................. 28
4.2.5 Other Useful Operations .......................................................................................................................... 31
5.0 REGISTERS OPERATION............................................................................................................................. 32
5.1 MAC CORE REGISTERS.................................................................................................................................... 32
5.1.1 Command Register (CR) Offset 00H (Read/Write)................................................................................... 34
5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write).......................................................................... 34
5.1.3 Interrupt mask register (IMR) Offset 0FH (Write).................................................................................... 35
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write) .......................................................................... 35
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write) .................................................................... 35
5.1.6 Transmit Status Register (TSR) Offset 04H (Read)................................................................................... 36
5.1.7 Receive Configuration (RCR) Offset 0CH (Write).................................................................................... 36
5.1.8 Receive Status Register (RSR) Offset 0CH (Read) ................................................................................... 36
5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write)....................................................................................... 37
5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write) ................................................................. 37
5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write) ................................................................. 37
5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H (Read/Write)................................................. 37
2
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
5.1.13 Test Register (TR) Offset 15H (Write).................................................................................................... 37
5.1.14 Test Register (TR) Offset 15H (Read) .................................................................................................... 38
5.1.15 General Purpose Input Register (GPI) Offset 17H (Read)...................................................................... 38
5.1.16 GPO and Control (GPOC) Offset 17H (Write)....................................................................................... 38
5.1.17 SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write) ............................................................... 39
5.1.18 SPP Status Port Register (SPP_SPR) Offset 19H (Read)........................................................................ 39
5.1.19 SPP Command Port Register (SPP_CPR) Offset 1AH (Read/Write)....................................................... 39
5.2 THE EMBEDDED PHY REGISTERS ..................................................................................................................... 40
5.2.1 MR0 -- Control Register Bit Descriptions................................................................................................. 41
5.2.2 MR1 -- Status Register Bit Descriptions................................................................................................... 42
5.2.3 MR2, MR3 -- Identification Registers (1 and 2) Bit Descriptions.............................................................. 43
5.2.4 MR4 – Autonegotiation Advertisement Registers Bit Descriptions............................................................ 43
5.2.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................. 43
5.2.6 MR5 –Autonegotiation Link Partner(LP)Ability Register (Next Page)Bit Descriptions ............................. 44
5.2.7 MR6 – Autonegotiation Expansion Register Bit Descriptions................................................................... 44
5.2.8 MR7 –Next Page Transmit Register Bit Descriptions ............................................................................... 45
5.2.9 MR16 – PCS Control Register Bit Descriptions........................................................................................ 45
5.2.10 MR17 –Autonegotiation Register A Bit Descriptions.............................................................................. 46
5.2.11 MR18 –Autonegotiation Register B Bit Descriptions.............................................................................. 46
5.2.12 MR20 –User Defined Register Bit Descriptions...................................................................................... 46
5.2.13 MR21 –RXER Counter Register Bit Descriptions ................................................................................... 47
5.2.14 MR28 –Device-Specific Register 1 (Status Register) Bit Descriptions..................................................... 47
5.2.15 MR29 –Device-Specific Register 2 (100Mbps Control) Bit Descriptions................................................. 48
5.2.16 MR30 –Device-Specific Register 3 (10Mbps Control) Bit Descriptions................................................... 49
5.2.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions ........................................................ 50
6.0 CPU I/O READ AND WRITE FUNCTIONS ................................................................................................. 51
6.1 ISA BUS TYPE ACCESS FUNCTIONS. ................................................................................................................... 51
6.2 80186 CPU BUS TYPE ACCESS FUNCTIONS......................................................................................................... 51
6.3 MC68K CPU BUS TYPE ACCESS FUNCTIONS...................................................................................................... 52
6.4 MCS-51 CPU BUS TYPE ACCESS FUNCTIONS. .................................................................................................... 52
6.5 CPU ACCESS MII STATION MANAGEMENT FUNCTIONS. .................................................................................... 53
7.0 ELECTRICAL SPECIFICATION AND TIMINGS....................................................................................... 54
7.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 54
7.2 GENERAL OPERATION CONDITIONS................................................................................................................... 54
7.3 DC CHARACTERISTICS..................................................................................................................................... 54
7.4 A.C. TIMING CHARACTERISTICS....................................................................................................................... 55
7.4.1 XTAL / CLOCK........................................................................................................................................ 55
7.4.2 Reset Timing ............................................................................................................................................ 55
7.4.3 ISA Bus Access Timing............................................................................................................................. 57
7.4.4 80186 Type I/O Access Timing................................................................................................................. 58
7.4.5 68K Type I/O Access Timing .................................................................................................................... 59
7.4.6 8051 Bus Access Timing........................................................................................................................... 60
7.4.7 MII Timing............................................................................................................................................... 61
8.0 PACKAGE INFORMATION........................................................................................................................... 62
APPENDIX A: APPLICATION NOTE 1............................................................................................................. 63
A.1 USING CRYSTAL 25MHZ................................................................................................................ 63
A.2 USING OSCILLATOR 25MHZ......................................................................................................... 63
APPENDIX B: POWER CONSUMPTION REFERENCE DATA...................................................................... 64
ERRATA OF AX88796 .......................................................................................................................................... 65
DEMONSTRATION CIRCUIT (A) : AX88796 WITH ISA BUS + HOMEPNA 1M8 PHY .............................. 66
3
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
FIGURES
FIG - 1 AX88796 BLOCK DIAGRAM ............................................................................................................................. 5
FIG - 2 AX88796 PIN CONNECTION DIAGRAM.............................................................................................................. 6
FIG - 3 AX88796 PIN CONNECTION DIAGRAM WITH SPP PORT OPTION......................................................................... 7
FIG - 4 AX88796 PIN CONNECTION DIAGRAM FOR ISA BUS MODE ............................................................................... 8
FIG - 5 AX88796 PIN CONNECTION DIAGRAM FOR 80X86 MODE .................................................................................. 9
FIG - 6 AX88796 PIN CONNECTION DIAGRAM FOR MC68K MODE.............................................................................. 10
FIG - 7 AX88796 PIN CONNECTION DIAGRAM FOR MCS-51 MODE............................................................................. 11
FIG - 8 RECEIVE BUFFER RING.................................................................................................................................... 22
FIG - 9 RECEIVE BUFFER RING AT INITIALIZATION ...................................................................................................... 23
TABLES
TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP.................................................................................................. 12
TAB - 2 10/100MBPS TWISTED-PAIR INTERFACES PINS GROUP ..................................................................................... 13
TAB - 3 BUILT-IN PHY LED INDICATOR PINS GROUP .................................................................................................. 13
TAB - 4 EEPROM BUS INTERFACE SIGNALS GROUP..................................................................................................... 14
TAB - 5 MII INTERFACE SIGNALS GROUP..................................................................................................................... 14
TAB - 6 STANDARD PRINTER PORT INTERFACE PINS GROUP ......................................................................................... 15
TAB - 7 GENERAL PURPOSES I/O PINS GROUP.............................................................................................................. 15
TAB - 8 MISCELLANEOUS PINS GROUP......................................................................................................................... 17
TAB - 9 POWER ON CONFIGURATION SETUP TABLE ..................................................................................................... 17
TAB - 10 I/O ADDRESS MAPPING ............................................................................................................................... 18
TAB - 11 LOCAL MEMORY MAPPING .......................................................................................................................... 18
TAB - 12 PAGE 0 OF MAC CORE REGISTERS MAPPING................................................................................................ 32
TAB - 13 PAGE 1 OF MAC CORE REGISTERS MAPPING................................................................................................ 33
TAB - 14 THE EMBEDDED PHY REGISTERS................................................................................................................. 40
TAB - 15 MII MANAGEMENT FRAME FORMAT ............................................................................................................ 53
TAB - 16 MII MANAGEMENT FRAMES- FIELD DESCRIPTION......................................................................................... 53
4
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
1.0 Introduction
1.1 General Description:
The AX88796 provides industrial standard NE2000 registers level compatible instruction set. Various drivers are easy
acquired, maintenance and usage. No much additional effort to be paid. Software is easily port to various embedded
systems with no pain and tears
The AX88796 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller
with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796 supports both 8 bit and 16 bit local
CPU interfaces include MCS-51 series, 80186 series, MC68K series CPU and ISA bus. The AX88796 implements both
10Mbps and 100Mbps Ethernet function based on IEEE802.3 / IEEE802.3u LAN standard. The AX88796 also provides
an extra IEEE802.3u compliant media-independent interface (MII) to support other media applications. Using MII
interface, Home LAN PHY type media can be supported.
As well as, the chip also provides optional Standard Print Port ( parallel port interface ), can be used for printer server
device or treat as simple general I/O port. The chip also support upto 3/1 additional General Purpose In/Out pins
The main difference between AX88796 and AX88195 are : 1) Embedded packet buffer memory 2) Built-in 10/100Mbps
PHY/Transceiver 3) Replace memory I/F with PHY/Transceiver I/F. 4) Canceling SAX address decoding. 5) Fix
interrupt status can’t always clean up problem of AX88195. 6) Add upto 3/1 general Purpose In/Out pins.
AX88796 use 128-pin LQFP low profile package, 25MHz operation, and single 3.3V operation with 5V I/O tolerance.
The ultra low power consumption is an outstanding feature and enlarges the application field. It is suitable for some
power consumption sensitive product like small size embedded products, PDA (Personal Digital Assistant) and Palm
size computer …etc.
1.2 AX88796 Block Diagram:
SMDC
SMDIO
8K* 16 SRAM
STA
and Memory Arbiter
EECS
EECK
EEDI
EEDO
TPI, TPO
MII I/F
MAC
Core
&
SEEPROM
I/F
Remote
DMA
FIFOs
PHY+
Tranceiver
SPP
/ GPIO
NE2000
Registers
Print Port
or
General
I/O
Host Interface
Ctl BUS
SA[9:0]
SD[15:0]
Fig - 1 AX88796 Block Diagram
5
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
1.3a AX88796 Pin Connection Diagram
The AX88796 is housed in the 128-pin plastic light quad flat pack. Fig - 2 shows the AX88796 pin
connection diagram.
GPI[0]/LINK
VDD
NC
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
VSS
VSS
I_ACT
I_SPEED
I_LINK
CPU[1]
CPU[0]
VDD
VDDA
VSSA
VSS
VDD
VSS
EECS
EECK
EEDI
EEDO
TEST2
IDDQ
BIST
CLKO25M
VSS
GPI[1]/DPX
TX_CLK
TX_EN
TXD[0]
TXD[1]
TXD[2]
TXD[3]
GPI[2]/SPD
VDD
VSS
I_OP
IO_BASE[0]
IO_BASE[1]
IO_BASE[2]
GPO[0]
AX88796
Local CPU Bus
10/100BASE MAC
Controller
NC
NC
45
44
43
42
41
40
39
/IOCS16
NC
SD[0]
SD[1]
VDD
NC
VDD
VSS
SD[2]
/CS
Fig - 2 AX88796 Pin Connection Diagram
6
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
1.3b AX88796 Pin Connection Diagram with SPP Port Option
SLCT
NC
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
VDD
VSS
VSS
I_ACT
I_SPEED
I_LINK
CPU[1]
CPU[0]
VDD
VDDA
VSSA
VSS
VDD
VSS
EECS
EECK
EEDI
EEDO
TEST2
IDDQ
BIST
CLKO25M
VSS
PE
/ACK
BUSY
AX88796
/STRB
/ATFD
/INIT
Local CPU Bus
10/100BASE MAC
Controller
/SLIN
/ERR
VDD
VSS
I_OP
IO_BASE[0]
IO_BASE[1]
IO_BASE[2]
GPO[0]
NC
NC
45
44
43
42
41
40
39
/IOCS16
(With SPP Port)
NC
SD[0]
SD[1]
VDD
NC
VDD
VSS
SD[2]
/CS
Fig - 3 AX88796 Pin Connection Diagram with SPP Port Option
7
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
1.3.1 AX88796 Pin Connection Diagram for ISA Bus Mode
GPI[0]/LINK
103
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
VDD
VSS
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VSS
I_ACT
I_SPEED
I_LINK
CPU[1]
CPU[0]
VDD
VDDA
VSSA
VSS
VDD
VSS
EECS
EECK
EEDI
EEDO
TEST2
IDDQ
BIST
CLKO25M
VSS
GPI[1]/DPX
TX_CLK
TX_EN
TXD[0]
AX88796
TXD[1]
TXD[2]
TXD[3]
Local CPU Bus
10/100BASE-TX
MAC Controller
(for ISA Bus I/F)
GPI[2]/SPD
VDD
VSS
I_OP
IO_BASE[0]
IO_BASE[1]
IO_BASE[2]
GPO[0]
NC
NC
45
44
43
42
41
40
39
/IOCS16
NC
SD[0]
SD[1]
VDD
NC
VDD
VSS
SD[2]
/CS
Fig - 4 AX88796 Pin Connection Diagram for ISA Bus Mode
8
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
1.3.2 AX88796 Pin Connection Diagram for 80x86 Mode
GPI[0]/LINK
VDD
NC
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
VSS
VSS
I_ACT
I_SPEED
I_LINK
CPU[1]
CPU[0]
VDD
VDDA
VSSA
VSS
VDD
VSS
EECS
EECK
EEDI
EEDO
TEST2
IDDQ
BIST
CLKO25M
VSS
GPI[1]/DPX
TX_CLK
TX_EN
TXD[0]
TXD[1]
TXD[2]
TXD[3]
GPI[2]/SPD
VDD
VSS
I_OP
IO_BASE[0]
IO_BASE[1]
IO_BASE[2]
GPO[0]
AX88796
Local CPU Bus
10/100BASE-TX
MAC Controller
NC
NC
NC
45
44
43
42
41
40
39
NC
(for x86 Interface)
SD[0]
SD[1]
VDD
NC
VDD
VSS
SD[2]
/CS
Fig - 5 AX88796 Pin Connection Diagram for 80x86 Mode
9
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
1.3.3 AX88796 Pin Connection Diagram for MC68K Mode
GPI[0]/LINK
103
NC
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
VDD
VSS
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
VSS
I_ACT
I_SPEED
I_LINK
CPU[1]
CPU[0]
VDD
VDDA
VSSA
VSS
VDD
VSS
EECS
EECK
EEDI
EEDO
TEST2
IDDQ
BIST
CLKO25M
VSS
GPI[1]/DPX
TX_CLK
TX_EN
TXD[0]
AX88796
TXD[1]
TXD[2]
TXD[3]
Local CPU Bus
10/100BASE-TX
MAC Controller
GPI[2]/SPD
VDD
VSS
I_OP
IO_BASE[0]
IO_BASE[1]
IO_BASE[2]
GPO[0]
NC
NC
45
44
43
42
41
40
39
NC
NC
(for 68K Interface)
SD[0]
SD[1]
VDD
NC
VDD
VSS
/CS
SD[2]
Fig - 6 AX88796 Pin Connection Diagram for MC68K Mode
10
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
1.3.4 AX88796 Pin Connection Diagram for MCS-51 Mode
GPI[0]/LINK
VDD
NC
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
VSS
VSS
I_ACT
I_SPEED
I_LINK
CPU[1]
CPU[0]
VDD
VDDA
VSSA
VSS
VDD
VSS
EECS
EECK
EEDI
EEDO
TEST2
IDDQ
BIST
CLKO25M
VSS
GPI[1]/DPX
TX_CLK
TX_EN
TXD[0]
TXD[1]
TXD[2]
TXD[3]
GPI[2]/SPD
VDD
VSS
I_OP
IO_BASE[0]
IO_BASE[1]
IO_BASE[2]
GPO[0]
AX88796
Local CPU Bus
10/100BASE-TX
MAC Controller
NC
NC
45
44
43
42
41
40
39
NC
NC
(for 8051 Interface)
SD[0]
SD[1]
VDD
NC
VDD
VSS
/CS
SD[2]
Fig - 7 AX88796 Pin Connection Diagram for MCS-51 Mode
11
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
2.0 Signal Description
The following terms describe the AX88796 pin-out:
All pin names with the “/” suffix are asserted low.
The following abbreviations are used in following Tables.
I
O
I/O
OD
Input
Output
Input/Output
Open Drain
PU
PD
P
Pull Up
Pull Down
Power Pin
2.1 Local CPU Bus Interface Signals Group
SIGNAL
SA[9:1],
SA[0]/LDS
TYPE
PIN NO.
15,
12 – 4
DESCRIPTION
I
System Address : Signals SA[9:0] are address bus input lines, which
lower I/O spaces on chip. SA[0] also means Lower Data Strobe
(/LDS) active low signal in 68K application mode.
/BHE
or
/UDS
I/PU
I/O/PD
O
22
Bus High Enable or Upper Data Strobe : Bus High Enable is active
low signal in some 16-bit application mode, which enable high bus
(SD[15:8]) active. The signal also name as Upper Data Strobe (/UDS)
for 68K application mode.
SD[15:0]
23 – 26,
29 – 33, bus.
35 – 39,
System Data Bus : Signals SD[15:0] constitute the bi-directional data
41 – 42
IREQ/IREQ
16
Interrupt Request : When ISA BUS or 80186 CPU mode is select.
IREQ is asserted high to indicate the host system that the chip
requires host software service. When MC68K or MCS-51 CPU mode
is select. /IREQ is asserted low to indicate the host system that the
chip requires host software service.
RDY/DTACK
OD
2
Ready : This signal is set low to insert wait states during Remote
DMA transfer.
/Dtack : When Motorola CPU type is selected, the pin is active low
inform CPU that data is accepted.
/CS
I/PU
I/PU
I/PU
128
19
Chip Select
When the /CS signal is asserted, the chip is selected.
I/O Read :The host asserts /IORD to read data from AX88796 I/O
space. When Motorola CPU type is select , the pin is useless.
I/O Write :The host asserts /IOWR to write data into AX88796 I/O
space. When Motorola CPU type is select, the pin is active high for
read operation at the same time.
/IORD
/IOWR
or
R/W
18
/OCS16
OD
123
1
I/O is 16 Bit Port : The /IOIS16 is asserted when the address at the
range corresponds to an I/O address to which the chip responds, and
the I/O port addressed is capable of 16-bit access.
Address Enable : The signal is asserted when the address bus is
available for DMA cycle. When negated (low), AX88796 an I/O slave
device may respond to addresses and I/O command.
PSEN : This signal is active low for 8051 program access. For I/O
device, AX88796, this signal is active high to access the chip. This
signal is for 8051 bus application only.
AEN
I/PD
or
/PSEN
Tab - 1 Local CPU bus interface signals group
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
2.2 10/100Mbps Twisted-Pair Interface pins group
SIGNAL
TPI+
TYPE
PIN NO.
DESCRIPTION
Received Data. Positive differential received 125M baud MLT3 or
10M baud Manchester data from magnetic.
I
70
TPI-
I
71
88
87
Received Data. Negative differential received 125M baud MLT3 or
10M baud Manchester data from magnetic.
TPO+
TPO-
O
O
Transmit Data. Positive differential transmit 125M baud MLT3 or
10M baud Manchester data to magnetic.
Transmit Data. Negative differential transmit 125M baud MLT3 or
10M baud Manchester data to magnetic.
REXT10
REXT100
REXTBS
I
I
I
84
83
74
Current Setting 10Mbits/s. An external resistor 20k ohm is placed
from this signal to ground to set the 10Mbits/s TP driver transmit
output level.
Current Setting 100Mbits/s. An external resistor 2.49k ohm is placed
from this signal to ground to set the 100Mbits/s TP driver transmit
output level.
External Bias Resistor. Band Gap Reference for the Receive Channel.
Connect this signal to a 24.9k ohm +/- 1 percent resistor to ground.
The parasitic load capacitance should be less than 15 pF.
Tab - 2 10/100Mbps Twisted-Pair Interfaces pins group
2.3 Built-in PHY LED indicator pins group
SIGNAL
I_ACT
TYPE
O
PIN NO.
DESCRIPTION
62
Active Status : When I_OP is logic 1. If there is activity, transmit or
receive, on the line occurred, the output will be driven low for 0.67 sec
and then driven high at least 0.67 sec.
or
I_FULL/COL
Full-Duplex/Collision Status. When I_OP is logic 0. If this signal is
low, it indicates full-duplex link established, and if it is high, then the
link is in half-duplex mode. When in half-duplex and collision
occurrence, the output will be driven low for 0.67 sec and driven high
at least 0.67 sec. (Current sink capacity is 6mA)
I_SPEED
O
O
61
60
Speed Status : If this signal is low, it indicates 100Mbps, and if it is
high, then the speed is 10Mbps. (Current sink capacity is 6mA)
Link Status : When I_OP is logic 1. If this signal is low, it indicates
link, and if it is high, then the link is fail.
I_LINK
Or
I_LK/ACT
Link Status/Active : When I_OP is logic 0. If this signal is low, it
indicates link, and if it is high, then the link is fail. When in link status
and line activity occurrence, the output will be driven low for 0.67 sec
and driven high at least 0.67 sec. (Current sink capacity is 6mA)
Tab - 3 Built-in PHY LED indicator pins group
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
2.4 EEPROM Signals Group
SIGNAL
EECS
EECK
EEDI
TYPE
O
O/PD
O
PIN NO.
DESCRIPTION
51
50
49
48
EEPROM Chip Select : EEPROM chip select signal.
EEPROM Clock : Signal connected to EEPROM clock pin.
EEPROM Data In : Signal connected to EEPROM data input pin.
EEPROM Data Out : Signal connected to EEPROM data output pin.
EEDO
I/PU
Tab - 4 EEPROM bus interface signals group
2.5 MII interface signals group(Optional)
SIGNAL
RXD[3:0]
TYPE
I/PU
PIN NO.
98 – 95
DESCRIPTION
Receive Data : RXD[3:0] is driven by the PHY synchronously with
respect to RX_CLK.
CRS
I/PD
I/PD
100
102
Carrier Sense : Asynchronous signal CRS is asserted by the PHY
when either the transmit or receive medium is non-idle.
Receive Data Valid : RX_DV is driven by the PHY synchronously
with respect to RX_CLK. Asserted high when valid data is present on
RXD [3:0].
RX_DV
RX_ER
(Omit)
I/PU
No Support Receive Error : RX_ER ,is driven by PHY and synchronous to
RX_CLK, is asserted for one or more RX_CLK periods to indicate to
the port that an error has detected.
RX_CLK
99
Receive Clock : RX_CLK is a continuous clock that provides the
timing reference for the transfer of the RX_DV,RXD[3:0] and
RX_ER signals from the PHY to the MII port of the repeater.
Collision : this signal is driven by PHY when collision is detected.
Transmit Enable : TX_EN is transition synchronously with respect to
the rising edge of TX_CLK. TX_EN indicates that the port is
presenting nibbles on TXD [3:0] for transmission.
COL
TX_EN
I/PD
O
101
108
TXD[3:0]
O
112 – 109 Transmit Data : TXD[3:0] is transition synchronously with respect to
the rising edge of TX_CLK. For each TX_CLK period in which
TX_EN is asserted, TXD[3:0] are accepted for transmission by the
PHY.
TX_CLK
MDC
I/PU
107
Transmit Clock : TX_CLK is a continuous clock from PHY. It
provides the timing reference for the transfer of the TX_EN and
TXD[3:0] signals from the MII port to the PHY.
Station Management Data Clock : The timing reference for MDIO.
All data transfers on MDIO are synchronized to the rising edge of this
clock. The signal output reflects MDC register value. About MDC
register, please refer to MII/EEPROM Management register bit 0.
MDC clock frequency is a 2.5MHz maximum accourding to IEEE
802.3u MII specification. Acturely, many PHYs are designed to accept
higher frequency than 2.5MHz.
O/PU
67
MDIO
I/O/PU
66
Station Management Data Input/Output :Serial data input/output
transfers from/to the PHYs . The transfer protocol has to meet the
IEEE 802.3u MII specification. For more information, please refer to
section 6.5 CPU Access MII Station Management functions.
Tab - 5 MII interface signals group
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
2.6 Standard Printer Port (SPP) Interface pins group (Optional)
SIGNAL
PD[7:5]
TYPE
I/O/PD
I/O/PU
PIN NO.
DESCRIPTION
102 – 100 Parallel Data :The bi-directional parallel data bus is used to transfer
PD[4:0]
BUSY
/ACK
PE
99 - 95
108
information between CPU and peripherals. Default serve as input,
using /DOE bit of register offset x1Ah to set the direction.
Busy : This is a status input from the printer, high indicating that the
printer is not ready to receive new data.
Acknowledge : A low active input from the printer indicating that it
has received the data and is ready to accept new data.
Paper Empty : A status input from the printer, high indicating that the
printer is out of paper.
Slect: This high active input from the printer indicating that it has
power on.
Error : A low active input from the printer indicating that there is an
error condition at the printer.
I/PU
I/PU
I/PU
I/PU
I/PU
107
106
SLCT
/ERR
103
113
/SLCTIN
/INIT
/ATFD
O
O
O
112
111
110
Slect In: This active low output selects the printer.
Init: This signal is used to initiate the printer when low.
Auto Feed :This output goes low to cause the printer to automatically
feed one line after each line is printed.
/STRB
O
109
Strobe : A low active pulse on this output is used to strobe the print
data into the printer.
Tab - 6 Standard Printer Port Interface pins group
2.7 General Purpose I/O pins group
Signal Name
GPI[2]/SPD
GPI[1]/DPX
Type
I/PU
I/PU
Pin No.
113
Description
Read register offset 17h bit 6 value reflects this input value.
When MII port is selected. Read register offset 17h bit 5 value reflects
this input value.
106
When SPP port is selected. The pin is defined as PE.
When MII port is selected. Read register offset 17h bit 4 value reflects
this input value.
When SPP port is selected. The pin is defined as SLCT.
Default “1”. The pin reflects write register offset 17h bit 0 inverted
value.
GPI[0]/LINK
GPO[0]
I/PU
O
103
120
Tab - 7 General Purposes I/O pins group
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
2.8 Miscellaneous pins group
SIGNAL
TYPE
PIN NO.
DESCRIPTION
LCLK/XTALIN
I
79
CMOS Local Clock : A 25Mhz clock, +/- 100 PPM, 40%-60% duty
cycle. The signal not supports 5 Volts tolerance.
Crystal Oscillator Input : A 25Mhz crystal, +/- 25 PPM can be
connected across XTALIN and XTALOUT.
XTALOUT
O
80
Crystal Oscillator Output : A 25Mhz crystal, +/- 25 PPM can be
connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should
be left floating.
CLKO25M
RESET
O
I/PU
44
3
Clock Output : This clock is source from LCLK/XTALIN.
Reset :
Reset is active high then place AX88796 into reset mode immediately.
During the falling edge the AX88796 loads the power on setting data.
CPU type selection:
CPU[1:0]
I/PU
59, 58
CPU[1]
CPU[0]
CPU TYPE
ISA BUS
80186
MC68K
MCS-51 (805X)
0
0
1
1
0
1
0
1
IO_BASE[2:1]
IO_BASE[0]
I/PU
I/PD
119, 118, I/O Base Address Selection:
117
IO_BASE[2] IO_BASE[1] IO_BASE[0]
IO_BASE
300h
320h
340h
360h
380h
3A0h
200h(default)
220h
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
1
0
1
0
1
1
1
0
1
I_OP
I/PU
I/PD
116
LED Indicator Option : Selection of LED display mode.
I_OP = 0: I_LK/ACT, I_SPEED and I_FULL/COL LED display
mode.
I_OP = 1: I_LINK, I_SPEED and I_ACT LED display mode. (default)
Test Pins : Active high
TEST[2:1]
47, 65
These pins are just for test mode setting purpose only. Must be pull
down or keep no connection when normal operation.
For test only. Must be pulled down at normal operation.
For test only. Must be pulled down or keep no connection when normal
operation.
IDDQ
BIST
I
46
45
I/PD
ZVREG
NC
O
N/A
P
92
This sets the common mode voltage for 10Base-T and 100Base-TX
modes. It should be connected to the center tap of the transmit side of
the transformer
17, 20, 21, No Connection : for manufacturing test only.
64, 122, 124,
125
VDD
VSS
13, 27, 40, Power Supply : +3.3V DC.
53, 57, 104,
114, 126
P
14, 28, 34, Power Supply : +0V DC or Ground Power.
43, 52, 54, 63,
94, 105,115,
127
VDDA
P
56, 69,
Power Supply for Analog Circuit: +3.3V DC.
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ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
73, 82
55, 68,
72, 75, 85,
76
VSSA
P
P
P
P
P
Power Supply for Analog Circuit: +0V DC or Ground Power.
VDDM
VSSM
VDDPD
VSSPD
Powers the analog block around the transmit/receive area. This should
be connected to VDDA: +3.3V DC.
Powers the analog block around the transmit/receive area. This should
be connected to VSSA: +0V DC or Ground Power.
The Phase Detector (or PLL) power. This should be isolated with other
power: +3.3V DC.
77, 93
78
81
The Phase Detector (or PLL) power. This should be isolated with other
power: +0V DC or Ground.
VDDO
VSSO
P
P
91
Power Supply for Transceiver Output Driver: +3.3V DC.
86, 89, 90 Power Supply for Transceiver Output Driver: +0V DC or Ground.
Tab - 8 Miscellaneous pins group
2.9 Power on configuration setup signals cross reference table
Signal Name
/SPP_SET
Share with
MDC
Description
Standard Printer Port Selection:
/SPP_SET = 0 : Standard Printer Port or GPIO is selected
/SPP_SET = 1 : MII port is selected (default)
PPD_SET
EECK
PPD_SET = 0 : Internal PHY in normal mode. (default)
PPD_SET = 1 : Internal PHY in power down mode.
Tab - 9 Power on Configuration Setup Table
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AX88796 L
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3.0 Memory and I/O Mapping
There are three memories or I/O mapping used in AX88796.
1. EEPROM Memory Mapping
2. I/O Mapping
3. Local Memory Mapping
3.1 EEPROM Memory Mapping
User can define by them and can access via I/O address offset 14H MII/EEPROM registers.
The contants of EEPROM will not be loading to any registers automaticlly.
3.2 I/O Mapping
SYSTEM I/O OFFSET
FUNCTION
0000H
001FH
MAC CORE REGISTER
Tab - 10 I/O Address Mapping
3.3 SRAM Memory Mapping
OFFSET
0000H
3FFFH
4000H
7FFF
FUNCTION
RESERVED
NE2000 COMPATABLE MODE
8K X 16 SRAM BUFFER
RESERVED
8000H
FFFFH
Tab - 11 Local Memory Mapping
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
4.0 Basic Operation
4.1 Receiver Filtering
The address filtering logic compares the Destination Address Field (first 6 bytes of the received packet) to the Physical
address registers stored in the Address Register Array. If any one of the six bytes does not match the pre-programmed
physical address, the Protocol Control Logic rejects the packet. This is for unicast address filtering. All multicast
destination addresses are filtered using a hashing algorithm. (See following description.) If the multicast address indexes
a bit that has been set in the filter bit array of the Multicast Address Register Array the packet is accepted, otherwise it is
rejected by the Protocol Control Logic. Each destination address is also checked for all 1's which is the reserved broadcast
address.
4.1.1 Unicast Address Match Filter
The physical address registers are used to compare the destination address of incoming packets for rejecting or accepting
packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the sequence in
PAR0-PAR5 to the bit sequence of the received packet.
D7
D6
D5
D4
D3
D2
D1
D0
PAR0
PAR1
PAR2
PAR3
PAR4
PAR5
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA9
DA17
DA25
DA33
DA41
DA0
DA8
DA16
DA24
DA32
DA40
DA15
DA23
DA31
DA39
DA47
DA14
DA22
DA30
DA38
DA46
DA13
DA21
DA29
DA37
DA45
DA12
DA20
DA28
DA36
DA44
DA11
DA19
DA27
DA35
DA43
DA10
DA18
DA26
DA34
DA42
Note: The bit sequence of the received packet is DA0, DA1, … DA7, DA8 ….
4.1.2 Multicast Address Match Filter
The Multicast Address Registers provide filtering of multicast addresses hashed by the CRC logic. All destination
addresses are fed through the 32 bits CRC generation logic and as the last bit of the destination address enters the CRC,
the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode to index
a unique filter bit (FB0-63) in the Multicast Address Registers. If the filter bit selected is set, the multicast packet is
accepted. The system designer would use a program to determine which filter bits to set in the multicast registers. All
multicast filter bits that correspond to Multicast Address Registers accepted by the node are then set to one. To accept all
multicast packets all of the registers are set to all ones.
D7
D6
D5
D4
D3
D2
D1
D0
MAR0
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
FB7
FB6
FB5
FB4
FB3
FB2
FB1
FB9
FB0
FB8
FB15
FB23
FB31
FB39
FB47
FB55
FB63
FB14
FB22
FB30
FB38
FB46
FB54
FB62
FB13
FB21
FB29
FB37
FB45
FB53
FB61
FB12
FB20
FB28
FB36
FB44
FB52
FB60
FB11
FB19
FB27
FB35
FB43
FB51
FB59
FB10
FB18
FB26
FB34
FB42
FB50
FB58
FB17
FB25
FB33
FB41
FB49
FB57
FB16
FB24
FB32
FB40
FB48
FB56
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AX88796 L
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32-bit CRC Generator
X=31 to X=26
Clock
Latch
1 of 64 bit decoder
Filter bit array
Selected bit
0 = reject, 1= accept
If address Y is found to hash to the value 32 (20H), then FB32 in MAR2 should be initialized to ``1''. This will cause the
AX88796 to accept any multicast packet with the address Y.
Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter up to 64
logical address filteres if these addresses are chosen to map into unique locations in the multicast filter.
Note: The first bit of received packet sequence is 1’s stands by Multicast Address.
4.1.3 Broadcast Address Match Filter
The Broadcast check logic compares the Destination Address Field (first 6 bytes of the received packet) to all 1’s, that is
the values are “FF FF FF FF FF FF FF” in Hex format. If any bit of the six bytes does not equal to 1’s, the Protocol Control
Logic rejects the packet.
4.1.4 Aggregate Address Filter with Receive Configuration Setup
The final address filter decision depands on the destination address types, identified by the above 3 address
match filters, and the setup of parameters of Receive Configuration Register.
Definitions of address match filter result are as following:
Signal
Phy
Value
=1
Description
Unicast Address Match
Unicast Address not Match
Multicast Address Match
Multicast Address not Match
Brocast Address Match
Brocast Address not Match
Aggregate Address Match
Aggregate Address not Match
=0
=1
=0
=1
=0
=1
=0
Mul
Bro
AGG
The meaning of AB, AM and PRO signals, please refer to “Receive Configuration Register”
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
Aggregate Address Filter function will be:
Bro
AND
Logic
AB
/Bro
/Mul
AND
Logic
PRO
AGG
OR
Logic
/Bro
Mul
AM
AND
Logic
Phy
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
4.2 Buffer Management Operation
There are four buffer memory access types used in AX88796.
1. Packet Reception (Write data to memory from MAC)
2. Packet Transmision (Read data from memory to MAC)
3. Filling Packets to Transmit Buffer (Host fill data to memory)
4. Removing Packets from the Receive Buffer Ring (Host read data from memory)
The type 1 and 2 operations act as Local DMA. Type 1 does Local DMA write operation and type 2 does Local
DMA read operation. The type 3 and 4 operations act as Remote DMA. Type 3 does Remote DMA write
operation and type 4 does Remote DMA read operation.
4.2.1 Packet Reception
The Local DMA receive channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length
256 byte (128 word) buffers for storage of received packets. The location of the Receive Buffer Ring is
programmed in two registers, a Page Start and a Page Stop Register. Ethernet packets consist of minimum
packet size (64 bytes) to maximum packet size (1522 bytes), the 256 byte buffer length provides a good
compromise between short packets and longer packets to most efficiently use memory. In addition these buffers
provide memory resources for storage of back-to-back packets in loaded networks. The assignment of buffers
for storing packets is controlled by Buffer Management Logic in the AX88796. The Buffer Management Logic
provides three basic functions: linking receive buffers for long packets, recovery of buffers when a packet is
rejected, and recirculation of buffer pages that have been read by the host.
At initialization, a portion of the 16k byte (or 8k word) address space is reserved for the receiver buffer ring.
Two eight bit registers, the Page Start Address Register (PSTART) and the Page Stop Address Register
(PSTOP) define the physical boundaries of where the buffers reside. The AX88796 treats the list of buffers as a
logical ring; whenever the DMA address reaches the Page Stop Address, the DMA is reset to the Page Start
Address.
4000h
4
…
3
n-2
Page Start
Buffer #1
Buffer #2
Buffer #3
…
…
n-1
2
…
…
1
n
Buffer #n
Page Stop
8000h
Physical Memory Map
Logic Receive Buffer Ring
Fig - 8 Receive Buffer Ring
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
INITIALIZATION OF THE BUFFER RING
Two static registers and two working registers control the operation of the Buffer Ring. These are the Page Start
Register, Page Stop Register (both described previously), the Current Page Register and the Boundary Pointer
Register. The Current Page Register points to the first buffer used to store a packet and is used to restore the
DMA for writing status to the Buffer Ring or for restoring the DMA address in the event of a Runt packet, a
CRC, or Frame Alignment error. The Boundary Register points to the first packet in the Ring not yet read by the
host. If the local DMA address ever reaches the Boundary, reception is aborted. The Boundary Pointer is also
used to initialize the Remote DMA for removing a packet and is advanced when a packet is removed. A simple
analogy to remember the function of these registers is that the Current Page Register acts as a Write Pointer and
the Boundary Pointer acts as a Read Pointer.
4000h
4
…
3
n-2
Page Start
Buffer #1
Buffer #2
Buffer #3
…
Boundary Page
Current Page
n-1
2
…
…
…
1
n
Buffer #n
Page Stop
8000h
Physical Memory Map
Logic Receive Buffer Ring
Fig - 9 Receive Buffer Ring At Initialization
BEGINNING OF RECEPTION
When the first packet begins arriving the AX88796 and begins storing the packet at the location pointed to by the
Current Page Register. An offset of 4 bytes is reserved in this first buffer to allow room for storing receive status
corresponding to this packet.
LINKING RECEIVE BUFFER PAGES
If the length of the packet exhausts the first 256 bytes buffer, the DMA performs a forward link to the next buffer
to store the remainder of the packet. For a maximal length packet the buffer logic will link six buffers to store the
entire packet. Buffers cannot be skipped when linking, a packet will always be stored in contiguous buffers.
Before the next buffer can be linked, the Buffer Management Logic performs two comparisons. The first
comparison tests for equality between the DMA address of the next buffer and the contents of the Page Stop
Register. If the buffer address equals the Page Stop Register, the buffer management logic will restore the DMA
to the first buffer in the Receive Buffer Ring value programmed in the Page Start Address Register. The second
comparison test for equality between the DMA address of the next buffer address and the contents of the
Boundary Pointer Register. If the two values are equal the reception is aborted. The Boundary Pointer Register
can be used to protect against overwriting any area in the receive buffer ring that has not yet been read. When
linking buffers, buffer management will never cross this pointer, effectively avoiding any overwrites. If the
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
buffer address does not match either the Boundary Pointer or Page Stop Address, the link to the next buffer is
performed.
LINKING BUFFERS
Before the DMA can enter the next contiguous 256 bytes buffer, the address is checked for equality to PSTOP
and to the Boundary Pointer. If neither are reached, the DMA is allowed to use the next buffer.
BUFFER RING OVERFLOW
If the Buffer Ring has been filled and the DMA reaches the Boundary Pointer Address, reception of the incoming
packet will be aborted by the AX88796. Thus, the packets previously received and still contained in the Ring will
not be destroyed. In a heavily loaded network environment the local DMA may be disabled, preventing the
AX88796 from buffering packets from the network. To guarantee this will not happen, a software reset must be
issued during all Receive Buffer Ring over flows (indicated by the OVW bit in the Interrupt Status Register).
The following procedure is required to recover from a Receiver Buffer Ring Overflow. If this routine is not
adhered to, the AX88796 may act in an unpredictable manner. It should also be noted that it is not permissible to
service an overflow interrupt by continuing to empty packets from the receive buffer without implementing the
prescribed overflow routine.
Note: It is necessary to define a variable in the driver, which will be called ``Resend''.
1. Read and store the value of the TXP bit in the AX88796's Command Register.
2. Issue the STOP command to the AX88796. This is accomplished be setting the STP bit in the AX88796's
Command Register. Writing 21H to the Command Register will stop the AX88796.
3. Wait for at least 1.5 ms. Since the AX88796 will complete any transmission or reception that is in progress,
it is necessary to time out for the maximum possible duration of an Ethernet transmission or reception. By
waiting 1.5 ms this is achieved with some guard band added. Previously, it was recommended that the RST bit
of the Interrupt Status Register be polled to insure that the pending transmission or reception is completed.
This bit is not a reliable indicator and subsequently should be ignored.
4. Clear the AX88796's Remote Byte Count registers (RBCR0 and RBCR1).
5. Read the stored value of the TXP bit from step 1, above. If this value is a 0, set the ``Resend'' variable to a 0
and jump to step 6. If this value is a 1, read the AX88796's Interrupt Status Register. If either the Packet
Transmitted bit (PTX) or Transmit Error bit (TXE) is set to a 1, set the ``Resend'' variable to a 0 and jump to
step 6. If neither of these bits is set, place a 1 in the ``Resend'' variable and jump to step 6. This step determines
if there was a transmission in progress when the stop command was issued in step 2. If there was a
transmission in progress, the AX88796's ISR is read to determine whether or not the packet was recognized by
the AX88796. If neither the PTX nor TXE bit was set,then the packet will essentially be lost and retransmitted
only after a time-out takes place in the upper level software. By determining that the packet was lost at the
driver level, a transmit command can be reissued to the AX88796 once the overflow routine is completed (as
in step 11). Also, it is possible for the AX88796 to defer indefinitely, when it is stopped on a busy network.
Step 5 also alleviates this problem. Step 5 is essential and should not be omitted from the overflow routine, in
order for the AX88796 to operate correctly.
6. Place the AX88796 in mode 1 loopback. This can be accomplished by setting bits D2 and D1, of the Transmit
Configuration Register to ``0,1''.
7. Issue the START command to the AX88796. This can be accomplished by writing 22H to the Command
Register. This is necessary to activate the AX88796's Remote DMA channel.
8. Remove one or more packets from the receive bufferring.
9. Reset the overwrite warning (OVW, overflow) bit in the Interrupt Status Register.
10. Take the AX88796 out of loopback. This is done by writing the Transmit Configuration Register with the
value it contains during normal operation. (Bits D2 and D1 should both be programmed to 0.)
11. If the ``Resend'' variable is set to a 1, reset the ``Resend'' variable and reissue the transmit command. This is
done by writing a value of 26H to the Command Register. If the ``Resend'' variable is 0, nothing needs to
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
bedone.
END OF PACKET OPERATIONS
At the end of the packet the AX88796 determines whether the received packet is to be accepted or rejected. It
either branches to a routine to store the Buffer Header or to another routine that recovers the buffers used to store
the packet.
SUCCESSFUL RECEPTION
If the packet is successfully received as shown, the DMA is restored to the first buffer used to store the packet
(pointed to by the Current Page Register). The DMA then stores the Receive Status, a Pointer to where the next
packet will be stored and the number of received bytes. Note that the remaining bytes in the last buffer are
discarded and reception of the next packet begins on the next empty 256 byte buffer boundary. The Current Page
Register is then initialized to the next available buffer in the Buffer Ring. (The location of the next buffer had
been previously calculated and temporarily stored in an internal scratchpad register.)
BUFFER RECOVERY FOR REJECTED PACKETS
If the packet is a runt packet or contains CRC or Frame Alignment errors, it is rejected. The buffer management
logic resets the DMA back to the first buffer page used to store the packet (pointed to by CPR), recovering all
buffers that had been used to store the rejected packet. This operation will not be performed if the AX88796 is
programmed to accept either runt packets or packets with CRC or Frame Alignment errors. The received CRC
is always stored in buffer memory after the last byte of received data for the packet.
Error Recovery
If the packet is rejected as shown, the DMA is restored by the AX88796 by reprogramming the DMA starting
address pointed to by the Current Page Register.
4.2.2 Packet Transmision
The Local DMA Read is also used during transmission of a packet. Three registers control the DMA transfer
during transmission, a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers
(TBCR0,1). When the AX88796 receives a command to transmit the packet pointed to by these registers, buffer
memory data will be moved into the FIFO as required during transmission. The AX88796 Controller will
generate and append the preamble, synch and CRC fields.
TRANSMIT PACKET ASSEMBLY
The AX88796 requires a contiguous assembled packet with the format shown. The transmit byte count includes
the Destination Address, Source Address, Length Field and Data. It does not include preamble and CRC. When
transmitting data smaller than 46 bytes, the packet must be padded to a minimum size of 64 bytes. The
programmer is responsible for adding and stripping pad bytes. The packets are placed in the buffer RAM by the
system. System programs the AX88796 Core's Remote DMA to move the data from the data port to the RAM
handshaking with system transfers loading the I/O data port.
The data transfer must be 16 bits (1 word) when in 16-bit mode, and 8 bits when the AX88796 Controller is set
in 8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register and setting
the CPU[1:0] pins for ISA, 80186 or MC68K mode.
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
Destination Address
6 Bytes
6 Bytes
2 Bytes
46 Bytes
Min.
Source Address
Length / Type
Data
(Pad if < 46 Bytes)
General Transmit Packet Format
TRANSMISSION
Prior to transmission, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count
Registers) must be initialized. To initiate transmission of the packet the TXP bit in the Command Register is set.
The Transmit Status Register (TSR) is cleared and the AX88796 begins to prefetch transmit data from memory.
If the Interpacket Gap (IPG) has timed out the AX88796 will begin transmission.
CONDITIONS REQUIRED TO BEGIN TRANSMISSION
In order to transmit a packet, the following three conditions must be met:
1. The Interpacket Gap Timer has timed out
2. At least one byte has entered the FIFO. (This indicates that the burst transfer has been started)
3. If a collision had been detected then before transmission the packet backoff time must have timed out.
COLLISION RECOVERY
During transmission, the Buffer Management logic monitors the transmit circuitry to determine if a collision has
occurred. If a collision is detected, the Buffer Management logic will reset the FIFO and restore the Transmit
DMA pointers for retransmission of the packet. The COL bit will be set in the TSR and the NCR (Number of
Collisions Register) will be incremented. If 15 retransmissions each result in a collision the transmission will be
aborted and the ABT bit in the TSR will be set.
Transmit Packet Assembly Format
The following diagrams describe the format for how packets must be assembled prior to transmission for
different byte ordering schemes. The various formats are selected in the Data Configuration Register and setting
the CPU[1:0] pins for ISA, 80186, MC68K or MCS-51 mode.
D15
D8 D7
D0
Destination Address 0
Destination Address 1
Destination Address 3
Destination Address 5
Source Address 1
Source Address 3
Source Address 5
Type / Length 1
Data 1
Destination Address 2
Destination Address 4
Source Address 0
Source Address 2
Source Address 4
Type / Length 0
Data 0
…
…
BOS = 0, WTS = 1 in Data Configuration Register.
This format is used with ISA or 80186 Mode.
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3-in-1 Local Bus Fast Ethernet Controller
D15
D8 D7
D0
Destination Address 1
Destination Address 0
Destination Address 2
Destination Address 4
Source Address 0
Source Address 2
Source Address 4
Type / Length 0
Data 0
Destination Address 3
Destination Address 5
Source Address 1
Source Address 3
Source Address 5
Type / Length 1
Data 1
…
…
BOS = 1, WTS = 1 in Data Configuration Register.
This format is used with MC68K Mode.
D7
D0
Destination Address 0 (DA0)
Destination Address 1 (DA1)
Destination Address 2 (DA2)
Destination Address 3 (DA3)
Destination Address 4 (DA4)
Destination Address 5 (DA5)
Source Address 0 (SA0)
Source Address 1 (SA1)
Source Address 2 (SA2)
Source Address 3 (SA3)
Source Address 4 (SA4)
Source Address 5 (SA5)
Type / Length 0
Type / Length 1
Data 0
Data 1
…
BOS = 0, WTS = 0 in Data Configuration Register.
This format is used with ISA, 80186 or MCS-51 Mode.
Note: All examples above will result in a transmission of a packet in order of DA0 (Destination Address 0),
DA1, DA2, DA3 . . . in byte. Bits within each byte will be transmitted least significant bit first.
4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory)
The Remote DMA channel is used to both assemble packets for transmission, and to remove received packets
from the Receive Buffer Ring. It may also be used as a general purpose slave DMA channel for moving blocks
of data or commands between host memory and local buffer memory. There are two modes of operation, Remote
Write and Remote Read Packet.
Two register pairs are used to control the Remote DMA, a Remote Start Address (RSAR0, RSAR1) and a
Remote Byte Count (RBCR0, RBCR1) register pair. The Start Address Register pair points to the beginning of
the block to be moved while the Byte Count Register pair is used to indicate the number of bytes to be
transferred. Full handshake logic is provided to move data between local buffer memory (Embedded Memory)
and a bidirectional I/O port.
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REMOTE WRITE
A Remote Write transfer is used to move a block of data from the host into local buffer memory. The Remote
DMA will read data from the I/O port and sequentially write it to local buffer memory beginning at the Remote
Start Address. The DMA Address will be incremented and the Byte Counter will be decremented after each
transfer. The DMA is terminated when the Remote Byte Count Register reaches a count of zero.
4.2.4 Removing Packets from the Ring (Host read data from memory)
REMOTE READ
A Remote Read transfer is used to move a block of data from local buffer memory to the host. The Remote DMA
will sequentially read data from the local buffer memory, beginning at the Remote Start Address, and write data
to the I/O port. The DMA Address will be incremented and the Byte Counter will be decremented after each
transfer. The DMA is terminated when the Remote Byte Count Register reaches zero.
Packets are removed from the ring using the Remote DMA or an external device. When using the Remote DMA.
The Boundary Pointer can also be moved manually by programming the Boundary Register. Care should be
taken to keep the Boundary Pointer at least one buffer behind the Current Page Pointer. The following is a
suggested method for maintaining the Receive Buffer Ring pointers.
1. At initialization, set up a software variable (next_pkt) to indicate where the next packet will be read. At the
beginning of each Remote Read DMA operation, the value of next_pkt will be loaded into RSAR0 and
RSAR1.
2. When initializing the AX88796 set:
BNRY = PSTART
CPR = PSTART + 1
Next_pkt = PSTART + 1
3. After a packet is DMAed from the Receive Buffer Ring, the Next Page Pointer (second byte in AX88796
receive packet buffer header) is used to update BNRY and next_pkt.
Next_pkt = Next Page Pointer
BNRY = Next Page Pointer - 1
If BNRY < PSTART then BNRY = PSTOP – 1
Note the size of the Receive Buffer Ring is reduced by one 256-byte buffer; this will not, however, impede the
operation of the AX88796. The advantage of this scheme is that it easily differentiates between buffer full and
buffer empty: it is full if BNRY = CPR; empty when BNRY = CPR-1.
STORAGE FORMAT FOR RECEIVED PACKETS
The following diagrams describe the format for how received packets are placed into memory by the local DMA
channel. These modes are selected in the Data Configuration Register and setting the CPU[1:0] pins for ISA,
80186, MC68K or MCS-51 mode.
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3-in-1 Local Bus Fast Ethernet Controller
D15
D8 D7
D0
Next Packet Pointer
Receive Status
Receive Byte Count 1
Destination Address 1
Destination Address 3
Destination Address 5
Source Address 1
Source Address 3
Source Address 5
Type / Length 1
Data 1
Receive Byte Count 0
Destination Address 0
Destination Address 2
Destination Address 4
Source Address 0
Source Address 2
Source Address 4
Type / Length 0
Data 0
…
…
BOS = 0, WTS = 1 in Data Configuration Register.
This format is used with ISA or 80186 Mode.
D15
D8 D7
D0
Receive Status
Next Packet Pointer
Receive Byte Count 0
Destination Address 0
Destination Address 2
Destination Address 4
Source Address 0
Source Address 2
Source Address 4
Type / Length 0
Data 0
Receive Byte Count 1
Destination Address 1
Destination Address 3
Destination Address 5
Source Address 1
Source Address 3
Source Address 5
Type / Length 1
Data 1
…
…
BOS = 1, WTS = 1 in Data Configuration Register.
This format is used with MC68K Mode.
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
D7
D0
Receive Status
Next Packet Pointer
Receive Byte Count 0
Receive Byte Count 1
Destination Address 0
Destination Address 1
Destination Address 2
Destination Address 3
Destination Address 4
Destination Address 5
Source Address 0
Source Address 1
Source Address 2
Source Address 3
Source Address 4
Source Address 5
Type / Length 0
Type / Length 1
Data 0
Data 1
…
BOS = 0, WTS = 0 in Data Configuration Register.
This format is used with ISA, 80186 or MCS-51 Mode.
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AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
4.2.5 Other Useful Operations
MEMORY DIAGNOSTICS
Memory diagnostics can be achieved by Remote Write/Read DMA operations. The following is a suggested step
for memory test and assume the AX88796 has been well initilized.
1. Issue the STOP command to the AX88796. This is accomplished be setting the STP bit in the AX88796's
Command Register. Writing 21H to the Command Register will stop the AX88796.
2. Wait for at least 1.5 ms. Since the AX88796 will complete any reception that is in progress, it is necessary to
time out for the maximum possible duration of an Ethernet reception. This action prevents buffer memory
from written data through Local DMA Write.
3. Write data pattern to MUT (memory under test) by Remote DMA write operation.
4. Read data pattern from MUT (memory under test) by Remote DMA read operation.
5. Compare the read data pattern with original write data pattern and check if it is equal.
6. Repeat step 3 to step 5 with various data pattern.
LOOPBACK DIAGNOSTICS
1. Issue the STOP command to the AX88796. This is accomplished be setting the STP bit in the AX88796's
Command Register. Writing 21H to the Command Register will stop the AX88796.
2. Wait for at least 1.5 ms. Since the AX88796 will complete any reception that is in progress, it is necessary to
time out for the maximum possible duration of an Ethernet reception. This action prevents buffer memory
from written data through Local DMA Write.
3. Place the AX88796 in mode 1 loopback. (MAC internal loopback) This can be accomplished by setting bits
D2 and D1, of the Transmit Configuration Register to ``0,1''.
4. Issue the START command to the AX88796. This can be accomplished by writing 22H to the Command
Register. This is necessary to activate the AX88796's Remote DMA channel.
5. Write data that want to transmit to transmit buffer by Remote DMA write operation.
6. Issue the TXP command to the AX88796. This can be accomplished by writing 26H to the Command
Register.
7. Read data current receive buffer by Remote DMA read operation.
8. Compare the received data with original transmit data and check if it is equal.
9. Repeat step 5 to step 8 for more packets test.
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5.0 Registers Operation
5.1 MAC Core Registers
All registers of MAC Core are 8-bit wide and mapped into pages which are selected by PS (Page Select) in
the Command Register.
PAGE 0 (PS1=0,PS0=0)
OFFSET
READ
Command Register
WRITE
Command Register
00H
( CR )
( CR )
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Status Register
( TSR )
Number of Collisions Register
( NCR )
Current Page Register
( CPR )
Interrupt Status Register
( ISR )
Current Remote DMA Address 0
( CRDA0 )
Page Start Register
( PSTART )
Page Stop Register
( PSTOP )
Boundary Pointer
( BNRY )
Transmit Page Start Address
( TPSR )
Transmit Byte Count Register 0
( TBCR0 )
Transmit Byte Count Register 1
( TBCR1 )
Interrupt Status Register
( ISR )
Remote Start Address Register 0
( RSAR0 )
Remote Start Address Register 1
( RSAR1 )
Remote Byte Count 0
( RBCR0 )
Remote Byte Count 1
( RBCR1 )
Receive Configuration Register
( RCR )
Current Remote DMA Address 1
( CRDA1 )
Reserved
Reserved
Receive Status Register
( RSR )
0DH
0EH
Reserved
Reserved
Transmit Configuration Register ( TCR )
Data Configuration Register
( DCR )
0FH
Reserved
Interrupt Mask Register
( IMR )
10H, 11H
12H
Data Port
IFGS1
Data Port
IFGS1
13H
IFGS2
IFGS2
14H
15H
16H
17H
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPI
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPOC
18H - 1AH Standard Printer Port (SPP)
1BH - 1EH Reserved
Standard Printer Port (SPP)
Reserved
1FH
Reset
Reserved
Tab - 12 Page 0 of MAC Core Registers Mapping
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3-in-1 Local Bus Fast Ethernet Controller
PAGE 1 (PS1=0,PS0=1)
OFFSET
READ
Command Register
( CR )
Physical Address Register 0
( PARA0 )
Physical Address Register 1
( PARA1 )
Physical Address Register 2
( PARA2 )
Physical Address Register 3
( PARA3 )
Physical Address Register 4
( PARA4 )
Physical Address Register 5
( PARA5 )
WRITE
Command Register
( CR )
Physical Address Register 0
( PAR0 )
Physical Address Register 1
( PAR1 )
Physical Address Register 2
( PAR2 )
Physical Address Register 3
( PAR3 )
Physical Address Register 4
( PAR4 )
Physical Address Register 5
( PAR5 )
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Current Page Register
( CPR )
Multicast Address Register 0
( MAR0 )
Multicast Address Register 1
( MAR1 )
Multicast Address Register 2
( MAR2 )
Multicast Address Register 3
( MAR3 )
Multicast Address Register 4
( MAR4 )
Multicast Address Register 5
( MAR5 )
Multicast Address Register 6
( MAR6 )
Multicast Address Register 7
( MAR7 )
Multicast Address Register 7
( MAR7 )
10H, 11H
12H
Data Port
Inter-frame Gap Segment 1
IFGS1
Data Port
Inter-frame Gap Segment 1
IFGS1
13H
Inter-frame Gap Segment 2
IFGS2
Inter-frame Gap Segment 2
IFGS2
14H
15H
16H
17H
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPI
MII/EEPROM Access
Test Register
Inter-frame Gap (IFG)
GPOC
18H - 1AH Standard Printer Port (SPP)
1BH - 1EH Reserved
Standard Printer Port (SPP)
Reserved
1FH
Reset
Reserved
Tab - 13 Page 1 of MAC Core Registers Mapping
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3-in-1 Local Bus Fast Ethernet Controller
5.1.1 Command Register (CR) Offset 00H (Read/Write)
FIELD NAME
DESCRIPTION
7:6
PS1,PS0 PS1,PS0 : Page Select
The two bits selects which register page is to be accessed.
PS1
0
0
PS0
0
1
page 0
page 1
5:3
RD2,RD1 RD2,RD1,RD0 : Remote DMA Command
,RD0 These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88796 when a Remote
DMA has been completed. The Remote Byte Count should be cleared when a Remote DMA
has been aborted. The Remote Start Address is not restored to the starting address if the
Remote DMA is aborted.
RD2 RD1 RD0
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Not allowed
Remote Read
Remote Write
Not allowed
Abort / Complete Remote DMA
2
1
0
TXP TXP : Transmit Packet
This bit could be set to initiate transmission of a packet
START START :
This bit is used to active AX88796 operation.
STOP STOP : Stop AX88796
This bit is used to stop the AX88796 operation.
5.1.2 Interrupt Status Register (ISR) Offset 07H (Read/Write)
FIELD NAME
DESCRIPTION
7
RST Reset Status :
Set when AX88796 enters reset state and cleared when a start command is issued to the
CR. Writing to this bit is no effect.
6
5
RDC Remote DMA Complete
Set when remote DMA operation has been completed
CNT Counter Overflow
Set when MSB of one or more of the Tally Counters has been set.
OVW OVERWRITE : Set when receive buffer ring storage resources have been exhausted.
TXE Transmit Error
4
3
Set when packet transmitted with one or more of the following errors
n
n
Excessive collisions
FIFO Underrun
2
RXE Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
FIFO Overrun
Missed Packet
1
0
PTX Packet Transmitted
Indicates packet transmitted with no error
PRX Packet Received
Indicates packet received with no error.
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5.1.3 Interrupt mask register (IMR) Offset 0FH (Write)
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
-
Reserved
RDCE DMA Complete Interrupt Enable. Default “low” disabled.
CNTE Counter Overflow Interrupt Enable. Default “low” disabled.
OVWE Overwrite Interrupt Enable. Default “low” disabled.
TXEE Transmit Error Interrupt Enable. Default “low” disabled.
RXEE Receive Error Interrupt Enable. Default “low” disabled.
PTXE Packet Transmitted Interrupt Enable. Default “low” disabled.
PRXE Packet Received Interrupt Enable. Default “low” disabled.
5.1.4 Data Configuration Register (DCR) Offset 0EH (Write)
FIELD NAME
DESCRIPTION
7
6:2
1
RDCR Remote DMA always completed
-
-
Reserved
Reserved
0
WTS Word Transfer Select
0 : Selects byte-wide DMA transfers.
1 : Selects word-wide DMA transfers.
5.1.5 Transmit Configuration Register (TCR) Offset 0DH (Write)
FIELD NAME
DESCRIPTION
7
FDU Full Duplex :
This bit indicates the current media mode is Full Duplex or not.
0 : Half duplex
1 : Full duplex
6
5
PD
Pad Disable
0 : Pad will be added when packet length less than 60.
1 : Pad will not be added when packet length less than 60.
RLO Retry of late collision
0 : Don’t retransmit packet when late collision happens.
1 : Retransmit packet when late collision happens.
Reserved
LB1,LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
4:3
2:1
-
Mode 0
Mode 1
Mode 2
0
0
1
0
1
0
Normal operation
Internal AX88796 loop-back
PHYcevisor loop-back
0
CRC Inhibit CRC
0 : CRC appended by transmitter.
1 : CRC inhibited by transmitter.
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5.1.6 Transmit Status Register (TSR) Offset 04H (Read)
FIELD NAME
DESCRIPTION
7
6:4
3
OWC Out of window collision
Reserved
ABT Transmit Aborted
Indicates the AX88796 aborted transmission because of excessive collision.
COL Transmit Collided
-
2
Indicates that the transmission collided at least once with another station on the network.
Reserved
PTX Packet Transmitted
Indicates transmission without error.
1
0
-
5.1.7 Receive Configuration (RCR) Offset 0CH (Write)
FIELD NAME
DESCRIPTION
7
6
-
Reserved
INTT Interrupt Trigger Mode for ISA and 80186 modes
0 : Low active
1 : High active (default)
Interrupt Trigger Mode for MCS-51 and MC68K modes
0 : High active
1 : Low active (default)
5
MON Monitor Mode
0 : Normal Operation
1 : Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not
buffered into memory.
4
3
PRO PRO : Promiscuous Mode
Enable the receiver to accept all packets with a physical address.
AM
AM : Accept Multicast
Enable the receiver to accept packets with a multicast address. That multicast address must
pass the hashing array.
2
1
0
AB
AR
AB : Accept Broadcast
Enable the receiver to accept broadcast packet.
AR : Accept Runt
Enable the receiver to accept runt packet.
SEP : Save Error Packet
SEP
Enable the receiver to accept and save packets with error.
5.1.8 Receive Status Register (RSR) Offset 0CH (Read)
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
-
Reserved
Receiver Disabled
DIS
PHY Multicast Address Received.
MPA Missed Packet
FO
FAE Frame alignment error.
CR CRC error.
PRX Packet Received Intact
FIFO Overrun
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ASIX ELECTRONICS CORPORATION
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3-in-1 Local Bus Fast Ethernet Controller
5.1.9 Inter-frame gap (IFG) Offset 16H (Read/Write)
FIELD NAME
DESCRIPTION
7
-
Reserved
6:0
IFG
Inter-frame Gap. Default value 15H.
5.1.10 Inter-frame gap Segment 1(IFGS1) Offset 12H (Read/Write)
FIELD NAME
DESCRIPTION
7
6:0
-
Reserved
Inter-frame Gap Segment 1. Default value 0cH.
IFG
5.1.11 Inter-frame gap Segment 2(IFGS2) Offset 13H (Read/Write)
FIELD NAME
DESCRIPTION
7
6:0
-
Reserved
Inter-frame Gap Segment 2. Default value 12H.
IFG
5.1.12 MII/EEPROM Management Register (MEMR) Offset 14H
(Read/Write)
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
EECLK EECLK:
EEPROM Clock
EEO EEO : (Read only)
EEPROM Data Out value. That reflects Pin-48 EEDO value.
EEI
EEPROM Data In. That output to Pin-49 EEDI as EEPROM data input value.
EECS EECS
EEPROM Chip Select
MDO MDO
MII Data Out. The value reflects to Pin-66 MDIO when MDIR=0.
MDI MDI: (Read only)
MII Data In. That reflects Pin-66 MDIO value.
EEI
MDIR MII STA MDIO signal Direction
MII Read Control Bit, asserts this bit let MDIO signal as the input signal. Deassert this bit
let MDIO as output signal.
0
MDC MDC
MII Clock. This value reflects to Pin-67 MDC.
5.1.13 Test Register (TR) Offset 15H (Write)
FIELD NAME
DESCRIPTION
7:5
4
3
-
Reserved
TF16T Test for Collision, default value is logic 0 (User always keep the default value unchanged)
TPE Test pin Enable, default value is logic 0 (User always keep the default value unchanged)
2:0
IFG
Select Test Pins Output, default value is logic 0 (User always keep the default value
unchanged)
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5.1.14 Test Register (TR) Offset 15H (Read)
FIELD NAME
DESCRIPTION
7:4
3
-
Reserved
RST_TX 100BASE-TX in Reset : This signal indicates that 100BASE-TX logic of internal PHY is
in reset.
B
2
1
0
RST_10B 10BASE-T in Reset : This signal indicates that 10BASE-T logic of internal PHY is in reset.
RST_B Reset Busy : This signal indicates that internal PHY is in reset.
AUTOD Autonegotiation Done : This signal goes high whenever internal PHY autonegotiation has
completed. It will go low if autonegotiation has to restart.
5.1.15 General Purpose Input Register (GPI) Offset 17H (Read)
FIELD NAME
DESCRIPTION
7
6
5
4
3
2
1
0
-
Reserved
GPI2 This register reflects GPI[2] input value. May connect to external PHY speed status.
GPI1 This register reflects GPI[1] input value. May connect to external PHY duplex status.
GPI0 This register reflects GPI[0] input value. May connect to external PHY link status.
-
Reserved
I_SPD This register reflects internal PHY speed status value. Logic one means 100Mbps
I_DPX This register reflects internal PHY duplex status value. Logic one means full duplex.
I_LINK This register reflects internal PHY link status value. Logic one means link ok.
5.1.16 GPO and Control (GPOC) Offset 17H (Write)
FIELD NAME
DESCRIPTION
7
6
-
Reserved
PPDSET Internal PHY Power Down Setting:
Default “0”, Internal PHY is in normal operation mode
Write PPDSET to “1” force Internal PHY into power down mode
MPSET Media Set by Program : The signal is valid only when MPSEL is set to high.
When MPSET is logic 0 , internal PHY is selected.
When MPSET is logic 1 , external MII PHY is selected.
MPSEL Media Priority Select :
5
4
MPSEL I_LINK
GPI0
Media Selected
Internal PHY
Internal PHY
External MII PHY
Internal PHY
Depend on MPSET bit
0
1
1
0
0
X
0
1
0
1
X
0
0
0
1
3:1
0
-
Reserved
/GPO0 Default “0”. The register reflects to GPO[0] pin with inverted value.
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5.1.17 SPP Data Port Register (SPP_DPR) Offset 18H (Read/Write)
FIELD NAME
7:0 DP
DESCRIPTION
Printer Data Port. Default is in input mode. Write /DOE of SPP_CPR register to logic “0”
to enable print data output to printer as bi-directional mode.
5.1.18 SPP Status Port Register (SPP_SPR) Offset 19H (Read)
FIELD NAME
DESCRIPTION
7
/BUSY Reading a ‘0’ indicates that the printer is not ready to receive new data.
The register reflects the inverted value of BUSY pin.
6
/ACK Reading a ‘0’ indicates that the printer has received the data and is ready to accept new data.
The register reflects the value of /ACK pin.
5
PE
Reading a ‘1’ indicates that the printer is out of paper.
The register reflects the value of PE pin.
4
SLCT Reading a ‘1’ indicates that the printer has power on.
The register reflects the value of SLCT pin.
3
/ERR Reading a ‘0’ indicates that there is an error condition at the printer.
The register reflects the value of /ERR pin.
2:0
-
Reserved
5.1.19 SPP Command Port Register (SPP_CPR) Offset 1AH (Read/Write)
FIELD NAME
DESCRIPTION
7:6
5
4
-
Reserved
/DOE
IRQEN
Setting to ‘0’ enables print data output to printer. Default sets to ‘1’.
IRQ enable : printer port interrupt is not supported.
3
SLCTIN Setting to ‘1’ selects the printer.
/SLIN pin reflects the inverted value of this signal.
2
1
0
/INIT Setting to ‘0’ initiates the printer
/INIT pin reflects the value of this signal.
ATFD Setting to ‘1’ causes the printer to automatically feed one line after each line is printed.
/ATFD pin reflects the inverted value of this signal.
STRB Setting a low-high-low pulse on this register is used to strobe the print data into the printer.
/STRB pin reflects the inverted value of this signal.
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3-in-1 Local Bus Fast Ethernet Controller
5.2 The Embedded PHY Registers
The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each
field of the registers. The format for the “FIELD” descriptions is as follows: the first number is the register number, the
second number is the bit position in the register and the name of the instantiated pad is in capital letters. The format for
the “TYPE” descriptions is as follows: R = read, W = write, LH = latch high, NA = not applicable.
ADDRESS
NAME
MR0
MR1
MR2
MR3
MR4
MR5
MR6
MR7
DESCRIPTION
DEFAULT(Hex Code)
0
1
2
3
4
5
6
7
Control
Status
PHY Identifier 1
PHY Identifier 2
3000h
7849h
0180h
BB10h
01E1h
0000
0000
0000
-
0000
0000
0000
-
Autonegotiation Advertisement
Autonegotiation Link Partner Ability
Autonegotiation Expansion
Next Page Transmit
8 - 15
16
17
18
19
20
21
22 - 24
25 - 27
28
MR8 -15 (Reserved)
MR16 PCS Control Register
MR17 Autonegotiation (read register A)
MR18 Autonegotiation (read register B)
MR19 Analog Test Register
MR20 User-defined Register
MR21 RXER Counter
MR22 -24 Analog Test Registers
MR25 -27 Analog Test (tuner) Registers
MR28 Device Specific 1
-
0000
-
-
-
29
30
31
MR29 Device Specific 2
MR30 Device Specific 3
MR31 Quick Status Register
2080
0000
-
Tab - 14 The Embedded PHY Registers
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5.2.1 MR0 -- Control Register Bit Descriptions
FIELD
TYPE
DESCRIPTION
0.15 (SW_RESET)
R/W
Reset. Setting this bit to a 1 will reset the PHY. All registers will be set to
their default state. This bit is self-clearing. The default is 0.
Loopback. When this bit is set to 1, no data transmission will take place on
the media. Any receive data will be ignored. The loopback signal path will
contain all circuitry up to, but not including, the PMD. The default value is
a 0.
Speed Selection. The value of this bit reflects the current speed of operation
(1 = 100Mbits/s; 0 = 10Mbits/s). This bit will only affect operating speed
when the autonegotiation enable bit (register 0, bit 12) is disabled (0). This
bit is ignored when autonegotiation is enabled (register 0, bit 12). This bit is
ANDed with the SPEED_PIN signal.
0.14 (LOOPBACK)
0.13(SPEED100)
R/W
R/W
0.12 (NWAY_ENA)
0.11 (PWRDN)
R/W
R/W
Autonegotiation Enable. The autonegotiation process will be enabled by
set-ting this bit to a 1. The default state is a 1.
Powerdown. The PHY may be placed in a low-power state by setting this bit
to a 1, both the 10Mbits/s transceiver and the 100Mbits/s transceiver will be
powered down. While in the power down state, the PHY will respond to
management transactions. The default state is a 0.
0.10 (ISOLATE)
R/W
R/W
Isolate. When this bit is set to a 1, the MII outputs will be brought to the
high-impedance state. The default state is a 0.
0.9 (REDONWAY)
Restart Autonegotiation. Normally, the autonegotiation process is started
at powerup. The process may be restarted by setting this bit to a 1. The
default state is a 0. The NWAYDONE bit (register 1, bit 5) is reset when this
bit goes to a 1. This bit is self-cleared when autonegotiation restarts.
Duplex Mode. This bit reflects the mode of operation (1 = full duplex; 0 =
half duplex). This bit is ignored when the autonegotiation enable bit
(register 0, bit 12) is enabled. The default state is a 0. This bit is ORed with
the F_DUP pin.
0.8 (FULL_DUP)
R/W
0.7 (COLTST)
R/W
NA
Collision Test. When this bit is set to a 1, the PHY will assert the MCOL
signal in response to MTX_EN.
Reserved. All bits will read 0.
0.6:0 (RESERVED)
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5.2.2 MR1 -- Status Register Bit Descriptions
FIELD
1.15 (T4ABLE)
TYPE
DESCRIPTION
100Base-T4 Ability. This bit will always be a 0.
0: Not able.
R
1: Able.
1.14 (TXFULDUP)
1.13 (TXHAFDUP)
1.12 (ENFULDUP)
1.11 (ENHAFDUP)
R
R
R
R
100Base-TX Full-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
100Base-TX Half-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
10Base-T Full-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
10Base-T Half-Duplex Ability. This bit will always be a 1.
0: Not able.
1: Able.
1.10:7 (RESERVED)
1.6 (NO_PA_OK)
R
R
Reserved. All bits will read as a 0.
Suppress Preamble. When this bit is set to a 1, it indicates that the PHY
accepts management frames with the preamble suppressed.
Autonegotiation Complete. When this bit is a 1, it indicates the
autonegotiation process has been completed. The contents of registers MR4,
MR5, MR6, and MR7 are now valid. The default value is a 0. This bit is reset
when autonegotiation is started.
1.5 (NWAYDONE)
R
1.4 (REM_FLT)
R
Remote Fault. When this bit is a 1, it indicates a remote fault has been
detected. This bit will remain set until cleared by reading the register. The
default is a 0.
1.3 (NWAYABLE)
1.2 (LSTAT_OK)
R
R
Autonegotiation Ability. When this bit is a 1, it indicates the ability to
perform autonegotiation. The value of this bit is always a 1.
Link Status. When this bit is a 1, it indicates a valid link has been
established. This bit has a latching function: a link failure will cause the bit
to clear and stay cleared until it has been read via the management interface.
Jabber Detect. This bit will be a 1 whenever a jabber condition is detected.
It will remain set until it is read, and the jabber condition no longer exists.
Extended Capability. This bit indicates that the PHY supports the
extended register set (MR2 and beyond). It will always read a 1.
1.1 (JABBER)
R
R
1.0 (EXT_ABLE)
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5.2.3 MR2, MR3 -- Identification Registers (1 and 2) Bit Descriptions
FIELD
TYPE
DESCRIPTION
2.15:0 (OUI[3:18])
R
Organizationally Unique Identifier. The third through the twenty-fourth
bit of the OUI assigned to the PHY manufacturer by the IEEE are to be
placed in bits. 2.15:0 and 3.15:10. This value is programmable.
Organizationally Unique Identifier. The remaining 6 bits of the OUI. The
value for bits 24:19 is programmable.
Model Number. 6-bit model number of the device. The model number is
programmable.
Revision Number. The value of the present revision number. The version
number is programmable.
3.15:10 (OUI[19:24])
3.9:4 (MODEL[5:0])
3.3:0 (VERSION[3:0])
R
R
R
5.2.4 MR4 – Autonegotiation Advertisement Registers Bit Descriptions
FIELD
TYPE
DESCRIPTION
4.15 (NEXT_PAGE)
R/W
Next Page. The next page function is activated by setting this bit to a 1. This
will allow the exchange of additional data. Data is carried by optional next
pages of information.
4.14 (ACK)
4.13 (REM_FAULT)
R/W
R/W
Acknowledge. This bit is the acknowledge bit from the link code word.
Remote Fault. When set to 1, the PHY indicates to the link partner a remote
fault condition.
4.12:10 (PAUSE)
R/W
Pause. When set to a 1, it indicates that the PHY wishes to exchange flow
control information with its link partner.
4.9 (100BASET4)
4.8 (100BASET_FD)
R/W
R/W
100Base-T4. This bit should always be set to 0.
100Base-TX Full Duplex. If written to 1, autonegotiation will advertise
that the PHY is capable of 100Base-TX full-duplex operation.
100Base-TX. If written to 1, autonegotiation will advertise that the PHY is
capable of 100Base-TX operation.
10Base-T Full Duplex. If written to 1, autonegotiation will advertise that
the PHY is capable of 10Base-T full-duplex operation.
10Base-T. If written to 1, autonegotiation will advertise that the PHY is
capable of 10Base-T operation.
4.7 (100BASETX)
4.6 (10BASET_FD)
4.5 (10BASET)
R/W
R/W
R/W
R/W
4.4:0 (SELECT)
Selector Field. Reset with the value 00001 for IEEE 802.3.
5.2.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register Bit
Descriptions
FIELD
TYPE
DESCRIPTION
5.15
R
Link Partner Next Page. When this bit is set to 1, it indicates that the link
partner wishes to engage in next page exchange.
Link Partner Acknowledge. When this bit is set to 1, it indicates that the
link partner has successfully received at least three consecutive and
consistent FLP bursts.
(LP_NEXT_PAGE)
5.14 (LP_ACK)
R
5.13
R
R
Remote Fault. When this bit is set to 1, it indicates that the link partner has
a fault.
Technology Ability Field. This field contains the technology ability of the
link partner. These bits are similar to the bits defined for the MR4 register
(see Table 16).
(LP_REM_FAULT)
5.12:5
(LP_TECH_ABILITY)
5.4:0 (LP_SELECT)
R
Selector Field. This field contains the type of message sent by the link
partner. For IEEE 802.3 compliant link partners, this field should read
00001.
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3-in-1 Local Bus Fast Ethernet Controller
5.2.6 MR5 –Autonegotiation Link Partner(LP)Ability Register (Next Page)Bit
Descriptions
FIELD
TYPE
DESCRIPTION
5.15
R
Next Page. When this bit is set to logic 0, it indicates that this is the last
page to be transmitted. Logic 1 indicates that additional pages will follow.
Acknowledge. When this bit is set to a logic 1, it indicates that the link
partner has successfully received its partner’s link code word.
Message Page. This bit is used by the NEXT _PAGE function to
differentiate a message page (logic 1) from an unformatted page (logic 0).
Acknowledge 2. This bit is used by the NEXT_PAGE function to indicate
that a device has the ability to comply with the message (logic 1) or not
(logic 0).
(LP_NEXT_PAGE)
5.14 (LP_ACK)
R
R
R
5.13
(LP__MES_PAGE)
5.12 (LP_ACK2)
5.11 (LP_TOGGLE)
5.10:0 (MCF)
R
R
Toggle. This bit is used by the arbitration function to ensure
synchronization with the link partner during next page exchange. Logic 0
indicates that the previous value of the transmitted link code word was logic
1. Logic 1 indicates that the previous value of the transmitted link code word
was logic 0.
Message/Unformatted Code Field. With these 11 bits, there are 2048
possible messages. Message code field definitions are described in annex
28C of the IEEE 802.3u standard.
5.2.7 MR6 – Autonegotiation Expansion Register Bit Descriptions
FIELD
6.15:5 (RESERVED)
6.4
TYPE
R
R/LH
DESCRIPTION
Reserved.
Parallel Detection Fault. When this bit is set to 1, it indicates that a fault
has been detected in the parallel detection function. This fault is due to more
than one technology detecting concurrent link conditions. This bit can only
be cleared by reading this register.
(PAR_DET_FAULT)
6.3
R
Link Partner Next Page Able. When this bit is set to 1, it indicates that the
link partner supports the next page function.
(LP_NEXT_PAGE_AB
LE)
6.2
R
R/LH
R
Next Page Able. This bit is set to 1, indicating that this device supports the
NEXT_PAGE function.
Page Received. When this bit is set to 1, it indicates that a NEXT_PAGE
has been received.
Link Partner Autonegotiation Capable. When this bit is set to 1, it
indicates that the link partner is autonegotiation capable.
(NEXT_PAGE_ABLE)
6.1 (PAGE_REC)
6.0
(LP_NWAY_ABLE)
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5.2.8 MR7 –Next Page Transmit Register Bit Descriptions
FIELD
TYPE
DESCRIPTION
7.15 (NEXT_PAGE)
R/W
Next Page. This bit indicates whether or not this is the last next page to be
transmitted. When this bit is 0, it indicates that this is the last page. When
this bit is 1, it indicates there is an additional next page.
7.14 (ACK)
7.13 (MESSAGE)
R
R/W
Acknowledge. This bit is the acknowledge bit from the link code word.
Message Page. This bit is used to differentiate a message page from an
unformatted page. When this bit is 0, it indicates an unformatted page.
When this bit is 1, it indicates a formatted page.
7.12 (ACK2)
R/W
R
Acknowledge 2. This bit is used by the next page function to indicate that a
device has the ability to comply with the message. It is set as follows:
When this bit is 0, it indicates the device cannot comply with the message.
When this bit is 1, it indicates the device will comply with the message.
Toggle. This bit is used by the arbitration function to ensure
synchronization with the link partner during next page exchange. This bit
will always take the opposite value of the toggle bit in the previously
exchanged link code word:
7.11 (TOGGLE)
If the bit is logic 0, the previous value of the transmitted link code word was
logic 1.
If the bit is a 1, the previous value of the transmitted link code word was a 0.
The initial value of the toggle bit in the first next page transmitted is the
inverse of the value of bit 11 in the base link code word, and may assume a
value of 1 or 0.
7.10:0 (MCF)
R/W
Message/Unformatted Code Field. With these 11 bits, there are 2048
possible messages. Message code field definitions are described in annex
28C of the IEEE 802.3u standard.
5.2.9 MR16 – PCS Control Register Bit Descriptions
FIELD
TYPE
R
R
R/W
DESCRIPTION
Locked. Locked pin from descrambler block.
Unused. Will always be read back as 0.
Generic Test Bits. These bits have no effect on the PCS block. They are for
external use only. A 0 should be written to these bits.
Loopback Configure. When this bit is high, the entire loopback is
performed in the PCS macro. When this bit is low, only the collision pin is
disabled in loopback.
16.15 (LOCKED)
16.14-12 (UNUSED)
16.11-4 (TESTBITS)
16.3 (LOOPBACK)
R/W
16.2 (SCAN)
16.1
LOOPBACK)
16.0 (SPEEDUP
COUNTERS)
R/W
R/W
Scan Test Mode.
(FORCE
Force Loopback. Force a loopback without forcing idle on the transmit side
or disabling the collision pin.
Speedup Counters. Reduce link monitor counter to 10 us from 620 us.
(Same as FASTTEST = 1.)
R/W
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5.2.10 MR17 –Autonegotiation Register A Bit Descriptions
FIELD
17.15-13
TYPE
R
DESCRIPTION
Reserved. Always 0.
Next Page Wait.
17.12
17.11
17.10
17.9
17.8
17.7
17.6
17.5
17.4
17.3
17.2
17.1
17.0
R
R
R
R
R
R
R
R
R
R
R
R
Wait Link_Fail_Inhibit_Wait_Timer (Link Status Check).
Wait Autoneg_Wait_Timer (Link Status Check).
Wait Break_Link_Timer (Transmit Disable).
Parallel Detection Fault.
Autonegotiation Enable.
FLP Link Good Check.
Complete Acknowledge.
Acknowledge Detect.
FLP Link Good.
Link Status Check.
Ability Detect.
Transmit Disable.
R
5.2.11 MR18 –Autonegotiation Register B Bit Descriptions
FIELD
TYPE
DESCRIPTION
Receiving FLPs. Any of FLP Capture, Clock, Data_0, or Data_1 (FLP
Rcv).
18.15
R
18.14
18.13
18.12
18.11
18.10
18.9
18.8
18.7
18.6
18.5
18.4
18.3
18.2
18.1
18.0
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
FLP Pass (FLP Rcv).
Link Pulse Count (FLP Rcv).
Link Pulse Detect (FLP Rcv).
Test Pass (NLP Rcv).
Test Fail Count (NLP Rcv).
Test Fail Extend (NLP Rcv).
Wait Max Timer Ack (NLP Rcv).
Detect Freeze (NLP Rcv).
Test Fail (NLP Rcv).
Transmit Count Ack (FLP Xmit).
Transmit Data Bit (FLP Xmit).
Transmit Clock Bit (FLP Xmit).
Transmit ability (FLP Xmit).
Transmit Remaining Acknowledge (FLP Xmit).
Idle (FLP Xmit).
5.2.12 MR20 –User Defined Register Bit Descriptions
FIELD
20.[15:0]
TYPE
R/W
DESCRIPTION
The data written into this user-defined register appears on the
REG20_OUT[15:0] bus.
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5.2.13 MR21 –RXER Counter Register Bit Descriptions
FIELD
TYPE
DESCRIPTION
21.0
W
This bit, when 0 puts this register in 16-bit counter mode. When 1, it puts
this register in 8-bit counter mode. This bit is reset to a 0 and cannot be read.
When in 16-bit counter mode, these maintain a count of RXERs. It is reset
on a read operation.
When in 8-bit counter mode, these maintain a count of RXERs. It is reset on
a read operation
When in 8-bit mode, these contain a count of false carrier events (802.3
section 27.3.1.5.1). It is reset on a read operation.
When in 8-bit mode, these contain a count of disconnect events (Link
Unstable 6, 802.3 section 27.3.1.5.1). It is reset on a read operation.
21.15:0
21.7:0
21.11:8
21.15:12
R
R
R
R
5.2.14 MR28 –Device-Specific Register 1 (Status Register) Bit Descriptions
FIELD
28.15:9 (UNUSED)
28.8 (BAD_FRM)
TYPE
R
R/LH
DESCRIPTION
Unused. Read as 0.
Bad Frame. If this bit is a 1, it indicates a packet has been received without
an SFD. This bit is only valid in 10Mbits/s mode.
This bit is latching high and will only clear after it has been read or the
device has been reset.
28.7 (CODE)
28.6 (APS)
R/LH
Code Violation. When this bit is a 1, it indicates a Manchester code
violation has occurred. The error code will be output on the MRXD lines.
Refer to Table 1 for a detailed description of the MRXD pin error codes.
This bit is only valid in 10Mbits/s mode.
This bit is latching high and will only clear after it has been read or the
device has been reset.
Autopolarity Status. When register 30, bit 3 is set and this bit is a 1, it
indicates the PHY has detected and corrected a polarity reversal on the
twisted pair.
R
If the APF_EN bit (register 30, bit 3) is set, the reversal will be corrected
inside the PHY. This bit is not valid in 100Mbits/s operation.
Disconnect. If this bit is a 1, it indicates a disconnect. This bit will latch
high until read. This bit is only valid in 100Mbits/s mode.
Unlocked. Indicates that the TX scrambler lost lock. This bit will latch high
until read. This bit is only valid in 100Mbits/s mode.
RX Error Status. Indicates a false carrier. This bit will latch high until
read. This bit is only valid in 100Mbits/s mode.
Force Jam. This bit will latch high until read. This bit is only valid in
100Mbits/s mode.
Link Up 100. This bit, when set to a 1, indicates a 100Mbits/s transceiver is
up and operational.
28.5 (DISCON)
R/LH
R/LH
R/LH
R/LH
R
28.4 (UNLOCKED)
28.3 (RXERR_ST)
28.2 (FRC_JAM)
28.1 (LNK100UP)
28.0 (LNK10UP)
R
Link Up 10. This bit, when set to a 1, indicates a 10Mbits/s transceiver is up
and operational.
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5.2.15 MR29 –Device-Specific Register 2 (100Mbps Control) Bit Descriptions
FIELD
TYPE
DESCRIPTION
29.15 (LOCALRST)
R/W
Management Reset. This is the local management reset bit. Writing logic 1
to this bit will cause the lower 16 registers and registers 28 and 29 to be reset
to their default values. This bit is self-clearing.
29.14 (RST1)
29.13 (RST2)
29.12 (100_OFF)
R/W
R/W
R/W
Generic Reset 1. This register is used for manufacture test only.
Generic Reset 2. This register is used for manufacture test only.
100Mbits/s Transmitter Off. When this bit is set to 0, it forces TPI low and
TPIN- high. This bit defaults to 1.
29.11 (LED_BLINK)
29.10 (CRS_SEL)
R/W
R/W
LED Blinking. This register, when 1, enables LED blinking. This is ORed
with LED_BLINK_EN. Default is 0.
Carrier Sense Select. MCRS will be asserted on receive only when this bit
is set to a 1. If this bit is set to logic 0, MCRS will by asserted on receive or
transmit. This bit is ORed with the CRS_SEL pin.
29.9 (LINK_ERR)
29.8 (PKT_ERR)
R/W
R/W
Link Error Indication. When this bit is a 1, a link error code will be
reported on MRXD[3:0] of the PHY when MRX_ER is asserted on the MII.
The specific error codes are listed in the MRXD pin description. If it is 0, it
will disable this function.
Packet Error Indication Enable. When this bit is a 1, a packet error code,
which indicates that the scrambler is not locked, will be reported on
MRXD[3:0] of the PHY when MRX_ER is asserted on the MII. When this
bit is 0, it will disable this function.
29.7 (PULSE_STR)
29.6 (EDB)
R/W
R/W
Pulse Stretching. When this bit is set to 1, the CS, XS, and RS output
signals will be stretched between approximately 42 ms - 84 ms. If this bit is
0, it will disable this feature. Default state is 0.
Encoder/Decoder Bypass. When this bit is set to 1, the 4B/5B-encoder and
5B/4B-decoder function will be disabled. This bit is ORed with the EDBT
pin.
29.5 (SAB)
29.4 (SDB)
R/W
R/W
Symbol Aligner Bypass. When this bit is set to 1, the aligner function will
be disabled.
Scrambler/Descrambler Bypass. When this bit is set to 1, the scrambling/
descrambling functions will be disabled. This bit is ORed with the SDBT
pin.
29.3 (CARIN_EN)
29.2 (JAM_COL)
29.1 (FEF-EN)
R/W
R/W
R/W
Carrier Integrity Enable. When this bit is set to a 1, carrier integrity is
enabled. This bit is ORed with the CARIN_EN pin.
Jam Enable. When this bit is a 1, it enables JAM associated with carrier
integrity to be ORed with MCOLMCRS.
Far-End Fault Enable. This bit is used to enable the far-end fault detection
and transmission capability. This capability may only be used if
autonegotiation is disabled. This capability is to be used only with media
which does not support autonegotiation. Setting this bit to 1 enables far-end
fault detection, and logic 0 will disable the function. Default state is 0.
Fiber-Optic Mode. When this bit is a 1, the PHY is in fiber-optic mode.
This bit is ORed with FX_MODE.
29.0 (FX)
R/W
48
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
5.2.16 MR30 –Device-Specific Register 3 (10Mbps Control) Bit Descriptions
FIELD
TYPE
DESCRIPTION
30.15 (Test10TX)
R/W
When high and 10Base-T is powered up, a continuous 10 MHz signal
(1111) will be transmitted. This is only meant for testing. Default 0.
When high, all 10Base-T logic will be powered up when the link is up.
Otherwise, portions of the logic will be powered down when no data is being
received to conserve power. Default is 0.
30.14 (RxPLLEn)
30.13 (JAB_DIS)
R/W
R/W
Jabber Disable. When this bit is 1, disables the jabber function of the
10Base-T receive. Default is 0.
30.12:7 (UNUSED)
30.6 (LITF_ENH)
R/W
R/W
Unused. Read as 0.
Enhanced Link Integrity Test Function. When high, function is enabled.
This is ORed with the LITF_ENH input. Default is 0.
30.5 (HBT_EN)
30.4 (ELL_EN)
R/W
R/W
Heartbeat Enable. When this bit is a 1, the heartbeat function will be
enabled. Valid in 10Mbits/s mode only.
Extended Line Length Enable. When this bit is a 1, the receive squelch
levels are reduced from a nominal 435 mV to 350 mV, allowing reception of
signals with a lower amplitude. Valid in 10Mbits/s mode only.
Autopolarity Function Disable. When this bit is a 0 and the PHY is in 10
Mbits/s mode, the autopolarity function will determine if the TP link is
wired with a polarity reversal.
30.3 (APF_EN)
R/W
If there is a polarity reversal, the PHY will assert the APS bit (register 28, bit
6) and correct the polarity reversal. If this bit is a 1 and the device is in 10
Mbits/s mode, the reversal will not be corrected.
30.2 (RESERVED)
30.1 (SERIAL _SEL)
R/W
R/W
Reserved.
Serial Select. When this bit is set to a 1, 10Mbits/s serial mode will be
selected. When the PHY is in 100Mbits/s mode, this bit will be ignored.
No Link Pulse Mode. Setting this bit to a 1 will allow 10Mbits/s operation
with link pulses disabled. If the PHY is configured for 100Mbits/s operation,
setting this bit will not affect operation.
30.0 (ENA_NO_LP)
R/W
49
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
5.2.17 MR31 –Device-Specific Register 4 (Quick Status) Bit Descriptions
FIELD
TYPE
DESCRIPTION
31.15 (ERROR)
R
Receiver Error. When this bit is a 1, it indicates that a receive error has been
detected. This bit is valid in 100Mbits/s only. This bit will remain set until
cleared by reading the register. Default is a 0.
31.14
R
False Carrier. When bit [31.7] is set to 0 and this bit is a 1, it indicates that the
carrier detect state machine has found a false carrier. This bit is valid in
100Mbits/s only. This bit will remain set until cleared by reading the register.
Default is 0.
(RXERR_ST)/(LINK_ST
AT_CHANGE)
Link Status Change. When bit [31.7] is set to a 1, this bit is redefined to become
the LINK_STAT_CHANGE bit and goes high whenever there is a change in link
status (bit [31.11] changes state)
31.13 (REM_FLT)
R
R
Remote Fault. When this bit is a 1, it indicates a remote fault has been detected.
This bit will remain set until cleared by reading the register. Default is a 0.
Unlocked/Jabber. If this bit is set when operating in 100Mbits/s mode, it
indicates that the TX descrambler has lost lock. If this bit is set when operating
in 10Mbits/s mode, it indicates a jabber condition has been detected. This bit will
remain set until cleared by reading the register.
31.12
(UNLOCKED)/(JABBE
R)
31.11 (LSTAT_OK)
R
Link Status. When this bit is a 1, it indicates a valid link has been established.
This bit has a latching low function: a link failure will cause the bit to clear and
stay cleared until it has been read via the management interface.
Link Partner Pause. When this bit is set to a 1, it indicates that the
LU3X54FTL wishes to exchange flow control information.
Link Speed. When this bit is set to a 1, it indicates that the link has negotiated to
100Mbits/s. When this bit is a 0, it indicates that the link is operating at
10Mbits/s.
31.10 (PAUSE)
R
R
31.9 (SPEED100)
31.8 (FULL_DUP)
31.7 (INT_CONF)
R
Duplex Mode. When this bit is set to a 1, it indicates that the link has negotiated
to full-duplex mode. When this bit is a 0, it indicates that the link has negotiated
to half-duplex mode.
Interrupt Configuration. When this bit is set to a 0, it defines bit [31.14] to be
the RXERR_ST bit and the interrupt pin (MASK_STAT_INT) goes high
whenever any of bits [31.15:12] go high, or bit [31.11] goes low. When this bit is
set high, it redefines bit [31.14] to become the LINK_STAT_CHANGE bit, and
the interrupt pin (MASK_STAT_INT) goes high only when the link status
changes (bit [31.14] goes high). This bit defaults to 0.
R/W
31.6 (INT_MASK)
R/W
R
Interrupt Mask. When set high, no interrupt is generated by this channel under
any condition. When set low, interrupts are generated according to bit [31.7].
Lowest Autonegotiation State. These 3 bits report the state of the lowest
autonegotiation state reached since the last register read, in the priority order
defined below:
31.5:3
(LOW_AUTO__STATE)
000: Autonegotiation enable.
001: Transmit disables or ability detects.
010: Link status check.
011: Acknowledge detects.
100: Complete acknowledges.
101: FLP link good check.
110: Next page wait.
111: FLP link good.
31.2:0
(HI_AUTO_STATE)
R
Highest Autonegotiation State. These 3 bits report the state of the highest
autonegotiation state reached since the last register read, as defined above for bit
[31.5:3].
50
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
6.0 CPU I/O Read and Write Functions
6.1 ISA bus type access functions.
ISA bus I/O Read function
Function Mode
Standby Mode
Byte Access
/CS
H
L
L
L
/BHE
X
H
H
L
A0
X
L
H
L
/IORD
/IOWR
SD[15:8]
High-Z
Not Valid
Not Valid
Odd-Byte
SD[7:0]
High-Z
Even-Byte
Odd-Byte
Even-Byte
X
L
L
L
X
H
H
H
Word Access
ISA bus I/O Write function
Function Mode
Standby Mode
Byte Access
/CS
H
L
L
L
/BHE
X
H
H
L
A0
X
L
H
L
/IORD
/IOWR
SD[15:8]
SD[7:0]
X
Even-Byte
Odd-Byte
Even-Byte
X
H
H
H
X
L
L
L
X
X
X
Word Access
Odd-Byte
6.2 80186 CPU bus type access functions.
80186 CPU bus I/O Read function
Function Mode
Standby Mode
Byte Access
/CS
H
L
L
L
/BHE
X
H
L
L
A0
X
L
H
L
/IORD
/IOWR
SD[15:8]
High-Z
Not Valid
Odd-Byte
Odd-Byte
SD[7:0]
High-Z
Even-Byte
Not Valid
Even-Byte
X
L
L
L
X
H
H
H
Word Access
80186 CPU bus I/O Write function
Function Mode
Standby Mode
Byte Access
/CS
H
L
L
L
/BHE
X
H
L
L
A0
X
L
H
L
/IORD
/IOWR
SD[15:8]
X
SD[7:0]
X
Even-Byte
X
X
H
H
H
X
L
L
L
X
Odd-Byte
Odd-Byte
Word Access
Even-Byte
51
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
6.3 MC68K CPU bus type access functions.
68K bus I/O Read function
Function Mode
Standby Mode
Byte Access
/CS
H
L
L
L
/UDS /LDS
R/W
X
H
H
H
SD[15:8]
High-Z
Not Valid
Even-Byte
Even-Byte
SD[7:0]
High-Z
Odd-Byte
Not Valid
Odd-Byte
X
H
L
L
X
L
H
L
Word Access
68K bus I/O Write function
Function Mode
Standby Mode
Byte Access
/CS
H
L
L
L
/UDS /LDS
R/W
X
L
L
L
SD[15:8]
X
SD[7:0]
X
Odd-Byte
X
X
H
L
L
X
L
H
L
X
Even-Byte
Even-Byte
Word Access
Odd-Byte
6.4 MCS-51 CPU bus type access functions.
8051 bus I/O Read function
Function Mode
Standby Mode
/CS
H
X
L
L
/PSEN SA0
/IORD
/IOWR
SD[15:8]
High-Z
High-Z
Not Valid
Not Valid
SD[7:0]
High-Z
High-Z
Even-Byte
Odd-Byte
X
L
H
H
X
X
L
X
X
L
L
X
X
H
H
Byte Access
H
8051 bus I/O Write function
Function Mode
Standby Mode
/CS
H
X
L
L
/PSEN SA0
/IORD
/IOWR
SD[15:8]
SD[7:0]
X
X
L
H
H
X
X
L
X
X
H
H
X
X
L
L
X
X
X
X
X
Byte Access
Even-Byte
Odd-Byte
H
52
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
6.5 CPU Access MII Station Management functions.
Basic Operation
The primary function of station management is to transfer control and status information about the PHY to a
management entity. This function is accomplished by the MDC clock input from MAC entity, which has a
maximum frequency of 12.5 MHz (for internal PHY only, as to external PHY please refer to the relevant
specification), along with the MDIO signal.
The Internal PHY address is fixed to 10h and the equivalent circuit is shown as below:
From Register
Offset 14h
(Internal PHY)
MDIO-OUT MDIO-IN
MDC
Pin67
MDC
MDC
MDO
Pin66
MDIO
0
MDI
Y (MUX)
1
MDIR
S
If (PHY_ID==10h) then S=1 else S=0
A specific set of registers and their contents (described in Tab - 16 MII Management Frames- field Description)
defines the nature of the information transferred across the MDIO interface. Frames transmitted on the MII
management interface will have the frame structure shown in Tab - 15 MII Management Frame Format. The
order of bit transmission is from left to right. Note that reading and writing the management register must be
completed without interruption.
Read/Write Pre
(R/W)
ST
OP
PHYAD REGAD TA
DATA
IDLE
R
W
1. . .1
1. . .1
01
01
10
01
AAAAA RRRRR
AAAAA RRRRR
Z0
10
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
Z
Z
Tab - 15 MII Management Frame Format
Field
Descriptions
Pre
ST
OP
Preamble. The PHY will accept frames with no preamble. This is indicated by a 1 in register 1, bit 6.
Start of Frame. The start of frame is indicated by a 01 pattern.
Operation Code. The operation code for a read transaction is 10. The operation code for a write
transaction is a 01.
PHYADD
PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity that is
attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for
each entity.
REGAD
TA
Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY. The
first register address bit transmitted and received is the MSB of the address.
Turnaround. The turnaround time is a 2-bit time spacing between the register address field, and
the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a
write to the PHY, these bits is driven to 10 by the station. During a read, the MDIO is not
driven during the first bit time and is driven to a 0 by the PHY during the second bit time.
Data. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register
being addressed.
DATA
IDLE
Idle Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will be
disabled and the PHY’s pull-up resistor will pull the MDIO line to logic 1.
Tab - 16 MII Management Frames- field Description
53
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
7.0 Electrical Specification and Timings
7.1 Absolute Maximum Ratings
Description
Operating Temperature
Storage Temperature
Supply Voltage
Input Voltage
SYM
Min
Max
Units
°C
°C
V
V
V
Ta
Ts
0
+85
-55
-0.3
-0.3
-0.3
-55
+150
+4.6
5.5*
Vdd+0.5
+220
Vdd
Vin
Vout
Tl
Output Voltage
Lead Temperature (soldering 10 seconds maximum)
°C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure
to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability.
Note: * All digital input signals can sustain 5 Volts input voltage except pin-79 LCLK/XTALIN
7.2 General Operation Conditions
Description
SYM
Ta
Vdd
Min
+3.14
Tpy
25
+3.30
Max
+75
+3.46
Units
°C
V
Operating Temperature
Supply Voltage
0
7.3 DC Characteristics
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 75°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current
Output Leakage Current
SYM
Min
Tpy
Max
Units
V
V
V
V
Vil
Vih
Vol
Voh
Iil
-
1.9
-
0.8
-
0.4
-
+1
+1
Vdd-0.4
-1
-1
uA
uA
Iol
Description
Power Consumption (3.3V)
SYM
SPt3v
Min
Tpy
Max
Units
mA
94
120
54
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
7.4 A.C. Timing Characteristics
7.4.1 XTAL / CLOCK
Thigh
LCLK/XTALIN
Tr
Tf
Tlow
Tcyc
CLKO
Tod
Symbol
Tcyc
Description
Min
Typ.
40
20
20
-
Max
Units
ns
ns
ns
ns
CYCLE TIME
Thigh
Tlow
CLK HIGH TIME
CLK LOW TIME
CLK SLEW RATE
16
16
1
24
24
4
Tr/Tf
Tod
LCLK/XTALIN TO CLKO OUT DELAY
10
7.4.2 Reset Timing
LCLK/XTALIN
RESET
/RESET
Symbol
Description
Min
Typ.
Max
Units
Trst
Reset pulse width
100
-
-
LClk
Warning: Some chips may needed long power down for successful PHY auto
negotiation
Root of cause:
The PHY inside of AX88796 has a special request due to the semiconductor’s process. Namely,
it needs a very long power down for successful Auto Negotiation for some chips. We made a test
in lab and found it would be no problem if the PHY's initial time kept for 2 sec for all chips. If the
power down is less then this number, some of the PHY's Auto Negotiation will not be complete
and there will be potential to cause the link fail. If the auto negotiation time is not long enough,
uncertain numbers of chip may not work properly.
55
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
Countermeasure:
Following actions will fix the problem of long auto negotiation.
(1) Software approach:
1. Set the PHY register MR0 with 0x800h (1000,0000,0000) -- bit 11 of MR0 to '1'
(Power down Mode).
2. Wait for 2.5 sec
3. Set the PHY register MR0 with 0x1200h(0001,0010,0000,0000) -- bit 12,9 of MR0 to
'1' (auto negotiation enable and restart auto negotiation)
(2) Hardware approach:
Put the pin 3 (reset pin) high (reset) for 2.5 sec.
56
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
7.4.3 ISA Bus Access Timing
Tsu(AEN)
Th(AEN)
AEN
Tsu(A)
Th(A)
/BHE
SA[9:0],/CS
Tv(CS16-A)
Tdis(CS16-A)
/IOCS16
Ten(RD)
/IOWR,/IORD
Tv(RDY)
Tdis(RDY)
Tdis(RD)
RDY
Read Data
SD[15:0](Dout)
DATA Valid
Tsu(WR)
Th(WR)
Write Data
SD[15:0](Din)
DATA Input Establish
Symbol
Tsu(A)
Description
Min
Typ.
Max
-
-
-
-
20
6
20
-
20
4
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADDRESS SETUP TIME
ADDRESS HOLD TIME
AEN SETUP TIME
0
5
0
5
-
-
-
0
-
0.5
5
-
-
-
-
-
-
-
-
-
-
-
-
Th(A)
Tsu(AEN)
Th(AEN)
Tv(CS16-A)
AEN HOLD TIME
/IOCS16 VALID FROM ADDRESS CHANGE
Tdis(CS16-A) /IOCS16 DISABLE FROM ADDRESS CHANGE
Tv(RDY)
Tdis(RDY)
Ten(RD)
Tdis(RD)
Tsu(WR)
Th(WR)
RDY VALID FROM SA[9:0]=310 VALID
RDY DISABLE FROM /IORD OR /IOWR
OUTPUT ENABLE TIME FROM /IORD
OUTPUT DISABLE TIME FROM /IORD
DATA SETUP TIME
DATA HOLD TIME
5
-
57
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
7.4.4 80186 Type I/O Access Timing
Tsu(A)
Th(A)
/BHE
SA[9:0],/CS
Tw(RW)
/IOWR,/IORD
Tv(RDY)
RDY
Tdis(RDY)
Tdis(RD)
Ten(RD)
Read Data
SD[15:0](Dout)
DATA Valid
Tsu(WR)
Th(WR)
Write Data
SD[15:0](Din)
DATA Input Establish
Symbol
Tsu(A)
Description
ADDRESS SETUP TIME
Min
Typ.
Max
-
-
20
-
20
4
Units
ns
ns
ns
ns
ns
ns
ns
ns
0
5
-
0
-
0.5
5
5
-
-
-
-
-
-
-
-
Th(A)
ADDRESS HOLD TIME
Tv(RDY)
Tdis(RDY)
Ten(RD)
Tdis(RD)
Tsu(WR)
Th(WR)
Tw(RW)
RDY VALID FROM /IORD OR /IOWR
RDY DISABLE FROM SA[9:0]=310 VALID
OUTPUT ENABLE TIME FROM /IORD
OUTPUT DISABLE TIME FROM /IORD
DATA SETUP TIME
-
-
DATA HOLD TIME
/IORD OR /IOWR WIDTH TIME
50
ns
58
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
7.4.5 68K Type I/O Access Timing
Tsu(A)
Th(A)
SA[9:1],/CS
Tv(DS-WR)
/UDS,/LDS
Tw(DS)
Tdis(WR-DS)
(Read)
R/W
Ten(DS)
(Write)
R/W
Tv(DTACK)
Tdis(DTACK)
Tdis(DS)
/DTACK
(Read Data)
SD[15:0](Dout)
DATA Valid
Tsu(DS)
Th(DS)
(Write Data)
SD[15:0](Din)
DATA Input Establish
Symbol
Tsu(A)
Description
ADDRESS SETUP TIME
Min
0
5
0
5
-
0
-
0.5
5
Typ.
Max
-
-
-
-
20
-
20
4
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
-
-
-
Th(A)
ADDRESS HOLD TIME
Tv(DS-WR)
/UDS OR /LDS VALID FROM /W
Tdis(WR-DS) /W DISABLE FROM /UDS OR /LDS
Tv(DTACK) DACK VALID FROM /UDS OR /LDS
Tdis(DTACK) DACK DISABLE FROM /UDS OR /LDS
Ten(DS)
Tdis(DS)
Tsu(DS)
Th(DS)
OUTPUT ENABLE TIME FROM /UDS OR /LDS
OUTPUT DISABLE TIME FROM /UDS OR /LDS
DATA SETUP TIME
ns
ns
DATA HOLD TIME
5
-
Tw(DS)
/UDS OR /LDS WIDTH TIME
50
ns
59
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
7.4.6 8051 Bus Access Timing
/PSEN
Tsu(PSEN)
Th(PSEN)
Th(A)
Tsu(A)
SA[9:0],CS
Ten(RD)
/IOWR,/IORD
Tw(RW)
Tv(RDY)
Tdis(RDY)
(For Reference)
RDY
Tdis(RD)
Read Data
SD[7:0](Dout)
DATA Valid
Tsu(WR)
Th(WR)
Write Data
SD[7:0](Din)
DATA Input Establish
Symbol
Tsu(A)
Description
Min
0
5
0
5
-
0.5
5
Typ.
Max
-
-
-
-
20
4
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ADDRESS SETUP TIME
ADDRESS HOLD TIME
/PSEN SETUP TIME
/PSEN HOLD TIME
-
-
-
-
-
-
-
-
Th(A)
Tsu(PSEN)
Th(PSEN)
Ten(RD)
Tdis(RD)
Tsu(WR)
Th(WR)
OUTPUT ENABLE TIME FROM /IORD
OUTPUT DISABLE TIME FROM /IORD
DATA SETUP TIME
DATA HOLD TIME
5
-
Tw(RW)
/IORD OR /IOWR WIDTH TIME
50
ns
60
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
7.4.7 MII Timing
Ttclk
Ttch Ttcl
TXCLK
TXD<3:0>
TXEN
Ttv
Tth
Trclk
Trs
Trch Trcl
RXCLK
RXD<3:0>
RXDV
Trh
Trs1
RXER
Symbol
Ttclk Cycle time(100Mbps)
Description
Min
-
-
14
140
14
140
-
5
-
-
14
140
14
140
6
Typ.
40
400
-
-
-
-
-
-
40
400
-
-
-
-
-
-
-
Max
-
-
26
260
26
260
20
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Ttclk Cycle time(10Mbps)
Ttch
Ttch
Trch
Trch
Ttv
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
Clock to data valid
Data output hold time
Tth
Trclk Cycle time(100Mbps)
Trclk Cycle time(10Mbps)
-
-
Trch
Trch
Trcl
Trcl
Trs
high time(100Mbps)
high time(10Mbps)
low time(100Mbps)
low time(10Mbps)
data setup time
26
260
26
260
-
Trh
data hold time
10
10
-
-
Trs1
RXER data setup time
61
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
8.0 Package Information
He
E
A
A2 A1
e
pin 1
b
q
SYMBOL
MILIMETER
MIN.
0.05
NOM
MAX
0.15
A1
A2
A
0.1
1.35
1.40
1.45
1.6
b
0.17
13.90
19.90
0.22
14.00
20.00
0.5
0.27
D
14.10
20.10
E
e
Hd
He
L
15.60
21.00
0.45
16.00
22.00
0.60
16.40
23.00
0.75
L1
q
1.00
0°
7°
62
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
Appendix A: Application Note 1
A.1 Using Crystal 25MHz
AX88796
CLKO25M
25MHz
XTALIN
25MHz
Crystal
XTALOUT
33pf
33pf
Note : The capacitors (33pf) may be various depend on the specification of crystal. While designing,
please refer to the suggest circuit provided by crystal supplier.
A.2 Using Oscillator 25MHz
AX88796
CLKO 25M
25MHz
XTALIN
XTALOUT
NC
3.3V Power OSC 25MHz
63
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
Appendix B: Power Consumption Reference Data
The following reference data of power consumption are measured base on prime application, that is AX88796 +
EEPROM, at 3.3V/25 °C room temperature.
Item
Test Conditions
Power save mode ( Power Down register bit set to “1” asserted)
Idel without Link
Idel with 10M Link
Idel with 100M Link
Full traffic with 10Mbps at half-duplex mode
Full traffic with 10Mbps at full-duplex mode
Full traffic with 100Mbps at half-duplex mode
Full traffic with 100Mbps at full-duplex mode
Power save mode ( Power Down register bit set to “1” asserted) no LED drive
Typical Value Units
1
2
3
4
5
6
7
8
9
0
22
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
30
91
48 – 80
48 – 80
88 – 94
88 – 94
0
10 Idel without Link, no LED drive
11 Idel with 10M Link, no LED drive
12 Idel with 100M Link, no LED drive
13 Full traffic with 10Mbps at half-duplex mode, no LED drive
14 Full traffic with 10Mbps at full-duplex mode, no LED drive
15 Full traffic with 100Mbps at half-duplex mode, no LED drive
16 Full traffic with 100Mbps at full-duplex mode, no LED drive
22
25
84
46 – 66
46 – 66
83
83
64
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
Errata of AX88796
1. MII Station Management functions has some defference from previous target
specification.
Description: The target specification is using station management can access both
internal PHY registers and external PHY registers when the PHY address is matched
as describe in section 5.5. Anyway, this version can only access the current selected
PHY’s registers. How do you know which is the selected media or PHY? Please refer
to section 4.1.16 GPO and Control (GPOC) register.
Solution: The defect will not affect single media application that is using embedded
PHY. When using MII interface connects to external media (for example HomePNA)
to come out with combo solution. Care must be taken, be sure which media is the
current selected when you access PHY registers.
2. AX88796 can’t support 68K CPU with byte mode
Solution: Please using word mode for high performance. MC68008 has only 8-bit bus, so
AX88796 can’t support this CPU.
3. When AX88796 transmit a packet and the packet is collided for 16 times. The packet
will be reported as as PTX bit asserted rather than TXE asserted.
Solution: Packet collided 16 times and aborted is normal way, even that is rare happen
in live network, in very heavy traffic. While the upper protocol layer will handle the
situation and cover the packet loss.
65
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
Demonstration Circuit (A) : AX88796 with ISA Bus + HomePNA 1M8 PHY
AX88796 10BASE-T/100BASE-TX & 1M HomePNA Application with NS83851 PHYceiver.
(reference only)(ISA Mode)
SD[0..7]]
SA[0..9]
ISA1
SA[0..9]
SD[0..15]
SD[0..15]
GND
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
GND
RESDRV
+5V
IRQ<9>
-5V
DRQ<2>
-12V
NOWS#
+12V
IOCHK#
D<7>
D<6>
D<5>
D<4>
D<3>
D<2>
D<1>
RESET
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
RDY
AEN
BHE#
5V
BHE#
IORD#
IOWR#
AEN
C60
IORD#
IOWR#
AEN
C59
0.1u
+
47u/16v
DIP 100mil & SMD1206
RESET
RESET
B9
D<0>
CHRDY
AEN
GND
IRQ
RDY
IOIS16#
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
B27
B28
B29
B30
B31
IRQ
RDY
IOIS16#
GND
SMWTC#
SMRDC
LOWC#
LORC#
DAK<3>#
DRQ<3>
DAK<1>#
DRQ<1>
REFRSH#
BCLK
IRQ<7>
IRQ<6>
IRQ<5>
IRQ<4>
IRQ<3>
DAK<2>#
T/C
SA<19>
SA<18>
SA<17>
SA<16>
SA<15>
SA<14>
SA<13>
SA<12>
SA<11>
SA<10
SA<9>
SA<8>
SA<7>
SA<6>
SA<5>
SA<4>
SA<3>
SA<2>
SA<1>
SA<0>
IOWR#
IORD#
3.3V
GND
3.3V
GND
JP2 is setting IRQ
JP2
SA[0..9]
IRQ
IRQ3
IRQ7
IRQ5
IRQ3
1
3
5
7
9
2
4
6
8
10
SA9
SA8
SA7
SA6
SA5
SA4
SA3
SA2
SA1
SA0
IRQ5
IRQ7
IRQ11
IRQ12
10PIN JUMP
BALE
+5V
OSC
GND
5V
C54
C55
0.1u
GND
+
BHE#
D1
D2
D3
D4
D5
D6
D7
D8
C1
C2
C3
C4
C5
C6
C7
C8
47u/16v
DIP 100mil & SMD 1206
M16#
IO16#
SBHE#
LA<23>
LA<22>
LA<21>
LA<20>
LA<19>
LA<18>
LA<17>
MRDC#
MWTC#
D<8>
IOIS16#
IRQ<10>
IRQ<11>
IRQ<12>
IRQ<13>
IRQ<14>
DAK<0>#
DRQ<0>
DAK<5>#
DRQ<5>
DAK<6>#
DRQ<6>
DAK<7>#
DRQ<7>
+5V
IRQ11
IRQ12
SD[8..15]
D9
C9
D10
D11
D12
D13
D14
D15
D16
D17
D18
C10
C11
C12
C13
C14
C15
C16
C17
C18
SD8
SD9
D<9>
SD10
SD11
SD12
SD13
SD14
SD15
D<10>
D<11>
D<12>
D<13>
D<14>
D<15>
5V
C52
MASTER16#
GND
C53
0.1u
GND
+
47u/16v
DIP 100mil & SMD 1206
ISA
16Bit ISA SLOT
U1
OUT
ADJ/GND
3.3V
4
3
2
1
5V
IN
OUT
3.3V
GND
C18
0.1u
C26
0.1u
C17
+
C23
+
47u/16v AMS1117
SOT-223
47u/16v
DIP 100mil & SMD 1206
DIP 100mil & SMD 1206
ASIX ELECTRONIC CORPORATION
Title
ISA BUS
Size
A4
Document Number
796NS3A.SCH
Rev
2.0
Date:
Thursday, April 19, 2001
Sheet
1
of
4
66
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
RXER
RXER
RXDV
COL
CRS
P1
RXDV
COL
CRS
RXCK
RXD0
RXD1
RXD2
RXD3
TXCK
TXD0
TXD1
RXD0
GPI2
RXD1
TXD2
RXD2
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
STROB#
ATFD#
PD0
RXCK
RXD0
RXD1
RXD2
RXD3
TXCK
ERR
PD1
INIT#
PD2
TXD3
RXD3
SLIN#
PD3
TXEN
TXD0
TXD1
TXD2
TXD3
TXEN
TXD0
TXD1
TXD2
TXD3
RXCK
CRS
PD4
PD5
PD6
PD7
ACK
BUSY
PE
SA[0..9]
SD[0..15]
U3
RXD0
RXD1
RXD2
RXD3
RXCK
CRS
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
4
5
6
7
8
95
96
97
98
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SD8
SD9
SD10
SD11
SD12
SD13
SD14
SD15
/BHE
IRQ
/IOIS16
/IORD
/IOWR R/W
RESET
RDY
AEN
/CS
/LDS
PD0
PD1
PD2
PD3
PD4
RXD0
RXD1
RXD2
RXD3
RX_CLK
CRS
BHE#
IORD#
IOWR#
COL
MDC
MDIO
BHE#
IORD#
MDC
MDIO
RXDV
TXCK
TXEN
GPI1
GPI0
IOWR#
AEN
99
PCLK
AEN
PCLK
RESET
9
100
101
102
107
108
109
110
111
112
66
RESET
IREQ
IRQ
PD5
COL
10
11
12
15
42
41
39
38
37
36
35
33
32
31
30
29
26
25
24
23
22
16
123
19
18
3
PD6
PD7
/ACK
BUSY
/STRB
/ATFD
/INIT
COL
RXDV
TXCK
TXEN
TXD0
TXD1
TXD2
TXD3
MDIO
MDC
TPIP
TPIN
RDY
RDY
IOIS16#
TPIP
TPIN
RX_DV
TX_CLK
TX_EN
TXD0
TXD1
TXD2
TXD3
MDIO
MDC
IOIS16#
3.3V
GND
ZVREG
TPOP
TPON
3.3V
GND
ZVREG
TPOP
TPON
SLCT
/SLCTIN
DB-25F
67
R49
R46
10K
10K
*1
/SPP_SET
GPI0
GPI1
GPI2
103
106
113
*6 Use Crystal or Oscillator.
SLCT
PE
/ERR
GPI0/LINK
GPI1/DPX
GPI2/SPD
SD8
SD9
U4
SD10
SD11
SD12
SD13
SD14
SD15
Y1
25MHZ
CLKO25
PCLK
XIN
44
R20
R48
20
XOUT
5
4
XIN
CLKO25M
OUT
XIN
XOUT
3.3V
79
80
8
LCLK/XTALIN
XTALOUT
VCC
GND
R52
2M
BHE#
IRQ
EECS
EESK
EEDI
EEDO
51
50
49
48
25MHZ OSC
/UDS
/IRQ
EECS
10K
C30
33p
C28
33p
C42
0.01u
*2
PPD_SET
EECK
EEDI
EEDO
IOIS16#
IORD#
IOWR#
RESET
RDY
AEN
CS#
ZVREG
TPOP
TPON
92
88
87
ZVREG
TPOP
TPON
2
1
128
/DTACK
/PSEN
TPIP
TPIN
L1
70
71
TPIP
TPIN
3.3V
3.3VD
C20
R5
U2
3.3V
D3
D2
D1
LED
LED
LED
R9
R8
R7
330
330
330
EECS
EESK
EEDI
EEDO
1
2
3
4
8
Link LED
Speed LED
FULL LED
0
CS
SK
DI
VCC
NC
NC
LINK
SPEED
FULL
C19 F.B.
SMD 1206
0.1u
60
61
62
7
6
5
+
+
LINK_LED LINK/ACT_LED
SPEEDLED
ACT_LED FULL/COL_LED
3.3V
C24
0.1u
GND
0.01u
GND
C1
C2
DO
GND
GND
REXTBS
REXT100
REXT10
13
27
40
53
74
83
84
R23
R22
R21
24.9K 1%
2.49K 1%
20.1K 1%
93C56R
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
REXTBS
REXT100
REXT10
4.7uF/16V
SMD 1206
4.7uF/16V
SMD 1206
57
45
46
47
65
BIST
IDDQ
TEST2
TEST1
IDDQ
104
114
126
R25
10K
*3 CPU Type select
3.3VD
C21
C22
0.01u
C33
C7
C6
C25
C5
14
28
34
43
52
54
63
94
CPU1 CPU0 MODE
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
CPU0
CPU1
LEDOP
1
3
58
59
R26
R27
R6
R1
R2
10K
*3
CPU0
CPU1
0.01u
0.01u
0.01u
0.01u
0.01u
0.01u
10K
10K
10K
10K
10K
*3
OFF
OFF
ON
OFF
ON
8051
GND
116
117
118
119
120
*4
*5
*5
*5
MC68K
80186
LED_OP
IO_BASE0
IO_BASE1
IO_BASE2
GPO0
2
4
6
3.3V
OFF
ON
ON
ISA BUS
5
R3
105
115
127
JP1
6PIN JUMP
3.3VO
L2
3.3V
91
*5 IOBASE Select
IOBASE2IOBASE1IOBASE0IO BASE
VDDO
F.B.
C3 SMD 1206
C10
0.1u
C4
C12
86
89
90
C11
+
+
+
+
VSSO
VSSO
VSSO
56
69
73
82
76
VDDA
VDDA
VDDA
VDDA
VDDM
0.001u
0.1u
4.7uF/16V
SMD 1206
4.7uF/16V
SMD 1206
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
ON
200h default
220h
L3
3.3V
3.3VA
L5
OFF
ON
380h
3.3VP
3.3V
C43
78
81
ON
3A0h
C9
0.01u
C34
C32
C31
C27
VDDPD
VSSPD
C14 F.B.
SMD 1206
0.1u
55
68
72
75
85
77
93
F.B.
C36 SMD 1206
+
+
OFF
OFF
ON
OFF
ON
340H
VSSA
VSSA
VSSA
VSSA
VSSA
VSSM
VSSM
C29
0.1u
C35
C37
0.1u
ON
360h
0.01u
0.01u
0.01u
0.01u
C13
C8
ON
OFF
ON
300h
0.001u
GND
4.7uF/16V
SMD 1206
4.7uF/16V
SMD 1206
ON
ON
320h
4.7uF/16V
SMD 1206
4.7uF/16V
SMD 1206
AX88796
LQFP
*1 Pin 67 SPP_SET#
Pin 67 SPP_SET#
=
=
0
:
1 : Select MII interface.(Default)
Select printer interface.
*2 Pin 50 PPD_SET
Pin 50 PPD_SET
=
=
0
1
: Internal PHY in normal mode.(default)
: Internal PHY in power down mode.(match up CIS)
*4 Pin 116 I_OP
Pin 116 I_OP
=
=
0
1
:
:
LNK/ACT
LNK
& FULL/COL LED Display be used.
ACT LED Display be used.
ASIX ELECTRONICS CORPORATION
AX88796
&
Title
Size
A3
Document Number
796NS3A1.SCH
Rev
2.0
Date:
Thursday, April 19, 2001
Sheet
2
of
4
67
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
RESET
RESET
RXER
RXDV
COL
RXER
RXDV
COL
CRS
CRS
RXCK
RXD0
RXD1
RXD2
RXD3
TXCK
RXCK
RXD0
RXD1
RXD2
RXD3
TXCK
TIP
RING
TIP
RING
U5
TXD3
TXD2
TXD1
TXD0
TXEN
TXCLK
36
35
34
33
32
31
TXD3
TXD2
TXD1
TXD0/TXD
TX_EN
TX_CLK
TXEN
TXD0
TXD1
TXD2
TXD3
TXEN
TXD0
TXD1
TXD2
TXD3
TXCK
R28
R12
20
20
RXD3
RXD2
RXD1
RXD0
RXDV
RXCLK
23
24
25
26
27
28
RXD3/PHYAD0
RXD2/CMDDIS#
RXD1/HI_POWER_EN#
RXD0/RXD/LOW_SPEED_EN#
RX_DV/GPSI_SEL#
RX_CLK
MDC
MDIO
MDC
MDIO
PCLK
RXCK
3.3V
PCLK
Set PHY address to 00001.
7
TIP
TIP
3.3V
GND
COL
CRS
37
38
3.3V
GND
COL/MDIO_INT_EN#
CRS/PIN_INTRP_EN#
8
RING
RING
3.3V
R18
4.7K
RXD3
R11
4.7K
R13
4.7K
R15
4.7K
R17
4.7K
R19
4.7K
MDIO
MDC
21
22
MDIO
MDC
ACTLED
COLLED
SPDLED
PWRLED
RBIAS
4
RBIAS
PCLK
45
46
X1
X2
R33
9.31K
1%
GND
3.3V
3.3V
19
29
IO_VDD1
IO_VDD2
C41
0.01u
C39
+
C40
0.1u
C15
C38
39
CORE_VDD
0.01u
0.01u
GND
3.3V
LED4
4.7uF/16V
SMD 1206
L6
3.3VA1
3.3VA2
48
5
11
R14
330
R10
330
R16
330
D5
D4
D6
LED
ANA_VDD1
ANA_VDD2
ANA_VDD3
17
18
COLLED
ACTLED
LED_COL/PHYAD2
LED_ACT/PHYAD1
LED5
LED6
LED
LED
16
15
SPDLED
PWRLED
C50
0.1u
C49
0.1u
C48
LED_SPEED/PHYAD3
LED_POWER/PHYAD4
F.B.
SMD 1206
0.01u
44
RESET#
RESET#
GND
3.3V
20
30
IO_GND1
IO_GND2
L4
40
41
CORE_GND
CORE_SUB(0V)
C44
0.1u
C46
C16
0.1u
47
3
6
10
1
2
12
13
14
42
43
F.B.
SMD 1206
ANA_GND1
ANA_GND2
ANA_GND3
ANA_GND4
SUB_GND1
SUB_GND2
SUB_GND3
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0.01u
GND
9
3.3V
DP83851C
TQFP
R37
4.7K
R29
2K
RESET#
ASIX ELECTRONICS CORPORATION
DP83851C
R30
2K
Title
RESET
Q1
2SC2412K
Size
A4
Document Number
796NS3A2.SCH
Rev
2.0
Date:
Thursday, April 19, 2001
Sheet
3
of
4
68
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
R34
0
ZVREG
C47
C61
+
R35
49.9
4.7uF/16V
SMD 1206
0.01u
R36
49.9
T2
14
16
15
12
10
11
J3
CT
TD+
TD-
CT
TX+
TX-
TPOP
TPON
TPOP
TPON
1
2
TPIP
TPIN
1
2
3
7
6
5
TPIP
TPIN
RD+
RD-
CT
RX+
RX-
CT
3
6
4
5
R43
49.9
R42
49.9
16ST8515
*7 1CT : 1CT
7
8
R44
75
R39
75
R41
75
R40
75
RJ45N
C57
0.1u
C56
C58
0.001u
0.001u
C51
0.01u/2KV
SMD 1206
GND_CH
C62
0.1u
3.3V
3.3V
GND_CH
C45
0.1u
*8 RECEIVE 1CT : 1CT
TRANSMIT 1CT : 1CT
R31
49.9
R32
49.9
J1
1
2
3
4
5
6
NC
A1
TIP
RING
A2
T1
TIP
RING
1
2
3
10
9
TIP
RING
+
-
TIP
RING
GND
NC
HR002
RJ11-S
J2
GND
GND
1
2
3
4
5
6
NC
A1
TIP
RING
A2
R38
0
NC
RJ11-S
ASIX ELECTRONIC CO.
Title
RJ45 & RJ11
Size
A4
Document Number
796NS3A3.SCH
Rev
2.0
Date:
Thursday, April 19, 2001
Sheet
4
of
4
69
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
THIS PAGE LEFT BLANK
70
ASIX ELECTRONICS CORPORATION
AX88796 L
3-in-1 Local Bus Fast Ethernet Controller
Date
Revision
V. 1.7
Comment
24/01/02
1
2
3
4
Remove Tally counter at MAC register list
Modify RDY timing diagram in ISA and 186 mode
Remove BOS bit in DCR register
Include LED current sink value
4F, NO.8, HSIN ANN RD., SCIENCE-BASED
INDUSTRIAL PARK, HSINCHU, TAIWAN, R.O.C.
TEL: 886-3-5799500
FAX: 886-3-5799558
Email: support@asix.com.tw
Web: http://www.asix.com.tw
71
ASIX ELECTRONICS CORPORATION
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