AX88850 [ASIX]
100BASE-TX/FX Repeater Controller; 100BASE - TX / FX中继控制器
| 型号： | AX88850 |
| 厂家： | 
ASIX ELECTRONICS CORPORATION |
| 描述： | 100BASE-TX/FX Repeater Controller |
| 文件： | 总39页 (文件大小：419K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AX88850
100BASE-TX/FX Repeater Controller
ASIX AX88850
100BASE-TX/FX
Repeater Controller
Data Sheet(11/03/’97)
DOCUMENT NO. : AX850D2.DOC
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
AX88850
PRELIMINARY
CONTENTS
1.0 AX88850 OVERVIEW......................................................................................................................................... 5
1.1 GENERAL DESCRIPTION ....................................................................................................................................... 5
1.2 FEATURES............................................................................................................................................................ 6
1.3 BLOCK DIAGRAM................................................................................................................................................. 7
1.4 PIN CONNECTION DIAGRAM FOR AX88851 (16MII + 2MII MODE) .................................................................... 8
1.5 PIN CONNECTION DIAGRAM FOR AX88852 (8MII + 2MII MODE) ...................................................................... 9
1.6 PIN CONNECTION DIAGRAM FOR AX88853 (8PCS + 2MII MODE) ................................................................... 10
1.7 PIN CONNECTION DIAGRAM FOR AX88854 (MANAGEMENT MODE).................................................................. 11
2.0 PIN DESCRIPTION........................................................................................................................................... 12
2.1A PCS INTERFACE............................................................................................................................................. 12
2.1B MII INTERFACE (SHARE BUS MII GROUP 0 PORT & MII GROUP 1 PORT)........................................................ 13
2.2 MII INTERFACE ( TWO INDIVIDUAL MII PORTS )............................................................................................... 14
2.3 STATION MANAGEMENT INTERFACE.................................................................................................................. 15
2.4 MANAGEMENT INFORMATION BASE (MIB) INTERFACE..................................................................................... 15
2.5 EXPANSION BUS INTERFACE.............................................................................................................................. 16
2.7 MISCELLANEOUS ............................................................................................................................................... 19
3.0 FUNCTIONAL DESCRIPTION...................................................................................................................... 20
3.1 PCS INTERFACE LOGIC ...................................................................................................................................... 20
3.2 CARRIER INTEGRITY MONITOR STATE MACHINE ( AX88853 PCS MODE ONLY ).............................................. 20
3.3 REPEATER STATE MACHINE .............................................................................................................................. 20
3.4 JABBER STATE MACHINE................................................................................................................................... 21
3.5 PARTITION STATE MACHINE.............................................................................................................................. 21
3.6 EXPANSION LOGIC(CASCADE INTERFACE)......................................................................................................... 22
3.7 MANAGEMENT LOGIC........................................................................................................................................ 22
3.8 MANAGEMENT COUNTERS................................................................................................................................. 23
3.9 STATION MANAGEMENT ACCESS INTERFACE .................................................................................................... 23
3.10 RID RECEIVE-TRANSMIT INTERFACE(DAISY CHAIN LOGIC)........................................................................... 23
3.11 LED INTERFACE.............................................................................................................................................. 25
3.11.1 LED Status Driver wave-form for AX88851............................................................................................ 25
3.11.2 LED Status Driver wave-form for AX88852............................................................................................ 26
3.11.3 LED Status Driver wave-form for AX88853............................................................................................ 26
3.11.4 LED Status Driver wave-form for AX88854............................................................................................ 27
3.12 POWER ON CONFIGURATION(INITIAL SETTING) ............................................................................................... 27
4.0 REGISTERS........................................................................................................................................................ 28
4.1 PAGE 0 REGISTER MAP..................................................................................................................................... 28
4.2 PAGE 1 REGISTER MAP..................................................................................................................................... 29
4.3 PAGE 2 REGISTER MAP..................................................................................................................................... 29
4.4 PAGE 3 REGISTER MAP..................................................................................................................................... 29
4.5 CONFIGURATION REGISTER (CONFIG)............................................................................................................. 30
4.6 PAGE REGISTER (PAGE) ................................................................................................................................... 30
4.7 PARTITION STATUS REGISTER (PARTITION) ................................................................................................... 31
4.8 JABBER STATUS REGISTER (JABBER) .............................................................................................................. 31
4.9 ADMINISTRATION REGISTER (ADMIN)............................................................................................................. 31
4.10 DEVICE ID REGISTER (DEVICEID) ................................................................................................................ 32
4.11 SILICON REVISION REGISTER........................................................................................................................... 32
4.12 PORT MANAGEMENT COUNTER REGISTERS ..................................................................................................... 33
4.12.1 Short Event Counter Registers................................................................................................................. 33
4.12.2 Late Event Counter Registers .................................................................................................................. 33
4.12.3 Collision Counter Registers..................................................................................................................... 33
4.12.4 Auto-Partition Counter Registers ............................................................................................................ 33
4.12.5 False Carrier Counter Registers.............................................................................................................. 33
2
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
5.0 ELECTRICAL SPECIFICATION AND TIMING ......................................................................................... 34
5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 34
5.2 GENERAL OPERATION CONDITIONS ................................................................................................................... 34
5.3 DC CHARACTERISTICS ...................................................................................................................................... 34
5.4 AC SPECIFICATIONS........................................................................................................................................... 35
5.4.1 MII Interface Timing Tx & Rx................................................................................................................... 35
5.4.2 Station Management ................................................................................................................................. 36
5.4.3 PCS Interface Timing................................................................................................................................. 37
5.4.4 LED DISPLAY ........................................................................................................................................... 37
5.4.5 LED Display After Reset........................................................................................................................... 38
5.4.6 Repeater ID Daisy Chain........................................................................................................................... 38
5.4.7 Expansion Bus............................................................................................................................................ 39
6.0 PACKAGE INFORMATION............................................................................................................................ 40
3
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
FIGURES
FIG - 1 CHIP BLOCK DIAGRAM (PCS MODE CONFIGURATION -- 8 PCS + 2 MII).....................................................................7
FIG - 2 CHIP BLOCK DIAGRAM(MII MODE CONFIGURATION -- 16 MII + 2 MII) .....................................................................7
FIG - 3 PIN CONNECTION DIAGRAM FOR 16MII MODE............................................................................................................8
FIG - 4 PIN CONNECTION DIAGRAM FOR 8MII MODE..............................................................................................................9
FIG - 5 PIN CONNECTION DIAGRAM FOR 8PCS MODE..........................................................................................................10
FIG - 6 PIN CONNECTION DIAGRAM FOR MANAGEMENT MODE.............................................................................................11
4
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.0 AX88850 Overview
The AX88850 series 100Mbps Repeater Controllers are designed for both low cost
dumb HUB and high performance intelligent HUB applications. The AX88850 series
product support up-to ten 100Mbps links with its 8 PCS (Physical coding sub-layer , also
called Symbol Interface) interfaces and 2 dedicated MII interfaces or supports up-to eighteen
100Mbps links with 2 shared 8 ports MII interfaces and 2 dedicated MII interfaces.
Maximum up-to 144 ports can be constructed when using expansion bus cascades 8
AX88850s. The AX88850 is designed base on IEEE 802.3u clause 27 “ Repeater for
100Mb/s base-band networks” . It is fully compatible with IEEE 802.3u standard.
1.1 General Description
The AX88850 Repeater Controller is a subset of a repeater set containing all the
repeater-specific components and functions, exclusive of PHY components and functions.
The AX88850 family has two kind of interfaces to connect to PHY devices. There are
Physical coding sub-layer (PCS) interface and Media Independent Interface (MII).
The AX88850 supports 8 PCS ports interface or 2 shared bus (8 ports/per bus) MII
interfaces, 2 dedicated MII ports interface, an expansion port interface, a management
information base IC interface, a repeater ID daisy chain interface, a serial register interface
and LED display interface.
5
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.2 Features
·
·
·
IEEE 802.3u repeater compatible
Supports 10 or 18 network connections optional configuration.
8 PCS interfaces direct interface to PHY chip with PCS interface ( ie.LUC3X04,
KS8761, QSI6611, NWK914 ) to save user cost
·
·
·
16 MII interfaces to double the network connections.
2 dedicated MII interfaces can also support 100BASE-T4/FX PHY interfaces
The 2 dedicated MII interfaces can also easily connect to MII interface of 100BASE
MAC controller for network management purpose or other bridging devices.
Up-to 8 repeater chips can be cascaded for large HUB application
Low latency design supports Class II repeater implementation with large port number.
All ports can be separately isolated or partitioned in response to fault condition
Separate jabber and partition state machines for each port
·
·
·
·
·
Separate carrier integrity monitor state machines for each port to protect network from
some transient fault conditions (AX88853 PCS mode only)
·
·
·
·
Management interface for AX88856 (MIB IC) allows all repeater MIBs to be maintained
Large per-port management counters to reduce CPU overhead
External pins setup or automatic daisy chain channel setup repeater ID.
Per-port LED display for Jabber, Partition, Link/Activity. Global utilization and
collision (%) presentation.
·
Power on LED diagnosis. All the LED display will follow the “ON-OFF-ON-OFF-
Normal” operation procedure during/after power on reset.
·
·
Dedicated collision LED display
208-pin PQFP
The AX88850 Family has the following members:
AX88851
AX88852
AX88853
AX88854
AX88856
16 shared MII ports + 2 dedicated MII ports
8 shared MII ports + 2 dedicated MII ports
8 PCS (Symbol) Interface ports + 2 dedicated MII ports
AX88851 + AX88853 + management function
MIB co-processor for intelligent Hub applications
Function availability list
Parts Number 16MII + 2MII 8MII + 2MII
8PCS + 2MII Management I/F
4
AX88851
AX88852
AX88853
AX88854
4
4
4
4
4
4
6
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.3 Block Diagram
sy m
I/F
P er p o rt J a b b er ctl,
4 B /5 B
a u to -p a rtitio n S M
&
R eg iste rs
M IB I/F
Q -P H Y
C o d in g /
D ec o d in g
P er p o rt C o llisio n
P a rtitio n c o u n ter s.
,
&
S rr a m b ler/
D escr a m b le r
C a sca d e
A rb itr a tio n
L o g ic
R ep e a te r S ta te
M a ch in e
(P o rt 1
P o rt 7
-
M U X
)
Q -P H Y
M II
R ec o n c ilia -
tio n
P H Y
E la stic ity B u ffe r
C o llisio n H a n d lin g L o g ic
I/F
P o rt 8
P o rt 9
-
P H Y
Fig - 1 Chip Block Diagram (PCS mode configuration -- 8 PCS + 2 MII)
M II
I/F
M II
P er port Jabb er ctl,
auto-p artition SM &
Q -PH Y
Q -PH Y
interface
R econcilia-
tion layer
R egisters
M IB I/F
P er port C ollision ,
P artition counters.
P ort 0 -
P ort 7
M II
I/F
C ascade
A rbitration
L ogic
M II
interface
R econcilia-
tion layer
Q -PH Y
Q -PH Y
R epeater S tate
M ach in e
M U X
P ort 10 -
P ort 17
M II
P ort 8
P H Y
P H Y
E lasticity B uffer
C ollision H an dling L ogic
M II
I/F
P ort 9
Fig - 2 Chip Block Diagram(MII mode configuration -- 16 MII + 2 MII)
7
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.4 Pin Connection Diagram for AX88851 (16MII + 2MII mode)
IRD_CK
/IRD_V
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
RX_ER<1>
VDD
104
103
102
101
100
99
/IRD_ER
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
N C
N C
VDD
98
97
9 6
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
M1_RXEN7
M1_RXEN6
M1_RXEN5
M1_RXEN4
M1_TXEN7
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
N C
N C
N C
N C
ASIX
N C
N C
N C
AX 88851
VDD1
VSS1
M0_TXEN0
M0_TXEN1
M0_TXEN2
M0_TXEN3
M0_RXEN0
M0_CRS0
M0_CRS1
M0_CRS2
M0_CRS3
N C
N C
N C
VSS
M0_RXEN1
M0_RXEN2
M0_RXEN3
M0_TXEN4
M0_TXEN5
M0_CRS4
M0_CRS5
M0_CRS6
M0_CRS7
N C
VDD
N C
N C
(16 MII Mode)
N C
N C
N C
N C
N C
M1_TXEN6
M1_TXEN5
M1_TXEN4
M1_RXEN3
M1_RXEN2
VSS
M1_RXEN1
N C
N C
M1_CRS7
M1_CRS6
M1_CRS5
M1_CRS4
Fig - 3 Pin Connection Diagram for 16MII Mode
8
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.5 Pin Connection Diagram for AX88852 (8MII + 2MII mode)
IRD_CK
/IRD_V
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
RX_ER<1>
VDD
104
103
102
101
100
99
/IRD_ER
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
TXD<2>
TXD<1>
TXD<0>
VSS
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
N C
N C
VDD
98
97
9 6
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
TX_ER
COL
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
N C
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
VDD1
VSS1
N C
N C
N C
ASIX
N C
N C
N C
AX 88852
N C
VDD1
VSS1
N C
N C
N C
M0_TXEN0
M0_TXEN1
M0_TXEN2
M0_TXEN3
M0_RXEN0
M0_CRS0
M0_CRS1
M0_CRS2
M0_CRS3
N C
N C
N C
VSS
M0_RXEN1
M0_RXEN2
M0_RXEN3
N C
VDD
N C
N C
(8 MII Mode)
N C
N C
N C
N C
N C
N C
N C
N C
M1_RXEN3
M1_RXEN2
VSS
M1_RXEN1
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
N C
Fig - 4 Pin Connection Diagram for 8MII Mode
9
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.6 Pin Connection Diagram for AX88853 (8PCS + 2MII mode)
IRD_CK
/IRD_V
/IRD_ER
VSS
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
RX_ER<1>
VDD
104
103
102
101
100
99
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
N C
N C
VDD
98
97
9 6
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
GEP<0>
GEP<1>
GEP<2>
GEP<3>
VSS
RDATA<0><0>
RDATA<0><1>
ASIX
RDATA<0><2>
RDATA<0><3>
RDATA<0><4>
RSCLK<0>
VDD1
VSS1
TDATA<7><4>
TDATA<7><3>
TDATA<7><2>
TDATA<7><1>
AX88853
RSD<0>
VDD1
VSS1
TDATA<0><0>
TDATA<0><1>
TDATA<0><2>
TDATA<0><3>
TDATA<0><4>
TDATA<7><0>
VDD
RSD<7>
RSCLK<7>
(PCS Mode)
RDATA<7><4>
RDATA<7><3>
RDATA<7><2>
RDATA<7><1>
RDATA<7><0>
RDATA<1><0>
RDATA<1><1>
RDATA<1><2>
RDATA<1><3>
RDATA<1><4>
RSCLK<1>
TDATA<6><4>
TDATA<6><3>
TDATA<6><2>
TDATA<6><1>
TDATA<6><0>
VSS
RSD<6>
RSCLK<6>
RDATA<6><4>
RDATA<6><3>
RDATA<6><2>
RDATA<6><1>
RDATA<6><0>
RSD<1>
VSS
TDATA<1><0>
TDATA<1><1>
TDATA<1><2>
TDATA<1><3>
TDATA<1><4>
RDATA<2><0>
RDATA<2><1>
RDATA<2><2>
RDATA<2><3>
RDATA<2><4>
Fig - 5 Pin Connection Diagram for 8PCS Mode
10
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
1.7 Pin Connection Diagram for AX88854 (Management mode)
IRD_CK
/IRD_V
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
RX_ER<1>
VDD
104
103
102
101
100
99
/IRD_ER
RXD<1><3>
RXD<1><2>
RXD<1><1>
RXD<1><0>
TX_EN<1>
TXD<3>
VSS
IRD<0>
IRD<1>
IRD<2>
IRD<3>
/RST
TEST
VSS
LCLK
N C
N C
VDD
GEP<0>
GEP<1>
GEP<2>
98
97
9 6
TXD<2>
TXD<1>
TXD<0>
VSS
TX_ER
COL
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
CRS<0>
RX_DV<0>
RX_CLK<0>
RX_ER<0>
RXD<0><3>
RXD<0><2>
RXD<0><1>
RXD<0><0>
TX_EN<0>
OPT0
GEP<3>
VSS
RDATA<0><0>
RDATA<0><1>
RDATA<0><2>
RDATA<0><3>
RDATA<0><4>
RSCLK<0>
ASIX
VDD1
VSS1
TDATA<7><4>
TDATA<7><3>
TDATA<7><2>
TDATA<7><1>
TDATA<7><0>
VDD
RSD<7>
RSCLK<7>
RDATA<7><4>
RDATA<7><3>
RDATA<7><2>
RSD<0>
VDD1
VSS1
AX 88854
M1_RXEN7
M1_RXEN6
M1_RXEN5
M1_RXEN4
M1_TXEN7
TDATA<0><0>
TDATA<0><1>
TDATA<0><2>
TDATA<0><3>
TDATA<0><4>
M0_TXEN0
M0_TXEN1
M0_TXEN2
M0_TXEN3
M0_RXEN0
M0_CRS0
(Management Mode)
RDATA<1><0>
RDATA<1><1>
M0_CRS1
RDATA<1><2>
RDATA<1><3>
RDATA<1><4>
RSCLK<1>
193 M0_CRS2
RDATA<7><1>
RDATA<7><0>
194 M0_CRS3
195
196
197
198
M1_TXEN6
M1_TXEN5
M1_TXEN4
TDATA<6><4>
TDATA<6><3>
TDATA<6><2>
TDATA<6><1>
TDATA<6><0>
VSS
RSD<6>
RSCLK<6>
RDATA<6><4>
RDATA<6><3>
RDATA<6><2>
RDATA<6><1>
RDATA<6><0>
RSD<1>
VSS
TDATA<1><0>
TDATA<1><1>
199
M1_RXEN3 62
M0_RXEN1
M1_RXEN2
61
200
201
202
203
204
205
206
207
208
M0_RXEN2
M0_RXEN3
M0_TXEN4
M0_TXEN5
TDATA<1><2>
TDATA<1><3>
TDATA<1><4>
RDATA<2><0>
RDATA<2><1>
RDATA<2><2>
RDATA<2><3>
RDATA<2><4>
60
M1_RXEN1
59
58
57
56
M0_CRS4
M0_CRS5
M0_CRS6
M0_CRS7
M1_CRS7
M1_CRS6 55
M1_CRS5 54
M1_CRS4
53
Fig - 6 Pin Connection Diagram for Management Mode
11
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
2.0 Pin Description
2.1A PCS interface
Signal Name Type Pin No.
Description
RDATA[0][4:0]
RDATA[1][4:0]
RDATA[2][4:0]
RDATA[3][4:0]
RDATA[4][4:0]
I/PU 181-177, Receive Symbol Data : Data is input synchronously with the rising edge of
I/PD* 195-191 RSCLK
I/PD* 208-204
I/PD*
14-10
I/PD* 30,29,26-
24
RDATA[5][4:0]
RDATA[6][4:0]
RDATA[7][4:0]
RSCLK[0]
RSCLK[1]
RSCLK[2]
I/PD*
I/PD*
I/PU
I
44-40
57-53
70-66
182
196
2
Receive Symbol Clock : This 25Mhz input signal is phase-locked to the
incoming signal at PHY. RSCLK is used to clock in received data from the
RDATA[4:0] data bus.
I
I
RSCLK[3]
I
15
RSCLK[4]
I
31
RSCLK[5]
I
45
RSCLK[6]
I
58
RSCLK[7]
I
71
RSD[0]
RSD[1]
RSD[2]
RSD[3]
RSD[4]
RSD[5]
RSD[6]
RSD[7]
I /PD
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
I/PD
183
197
3
16
32
46
59
72
Receive Signal Detect : This asynchronous input signal indicates that the
receive signal is above the detection threshold and will be used for link test
state machine.
TDATA[0][4:0]
TDATA[1][4:0]
TDATA[2][4:0]
TDATA[3][4:0]
TDATA[4][4:0]
TDATA[5][4:0]
TDATA[6][4:0]
TDATA[7][4:0]
O/L 190-186 Transmit Symbol Data : These signals are 4B/5B encoded transmit data
O/L 203-199 symbol, driven at the rising edge of local 25Mhz clock. LCLK
O/L
8-4
O/H** 22-18
O/H** 38-34
O/L
O/L
O/L
51-47
65-61
78-74
* RDATA[1:6][4] are pull up.
** TDATA[3][4] and TDATA[4][4] drive capability are MH
Note : “Type” has the following attributes
I : Input
O : Output
I/O : Bi-direction
PU : Pull Up
PD : Pull Down
H : Driving High Current 16mA
MH : Driving Middle High Current 12mA
ML : Driving Middle Low Current 8mA
L : Driving Low Current 4mA
12
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
2.1B MII interface (share bus MII group 0 port & MII group 1 port)
M0 -- MII group 0 ; M1 -- MII group 1
Signal Name Type Pin No.
Description
M0_TX_ER
M1_TX_ER
M0_TXD[3:0]
M1_TXD[3:0]
O/ML
O/ML
O/H
22
38
Transmit Error : TX_ER is transition synchronously with respect to the rising
edge of TX_CLK . Asserted high when a code violation is request to be send
21-18 Transmit Data : TXD[3:0] is transition synchronously with respect to the
37-34 rising edge of TX_CLK. For each TX_CLK period in which TX_EN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
O/H
M0_TX_EN[7:0]
M1_TX_EN[7:0]
O/L
4,3,203, Transmit Enable : TX_EN is transition synchronously with respect to the
202, rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles
189-186 on TXD [3:0] for transmission.
O/L 74,65-63,
50-47
M0_RXD[3:0]
M1_RXD[3:0]
M0_RX_ER
M1_RX_ER
I/PU
13-10 Receive Data : RXD [3:0] is driven by the PHY synchronously with respect to
I/PU 29,26-24 RX_CLK.
I/PD
I/PD
14
30
Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is
asserted for one or more RX_CLK periods to indicate to the port that an error
has detected.
M0_RX_CLK
M1_RX_CLK
I
I
15
31
Receive Clock : RX_CLK is a continuous clock that provides the timing
reference for the transfer of the RX_DV,RXD [3:0] and RX_ER signals from
the PHY to the MII port of the repeater.
M0_RX_DV
M1_RX_DV
M0_CRS[7:0]
I/PD
I/PD
16
32
Receive Data Valid : RX_DV is driven by the PHY synchronously with
respect to RX_CLK. Asserted high when valid data is present on RXD [3:1].
I/PD 207-204, Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either
194-191 the transmit or receive medium is non-idle.
M1_CRS[7:0]
I/PD
56-53,
43-40
M0_RX_EN[7:0]
O/L
8-4, Receive Enable : Assert high to the respective PHY chip to enable its receive
201-199, data.
190
M1_RX_EN[7:0]
O/L
78-75,
62,61,59,
51
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ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
2.2 MII interface ( two individual MII ports )
Signal Name Type Pin No.
TX_ER
(share)
Description
O/ML
92
Transmit Error : TX_ER is transition synchronously with respect to the rising
edge of TX_CLK . Asserted high when a code violation is request to be send
TXD[3:0]
(share)
O/ML
97-94 Transmit Data : TXD[3:0] is transition synchronously with respect to the
rising edge of TX_CLK. For each TX_CLK period in which TX_EN is
asserted, TXD[3:0] are accepted for transmission by the PHY.
TX_EN[0]
TX_EN[1]
O/L
O/L
82
98
Transmit Enable : TX_EN is transition synchronously with respect to the
rising edge of TX_CLK. TX_EN indicates that the port is presenting nibbles
on TXD [3:0] for transmission.
RXD[0][3:0]
RXD[1][3:0]
RX_ER[0]
I/PU
I/PU
I/PD
I/PD
86-83 Receive Data : RXD [3:0] is driven by the PHY synchronously with respect to
102-99 RX_CLK.
87
Receive Error : RX_ER ,is driven by PHY and synchronous to RX_CLK, is
asserted for one or more RX_CLK periods to indicate to the port that an error
has detected.
RX_ER[1]
104
RX_CLK[0]
RX_CLK[1]
I
I
88
105
Receive Clock : RX_CLK is a continuous clock that provides the timing
reference for the transfer of the RX_DV,RXD [3:0] and RX_ER signals from
the PHY to the MII port of the repeater.
RX_DV[0]
RX_DV[1]
CRS[0]
CRS[1]
COL
I/PD
I/PD
I/PD
I/PD
O/ML
89
106
90
107
91
Receive Data Valid : RX_DV is driven by the PHY synchronously with
respect to RX_CLK. Asserted high when valid data is present on RXD [3:1].
Carrier Sense : Asynchronous signal CRS is asserted by the PHY when either
the transmit or receive medium is non-idle.
Collision Signal :This pin indicates collision(s) , that occurred at the collision
domain of the hub, to MII interface devices. Both the MII port use this signal
commonly.
(share)
OPT0
OPT1
I/PU
I/PU
81
108
Option for external device type : Default ‘high’ is for PHY type device.
Otherwise, ‘low’ for MAC type device.
14
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AX88850
PRELIMINARY
2.3 Station Management Interface
Signal Name Type Pin No.
Description
SMDC
I
116
Station Management Data Clock : The timing reference for MDIO. All data
transfers on MDIO are synchronized to the rising edge of this clock. MDC is
limited to a maximum frequency of 2.5MHz.
SMDIO
I/O/L
/PU
115
Station Management Data Input / Output : Serial data input/output transfers
from/to the internal registers or PHYs . The transfer protocol conforms to the
IEEE 802.3u MII specification.
/SMDV
SMDIR
I/PU
O/L
114
110
Station Management Data Valid : Asserted when a valid read/write command
is present.
Station Management Data Direction : Direction signal for an external bi-
directional buffer on the MDIO signal.
0 = MDIO data flows into the AX88850
1 = MDIO data flows out of the AX88850
Defaults to 0 when no register access is present.
BSMDC
O/L
112
111
Buffered Station Management Data Clock : Buffered MDC signal. Allow
more devices to be chained on the MII serial bus.
Buffered Station Management Data Input /Output : Buffered MDIO signal.
When the “PHY_access” bit in the CONFIG register is set High, the MDIO
signal is passed through to BMDIO for accessing the physical device chips.
BSMDIO
I/O/L
/PU
2.4 Management Information Base (MIB) Interface
Signal Name Type Pin No.
Description
MD
I/O/Z
/MH
/PU
155
Management Data : Outputs management information for the AX88856 MIB
chip. This signal carries with RID_CH signal and port number of the in-
coming packet and is synchronous to IRD_CK signal.
Repeated Packet Ready : Repeated packet data ready to copy to MIB chip
indicator.
MTX_RDY
O/L
109
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AX88850
PRELIMINARY
2.5 Expansion Bus Interface
Signal Name Type Pin No.
Description
IRD[3:0]
/IRD_ER
/IRD_V
I/O/Z 164-161 INTER REPEATER DATA : Nibble data input/output. Transfer data from
/MH
/PU
the “active” AX88850 to all other “inactive” AX88850s. The bus-master of
the IRD bus is determined by IR_VECT bus arbitration.
I/O/Z
/MH
/PU
I/O/Z
/MH
/PU
159
158
INTER REPEATER DATA ERROR: This signal reflect the RX_ER status
of the active port across the inter repeater bus. Used to track receive errors
from the PHY in real time.
INTER REPEATER DATA VALID : This signal reflect the RX_DV status
of the active port across the inter repeater bus. Used to frame good packets.
IRD_CK
I/O/Z
/MH
O/L
157
154
INTER REPEATER CLOCK VALID : All inter repeater signals are
synchronized to the rising edge of this clock.
INTER REPEATER DATA IN/OUT DIRECTION : This pin indicates the
direction of data for external transceiver.
IRD_ODIR
“High” = IRD[3:0], /IRD_ER, /IRD_V , IRD_CK are Output.
“Low” = IRD[3:0], /IRD_ER, /IRD_V , IRD_CK are Input.
/IR_ACTO
[7:0]
I/O/OC 152-145 INTER REPEATER ACTIVITY IN/OUT: Then the local repeater activity
/H
appearance, the signal of the related RID (Repeater ID) will be asserted and as
a output pin. All other pins serve as input pins but except the collision
conditions. When collision occurred all of the signal of related (RID-1) pins
will served as outputs and will active during local collision period. The
exception case is when RID = 0, then (RID-1) is replaced with (RID+1)=1.
/IR_ACTI[7:0]
I/PU 143-136 INTER REPEATER ACTIVITY IN: These pins perform the same function
as /IR_ACTO[7:0] when they serve as input function. Then the
/IR_ACTO[7:0] insert external buffers the input function must be replaced
with /IR_ACTI [7:0].
or
The /IR_ACTI[7:0] also serve as power-on configuration input:
RID[4:0]
/IR_ACTI[4:0]
I/PU 140-136 Repeater Identification Number Parallel In RID[4:0]: When power on reset
these pin as inputs to setup the repeater ID of the chip. RID[2:0] indicate the
repeater ID from 0 to 7. RID[4:3] defines the group code in the cascade
system and must keep difference with PHY ID address definition.
/DIS_DAISY
/IR_ACTI[5]
I/PU
I/PU
141
142
Disable RID Daisy-chain Input. No matter what kind of data input from
DAISY_IN pin ,the repeater ID will never be changed from DAIST_IN.
/TO_ID_CLR
/IR_ACTI[6]
Time Out to Clear repeater ID : Within the time out period, if no daisy chain
repeater ID input. The repeater ID will be clear to RID=0 . Otherwise, the
repeater ID will remain the previous value ( power on configured value ,
previous daisy chain reconfigured value or the configuration value written via
station management port).The tome out period is about 4 to 5 second.
/IR_ACT_EN
/IR_ACTI[7]
I/PU
143
/IR_ACTI[7:0] pins function is enable when IR_ACT_EN is pulled “low”
when power on. Otherwise , it is disable.
16
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
2.6 LED Display
Signal Name Type Pin No.
Description
LED[7:0]
O/L 125-122, LED Display Information : Those signals indicate each port‘s Partition,
120-117 Jabber, Link/Activity, Utilization % (global), Collision % (global) in
sequence. For detail , see the LED timing specification
The Utilization % display define as following :
Group0 [ U4 :U0 ]
Utilization %
LED4 LED3 LED2 LED1 LED0
0
1
5
15
30
60
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Group1 [ UU4 :UU0 ]
Utilization %
LED4 LED3 LED2 LED1 LED0
0
2
10
20
40
80
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
The Collision % display define as following :
Group0 [ C4 :C0 ]
Collision %
LED4 LED3 LED2 LED1 LED0
0
1
2
5
10
15
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
Group1 [ CC4 :CC0 ]
Collision %
LED4 LED3 LED2 LED1 LED0
0
4
8
20
30
60
1
1
1
1
1
0
1
1
1
1
0
0
1
1
1
0
0
0
1
1
0
0
0
0
1
0
0
0
0
0
LED_SYN
/COLLED
O/L
126
127
LED status synchronous signal : The signal is a LED_CK period width signal
and repeated every 16 cycle. When high indicate the next cycle on the
LED[7:0] bus show the Partition status of port 8 to 0 respectively.
Collision LED Display : When Collision occur, the signal will
be “LOW” about 52.4 ms.
O/MH
17
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AX88850
PRELIMINARY
2.7 Miscellaneous
Signal Name Type Pin No.
Description
LCLK or
TX_CLK
/RST
I
168
Local Clock : Must be run at 25Mhz . Used for transmit data to PHY devices,
I
165
135
Reset : The chip is reset when this signal is asserted Low.
RST_DLY
O/L
Reset Delay : The signal is active high when reset and delay /RST signal
about 2 LCLK cycle. It is useful for power on configuration setup control of
/IR_ACTI[7:0].
DAISY_IN
I/PU
133
Repeater Identification Number Daisy-Chain In : This pin is a daisy chain
serial input for Repeater ID. A state machine always monitor the input if a
correct data (RID) present at the pin, the (RID+1) will be written to RID
register and override the power on setup RID for the chip.
DAISY_OUT
TEST
O/L
134
166
Repeater Identification Number Daisy-Chain Out : This pin is periodically
shift out the RID of itself to the next chained chip to inform that this ID has
already been occupied. The RID is shift out periodically every about 200us.
Test Pin : The pin is just for test mode setting purpose only. Must be pull low
when normal operation. When in test mode , GEP pins will be force to test
input signals.
I/PD
GEP[3:0]
MEDIA
I/O/L 175-172 General Purpose I/O Pins : Those pins just for system application usage. I.e.
/PU
for output control or input status report.
When reset the default function is for inputs.
I/PD
130
Media selection :
External pull-down for AX88853 with 4.7K ohm resister.
External pull-up for AX88851, AX88852 and AX88854 with 4.7K ohm
resister.
OPTION
VDD
I/PU
I
129
Option : Option for repeater state machine. User must pull this pin up.
1,17,27, POWER : +5V +/-5%
33,52,73,
80,103,
128,132,
156,171,
184
VSS
I
9,23,28, POWER: 0V
39,60,79,
93,113,
121,131,
144,153,
160,167,
176,185,
198
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ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
3.0 Functional Description
3.1 PCS interface logic
The PCS logic performs PCS / MII receiving / transmitting interface. When it receives, first deciphers the signals from
RDATA<4:0>, then do symbol alignment after detecting /J/K/ codes, then data is aligned to do 5B/4B decoding.
When it transmits, first do 4B/5B encoding to convert MII signals to PCS signals, then enciphers and send to
TDATA<4:0>.
When RSD is high from low, then link fail counter will count for 330u sec, then the port can receive packet normally.
During 330u sec that link fail counter counts, then receiving packet will be ignored. Cipher / No-cipher is selected by
station management access logic.
3.2 Carrier Integrity Monitor State Machine ( AX88853 PCS mode only )
For 100BASE-X systems, it is necessary that the repeater set protect the network from some transient fault conditions
that would disrupt network communications. Potential likely causes of such conditions are DTE and repeater power-
up and power-down transients, cable disconnects, and faulty wiring.
The AX88853 support CIM state machine with self-interrupt capability to prevent a segment’s spurious carrier
activity from reaching the repeater unit and hence propagating through the network.
3.3 Repeater State Machine
The repeater state machine is used to control repeater behavior, generates right signal in corresponding states. The
repeater state machine is in Idle state when there is no carrier . When there is carrier , the repeater state machine
goes to Data Forwarding State to ensure correct data forwarding. If collision happens anytime, The repeater state
machine detects collision then send jam pattern until collision ceases.
idle State
The idle state happens when these conditions exists:
a. /RST is low.
b. Reset emitted by station management access logic(RST_RSM).
c. There is no any carrier in M0_CRS[7:0], M1_CRS[7:0], and CRS{1:0] in MII mode. Or
receive IDLE code in PCS mode. If in cascade application, repeater receive no inter repeater
active signal.
In this state,M0_RXEN[7:0],M1_RXEN[7:0],M0_TXEN[7:0],M1_TXEN[7:0] are all low in MII
mode.
Data Forwarding State
When there is only one carrier in M0_CRS[7:0], M1_CRS[7:0]or CRS[0], CRS[1] in MII mode, or
only one of eight ports receives /J/K/ codes in PCS mode ,or only one of IR_ACTO[7:0] become low,
The repeater state machine stores receiving packet and transmits to all other ports. Exception for
a. The port is jabbered.
b. The port is partitioned.
c. There exists collision.
In this state, only one of M0_RXEN[7:0] and M1_RXEN[7:0] is high, or M0_RXEN[7:0] or
M1_RXEN[7:0] are all low because either packet is from two dedicated MII port or from inter-repeater
cascade interface in MII mode.
The repeater send packet from receiving port to all ports exclusive of the receiving that is
M0_TXEN[7:0] and M1_TXEN[7:0] all becomes high, and one may be low if that port is the receiving
port in MII mode. The repeater forwards data to TDATA[7:0] except for the receiving RDATA port in
PCS mode.
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AX88850
PRELIMINARY
Collision State
The Collision State happens when these conditions exists:
a. There are two or more signals high among M0_CRS[7:0],M1_CRS[7:0],CRS[1:0]. Or receive
collision messages from /IR_ACTO[7:0] in MII mode.
b. At least two ports of PCS ports receive /J/K/ code group or receive collision message from
/IR_ACTO[7:0] in PCS mode.
c. Only one carrier exists but RXDV still low exceeds 5 clock cycles. The repeater sends collision
pattern to all ports, that is, M0_TXEN[7:0] and M1_TXEN[7:0] all become high during collision
state.
3.4 Jabber State Machine
To prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber timer. If a
reception exceeds this duration(64K bit times for AX88850), the jabber condition will be detected. In this condition,
repeater unit will disable receive and transmit packets for the jabbered port and the other ports remain the normal
operation.
When the carrier is no longer detected for the jabbered port or reset the repeater, the jabber function will be clear and
re-enable reception and transmission.
3.5 Partition State Machine
The partition state machine is used to protect network from be upset by a port suffering continuous collision, each port
uses a partition state machine to detect and prevent this condition. When a port is suffering from continuous 32 or
64 times of collisions by CCLimits. Then it goes to Partition State. The port entering Partition State will be released
until a packet without collision more than 512 bit times or after power-on reset.
Partition function is enabled by default, and CCLimits is 64 by default. Enable/Disable partition function
(DIS_PART) and option of CCLimits to be 64 or 32 (COL_LIMIT32) are selected by station management access
logic.
20
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
3.6 Expansion Logic(Cascade Interface)
The expansion logic is used to stack numerous repeaters. The expansion logic can be divided into two types:
Expansion Logic with Buffer (maximum mode
In this mode, use /IR_ACTO[7:0] and /IR_ACTI[7:0] to cascade repeaters. Buffers are used both in
/IR_ACTO[7:0] and /IR_ACTI[7:0]. This mode is supposed to cascade repeaters on difference boards via cables.
There is a configuration bit /IR_ACT_EN to decide cascade signals are judges by /IR_ACTI[7:0](/IR_ACT_EN
= 0) or /IR_ACTO[7:0](/IR_ACT_EN = 1).
Expansion Logic without Buffer (minimum mode)
In this mode, use /IR_ACTO[7:0] to cascade repeaters. Just connect /IR_ACTO[7:0] without using buffer in this
part. This mode is supposed to cascade repeaters on the same board.
/IR_ACTO<7:0>
RPTR_ID<2:0>
Idle
FFh
FFh
FFh
FFh
FFh
FFh
FFh
FFh
Active
FEh
FDh
FBh
F7h
EFh
DFh
BFh
7Fh
Collision
FBh
FCh
F9h
F3h
E7h
CFh
9Fh
3Fh
0
1
2
3
4
5
6
7
In this table:
a. All /IR_ACTO[7:0] will be in open-drain state when repeater chip is idle. These signals are all high via
external pull high resister.
b. One signal of /IR_ACTO[7:0] is low in data forwarding state corresponding to different RPTR_ID[2:0].
c. Two signals of /IR_ACTO[7:0] are low in collision state corresponding to different RPTR_ID[2:0].
3.7 Management Logic
AX88850 provides the required management information associated with a packet for management chip which
statistics processed on a per packet basis. Transmit ready signal TX_RDY is used as a framing signal for management
data MD. Then management chip uses this data to determine the source of the current packet. MD data is synchronized
to the rising edge of IRD_CK. When collision occur, MD will be tri-state and becomes invalid.
MD frame format
idle
1
start bit
0
data0
PID[0]
data1
PID[1]
data2
PID[2]
data3
PID[3]
data4
PID[4]
data5
RID_CH
data6
PARITY
Notes:
a. PID[4:0] is the number of the receiving port.
b. RID_CH indicates change in RID.
c. PARITY = 1 when sum of 1‘s among PID[4:0] and RID_CH is even
PARITY = xnor (PID[4],PID[3],PID[2],PID[1],PID[0],RID_CH)
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AX88850
PRELIMINARY
3.8 Management Counters
There are four management counters in each port. These 16-bit-wide management counters keep track of the
following events:
Collision Event Counter
It indicates the number of times that collision occurrences on a port.
Partition Event Counter
It indicates the number of times that a port has been partition.
Short Event Counter
It indicates the number of packets that is shorter than 76 BT.
Late Event Counter
It indicates the number of collision occurrences time after 512 BT when carrier presents.
Fault Carrier Event Counter (AX88853 only)
It indicates the number of times that fault carrier occurrences on a port.
These counters can be read out by MIB serial access interface and will be clear after read operation.
3.9 Station Management Access Interface
The AX88850 provides 128 registers held in 4 pages of 32(Page 0 ~ 3 Register).These registers are 16 bits wide. Only
one register of one page can be access at the same time through the MII serial management bus. After power on
reset, Page 0 Register is the default setting. Change the value of PAGE REGISTER which exists in all pages, then
switches to any page. For example: Page 3 Register can be accessed by writing 03h to the PAGE REGISTER.
AX88850 can thus be managed through SMDC and SMDIO pins. The SMDC clock with maximum 2.5M Hz is used
to sample data train on SMDIO. The interface follows the serial management protocol defined by IEEE 802.3u clause
22.
Management frame format
PREAM START OPCODE DEV_AD REG_AD TA
DATA
IDLE
Z
READ
1.......1
01
10
AAAAA RRRRR
Z0 DDDDDDDDDDDDDDDD
WRITE 1.......1
01
01
AAAAA RRRRR
10 DDDDDDDDDDDDDDDD
Z
For the protocol to work, all serial data must be “synchronized” to incoming data. To ensure data locked, a preamble
of 32 consecutive 1‘s present before the start code, then the receive logic know the beginning of the data frame.
With the setting of PHY_ACCESS = 1(stored in CONFIGURATION REGISTER), the target access device may be
physical layer devices. In this mode, SMDIO is gated to BSMDIO. SMDIO and BSMDIO must turn on in the
appropriate direction for read/write access. In the cascade system, only one repeater chip has the set of
PHY_ACCESS at a time to avoid contention problems.
3.10 RID Receive-Transmit Interface(Daisy Chain Logic)
In the cascade system, repeater ID of each chip will be re-arranged by serial in/out daisy chain logic. The DAISY_IN
pin always monitor RID of the previous chained chip, and the value of (RID+1) will override the original RID of the
current chip. Then the DAISY_OUT pin will periodically (about 200us) send out the exact RID of current chip to
inform the next chained chip. By this way, each repeater chip in 8 AX88850 hub (maximum application) will keep
unique ID of itself. The RID is used in inter repeater bus arbitration and uniquely identify station management
accesses.
Note that only RID[2:0] can be changed and RID[4:3] must be the same value for all repeaters in the cascade system.
In this way, repeater ID won‘t be confused with PHY device ID during station management access.
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AX88850
PRELIMINARY
DAISY_IN/OUT frame format
idle
1
start bit
0
data0
RID[0]
data1
RID[1]
data2
RID[2]
data3
PARITY
Notes: PARITY = 1 when sum of 1‘s in RID[2:0] is even
There are two flag : /DIS_DAISY and /TO_ID_CLR which control daisy-chain access. If disable daisy-chain input
(/DIS_DAISY = 0), the RID of current chip can‘t be override and don‘t care the present data on DAISY_IN. If no
daisy-chain input, the RID of current chip can be clear to 0 during time out period with the setting of /TO_ID_CLR =
0. The timer is done about 4sec.
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AX88850
PRELIMINARY
3.11 LED Interface
AX88850 provides per-port LED status indication for partition, jabber, link/activity and support rate-based LED for
global utilization (%) and global collision frequency (%). Detail function is described on previous pin description
(LED interface). LED[7:0] are all active low.
3.11.1 LED Status Driver wave-form for AX88851
LED_SYN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 ~ D15
D0
D1
D2
D3
P0
J0
J1
J2
J3
J4
J5
J6
J7
A0
A1
A2
A3
A4
A5
A6
A7
C4
U4
A8
A9
J8
C0 P10
J10
A10 RID0 CC0
A11 RID1 CC1
A12 RID2 CC2
A13 RID3 CC3
A14 RID4 UU0
no useful phase
P0
J0
J1
J2
J3
J4
J5
J6
J7
A0
A1
A2
A3
A4
A5
A6
A7
C4
U4
A8
A9
J8
LED[0]
LED[1]
LED[2]
LED[3]
LED[4]
LED[5]
LED[6]
P1
P2
P3
P4
P5
P6
P7
C1 P11
J11
J12
J13
J14
J15
J16
J17
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
P1
P2
P3
P4
P5
P6
P7
C2
P12
P13
P14
P15
P16
P17
C3
U0
U1
U2
U3
J9
A15
"0" UU1
J9
P8
P9
A16 CC4
A17 UU4
UU2
UU3
P8
P9
LED[7]
Note 1 :
a. P17~0 indicates partition status for each port
b. J17~0 indicates jabber status for each port
c. L17~0 indicates link status for each port
d. A17~0 indicates activity status for each port
e. RID4~0 is the ID number of repeater chip
f.
The LED display support two estimations:C4~0 and CC4~0 which indicate global collision rate for
each 104.8ms sampling period. Users can choose any one presentation.
g. The LED display support two estimations:U4~0 and UU4~0 which indicate global utilization rate for
each 104.8ms sampling period. Users can choose any one presentation.
Note 2 : Reference port map as following table (Using per port Carrier Sense / Receive Signal Detect to identify port
number).
AX88851
AX88852
AX88853
AX88854
Port[7:0] == M0_CRS[7:0]
Port[3:0] == M0_CRS[3:0]
Port[7:0] == RSD[7:0]
Port[9:8] == CRS[1:0]
Port[9:8] == CRS[1:0]
Port[9:8] == CRS[1:0]
Port[17:10] == M1_CRS[7:0]
Port[7:4] == M1_CRS[3:0]
Reference to AX88851/AX88853 depended on MEDIA setting.
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AX88850
3.11.2 LED Status Driver wave-form for AX88852
PRELIMINARY
LED_SYN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 ~ D15
D0
D1
D2
D3
P0
J0
A0
C4
C0
P4
J4
A4
RID0 CC0
RID1 CC1
RID2 CC2
no useful phase
P0
J0
A0
C4
LED[0]
LED[1]
LED[2]
LED[3]
LED[4]
LED[5]
LED[6]
LED[7]
P1
P2
P3
J1
J2
J3
A1
A2
A3
U4
A8
A9
J8
C1
C2
C3
U0
U1
U2
U3
P5
P6
P7
J5
J6
J7
A5
A6
A7
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
P1
P2
P3
J1
J2
J3
A1
A2
A3
U4
A8
A9
J8
UU1
CC3
RID4 UU0
J9
"0"
CC4
UU4
UU1
UU2
UU3
J9
P8
P9
P8
P9
3.11.3 LED Status Driver wave-form for AX88853
LED_SYN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 ~ D15
D0
D1
D2
D3
L0/
A0
L0/
A0
P0
J0
C4
C0
RID0 CC0
RID1 CC1
RID2 CC2
UU1 CC3
RID4 UU0
no useful phase
P0
P1
P2
P3
P4
P5
P6
P7
J0
J1
J2
J3
J4
J5
J6
J7
C4
U4
A8
A9
J8
LED[0]
LED[1]
LED[2]
LED[3]
LED[4]
LED[5]
LED[6]
LED[7]
L1/
A1
L1/
A1
P1
P2
P3
P4
P5
P6
P7
J1
J2
J3
J4
J5
J6
J7
U4
A8
A9
J8
C1
C2
C3
U0
U1
U2
U3
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
L2/
A2
L2/
A2
L3/
A3
L3/
A3
L4/
A4
L4/
A4
L5/
A5
L5/
A5
J9
"0"
CC4
UU4
UU1
UU2
UU3
J9
L6/
A6
L6/
A6
P8
P9
P8
P9
L7/
A7
L7/
A7
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AX88850
PRELIMINARY
3.11.4 LED Status Driver wave-form for AX88854
LED_SYN
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 ~ D15
D0
D1
D2
D3
L0/
A0
L0/
A0
P0
J0
C4
C0
P10
J10
A10 RID0 CC0
no useful phase
P0
J0
C4
LED[0]
LED[1]
LED[2]
LED[3]
LED[4]
LED[5]
LED[6]
LED[7]
L1/
A1
L1/
A1
P1
P2
P3
P4
P5
P6
P7
J1
J2
J3
J4
J5
J6
J7
U4
C1
C2
C3
U0
U1
U2
U3
P11
P12
P13
P14
P15
P16
P17
J11
J12
J13
J14
J15
J16
J17
A11 RID1 CC1
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
no useful phase
P1
P2
P3
P4
P5
P6
P7
J1
J2
J3
J4
J5
J6
J7
U4
L2/
A2
L8/
A8
L2/
A2
L8/
A8
A12 RID2 CC2
UU1
L3/
A3
L9/
A9
L3/
A3
L9/
A9
A13
CC3
L4/
A4
L4/
A4
J8
J9
P8
P9
A14 RID4 UU0
J8
J9
P8
P9
L5/
A5
L5/
A5
A15
A16
A17
"0"
CC4
UU4
UU1
UU2
UU3
L6/
A6
L6/
A6
L7/
A7
L7/
A7
3.12 Power on Configuration(Initial Setting)
During power-on reset, /IR_ACTI[[7:0] are used as some configuration setting. These include inter repeater active
input pin enable/disable (/IR_ACT_EN); time out to clear repeater ID(/TO_ID_CLR); daisy-chain input
disable/enable (/DIS_DAISY); and repeater ID(RPTR_ID[4:0]). Detail function is described on previous pin
description (expansion bus interface). After reset, these setting are stored in DEVICE ID REGISTER which can be
modified by station management write commands.
Default setting
/IR_ACT_EN pull high
/TO_ID_CLR pull high
/DIS_DAISY pull high
Function
DISABLE inter repeater active in
DISABLE time out to clear repeater ID
ENABLE daisy-chain input
RPTR_ID = 11111
RPTR_ID
pull high
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AX88850
PRELIMINARY
4.0 REGISTERS
The AX88850 has 128 16-bit registers which are separated into four pages with each page 32 words. At
power-on or reset , the default value is page 0 registers. The register page can be changed by writing to the register
address 1 on all the four pages .
4.1 Page 0 Register MAP
Address (hex)
Name
CONFIG
Access
Description
0
1
2
3
4
5
R/W Set AX88850 configuration
PAGE
R/W Selects register from page 0 to page 3.
RO Indicates Auto-Partitioning status.(port0 - port9)
RO Indicates Jabber status. (port0 - port9)
R/W Port enable / disable, administration control/status(port0 - port9)
R/W Accesses 1) the AX88850 ID number configured externally on the
RID[4:0] pins. 2) the last receiving port number.
The device number of AX88850 may be overwritten after it has been
latched at the end of reset.
PARTITION
JABBER
ADMIN
DEVICE-ID
6
7
Reserved
Reserved
8
9
P8-SE
P8-LE
R/W Port 8 : 16-bit ShortEvent Counter (dedicated MII port 0)
R/W Port 8 : 16-bit LateEvent Counter
A
B
C
D
P8-COL
P8-PART
P9-SE
R/W Port 8 : 16-bit Collision Counter
R/W Port 8 : 16-bit Auto-partition Counter
R/W Port 9 : 16-bit ShortEvent Counter (dedicated MII port 1)
R/W Port 9 : 16-bit LateEvent Counter
P9-LE
E
F
10-13
P9-COL
P9-PART
P0-SE …
P0-PART
P1-SE …
P1-PART
P2-SE …
P2-PART
P3-SE …
P3-PART
R/W Port 9 : 16-bit Collision Counter
R/W Port 9 : 16-bit Auto-partition Counter
R/W Port 0 management counters ( as per ports 8,9 as above )
14-17
18-1B
1C-1F
R/W Port 1 management counters ( as per ports 8,9 as above )
R/W Port 2 management counters ( as per ports 8,9 as above )
R/W Port 3 management counters ( as per ports 8,9 as above )
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AX88850
PRELIMINARY
4.2 Page 1 Register MAP
Address (hex)
Name
CONFIG
Access
Description
0
1
2
R/W Set AX88850 configuration ( same as page 0 )
PAGE
R/W Selects register from page 0 to page 3. ( same as page 1 )
RO Indicates Auto-Partitioning status.(port10 - port17)
RO Indicates Jabber status. (port10 - port17)
PARTITION
JABBER
ADMIN
SI_REV
3
4
5
R/W Port enable / disable, administration control/status(port10 - port17)
RO Silicon revision code.
6-7
8-F
Reserved
P0-FCRS …
P7-FCRS
R/W Port 0 false carrier counters (address 8) to
Port 7 false carrier counters (address F)
Those counters are valid just for PCS mode port 0 to port 7.
As for MII mode , the false carrier counter will be available on PHY, but
some PHY chip manufacturer not support those functions.
R/W Port 4 management counters ( as per ports 8,9 as above )
10-13
14-17
18-1B
1C-1F
P4-SE …
P4-PART
P5-SE …
P5-PART
P6-SE …
P6-PART
P7-SE …
P7-PART
R/W Port 5 management counters ( as per ports 8,9 as above )
R/W Port 6 management counters ( as per ports 8,9 as above )
R/W Port 7 management counters ( as per ports 8,9 as above )
4.3 Page 2 Register MAP
Address (hex)
Name
CONFIG
Access
Description
0
1
R/W Set AX88850 configuration
R/W Selects register from page 0 to page 3.
Reserved
PAGE
2-F
10-13
P10-SE …
P10-PART
P11-SE …
P11-PART
P12-SE …
P12-PART
P13-SE …
P13-PART
R/W Port 10 management counters ( as per ports 8,9 as above )
14-17
18-1B
1C-1F
R/W Port 11 management counters ( as per ports 8,9 as above )
R/W Port 12 management counters ( as per ports 8,9 as above )
R/W Port 13 management counters ( as per ports 8,9 as above )
4.4 Page 3 Register MAP
Address (hex)
Name
CONFIG
Access
Description
0
1
R/W Set AX88850 configuration ( same as page 0 )
R/W Selects register from page 0 to page 3.. ( same as page 1 )
Reserved
PAGE
2-F
10-13
P14-SE …
P14-PART
P15-SE …
P15-PART
P16-SE …
P16-PART
P17-SE …
P17-PART
R/W Port 14 management counters ( as per ports 8,9 as above )
14-17
18-1B
1C-1F
R/W Port 15 management counters ( as per ports 8,9 as above )
R/W Port 16 management counters ( as per ports 8,9 as above )
R/W Port 17 management counters ( as per ports 8,9 as above )
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PRELIMINARY
4.5 Configuration Register (CONFIG)
Page 0 to Page 3 Address 0h
Bit
Bit Name
Access
Bit Description
D15-D8
Reserved
Written as “0” for future compatibility concern.
Undefined by read.
D7
D6
RST_FLAG
RID_CH
RO Reset Flag : The bit is set when power on reset and is clear after read
CONFIG register.
RO Repeater ID Changed : The bit is set when Daisy-Chain RID input
override the current RID or after power on reset. When read CONFIG
register will clear the bit.
D5
D4
DIS_CIPHER
MGTEN
R/W Disable Cipher Function : Then set the bit at PCS mode, the 5bit symbol
scramble and descrambler function are disable. Default is enable.
R/W Management Enable : This bit enable all the management counters.
0 : Management Counters disabled. (default)
1 : Management Counters enabled.
D3
COL_LIMIT32
R/W Collision limit : This bit configures the collision limit for Auto-
Partitioning.
0 : Consecutive Collision limit set to 64 (default). A port will
be partitioned on the 65th consecutive collision.
1 : Consecutive Collision limit set to 32 . A port will
be partitioned on the 33rd consecutive collision.
R/W Disable Auto-Partition : Set this bit disable the Auto-Partition
algorithm.
0 : Auto-Partition is not disabled (default)
1 : Auto-Partition is disabled .
R/W PHY access enable : This bit enable to access PHY register via MII serial
protocol.
0 : PHY access disabled (default)
1 : PHY access enabled .
R/W Reset Repeater State Machines : Setting the bit holds the RSM in reset.
The management event flags and counters are unaffected by this bit.
Setting this bit while a reception is in progress may truncate the packet.
0 : AX88850 in normal operation (default)
D2
D1
D0
DIS_PART
PHY_ACCESS
RST_RSM
1 : AX88850 held in reset .
4.6 Page Register (PAGE)
Page 0 to Page 3 Address 1h
Bit
Bit Name
Access
Bit Description
D15-D8
GEP[3:0]
R/W D11-D8 : GEP I/O control. Default = 0h for input mode. Otherwise, =1h,
enable output.
D15-D12 : GEP Data . Default = 0h.
When write, D15-D12 value present to GEP[3:0] if enabled.
When read, D15-D12 reflect the GEP[3:0] value.
Written as “0” for future compatibility concern.
undefined by read.
D7-D2
D1-D0
Reserved
PAGE[1:0]
R/W Those bits setting the register page to be accessed.
PAGE[1:0]
PAGE
0h
1h
2h
3h
0
1
2
3
(default)
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AX88850
PRELIMINARY
4.7 Partition Status Register (PARTITION)
Page 0 Address 2h
Bit
Bit Name
Reserved
PART[9: 0]
Access
Bit Description
D15-D10
D9-D0
undefined when read.
RO The respective port‘s PART bit is set to “1” when Partitioning is sensed
on that port. After reset, these bits are cleared to “0”.
Page 1 Address 2h
Bit
Bit Name
Access
Bit Description
D15-D8
D7-D0
Reserved
PART[17: 10]
undefined when read.
RO The respective port‘s PART bit is set to “1” when Partitioning is sensed
on that port. After reset, these bits are cleared to “0”.
4.8 Jabber Status Register (JABBER)
Page 0 Address 3h
Bit
Bit Name
Reserved
JAB[9: 0]
Access
Bit Description
D15-D10
D9-D0
undefined when read.
RO The respective port‘s JAB bit is set to “1” when Jabber condition is
detected on that port. After reset, these bits are cleared to “0”.
Page 1 Address 3h
Bit
Bit Name
Access
Bit Description
D15-D8
D7-D0
Reserved
JAB[17: 10]
undefined when read.
RO The respective port‘s JAB bit is set to “1” when Jabber condition is
detected on that port. After reset, these bits are cleared to “0”.
4.9 Administration Register (ADMIN)
Page 0 Address 4h
Bit
Bit Name
Access
Bit Description
Written as “0” for future compatibility concern.
undefined by read.
D15-D10
Reserved
D9-D0
ADMIN[9: 0]
R/W Administration Disable : Setting these bits to “0” enable the respective
port (TX and RX). Writing a 1 to any bit will disable that port. After reset,
these bits default to “0” ( all ports enable ). Note that port enable/disable
action will occur at the next network idle period.
Page 1 Address 4h
Bit
Bit Name
Access
Bit Description
Written as “0” for future compatibility concern.
undefined by read.
D15-D8
Reserved
D7-D0
ADMIN[17: 10] R/W Administration Disable : Setting these bits to “0” enable the respective
port (TX and RX). Writing a 1 to any bit will disable that port. After reset,
these bits default to “0” ( all ports enable ). Note that port enable/disable
action will occur at the next network idle period.
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AX88850
PRELIMINARY
4.10 Device ID Register (DEVICEID)
Page 0 Address 5h
Bit
D15-D13
D12-D8
D7
Bit Name
Temp
PORT_NUM
/IR_ACT_EN
Access
Bit Description
R/W Temporary Registers : reserved for system programer used.
*R/W Port Number : These bit indicate the last or current receiving port number.
*R/W Inter Repeater Active Input Pin Enable : This bit active low to enable
/IR_ACTI[7:0] pin as inter-repeater carrier sense detection input.
Otherwise, /IR_ACTI[7:0] pins is disable and only perform power-on
configuration inputs.
D6
/TO_ID_CLR
R/W Time Out to Clear repeater ID : Within the time out period, if no daisy
chain repeater ID input. The repeater ID will be clear to RID=0 .
Otherwise, the repeater ID will remain the previous value ( power on
configured value or previous daisy chain reconfigured value).The tome
out period is about 4 to 5 second.
D5
/DIS_DAISY
RPTR_ID
R/W Disable RID Daisy-chain Input: No matter what kind of data input from
DAISY_IN pin the RPTR_ID can’t be override.
D4-D0
R/W Repeater ID : At the rising edge of /RST , the value of RID[4:0] are
latched in this register as D[4:0]. The setting of RID[2:0]can be override
according to the data from serial daisy-chain DAISY_IN pin input except
/DIS_DAISY is configured to “low” .
Note that in system application, the maximum of 8 devices can be
cascade. Therefore only RID[2:0] can be variation and the RID[4:3] must
be keep the same value in the same system and avoid conflicted with PHY
device ID.
* Note : Host can’t override these signals.
4.11 Silicon Revision Register
Page 1 Address 5h
Bit
Bit Name
Access
Bit Description
D15-D0
SI_REV[15:0]
RO Silicon Reversion : Currently reads all 1‘s
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PRELIMINARY
4.12 Port Management Counter Registers
Each of the 18 ports of the AX88850 has a set of 4 event counters whose values can be read or pre-set (written)
through the Port Management Counter Registers. When PCS (symbol) mode is selected, there is a set of false carrier
counter / per port build-in on the chip. As for MII mode , the false carrier counter will be available on PHY, note that
some PHY chip manufacturer not support those functions.
4.12.1 Short Event Counter Registers
Per port (“n” =port number) counters that indicate the number of Carrier Events that were active for less than the
ShortEventMaxTime, which is defined as between 74 and 82 (76 nominal) bit times.
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_SE[15:0]
R/W P“n”_SE[15:0]
4.12.2 Late Event Counter Registers
Per port (“n”= port number) counters that indicate the number of collision that occurred after the
LateEventThreshold, , which is defined as between 480 and 565 (512 nominal) bit times. Both the Late Event and
collisions will be incremented when this event occurs.
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_LE[15:0]
R/W P“n”_LE[15:0]
4.12.3 Collision Counter Registers
Per port (“n”= port number) counters that indicate the number of collisions (COL asserted) .
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_CO[15:0]
R/W P“n”_CO[15:0]
4.12.4 Auto-Partition Counter Registers
Per port (“n”= port number) counters that indicate the number of times the port was auto-partitioned.
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_PART[15: R/W P“n”_PART[15:0]
0]
4.12.5 False Carrier Counter Registers
Per port (“n”= port number) counters that indicate the number of times the port was false carrier occurred.
Those counters are valid just for PCS mode port 0 to port 7. As for MII mode , the false carrier counter will be
available on PHY, but some PHY chip manufacturer not support those functions.
Bit
Bit Name
Access
Bit Description
D15-D0
P“n”_FCRS[15: R/W P“n”_FCRS[15:0]
0]
32
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
5.0 ELECTRICAL SPECIFICATION AND TIMING
5.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
°C
°C
V
V
V
Operating Temperature
Storage Temperature
Supply Voltage
Input Voltage
Output Voltage
Ta
Ts
Vcc
Vin
0
-55
-0.5
+70
+150
+7
Vss-0.5
Vss-0.5
-55
Vdd+0.5
Vdd+0.5
+250
Vout
Tl
Lead Temperature (soldering 10 seconds maximum)
°C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device.
Exposure to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability
5.2 General Operation Conditions
Description
SYM
Min
+4.75
Max
+70
+5.25
Units
°C
V
Operating Temperature
Supply Voltage
Ta
Vdd
0
5.3 DC Characteristics
(Vdd=4.75V to 5.25V, Vss=0V, Ta=0°C to 70°C)
Description
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current 1 (Note 1)
Input Leakage Current 2 (Note 2)
Output Leakage Current
SYM
Min
Vss-0.5
2
Max
Units
V
V
V
V
uA
uA
uA
Vil
0.8
Vih
Vol
Voh
Iil1
Iil1
Iol
Vdd+0.5
0.4
2.4
10
500
10
Note :
1. All the input pins without pull low or pull high.
2. Those pins had been pull low or pull high.
33
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
5.4 AC specifications
5.4.1 MII Interface Timing Tx & Rx
T0
T1
LCLK
T2
T2
T3
TX_EN
(MTX_RDY)
T3
TX_ER
TXD
Symbol
T0
Description
Local Clock Cycle Time
Local Clock High Time
TX_EN or MTX_RDY Delay from LCLK High
TX_ER or TXD Delay from LCLK High
Min
39.996
Typ.
Max
40.004
26
19
19
Units
ns
ns
ns
ns
40
20
14
14
T1
T2
T3
14
4
4
T4
T5
RX_CLK
CRS
T6
T7
RXE
T8
RXDV
T9
RXD
RXER
34
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
Symbol
T4
Description
Min
39.996
14
Typ.
40
20
Max
40.004
26
Units
ns
RX_CLK Clock Cycle Time
RX_CLK Clock High Time
T5
ns
T6
CRS to RXE Assertion Delay
20
ns
T7
T8
T9
CRS to RXE De-assertion Delay
CRS to RXDV Delay Requirement
RXD or RXDV setup to RX_CLK rise time
120
40
10
200
160
-
ns
ns
ns
5.4.2 Station Management
T1
T2
SMDC
T3 T4
T5
SMDIO
Write
Write
T6
T7
/SMDV
SMDIR
Read
Write
T8
BSMDC
BSMDIO
Symbol
Description
Min
400
40
10
10
Typ.
Max
-
-
-
-
50
-
-
Units
ns
ns
ns
ns
ns
ns
ns
ns
T1
T2
T3
T4
T5
T6
T7
T8
SMDC Period
SMDC High Time
SMDIO Setup Time to SMDC High(Write)
SMDIO Hold Time to SMDC High(Write)
SMDIO Valid from SMDC High(Read)
/SMDV Setup Time to SMDC High
/SMDV Hold Time to SMDC High
BSMDIO Buffer Delay Time
10
10
20
35
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
5.4.3 PCS Interface Timing
TX
LCLK
T0
TDATA
RX
T1
T2
RSCLK
RDATA
T3
T4
Symbol
T0
Description
Min
Typ.
Max
35
40.004
26
-
-
Units
ns
ns
ns
ns
ns
TDATA Valid From LCLK High
RSCLK Clock Cycle Time
RSCLK Clock High Time
RDATA Setup Time
12
T1
T2
T3
T4
39.996
14
40
20
13
10
RDATA Hold Time
5.4.4 LED DISPLAY
LCLK
T1
T2
LED[7:0
D15
D0
D1
D2
D3
D4
D15
D0
T3 T4
LED-SYN
T5
Symbol
Description
LED Valid from LCLK Low
LED Data Width
LED_SYN Valid from LCLK Low
LED-SYN Pulse Width
LED-SYN Cycle Time
Min
7
Typ.
Max
24
Units
ns
ns
ns
ns
T1
T2
T3
T4
T5
40
6
13
40
640
ns
36
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
5.4.5 LED Display After Reset
/Reset
T1
T2
T2
T2 T3
LED[7:0]
T4
LED_SYN
…………………………………
………………
Symbol
Description
Min
1000
Typ.
Max
Units
ns
ms
T1
T2
T3
Repeater reset time
LED Blink Time After Reset
LED Dark Time Before Normal Display
838.4
419.2
ms
5.4.6 Repeater ID Daisy Chain
T1
T2 T2
Daisy-Out
ID0 ID1 ID2
ID0 ID1 ID2
ID0 ID1 ID2
T3
Daisy-In
ID0 ID1 ID2
Symbol
Description
Min
Typ.
204.8
12.8
3.8
Max
Units
us
us
T1
T2
T3
Daisy Chain One Burst period
Start Bit Period or Data Width
Daisy Chain Data In Time-out *
s
Note : Daisy-Chain Data-In Time-out stands for no input data (always high level) for the specific time.
37
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
5.4.7 Expansion Bus
CRS
T1
T2
IRD-ODIR
IRD_CK
IRD[3:0]
/IRD_ER
/IRD_V
MD
T3
T5
T4
T6
ID0
T7
ID1 ID2
T8
Symbol
T1
Description
Min
-
160
10
10
5
5
3
3
Max
42
240
-
-
-
-
13
13
Units
ns
ns
ns
ns
ns
ns
ns
ns
CRS Assertion to IRD-ODIR Assertion
CRS De-Assertion to IRD-ODIR De-Assertion
IRD[3:0] Setup Time to IRD-CK High
/IRD_ER Setup Time to IRD-CK High
/IRD_V Setup Time to IRD-CK High
/IRD_V Hold Time from IRD-CK High
MD Setup Time to IRD-CK High
T2
T3
T4
T5
T6
T7
T8
MD Hold Time from IRD-CK High
38
ASIX ELECTRONICS CORPORATION
AX88850
PRELIMINARY
6.0 PACKAGE INFORMATION
He
A2 A1
E
e
pin 1
b
q
SYMBOL
MILIMETER
NOM
MIN.
0.05
MAX
0.5
A1
A2
b
0.25
3.32
3.17
3.47
0.10
0.20
0.30
D
27.90
27.90
28.00
28.00
0.50
28.10
28.10
E
e
Hd
He
L
30.35
30.35
0.45
30.60
30.60
0.60
30.85
30.85
0.75
L1
q
1.30
0
10
39
ASIX ELECTRONICS CORPORATION
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