AX88873P [ASIX]
10/100BASE Dual Speed 8-Port Repeater; 10 / 100BASE双速8端口中继器
| 型号： | AX88873P |
| 厂家： | 
ASIX ELECTRONICS CORPORATION |
| 描述： | 10/100BASE Dual Speed 8-Port Repeater |
| 文件： | 总21页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AX88873P
10/100BASE Dual Speed Repeater Controller
10/100BASE Dual Speed 8-Port Repeater
Ver. 1.1
Features
·
·
·
IEEE 802.3u repeater compatible
·
·
Separate jabber and partition state machines for
each port
Per-port LED display for Jabber, Partition, Activity
and global collision, utilization (%) for
10/100Mbps presentation
Power on LED diagnosis. All the LED display will
follow the “ON-OFF-ON-OFF-Normal” operation
procedure during/after power on reset
50MHz Operation, 3.3volt and 128-pin PQFP
Supports 8 10/100Mbps RMII I/F repeater ports
Accompany with AX88872 to build a low cost dual
speed repeater solution
Up-to 4 repeaters can be cascaded for vertical
expansion
Up-to 3 chips can be cascaded locally for horizontal
expansion
All ports can be separately isolated or partitioned in
response to fault condition
·
·
·
·
·
Product description
The AX88873 10/100Mbps Dual Speed repeater Controller is a counterpart of AX88872 without built in 4-ports
switch. It is design for low cost dual speed dumb HUB application.
The AX88873 directly supports up-to eight 10/100Mbps automatic links RMII interfaces. Maximum up-to 96
repeater ports can be constructed by stacking 1 AX88872 and 2 AX88873 chips horizontally and then cascading 4
horizontal boards vertically.
With using 128-pin low cost package, accompany with AX88872 to build up low cost dual speed repeater application.
Not only perform the repeater function but gain additional 2 switch ports. The 2 dual speed switch ports are connected
to external MII or RMII interfaces PHY for various applications. For example, one port is use for down link and the
other is used for up link to extend the network topology. The other case is one port for up link and the other port for
server.
The AX88873 is designed base on IEEE 802.3u clause 27 “ Repeater for 100Mb/s base-band networks” It is fully
compatible with IEEE 802.3u standard. Please refer Ax872-11.doc to get more information about AX88872.
System Block Diagram
10Mbps and 100Mbps Vertical cascade upto 4 stacks
Buffer
10Mbps horizontal cascade
100Mbps horizontal cascade
AX88873 #1
Repeater Controller
AX88873 #0
Repeater Controller
AX88872 #0
Swipeater Controller
PHY for Up-link
2 Quad RMII PHY
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Down-link or Server
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
Doc. No. AX873-11.DOC Date : APR/26/1999
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558
http://www.asix.com.tw
CONFIDENTIAL
CONTENTS
1.0 AX88873 OVERVIEW ....................................................................................................................................... 4
1.1 GENERAL DESCRIPTION...................................................................................................................................... 4
1.2 AX88873 BLOCK DIAGRAM:.............................................................................................................................. 4
1.3 PIN CONNECTION DIAGRAM ............................................................................................................................... 5
2.0 PIN DESCRIPTION........................................................................................................................................... 6
2.1 RMII INTERFACE FOR REPEATER PORTS............................................................................................................... 6
2.1.1 Repeater Port 0.......................................................................................................................................... 6
2.1.2 Repeater Port 1.......................................................................................................................................... 6
2.1.3 Repeater Port 2.......................................................................................................................................... 7
2.1.4 Repeater Port 3.......................................................................................................................................... 7
2.1.5 Repeater Port 4.......................................................................................................................................... 7
2.1.6 Repeater Port 5.......................................................................................................................................... 7
2.1.7 Repeater Port 6.......................................................................................................................................... 8
2.1.8 Repeater Port 7.......................................................................................................................................... 8
2.2 EXPANSION BUS INTERFACE FOR 100 MBPS......................................................................................................... 8
2.3 EXPANSION BUS INTERFACE FOR 10 MBPS........................................................................................................... 9
2.4 LED DISPLAY.................................................................................................................................................. 10
2.5 MISCELLANEOUS.............................................................................................................................................. 10
2.6 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 11
3.0 FUNCTIONAL DESCRIPTION..................................................................................................................... 12
3.1 REPEATER STATE MACHINE.............................................................................................................................. 12
3.2 RXE /TXE CONTROL ...................................................................................................................................... 12
3.3 JABBER STATE MACHINE.................................................................................................................................. 12
3.4 PARTITION STATE MACHINE............................................................................................................................. 12
3.5 LED DISPLAY INTERFACE ................................................................................................................................ 13
4.0 INTERNAL REGISTERS................................................................................................................................ 14
5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 15
5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 15
5.2 GENERAL OPERATION CONDITIONS................................................................................................................... 15
5.3 DC CHARACTERISTICS..................................................................................................................................... 15
5.4 AC SPECIFICATIONS ......................................................................................................................................... 16
5.4.1 RMII Interface Timing TX & RX............................................................................................................... 16
5.4.2 MII Interface Timing TX & RX................................................................................................................. 17
5.4.3 LED DISPLAY ......................................................................................................................................... 18
5.4.4 LED Display after Reset........................................................................................................................... 18
6.0 PACKAGE INFORMATION........................................................................................................................... 19
APPENDIX A: APPLICATIONS.......................................................................................................................... 20
A.1 16-PORT (24-PORT) REPEATER WITH 2-PORT SWITCH......................................................................................... 20
A.2 16-PORT REPEATER WITH UPTO 4 STACKS ......................................................................................................... 20
A.3 16-PORT REPEATER WITH UPTO 4 STACKS UP-LINK TO EXTERNAL SWITCH ........................................................... 21
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CONFIDENTIAL
FIGURES
FIG - 1 AX88873 BLOCK DIAGRAM ............................................................................................................................. 4
FIG - 2 PIN CONNECTION DIAGRAM.............................................................................................................................. 5
FIG - 3 APPLICATION FOR LED DISPLAY ..................................................................................................................... 13
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CONFIDENTIAL
1.0 AX88873 Overview
1.1 General Description
The AX88873 is a simple dual speed repeater that provides two expansion buses for 10M and 100M
segments respectively. Accompany with AX88872 (build-in a 4-port switch) can construct high port
count (16 ports or 24 ports) application and gain 2 additional switch ports. Additional two switch
ports are also useful for up-link or connection of server.
The pin count of chip is reduced to 128 when design uses RMII I/F instead of MII. It is not only
simplify the design but also user can choose low cost RMII Quad PHY.
1.2 AX88873 Block Diagram:
RMII
I/F
Per Port Jabber
Detection
10/100
Q-PHY
Led Interface
RMII /MII
translation
for Repeater
Port 0 -7
Per Port Partition
Detection
Repeater State
Machine of 100Mbps
10/100
Cascade
Q-PHY
Arbitration Logic
of 100Mbps
Repeater State
Machine of 10Mbps
Cascade
Arbitration Logic
of 10Mbps
Fig - 1 AX88873 Block Diagram
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1.3 Pin Connection Diagram
SPEED0
CRS_DV0
RXD0[0]
RXD0[1]
VDD
TXEN0
TXD0[0]
TXD0[1]
SPEED1
VSS
CRS_DV1
RXD1[0]
RXD1[1]
TXEN1
VSS
TXD1[0]
TXD1[1]
VDD
SPEED2
CRS_DV2
RXD2[0]
RXD2[1]
TXEN2
TXD2[0]
TXD2[1]
VSS
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
TIRD[2]
TIRD[1]
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
TIRD[0]
VSS
/TIRD_V
TIRD_CK
TIRD_ODIR
VDD
LED_CK
LED<1>
LED<0>
VSS
DAISY_OUT
DAISY_IN
VSS
AX88873
NC
VDD
REF_CLK
VSS
/RST
45
44
43
42
41
40
39
/TEST
MDO
MDC
TXD7[1]
TXD7[0]
TXEN7
Fig - 2 Pin Connection Diagram
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2.0 Pin Description
The following terms describe the AX88873 pin out:
All pin names with the “/” suffix are asserted low.
I
O
I/O
=
=
=
Input
Output
Input /Output
2.1 RMII interface for repeater ports
2.1.1 Repeater Port 0
Signal Name Type
Pin No.
Description
SPEED0
I
103
Speed Select : SPEED0 is not standard RMII signal. This signal is
sourced from PHY to inform repeater whether 10M or 100M speed is
auto-negociated. Active for 10Mbps speed is selected depending on
power on configuration.
CRS_DV0
I
104
Carrier Sense/Receive Data Valid
: CRS_DV is asserted
asynchronously on detection of carrier. CRS_DV is asserted by the PHY
when receive medium is non-idle. Loss of carrier shall result in the
desertion of CRS_DV synchronous to the cycle of REF_CLK, which
presents the first DI-bit of a nibble on to RXD0[1:0].
RXD0[1:0]
I
106,105
Receive Data : RXD0[1:0] is synchronous to REF_CLK
RXD0[1:0] shall be “00” to indicate idle when CRS_DV is disserted.
Value other than “00” are reserved for out-of-band signaling shall be
ignored by MAC Upon assertion of CRS_DV, PHY shall ensure that
RXD[1:0] = “00” until proper receive decoding takes place
Transmit Enable : TXEN0 is synchronous to REF_CLK.
TXEN0 indicates that MAC is presenting DI-bits on TXD[1:0] for
transmission. TXEN0 shall be negated prior to the 1st REF_CLK rising
edge following the final DI-bit of a frame
Transmit Data : TXD0[1:0] shall transition synchronously to
REF_CLK. TXD0[1:0] shall be “00” to indicate idle when TX_EN is
disserted. Value other than “00” are reserved for out-of-band signaling
shall be ignored by PHY. When TX_EN is asserted, TXD[1:0] are
accepted for transmission by PHY
TXEN0
O
O
108
TXD0[1:0]
110,109
2.1.2 Repeater Port 1
Signal Name Type
Pin No.
Description
SPEED1
I
111
Speed Select : Please references section 2.1.1 PORT0 description.
CRS_DV1
RXD1[1:0]
TXEN1
I
113
115,114
116
Carrier Sense/Receive Data Valid : Please references section 2.1.1
PORT0 description.
Receive Data : Please references section 2.1.1 PORT0 description.
I
O
O
Transmit Enable : Please references section 2.1.1 PORT0 description.
Transmit Data : Please references section 2.1.1 PORT0 description.
TXD1[1:0]
119,118
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2.1.3 Repeater Port 2
Signal Name Type
Pin No.
Description
SPEED2
I
121
Speed Select : Please references section 2.1.1 PORT0 description.
CRS_DV2
RXD2[1:0]
TXEN2
I
122
124,123
125
Carrier Sense/Receive Data Valid : Please references section 2.1.1
PORT0 description.
Receive Data : Please references section 2.1.1 PORT0 description.
I
O
O
Transmit Enable : Please references section 2.1.1 PORT0 description.
Transmit Data : Please references section 2.1.1 PORT0 description.
TXD2[1:0]
127,126
2.1.4 Repeater Port 3
Signal Name Type
Pin No.
Description
SPEED3
I
1
Speed Select : Please references section 2.1.1 PORT0 description.
CRS_DV3
RXD3[1:0]
TXEN3
I
2
Carrier Sense/Receive Data Valid : Please references section 2.1.1
PORT0 description.
Receive Data : Please references section 2.1.1 PORT0 description.
I
4,3
5
O
O
Transmit Enable : Please references section 2.1.1 PORT0 description.
Transmit Data : Please references section 2.1.1 PORT0 description.
TXD3[1:0]
7,6
2.1.5 Repeater Port 4
Signal Name Type
Pin No.
Description
SPEED4
I
9
Speed Select : Please references section 2.1.1 PORT0 description.
CRS_DV4
RXD4[1:0]
TXEN4
I
10
Carrier Sense/Receive Data Valid : Please references section 2.1.1
PORT0 description.
Receive Data : Please references section 2.1.1 PORT0 description.
I
12,11
13
O
O
Transmit Enable : Please references section 2.1.1 PORT0 description.
Transmit Data : Please references section 2.1.1 PORT0 description.
TXD4[1:0]
15,14
2.1.6 Repeater Port 5
Signal Name Type
Pin No.
Description
SPEED5
I
19
Speed Select : Please references section 2.1.1 PORT0 description.
CRS_DV5
RXD5[1:0]
TXEN5
I
20
Carrier Sense/Receive Data Valid : Please references section 2.1.1
PORT0 description.
Receive Data : Please references section 2.1.1 PORT0 description.
I
23,22
24
O
O
Transmit Enable : Please references section 2.1.1 PORT0 description.
Transmit Data : Please references section 2.1.1 PORT0 description.
TXD5[1:0]
26,25
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2.1.7 Repeater Port 6
Signal Name Type
Pin No.
Description
SPEED6
I
27
Speed Select : Please references section 2.1.1 PORT0 description.
CRS_DV6
RXD6[1:0]
TXEN6
I
28
Carrier Sense/Receive Data Valid : Please references section 2.1.1
PORT0 description.
Receive Data : Please references section 2.1.1 PORT0 description.
I
30,29
31
O
O
Transmit Enable : Please references section 2.1.1 PORT0 description.
Transmit Data : Please references section 2.1.1 PORT0 description.
TXD6[1:0]
33,32
2.1.8 Repeater Port 7
Signal Name Type
Pin No.
Description
SPEED7
I
35
Speed Select : Please references section 2.1.1 PORT0 description.
CRS_DV7
RXD7[1:0]
TXEN7
I
36
Carrier Sense/Receive Data Valid : Please references section 2.1.1
PORT0 description.
Receive Data : Please references section 2.1.1 PORT0 description.
I
38,37
39
O
O
Transmit Enable : Please references section 2.1.1 PORT0 description.
Transmit Data : Please references section 2.1.1 PORT0 description.
TXD7[1:0]
41,40
2.2 Expansion Bus Interface for 100 Mbps
Signal Name Type Pin No.
Description
HIRD[3:0]
I/O/Z 101,100
INTER REPEATER DATA : Nibble data input/output. Transfer data from
the “active” AX88872/3 to all other “inactive” AX88872/3 chips. The bus-
master of the IRD bus is determined by IR_ACT bus arbitration.
INTER REPEATER DATA VALID : This signal reflects the RX_DV
status of the active port. Used to frame good packets.
INTER REPEATER CLOCK VALID : All inter repeater signals are
synchronized to the rising edge of this clock.
INTER REPEATER DATA IN/OUT DIRECTION :
/PU
99,98
/HIRD_V
I/O/Z
/PU
I/O/Z
/PU
O
97
HIRD_CK
HIRD_ODIR
96
95
This pin indicates the direction of IRD data .
“High” = HIRD[3:0], /HIRD_V , HIRD_CK are Output.
“Low” = HIRD[3:0], /HIRD_V , HIRD_CK are Input.
/LHIR_ACT[2:0] I/O/OC 83,81,80
LOCAL REPEATER ACTIVITY IN/OUT : the function is the same as
/HIR_ACTO[3:0] but for local repeater activity only.
/HIR_ACTI[3:0]
I/PU
87,86
85,84
INTER REPEATER ACTIVITY IN: These pins perform the same
function as /HIR_ACTO[3:0] when they serve as input function. Then the
/HIR_ACTO[3:0] insert external buffers the input function must be replaced
with /HIR_ACTI [3:0].
/HIR_ACTO[3:0] I/O/OC 93,92
91,90
INTER REPEATER ACTIVITY IN/OUT: The local repeater activity
appearance, the signal of the related RID (Repeater ID) will be asserted and
as an output pin. All other pins serve as input pins but except the collision
conditions. When collision occurs , the signal of related (RID-1) pins will
also serve as outputs and will active during local collision period. The
exception case is when RID = 0, then (RID-1) is replaced with (RID+1).
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2.3 Expansion Bus Interface for 10 Mbps
Signal Name Type Pin No.
Description
TIRD[3:0]
I/O/Z
65,64
INTER REPEATER DATA : Nibble data input/output. Transfer data from
the “active” AX88872/3 to all other “inactive” AX88872/3 chips. The bus-
master of the IRD bus is determined by IR_ACT bus arbitration.
INTER REPEATER DATA VALID : This signal reflects the RX_DV
status of the active port. Used to frame good packets.
INTER REPEATER CLOCK VALID : All inter repeater signals are
synchronized to the rising edge of this clock.
INTER REPEATER DATA IN/OUT DIRECTION :
/PU
63,62
/TIRD_V
I/O/Z
/PU
I/O/Z
/PU
O
60
59
58
TIRD_CK
TIRD_ODIR
This pin indicates the direction of data for external transceiver.
“High” = TIRD[3:0], /TIRD_V , TIRD_CK are Output.
“Low” = TIRD[3:0], /TIRD_V , TIRD_CK are Input.
/LTIR_ACT[2:0] I/O/OC 68,67,66
LOCAL REPEATER ACTIVITY IN/OUT : the function is the same as
/TIR_ACTO[3:0] but for local repeater activity only.
/TIR_ACTI[3:0]
I/PU
74,73,
72,71
INTER REPEATER ACTIVITY IN: These pins perform the same
function as /HIR_ACTO[3:0] when they serve as input function. Then the
/HIR_ACTO[3:0] insert external buffers the input function must be replaced
with /HIR_ACTI [3:0].
/TIR_ACTO[3:0] I/O/OC 79,78
76,75
INTER REPEATER ACTIVITY IN/OUT: The local repeater activity
appearance, the signal of the related RID (Repeater ID) will be asserted and
as an output pin. All other pins serve as input pins but except the collision
conditions. When collision occurs , the signal of related (RID-1) pins will
also serve as outputs and will active during local collision period. The
exception case is when RID = 0, then (RID-1) is replaced with (RID+1).
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2.4 LED Display
Signal Name Type Pin No.
Description
LED[1:0]
O
55, 54 Those signals indicate each port‘ s statuses (such as activity, jabber and
partition) and global information(such as Collision , Repeater ID,
Utilization ) in sequence. For detail , see the LED timing specification
The utilization of 100M segment and 10M segment are using the same scale.
The Utilization % display define as following : (See Note 1 also)
1: Led off
0: Led on
Utilization % UTI0 UTI1 UTI2 UTI3 UTI4
UTI5
0
1
5
10
15
30
60
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
0
LED[0] : This signal also indicates 100M repeater collision ( Blinking )
during the interval of sequence shift
data.
LED[1] : This signal also indicates 10 M repeater collision ( Blinking )
during the interval of sequence shift data.
LED_CK
O
56
LED Clock : The signal is a discontinue clock for LED signals serial shift
out. The clock period width is 400nS and last 32 cycle with every 52.4ms
repeated.
2.5 Miscellaneous
Signal Name Type Pin No.
Description
/RST
I
45
47
51
Reset : Active Low
The chip is reset when this signal is asserted Low
Reference clock : The input is a continuous clock at 50Mhz for timing
reference with RMII interface.
REF_CLK
DAISY_IN
I
I/PU
Repeater Identification Number Daisy-Chain In : When MODE=” 1” ,
This pin is a daisy chain serial input for Repeater ID. A state machine always
monitors the input if a correct data (RID) present at the pin, the (RID+1) will
be written to RID register and override the power on setup RID for the chip.
Repeater Identification Number Daisy-Chain Out : When MODE=” 1” ,
This pin is periodically shift out the RID of itself to the next chained chip to
inform that this ID has already been occupied. The RID is shift out
periodically every about 200us.
Station Management Data Out : For setup PHY auto-negotiation registers.
A burst write commands are issue to setup PHY register after reset. The PHY
address 4h, 5h, 6h, 7h, 8h, 9h,Ah and Bh will be written as register 4h to
value 00A1h ( Advertise register set to 10/100 half-duplex mode)and register
0h to value 1000h(Enable auto-negotiation).
DAISY_OUT
MDO
O/ML
O
52
43
MDC
/TEST
O
I/PD
42
44
Station Management Data Clock Out : For MDO reference clock.
Test Pin : Active LOW
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CONFIDENTIAL
The pin is just for test mode setting purpose only. Must be pull high when
normal operation.
NC
O
I
16, 18
49,88
102
17, 34
48, 57
77, 89
107, 120
8, 21
NC : Keep no connection
VDD
POWER : +3.3V +/-5%
VSS
I
POWER: 0V
46, 50
53,61
69, 70
82, 94,
112, 117
128
2.6 Power on configuration setup signals cross reference table
Signal Name
Speed_Define
Share with
TXD7[1]
Description
Speed Setting for Repeater Port 0 to Port 7 :
0 : SPEED0~7 pin is Low for 10M,high for 100M
1 : SPEED0~7 pin is Low for 100M,high for 10M
Local Repeater ID Selection :
LRID_S1
LRID_S0
TXD5[1]
TXD5[0]
LRID_S1
LRID_S0
LRID No.
1
1
0
0
1
0
1
0
0
1
2
reserved
All of the above signals are pull-up for default values.
Note 1 :
The calculation formulae of Traffic Utilization between ASIX and NetCom is difference, so you will get different results
when using SmartBit (SB) testing this item.
We found the SmartBit calculate the Utilization without include 96 Bit time inter frame gap (IFG). So the utilization
value can be 100%. As well as we found SB used min packet size (64 byte) and min IFG (96 bit-time) as 100% utilization.
In theory, when max packet size (1518 byte) and min IFG the utilization will be more than 100%, but SB also treat it as
100%.
In our AX88873 design, we use real cable bandwidth as calculation base. We calculate the bit counts of carrier within a
unit time. Because of the existence of inter frame gap, In our calculation 100% utilization is impossible. So the above two
cases (64 byte packet size and 1518 byte packet size with min. IFG), we will count as 85.7% and 99.2%.
If using SB test result to indicate utilization LED the value must be modified. See the following reference table.
ASIX’ s Utilization%
SmartBit’ s Utilization%
1
2
5
7
10
12
15
17
30
34
60
68
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3.0 Functional Description
3.1 Repeater State Machine
The repeater state machine is in idle state when there is no carrier presented on any ports . When there is only
one port has receive activity, the repeater state machine will enter data -forwarding state to ensure correct
data forwarding to other connected ports. If collision happens anytime, The repeater state machine detects
collision then send jam pattern to all ports until collision ceases.
3.2 RXE /TXE Control
Idle state
CRS_DV(ALL) = 0, the repeater sends no data to any port.
RXE(ALL) = 0.
TXE(ALL) = 0.
Data Forwarding state
If CRS_DV(ALL) = 1, N is the only one port that has incoming packet.
RXE(N) = 1, RXE(ALLXN) = 0.
TXE(N) = 0, TXE(ALLXN) = 1.
Collision state
If CRS_DV(ALL) > 1, the repeater sends jam pattern to all ports.
RXE(ALL) = 0.
TXE(ALL) = 1.
One Port Left state
When all packets are back off except only one port still has activity, that is CRS_DV(ALL) = 1 again . N is the
only one left port that has incoming packet. The repeater sends jam pattern to all other port except for the still
activity ports.
RXE(ALL) = 0.
TXE(ALLXN) = 1.
3.3 Jabber State Machine
To prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber
timer. If a reception exceeds this duration (64K bit times for AX88872A), the jabber condition will be detected.
In this condition, repeater unit will disable receive and transmit packets for the jabbered port and the other ports
remain the normal operation.
When the carrier is no longer detected for the jabbered port or reset the repeater, the jabber state will be existed
and the port will receive and transmit packets normally.
3.4 Partition State Machine
The partition state machine is used to protect network from being upset when a port suffer continuous
collision, each port uses a partition state machine to detect and prevent this condition. When a port suffers from
continuous 64 times of collision events, then it goes to Partition State. The partitioned port will be not released
until a packet without collision be transmitted( more than 512 bit times for AX88872A) or reset the repeater.
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3.5 LED Display Interface
AX88873 provides per-port LED status indication for partition, jabber, activity and support rate - based LED
for 10 and 100Mbps segments utilization (%) . All LED[1:0] perform active low.
LED[1:0] Status Driver Wave-form as follows :
LED_CK
D0
D1
D2
D3
D4
D5
D6
D7 D8
10M
D9 D10 D11 D12 D13 D14 D15
10M 10M 10M 10M 10M
UTI5 UTI4 UTI3 UTI2 UTI1
100M 100M 100M 100M 100M 100M
UTI5 UTI4 UTI3 UTI2 UTI1 UTI0
RID3 RID2
RID1 RID0
UTI0
LED[0]
D16 D17 D18 D19 D20 D21 D22 D23
ACT7 ACT6 ACT5 ACT4 ACT3 ACT2 ACT1 ACT0
( This portation no clock presented )
LED[0]
Chip 0 Memory Test Fail and/or 100M Collision
Continue
JAB7 JAB6 JAB5 JAB4 JAB3 JAB2 JAB1 JAB0 N/A
PART PART PART PART PART PART PART PART
N/A
N/A
N/A
N/A
N/A
N/A
N/A
LED[1]
LED[1]
Continue
Chip 1 Memory Test Fail and/or 10M Collision
7
6
5
4
3
2
1
0
Notes:
a. PART7~0indicates partition status for each port
b. JAB7~0 indicates jabber status for each port
c. ACT7~0 indicates activity status for each port
d. RID3~0 is the ID of repeater chip
e. 10M UTI5~0 indicate global utilization rate of 10Mbps for each 104.8ms sampling period.
f. 100M UTI5~0 indicate global utilization rate of 100Mbps for each 104.8ms sampling period.
It must use external shift register to decode data on LED[1:0]. The application shows as follows:
Q
4
Q
4
Q
4
Q
1
Q
2
Q
3
Q
7
Q
1
Q
2
Q
3
Q
7
Q
1
Q
2
Q
3
Q
7
Q
0
Q
0
Q
0
Q
5
Q
5
Q
5
Q
6
Q
6
Q
6
LED[0]
74LS164(#3)
D
D
D
74LS164(#1)
74LS164(#2)
LED_CK
Fig - 3 Application for LED display
If the user don‘ t want to show jabber status, take away the latter 74LS164(#2). The application is the
same for LED[1].
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4.0 INTERNAL REGISTERS
The information reserve for intelligent function.
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5.0 ELECTRICAL SPECIFICATION AND TIMING
5.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
Operating Temperature
Storage Temperature
Supply Voltage
Input Voltage
Output Voltage
Ta
Ts
Vcc
Vin
Vout
Tl
0
+70
+150
+4
Vdd+0.5
Vdd+0.5
+220
°C
°C
V
V
V
-55
-0.3
-0.3
-0.3
-55
Lead Temperature (soldering 10 seconds maximum)
°C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure
to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability
5.2 General Operation Conditions
Description
SYM
Min
Max
Units
Operating Temperature
Supply Voltage
Ta
Vdd
0
+3.0
+70
+3.6
°C
V
5.3 DC Characteristics
(Vdd=3.0V to 3.6V, Vss=0V, Ta=0°C to 70°C)
Description
SYM
Min
Max
Units
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current 1 (Note 1)
Input Leakage Current 2 (Note 2)
Output Leakage Current
Vil
Vss-0.3
2
0.8
Vdd+0.5
0.4
V
V
V
V
uA
uA
uA
Vih
Vol
Voh
Iil1
Iil1
Iol
2.4
10
500
10
Description
Power Consumption
SYM
Min
Tpy
TBD
Max
Units
Pc
mA
Note :
1. All the input pins without pull low or pull high.
2. Those pins had been pull low or pull high.
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5.4 AC specifications
5.4.1 RMII Interface Timing TX & RX
T0
T1
REF_CLK
T2
T3
TX_EN
TXD
CRS_DV
T2
T3
RXD
Symbol
T0
Description
REF_CLK Clock Cycle Time
REF_CLK Clock High Time
CRS_DV, RXD, TXEN and TXD data setup to
REF_CLK rising edge
Min
19.998
Typ.
20
10
Max
20.002
13
Units
ns
ns
ns
T1
T2
7
4
T3
CRS_DV, RXD, TXEN and TXD data hold from
REF_CLK rising edge
2
ns
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5.4.2 MII Interface Timing TX & RX
T0
T1
TXCLK
TX_EN
T2
T3
T2
T3
TXD
Symbol
T0
Description
TXCLK Cycle Time
TXCLK High Time
TX_EN Delay from TXCLK High
TXD Delay from TXCLK High
Min
39.996
14
7.440
3.410
Typ.
40
20
Max
40.004 ns
26
21.760
13.320
Units
T1
T2
T3
ns
ns
ns
T4
T5
RX_CLK
CRS
T6
RXDV
T7
RXD
Symbol
Description
RX_CLK Clock Cycle Time
RX_CLK Clock High Time
CRS to RXDV Delay Requirement
RXD or RXDV setup to RX_CLK rise time
Min
39.996
14
40
10
Typ.
40
20
Max
40.004
26
160
-
Units
T4
T5
T6
T7
ns
ns
ns
ns
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5.4.3 LED DISPLAY
T3
LED_CK
--------
-------
-
D0
D1
D2
..............
D22 D23
D0
D1
D2
T4
T3
LED_CK
T1
T2
LED[1:0]
D0
D1
D2
D3
-------
D15
D0
Symbol
Description
Min
Typ.
Max
Units
T1
T2
T3
T4
LED setup to LED_CK High
LED hold from LED_CK High
LED_CK Period Width
190
200
200 ns
210 ns
ns
400
52.4
LED_CK Cycle burst out period
ms
5.4.4 LED Display after Reset
/Reset
T1
T2
T2
T2 T3
LED[2:0]
Symbol
T1
Description
Min
1000
Typ.
Max
Units
ns
Repeater reset time
T2
T3
LED Blink Time After Reset
LED Dark Time Before Normal Display
838.4
419.2
ms
ms
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6.0 Package Information
He
E
A2 A1
e
pin 1
b
q
SYMBOL
MILIMETER
NOM
MIN.
0.21
MAX
0.41
A1
A2
b
0.31
2.85
2.80
2.90
0.15
0.20
0.30
D
13.80
19.80
14.00
20.00
0.50
14.20
20.20
E
e
Hd
He
L
17.10
23.10
0.70
17.20
23.20
0.80
17.30
23.30
0.90
L1
q
1.60
0
8
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Appendix A: Applications
Some typical applications for AX88873 are illustrated bellow.
A.1 16-port (24-port) repeater with 2-port switch
10Mbps and 100Mbps Vertical cascade upto 4 stacks
Buffer
10Mbps horizontal cascade
100Mbps horizontal cascade
AX88873 #1
Repeater Controller
AX88872 #0
Swipeater Controller
PHY for Up-link
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Down-link or Server
Note : Add additional AX88873 to build a 24-port repeater
A.2 16-port repeater with upto 4 stacks
10Mbps and 100Mbps Vertical cascade upto 4 stacks
Repeater #3
Slave
Buffer
10Mbps horizontal cascade
100Mbps horizontal cascade
AX88873 #1
Repeater Controller
AX88872 #0
Swipeater Controller
PHY for Up-link
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Down-link or Server
Repeater #1,#2
Slave (omitted)
Repeater #0
Master
Buffer
10Mbps horizontal cascade
100Mbps horizontal cascade
AX88873 #1
Repeater Controller
AX88872 #0
Swipeater Controller
PHY for Up-link
2 Quad RMII PHY
2 Quad RMII PHY
PHY for Down-link or Server
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A.3 16-port repeater with upto 4 stacks up-link to external switch
10Mbps and 100Mbps Vertical cascade upto 4 stacks
Buffer
10Mbps and 100Mbps horizontal cascade
AX88873 #0
Repeater Controller
AX88873 #1
Repeater Controller
2 Quad RMII PHY
2 Quad RMII PHY
10Mbps and 100Mbps horizontal
Buffer
AX88873 #0
Repeater Controller
AX88873 #1
Repeater Controller
2 Quad RMII PHY
2 Quad RMII PHY
AX88620
8-port Switch Controller
or
AX88615
5-port Switch Controller
Quad PHY
Quad PHY or Single PHY
10M Link
100M
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