AX88875AP [ASIX]
10/100BASE 5-Port Dual Speed Bripeater Controller; 10 / 100BASE 5端口双速Bripeater控制器
| 型号： | AX88875AP |
| 厂家： | 
ASIX ELECTRONICS CORPORATION |
| 描述： | 10/100BASE 5-Port Dual Speed Bripeater Controller |
| 文件： | 总23页 (文件大小：288K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AX88875AP
10/100BASE Dual Speed Bripeater Controller
ASIX AX88875AP
10/100BASE 5-Port
Dual Speed “Bripeater” Controller
Data Sheets (10/16/’00)
Always contact ASIX for possible updates
before starting a design.
DOCUMENT NO. : AX875A-06.DOC
This data sheets contain new products information. ASIX ELECTRONICS reserves the rights to modify the products
specification without notice. No liability is assumed as a result of the use of this product. No rights under any patent
accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw
AX88875AP Bripeater
CONTENTS
1.0 AX88875A OVERVIEW..................................................................................................................................... 3
1.1 GENERAL DESCRIPTION...................................................................................................................................... 3
1.2 FEATURES.......................................................................................................................................................... 4
1.3 BLOCK DIAGRAM ............................................................................................................................................... 5
1.4 PIN CONNECTION DIAGRAM (MODE 0)................................................................................................................ 6
1.5 PIN CONNECTION DIAGRAM (MODE 1)................................................................................................................ 7
2.0 PIN DESCRIPTION........................................................................................................................................... 8
2.1 MII INTERFACES ................................................................................................................................................ 8
2.2 LED DISPLAY.................................................................................................................................................... 9
2.3 BUFFER MEMORY PINS GROUP ........................................................................................................................... 10
2.4 MISCELLANEOUS.............................................................................................................................................. 11
2.5 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 12
3.0 FUNCTIONAL DESCRIPTION..................................................................................................................... 13
3.1 REPEATER STATE MACHINE.............................................................................................................................. 13
3.2 RXE /TXE CONTROL................................................................................................................................... 13
3.3 JABBER STATE MACHINE.................................................................................................................................. 14
3.4 PARTITION STATE MACHINE............................................................................................................................. 14
3.5 LED DISPLAY INTERFACE ................................................................................................................................ 14
4.0 INTERNAL REGISTERS................................................................................................................................ 16
4.1 CONFIGURATION REGISTER (CONFIG)............................................................................................................. 16
5.0 ELECTRICAL SPECIFICATION AND TIMING.......................................................................................... 17
5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 17
5.2 GENERAL OPERATION CONDITIONS................................................................................................................... 17
5.3 DC CHARACTERISTICS..................................................................................................................................... 17
5.4 AC SPECIFICATIONS ......................................................................................................................................... 18
5.4.1 MII Interface Timing Tx & Rx .................................................................................................................. 18
5.4.2 SRAM read cycle and write cycle............................................................................................................. 19
5.4.3 LED DISPLAY ......................................................................................................................................... 20
5.4.4 LED Display After Reset .......................................................................................................................... 20
6.0 PACKAGE INFORMATION........................................................................................................................... 21
APPENDIX A: APPLICATIONS.......................................................................................................................... 22
A.1 STAND-ALONG 5-PORTS 10/100MBPS HUB APPLICATION ................................................................................. 22
A.2 STAND-ALONG 4-PORTS 10/100MBPS HUB WITH ONE MAC APPLICATION........................................................ 22
APPENDIX B: USING MII I/F CONNECTS TO MAC ...................................................................................... 23
FIGURES
FIG - 1 CHIP BLOCK DIAGRAM ..................................................................................................................................... 5
FIG - 2 PIN CONNECTION DIAGRAM (MODE 0) .............................................................................................................. 6
FIG - 3 PIN CONNECTION DIAGRAM (MODE 1) .............................................................................................................. 7
FIG - 4 APPLICATION FOR LED DISPLAY ..................................................................................................................... 15
FIG - 5 STAND-ALONG 5-PORTS 10/100MBPS HUB APPLICATION ................................................................................ 22
FIG - 6 STAND-ALONG 4-PORTS 10/100MBPS HUB WITH ONE MAC APPLICATION ....................................................... 22
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
1.0 AX88875A Overview
The AX88875A 10/100Mbps Dual Speed “Bripeater” Controller is “a dual speed
repeater with build in bridge function” It is design for low cost dumb HUB application. The
AX88875A directly supports up-to five 10/100Mbps automatic links MII interfaces specially for
SOHO market. The AX88875A is designed base on IEEE 802.3u clause 27 “ Repeater for
100Mb/s base-band networks” It is fully compatible with IEEE 802.3u standard.
1.1 General Description
The AX88875A Repeater Controller is a subset of a repeater set containing all the
repeater-specific components and functions, exclusive of PHY components and functions. The
AX88875A has five Media Independent Interfaces (MII) to connect to PHY or MAC devices.
The AX88875A supports 5 MII interfaces ports, a bridge packet buffer SRAM interface
and LED display interface. AX88875A without support expansion port to cascade to other
AX88850 and AX88860 pure 100Mbps repeater chips..
The AX88875A supports stand along 10/100Mbps dual speed repeater applications with
two LED display mode.
The AX88871A has two LED display mode.
Mode 0
Mode 1
Direct LED display mode.
Rich LED display mode.
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
1.2 Features
·
·
·
IEEE 802.3u repeater compatible
Supports per port 10/100Mbps alternative with auto detected
Build in 10/100Mbps bridge engine with following features
1.Minimum 32K bytes, maximum 128K bytes SRAM to buffer packets
2.Seamless buffer management without waste any space of buffer memory
3.Simple asynchronous 8-bit SRAM interface to reduce system cost
4.256 or 1024 entries is supported
5.Auto learning and filtering
6.Two forwarding modes are supported : Store-n-Forward and fragment-free
7.Flow-control is supported optionally.
8.Buffer RAM auto testing
9.Routing and Learning at wire speed (148810 packets/sec at 100Mbps)
Supports 5 10/100Mbps network connections
·
·
·
·
·
·
·
5 dedicated MII interfaces can support 100BASE-TX/T4/FX PHY interfaces
5th Port can connect to bridge, switch or MAC type device optionally.
Low latency design supports Class II repeater implementation
All ports can be separately isolated or partitioned in response to fault condition
Separate jabber and partition state machines for each port
Per-port LED display for Jabber, Partition, Activity. Global partition, RAM test fail and
collision, utilization (%) for 10/100Mbps presentation
Power on LED diagnosis. All the LED display will follow the “ON-OFF-ON-OFF-Normal”
operation procedure during/after power on reset
·
·
160-pin PQFP
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
1.3 Block Diagram
Per port Jabber ctl,
auto-partition SM &
MIB I/F
MII
Registers
(Reserved)
Per port Collision ,
Partition counters.
I/F
MII
interface
10/100
Q-PHY
Re-concilia-
tion
Cascade
Arbitration Logic
of 100Mbps
Repeater State
Machine of 100Mbps
Sub-layer
MUX
(Reserved)
10/100
PHY
MII
I/F
Repeater State
Machine of 10Mbps
(Reserved)
(Port 0 -
Port 4 )
or
MAC
Collision
100Mbps
to
10Mbps
Bridge
Speed
Detection
circuit
Elasticity Buffer
for 100Mbps
and 10Mbps
Handling Logic
for 100Mbps
and10Mbps
Fig - 1 Chip Block Diagram
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
1.4 Pin Connection Diagram (Mode 0)
/LACT[4]
121
BMA[9]
BMA[8]
/BMWR
/LUTI[3]
/LUTI[2]
/LUTI[1]
/LUTI[0]
/BMA[15]
MCLK
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
122
/LACT[2]
123
/LACT[3]
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
VDD
NC
/LACT[0]
/LACT[1]
NC
TEST1
/RST
MDO
MDC
/LCOL100
VSS
VSS
LCLK
/HALF10
VDD
COL_O[4]
TXER[4]
TXD[4][3]
TXD[4][2]
TXD[4][1]
TXD[4][0]
TXEN[4]
RXD[4][3]
RXD[4][2]
RXD[4][1]
RXD[4][0]
RXCLK[4]
VDD1
COL[4]
PULL_DN
PULL_DN
VDD1
VSS1
RXER[0]
RXDV[0]
CRS[0]
AX88875AP
( Mode 0 )
RXCLK[0]
RXD[0][0]
RXD[0][1]
RXD[0][2]
RXD[0][3]
VSS
TXEN[0]
TXD[0][0]
TXD[0][1]
TXD[0][2]
TXD[0][3]
TXER[0]
RXER[1]
RXDV[1]
CRS[1]
RXCLK[1]
RXD[1][0]
RXD[1][1]
VSS1
CRS[4]
RXDV[4]
RXER[4]
VDD
SET2
SET1
COL[0]
SET0
PULL_DN
VSS
TXER[3] COL[3]
TXD[3][3]
TXD[3][2]
TXD[3][1]
Fig - 2 Pin Connection Diagram (Mode 0)
Note : Power on configuration setup signals refer section 2.5 cross referance table
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
1.5 Pin Connection Diagram (Mode 1)
NC
121
BMA[9]
BMA[8]
/BMWR
LED_CK
LED[2]
LED[1]
LED[0]
/BMA[15]
MCLK
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
NC
122
NC
123
NC
124
VDD
125
NC
126
NC
NC
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
NC
TEST1
/RST
VSS
LCLK
/HALF10
VDD
MDO
MDC
/LCOL100
VSS
COL_O[4]
TXER[4]
COL[4]
PULL_DN
PULL_DN
VDD1
TXD[4][3]
TXD[4][2]
TXD[4][1]
TXD[4][0]
TXEN[4]
RXD[4][3]
RXD[4][2]
RXD[4][1]
RXD[4][0]
RXCLK[4]
VDD1
VSS1
CRS[4]
RXDV[4]
RXER[4]
VDD
VSS1
RXER[0]
RXDV[0]
CRS[0]
AX88875AP
( Mode 1 )
RXCLK[0]
RXD[0][0]
RXD[0][1]
RXD[0][2]
RXD[0][3]
VSS
TXEN[0]
TXD[0][0]
TXD[0][1]
TXD[0][2]
TXD[0][3]
TXER[0]
RXER[1]
RXDV[1]
CRS[1]
SET2
SET1
COL[0]
SET0
PULL_DN
VSS
TXER[3] COL[3]
TXD[3][3]
TXD[3][2]
TXD[3][1]
RXCLK[1]
RXD[1][0]
RXD[1][1]
Fig - 3 Pin Connection Diagram (Mode 1)
Note : Power on configuration setup signals refer section 2.5 cross referance table
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
2.0 Pin Description
The following terms describe the AX88875A pinout:
All pin names with the “/” suffix are asserted low.
I
O
I/O
=
=
=
Input
Output
Input /Output
2.1 MII interfaces
Signal Name Type
Pin No.
Description
TXER[4:0]
O
66, 44, 28 Transmit Error : When /HALF10 pin set to “high”. TXER is transition
Or
or
9, 154
synchronously with respect to the rising edge of TXCLK . Asserted
high when a code violation is request to be send
COL[4:0]
I
Collision : When /HALF10 pin set to “low”. COL is input from PHY,
when 10Mbps PHY is in half-duplex mode.
TXD[4:0][3:0]
O
65 – 62, 43 – 40 Transmit Data : TXD[3:0] is transition synchronously with respect to
27 – 24, 8 – 5 the rising edge of TXCLK. For each TXCLK period in which TXEN is
153 - 150 asserted, TXD[3:0] are accepted for transmission by the PHY.
TXEN[4:0]
O
I
61, 39, 23 Transmit Enable : TXEN is transition synchronously with respect to the
4, 149
rising edge of TXCLK. TXEN indicates that the port is presenting
nibbles on TXD [3:0] for transmission.
RXD[4:0][3:0]
60 – 57, 37 – 34 Receive Data : RXD [3:0] is driven by the PHY synchronously with
22 – 19, 3, 2 respect to RXCLK.
160, 159,
147 - 144
RXER[4:0]
RXCLK[4:0]
RXDV[4:0]
I
I
I
51, 30, 15, Receive Error : RXER ,is driven by PHY and synchronous to RXCLK,
155, 140
is asserted for one or more RXCLK periods to indicate to the port that
an error has detected.
56, 33,
Receive Clock : RX_CLK is a continuous clock that provides the
18, 158, 143 timing reference for the transfer of the RXDV,RXD [3:0] and RXER
signals from the PHY to the MII port of the repeater.
52, 31,
Receive Data Valid : RX_DV is driven by the PHY synchronously with
16, 156, 141 respect to RXCLK. Asserted high when valid data is present on RXD
[3:0].
CRS[4:0]
I
53, 32,
17, 157, 142 receive medium is non-idle at full duplex mode.
67 Collision : Collision detection signal for port 4
Carrier Sense : Asynchronous signal CRS is asserted by the PHY when
COL_O[4]
O
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AX88875AP Bripeater
2.2 LED Display
Signal Name Type Pin No.
Description
LED[2:0]
O
76 - 74 LED Display Information : When MODE=” 1” , Those signals indicate each
port‘ s Partition, Jabber, Activity, Collision (global), Repeater ID, Utilization
% (global), Collision % (global) in sequence. For detail , see the LED timing
specification
or
/LUTI[2:0]
/LUTI[2:0] : When MODE=” 0” , Those pins drive utilization[2:0] LEDs
directly.
The Utilization % display define as following : (See Note 1 also)
Utilization % LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7
0
1
5
10
15
30
40
60
80+
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
The Collision % display define as following :
Collision % LED0 LED1 LED2 LED3 LED4 LED5 LED6 LED7
0
1
2
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
5
10
15
20
30
60+
LED_CK
or
O
77
LED clock signal : When MODE=” 1” , The signal is a discontinue clock for
LED signals serial shift out. The clock period width is 40nS and last 16 cycle
with every 125ms repeated.
/LUTI[3]
/LCOL10
or
/LUTI[4]
NC
/LUTI[3] : When MODE=” 0” , This pin drive utilization[3] LED directly.
Collision LED for 10Mbps : When MODE=” 1” , This pin indicates 10Mbps
repeater collision occurred.
/LUTI[4] : When MODE=” 0” , This pin drive utilization[4] LED directly.
NC : When MODE=” 1” , The pin function is reserved.
O/Z
O
113
112
69
or
/LUTI[5]
/LCOL100
/LUTI[5] : When MODE=” 0” , This pin drive utilization[5] LED directly.
Collision LED for 100Mbps : This pin indicates 100Mbps repeater collision
occurred.
O/Z
O
NC
121, 124 NC : When MODE=” 1” , The pin function is reserved.
or
123, 128
/LACT[4:0]
127
/LACT[4:0] : When MODE=” 0” ,Those pins drive activity[4:0] LEDs
directly.
NC or
/LPART[4:0]
O/OC 119-115 NC : When MODE=” 1” , The pin function is reserved. or
/LPART[4:0] : When MODE=” 0” , Those pins drive partition[4:0] LEDs
directly.
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
Note : The Utilization % display define as following for Mode 0 LED direct driving.
Utilization % /LUTI0 /LUTI1 /LUTI2 /LUTI3 /LUTI4 /LUTI5
0
1
5
10
15
30
60
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
1
0
0
1
1
1
1
1
1
0
Note 1 :
The calculation formulas of Traffic Utilization between ASIX and NetCom is difference, so you will
get different results when using SmartBit (SB) testing this item.
We found the SmartBit calculate the Utilization without include 96 Bit time inter frame gap. So the
utilization value can be 100%. As well as we found SB used min packet size (64 byte) and min IFG (96
bit-time) as 100% utilization. In theory, when max packet size(1518 byte) and min IFG the utilization
will be more than 100%, but SB also treat it as 100%.
In our AX88875 design, we use real cable bandwidth as calculation base. We calculate the bit counts of
carrier within a unit time. Because of the existence of inter frame gap, In our calculation 100%
utilization is impossible. So the above two cases (64 byte packet size and 1518 byte packet size with
min. IFG ), we will count as 85.7% and 99.2%.
If using SB test result to indicate utilization LED the value must be modified. See the following
reference table.
ASIX’ s Utilization%
SmartBit’ s Utilization%
1
2
5
7
10
12
15
17
30
34
60
68
2.3 Buffer memory pins group
Signal Name Type Pin No.
Description
BMA[16:0]
O
88-82, Buffer address bus.
80, 79,
107-104,
102-99
BMD[7:0]
/BMWR
/BMA[15]
I/O
I/O
I/O
97-90 Buffer data bus.
78
73
Memory control pin for write.
Invert Buffer address 15.
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
2.4 Miscellaneous
Signal Name Type Pin No.
Description
LCLK
/RST
NC
I
I
133
131
110
Local Clock : Must be run at 25Mhz . Used for transmit data to PHY devices,
Reset : The chip is reset when this signal is asserted Low.
NC : No Connection When MODE=” 1” .
I/PU
or
/LSEL10
/LSEL10 : When MODE=” 0” , This pin select 10Mbps global LED status
(utilization (%) and collision (%) ) when ‘low’ ; Otherwise , 100Mbps
LED status is selected.
NC
O/ML
111
NC : No Connection When MODE=” 1” .
or
/LCOL10
MCLK
MDO
/LCOL : When MODE=” 0” , This pin drives 10Mbps collision LED directly.
MII Clock Out : 2.5MHz 10Mbps MII reference clock
Station Management Data Out : For setup PHY auto-negotiation registers.
A burst write commands are issue to setup PHY register after reset. The PHY
address 4h, 5h, 6h, 7h, 8h, 9h,Ah and Bh will be written as register 4h to
value 00A1h ( Advertise register set to 10/100 half-duplex mode)and register
0h to value 1000h(Enable auto-negotiation).
O
O
72
71
MDC
TEST1
O
I/PD
70
130
Station Management Data Clock Out : For MDO reference clock.
Test Pin : The pin is just for test mode setting purpose only. Must be pull low
when normal operation.
/TEST2
I/PU
I/PU
I
114
134
Test Pin : The pin is just for test mode setting purpose only. Must be pull high
when normal operation.
Half-duplex mode in 10Mbps : Pull low with 10K ohm resister for 10Mbps
PHY in half-duplex mode.
/HALF10
PULL_DN
11, 12, 46 Pull Down : Those pins are not use for application. Designer must pull them
136, 137 down or tie to ground.
SET2, SET1,
SET0
O
49, 48, Setup Pins : Those pins are power on configuration use. Default internal pull
47
high. If necessary, pull low with 10K ohm resister. Tie to ground is
prohibited.
VDD
I
I
1, 13, 38 POWER : +5V +/-5%
50, 55, 81
103, 109
125, 135
138
10, 14, 29 POWER: 0V
45, 54, 68
89, 98,
VSS
108, 120,
132, 139
148,
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
2.5 Power on configuration setup signals cross reference table
Signal Name
OPT[4]
Share with
COL_O[4]
Description
OPT[4] : Option for external device type to connect to port 4. Default ‘ high’ is
for PHY type device. Otherwise, ‘ low’ for bridge, switch or MAC type device.
TXM_MODE : Option for internal used. Default ‘ high’ user may pull the pin
‘ low’ with 10K ohm resister for reserve transmition mode alternaty.
TXM_MODE
MODE
SET2
SET1
MODE = 0 : Direct LED display mode.
MODE = 1 : Rich LED display mode.
EN_FLOW_CTL = 0 : Disable flow control function.
EN_FLOW_CTL = 1 : Enable flow control function.
ST_FW = 0 : Fragment free forwording mode.
ST_FW = 1 : Store & forword forwording mode.
ENTRIES = 0 : 1024 entries supported
EN_FLOW_CTL SET0
ST_FW
TXD[4][3]
ENTRIES
TXD[4][2]
ENTRIES = 1 : 256 entries supported
MEM_SIZE[1]
MEM_SIZE[0]
TXD[4][1]
TXD[4][0]
MEM_SIZE[1] MEM_SIZE[0]
SIZE (K)
32K
64K
128K
N/A
1
1
0
0
1
0
1
0
/IR_ACT_EN
/BMWR
Inter Repeater Active Input Pin Enable : Designer must keep the pin pull high
to disable the function.
All of the above signals are pull-up for default values.
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
3.0 Functional Description
3.1 Repeater State Machine
The repeater state machine is used to control repeater behavior, generates right signal in corresponding
states. The repeater state machine is in Idle state when there is no carrier presented on any ports . When there
is only one port has receive activity, the repeater state machine will enter Data - forwarding State to ensure
correct data forwarding to other connected ports. If collision happens anytime, The repeater state machine
detects collision then send jam pattern to all ports until collision ceases.
idle State
The idle state happens when these conditions exists:
a. /RST is low.
b. All CRS[4:0] are not asserted high in single chip application.
Data Forwarding State
The state happens when the condition exists:
a. Only one signal asserted among CRS[4:0] in single chip application.
The repeater state machine stores receiving packet and transmits to all other ports except for
1. The port is jabbered.
2. The port is isolated.
Collision State
The Collision State happens when these conditions exists:
a. There are two or more signals asserted high among CRS[4:0] in single chip system.
b. Only one carrier exists but RXDV still low exceeds 4 clock cycles in 100BASE-T. The
repeater sends collision pattern to all ports.
One Port Left State
The state happens only when there is no collision but still one port which experienced collision
has receive activity. The repeater remains send collision pattern to all ports except the port.
3.2 RXE /TXE CONTROL
Idle state
The repeater sends no data to any port.
RXE(ALL) = 0.
TXE(ALL) = 0.
Data Forwarding state
If ACTIVE(X) = 1, X is the local connected port,
RXE(X) = 1, RXE(ALL-X) = 0.
TXE(X) = 0, TXE(ALL-X) = 1.
Collision state
The repeater sends jam pattern to all ports.
RXE(ALL) = 0.
TXE(ALL) = 1.
One Port Left state
The repeater sends jam pattern to all other port except for the still activity port.
RXE(ALL) = 0.
TXE(ALL-X) = 1. Suppose X is the one left port.
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
3.3 Jabber State Machine
To prevent an illegally long reception of data from reaching the repeater unit, each port has its own jabber
timer. If a reception exceeds this duration (64K bit times for AX88875A), the jabber condition will be detected.
In this condition, repeater unit will disable receive and transmit packets for the jabbered port and the other ports
remain the normal operation.
When the carrier is no longer detected for the jabbered port or reset the repeater, the jabber function will be
clear and re-enable reception and transmission.
3.4 Partition State Machine
The partition state machine is used to protect network from being upset when a port suffer continuous
collision, each port uses a partition state machine to detect and prevent this condition. When a port suffer from
continuous 64 times of collision events, then it goes to partition state. The partitioned port will be not released
until a packet without collision be transmitted( more than 512 bit times for AX88875A) or reset the repeater.
3.5 LED Display Interface
AX88875A provides per-port LED status indication for partition, jabber, activity and support rate -
based LED for global partition and collision, utilization (%) for 10/100Mbps. .Detail function is described on
the previous pin description(LED interface). LED[2:0] are all active low. There are two display ways :
complicated and simple way. It depends on the setting of MODE.
Rich LED display application (MODE = 1)
LED[2:0] Status Driver Wave-form as follows :
LED_CK
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9 D10 D11 D12 D13 D14 D15
PART
4
PART PART
PART PART
JAB4
JAB3 JAB2
JAB1 JAB0
3
2
1
0
LED[0]
LED[1]
LED[2]
G
RAM
PART FAIL
100M 10M
GCOL GCOL
'0'
ACT 4
ACT 3 ACT 2
ACT 1 ACT 0
10M 10M 10M 10M 10M 10M 10M
UTI7 UTI6 UTI5 UTI4 UTI3 UTI2 UTI1
10M 100M 100M 100M 100M 100M 100M 100M 100M
UTI0 UTI7 UTI6 UTI5 UTI4 UTI3 UTI2 UTI1 UTI0
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
Notes: a. PART4~0indicates partition status for each port b. JAB4~0 indicates jabber status for each port
c. ACT4~0 indicates activity status for each port
e. 10M UTI4~0 indicate global utilization rate of
10Mbps for each 104.8ms sampling period.
g. 10M GCOL indicate global collision
d. RID2~0 is the ID of repeater chip
f. 100M UTI4~0 indicate global utilization rate of
100Mbps for each 104.8ms sampling period.
h. 100M GCOL indicate global collision
J. RAM FAIL : Bridge RAM test fail.
i. GPART : indicate global partition.
It must use external shift register to decode data on LED[2:0]. The application shows as follows:
Q
4
Q
0
Q
1
Q
2
Q
3
Q
6
Q
0
Q
1
Q
2
Q
3
Q
4
Q
5
Q
6
Q
7
Q
5
Q
7
LED[0]
74LS164(#2)
D
D
74LS164(#1)
LED_CK
Fig - 4 Application for LED display
If the user don‘ t want to show jabber status, take away the latter 74LS164(#2). The application is the
same for LED[2:1].
Simple LED display application (MODE=0)
LED display for mode 1 vs. mode 0 referance table.
Mode 1
NC
NC
NC
NC
Mode 0
/PART[0]
/PART[1]
/PART[2]
/PART[3]
/PART[4]
Mode 1
NC
NC
NC
NC
Mode 0
/ACT[0]
/ACT[1]
/ACT[2]
/ACT[3]
/ACT[4]
Mode 1
LED[0]
LED[1]
LED[2]
LED_CK
NC
NC
NC
/LCOL100
Mode 0
/UTI[0]
/UTI[1]
/UTI[2]
/UTI[3]
/UTI[4]
/UTI[5]
/LCOL10
/LCOL100
NC
NC
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
4.0 INTERNAL REGISTERS
4.1 Configuration Register (CONFIG)
Bit
D9
Bit Name
/HALF10
Access
Bit Description
R/W Half-duplex mode in 10Mbps : “low” resister to 10Mbps PHY in half-
duplex mode. “high” resister to 10Mbps PHY in full-duplex mode.
R/W OPT[4] : Option for external device type to connect to port 4. Default
‘ high’ is for PHY type device. Otherwise, ‘ low’ for bridge, switch or
MAC type device.
D8
OPT[4]
D7
D6
TXM_MODE
MODE
R/W TXM_MODE : Option for internal used. Default ‘ high’ user may pull the
pin ‘ low’ with 10K ohm resister for reserve transmition mode alternaty.
R/W
MODE = 0 : Single chip repeater application.
MODE = 1 : Multiple chips cascaded repeater application.
R/W EN_FLOW_CTL = 0 : Disable flow control function.
EN_FLOW_CTL = 1 : Enable flow control function.
D5
D4
EN_FLOW_
CTL
ST_FW
R/W
ST_FW = 0 : fragment-free mode
ST_FW =1 : Store-n-Forward mode
ENTRIES = 0 : 1024 entries supported
D3
ENTRIES
R/W
ENTRIES = 1 : 256 entries supported
R/W MEM_SIZE[1] MEM_SIZE[1]
D2-1
MEM_SIZE[1]
MEM_SIZE[0]
SIZE (K)
32K
64K
128K
N/A
1
1
0
0
1
0
1
0
D0
/IR_ACT_EN
R/W Inter Repeater Active Input Pin Enable : Designer must keep the pin pull
high to disable the function.
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
5.0 ELECTRICAL SPECIFICATION AND TIMING
5.1 Absolute Maximum Ratings
Description
SYM
Min
Max
Units
Operating Temperature
Storage Temperature
Supply Voltage
Input Voltage
Output Voltage
Ta
Ts
Vcc
Vin
Vout
Tl
0
-55
-0.5
Vss-0.5
Vss-0.5
-55
+70
+150
+7
Vdd+0.5
Vdd+0.5
+235
°C
°C
V
V
V
Lead Temperature (soldering 10 seconds maximum)
°C
Note : Stress above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure
to Absolute Maximum Ratings conditions for extended period, adversely affect device life and reliability
5.2 General Operation Conditions
Description
SYM
Min
+4.75
Max
+70
+5.25
Units
Operating Temperature
Supply Voltage
Ta
0
°C
V
Vdd
5.3 DC Characteristics
(Vdd=4.75V to 5.25V, Vss=0V, Ta=0°C to 70°C)
Description
SYM
Min
Max
Units
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
Input Leakage Current 1 (Note 1)
Input Leakage Current 2 (Note 2)
Output Leakage Current
Vil
Vss-0.5
2
0.8
Vdd+0.5
0.4
V
V
V
V
uA
uA
uA
Vih
Vol
Voh
Iil1
Iil1
Iol
2.4
10
500
10
Description
SYM
Min
Tpy
Max
Units
Power Consumption
Pc
120
160
mA
Note :
1. All the input pins without pull low or pull high.
2. Those pins had been pull low or pull high.
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
5.4 AC specifications
5.4.1 MII Interface Timing Tx & Rx
T0
T1
LCLK
T2
T2
T3
TX_EN
T3
TX_ER
TXD
Symbol
T0
Description
Local Clock Cycle Time
Local Clock High Time
TX_EN Delay from LCLK High
TX_ER or TXD Delay from LCLK High
Min
39.996
14
7.440
3.410
Typ.
40
20
Max
40.004 ns
26
21.760
13.320
Units
T1
T2
T3
ns
ns
ns
T4
T5
RX_CLK
CRS
T6
T7
RXE
T8
RXDV
T9
RXD
RXER
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
Symbol
T4
Description
RX_CLK Clock Cycle Time
RX_CLK Clock High Time
CRS to RXE Assertion Delay
CRS to RXE De-assertion Delay
CRS to RXDV Delay Requirement
RXD or RXDV or RX_ER setup to RX_CLK rise
time
Min
39.996
14
Typ.
40
20
Max
40.004
26
Units
ns
T5
T6
T7
T8
ns
ns
ns
ns
ns
20
160
40
10
200
160
-
T9
5.4.2 SRAM read cycle and write cycle
T1
BMA[16:0]
/BMWR
BMD[7:0]
T2
T3
Symbol
T1
Description
Min
40
3
Max
Units
Read Cycle Time
-
-
-
ns
ns
ns
T2
T3
BMD[7:0] Setup Time
BMD[7:0] Hold Time
3
T4
BMA[16:0]
/BMWR
T5
BMD[7:0]
T6
T7
Symbol
T4
Description
Min
38
20
14
1
Max
Units
ns
ns
ns
ns
Write Cycle Time
Write Pulse Wtdth
-
-
-
T5
T6
T7
BMD[7:0] Data Valid to End of Write
BMD[7:0] Data Hold from End of Write
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
5.4.3 LED DISPLAY
T3
LED_CK
--------
-------
-
D0
D1
D2
.............. D14 D15
D0
D1
D2
T4
T3
LED_CK
T1
T2
LED[2:0]
D0
D1
D2
D3
-------
D15
D0
Symbol
Description
Min
Typ.
Max
Units
T1
T2
T3
T4
LED setup to LED_CK High
LED hold from LED_CK High
LED_CK Period Width
190
200
200 ns
210 ns
ns
400
52.4
continuous 16 LED_CK Cycle Time
ms
5.4.4 LED Display After Reset
/Reset
T1
T2
T2
T2 T3
LED[2:0]
Symbol
T1
Description
Min
1000
Typ.
Max
Units
ns
Repeater reset time
T2
T3
LED Blink Time After Reset
LED Dark Time Before Normal Display
838.4
419.2
ms
ms
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
6.0 PACKAGE INFORMATION
He
A2 A1
E
e
pin 1
b
q
SYMBOL
MILIMETER
NOM
MIN.
0.25
MAX
A1
A2
b
3.15
3.40
0.30
3.65
0.38
0.22
D
27.90
27.90
28.00
28.00
0.65
28.10
28.10
E
e
Hd
He
L
30.95
30.95
0.73
31.20
31.20
31.45
31.45
1.03
L1
q
1.60
0
7°
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
Appendix A: Applications
Two type of applications for AX88875A are illustrated bellow.
A.1 Stand-along 5-ports 10/100Mbps HUB Application
8 bits
SRAM
LED Array
AX88875A
Bripeater Controller
MII interface
MII interface
Quad
MII
Single
MII
Transceiver
Transceiver
Fig - 5 Stand-along 5-ports 10/100Mbps HUB Application
A.2 Stand-along 4-ports 10/100Mbps HUB with one MAC Application
8 bits
SRAM
LED Array
AX88875A
Bripeater Controller
MII interface
MII interface
Quad
MII
Transceiver
AX88195
MAC
CPU
Fig - 6 Stand-along 4-ports 10/100Mbps HUB with one MAC Application
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ASIX ELECTRONICS CORPORATION
AX88875AP Bripeater
Appendix B: Using MII I/F connects to MAC
Using MII interface to connect to MAC type device application for AX88875A is illustrated bellow.
25MHz
Clock
COL_O4
TXEN4
COL
10K
Gnd
CRS
RX_DV
RX_CLK
RXD[3:0]
RX_ER
(LCLK)
TXD4[3:0]
TXER4
CRS4
TX_EN
RXDV4
RXCLK4
RXD4[3:0]
RXER4
TX_CLK
TXD[3:0]
TX_ER
AX88875 / Repeater
AX88195 / MAC
Note : 1. The MAC needs to run at halfduplex mode.
2. Care must be taken that the receive side has enough setup and/or hold time
3. Some kind of CPU with embbeded MAC can also refer to this example
Using MII interface to connect to 10Mbps MAC device application for AX88875A is illustrated bellow.
COL_O4
COL
10K
Gnd
TXEN4
CRS
RX_DV
RX_CLK
RXD[3:0]
RX_ER
MCLK
TXD4[3:0]
TXER4
CRS4
TX_EN
RXDV4
RXCLK4
RXD4[3:0]
RXER4
TX_CLK
TXD[3:0]
TX_ER
AX88875 / Repeater
10Mbps MAC
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