AX88796BLF [ASIX]
Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller; 低引脚数的非PCI 8位/ 16位10 / 100M快速以太网控制器
| 型号： | AX88796BLF |
| 厂家： | 
ASIX ELECTRONICS CORPORATION |
| 描述： | Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller |
| 文件： | 总82页 (文件大小：605K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
AX88796BLF / AX88796BLI
Low-pin-count Non-PCI 8/16-bit
10/100M Fast Ethernet Controller
Features
Document No.: AX88796B_17/08/18/07
Support VLAN match filter
High-performance non-PCI local bus
Support both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series CPU and ISA
bus
SRAM-like host interface, easily interfaced to most
common embedded MCUs
Support Wake-on-LAN function to reduce power by
following events
Detection of a change in the network link state
Receipt of a Magic Packet
Receipt of a MS wakeup frame
Embed 8Kx16 bits SRAM for packet buffers
Support Slave-DMA to minimize CPU overhead
Support burst-mode read for highest performance
applications
NE2000 register level compatible instruction
Detection performance can be enhanced with only a
minor host driver modification from original
NE2000 driver
Interrupt pin with programmable Hold-off timer
Single-chip Fast Ethernet controller
Compatible with IEEE802.3, 802.3u standards
Integrate Fast Ethernet MAC/PHY transceiver in
one chip
Support 10Mbps and 100Mbps data rate
Support full and half duplex operations
Support 10/100Mbps N-way Auto-negotiation
operation
Support EEPROM interface to store MAC address
(Optional)
Support up to 2 (out) /1 (in/out) General Purpose pins
Support LED pins for various network activity
indications
Integrate voltage regulator and 25MHz crystal
oscillator
0.18um CMOS process. 3.3V power supply with 5V
tolerance I/O pins
64-pin LQFP , RoHS package
Operate over 0 to +70 °C or -40 to +85 °C temperature
range
Support twisted pair crossover detection and
auto-correction (HP Auto-MDIX)
Support IEEE 802.3x flow control for full-duplex
operation
US patent approved (NO 6799231)
Support back-pressure flow control for half-duplex
operation
Product description
The AX88796B is a low-pin-count (64-pin LQFP) non-PCI Ethernet controller for the Embedded and Industrial Ethernet
applications. The AX88796B supports 8/16-bit SRAM-like host interface, providing a glue-less connection to most
common embedded MCUs. The AX88796B integrates on-chip Fast Ethernet MAC and PHY, which is IEEE802.3
10Base-T and IEEE802.3u 100Base-TX compatible, and 8Kx16 bits embedded SRAM for packet buffering to
accommodate high bandwidth applications. The AX88796B has a wide array of features including support for Twisted
Pair Crossover Detection and Auto-Correction, Wake-on-LAN power management, and IEEE 802.3x and back-pressure
flow control. The AX88796B supports two operating temperature ranges, namely, commercial grade from 0 to 70 °C and
industrial grade from –40 to 85 °C. The small form factor of 64-pin LQFP package helps reduce the overall PCB space.
The programming of AX88796B is simple and compatible with NE2000, so the users don’t need any modification and
can easily port the software drivers to many embedded systems very quickly. Combining these features with ASIX’s free
TCP/IP software stack for 8-bit microcontrollers, AX88796B provides the best Ethernet solution for embedded
networking applications.
System Block Diagram
General
processor
51 series
/
186 bus
series
/
8bit / 16bit
Non-PCI bus
Address
AX88796B
With
10/100 Mbps
PHY
AX88796B
With
10/100 Mbps
PHY
CSn
RDn / WRn
Data Bus
ISA bus
Interrupt
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No
liability is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
First Released Date : 2006 / 03 / 01
4F, NO.8, HSIN ANN Rd., Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500 FAX: 886-3-579-9558
http://www.asix.com.tw
AX88796BLF / AX88796BLI
CONTENTS
1.0 INTRODUCTION......................................................................................................................................................4
2.0 SIGNAL DESCRIPTION..........................................................................................................................................6
3.0 MEMORY AND CSR MAPPING............................................................................................................................9
4.0 BASIC OPERATION ..............................................................................................................................................12
5.0 REGISTERS OPERATION....................................................................................................................................30
6.0 CPU READ AND WRITE FUNCTIONS ..............................................................................................................59
7.0 ELECTRICAL SPECIFICATION AND TIMINGS ............................................................................................62
8.0 PACKAGE INFORMATION .................................................................................................................................72
9.0 ORDERING INFORMATION ...............................................................................................................................73
APPENDIX A1: MCS51-LIKE (8-BIT)......................................................................................................................74
APPENDIX A2: ISA-LIKE (8/16-BIT).......................................................................................................................75
APPENDIX A3: 186-LIKE (16-BIT)...........................................................................................................................76
APPENDIX A4: CO-WORK WITH 32-BIT PROCESSOR.....................................................................................77
APPENDIX A5: BIG-ENDIAN PROCESSOR OF DATA BYTE LANDS.............................................................79
APPENDIX B: DISABLE AX88796B VOLTAGE REGULATOR..........................................................................80
REVERSION HISTORY...............................................................................................................................................81
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
FIGURES
FIG - 1 AX88796B BLOCK DIAGRAM.................................................................................................................................4
FIG - 2 AX88796B PIN OUT DIAGRAM...............................................................................................................................5
FIG - 3 INTERNAL SRAM MAP ..........................................................................................................................................11
FIG - 4 RECEIVE BUFFER RING..........................................................................................................................................15
FIG - 5 RECEIVE BUFFER RING AT INITIALIZATION...........................................................................................................16
FIG - 6 TX / RX FLOW CONTROL......................................................................................................................................26
FIG - 7 EEPROM CONNECTIONS.......................................................................................................................................28
FIG - 8 PME AND IRQ SIGNAL GENERATION.....................................................................................................................29
FIG - 9 SMI CONNECTIONS................................................................................................................................................61
TABLES
TAB - 1 LOCAL CPU BUS INTERFACE SIGNALS GROUP ........................................................................................................7
TAB - 2 10/100MBPS TWISTED-PAIR INTERFACES PINS GROUP...........................................................................................7
TAB - 3 BUILT-IN PHY LED INDICATOR PINS GROUP .........................................................................................................7
TAB - 4 EEPROM BUS INTERFACE SIGNALS GROUP............................................................................................................7
TAB - 5 MISCELLANEOUS PINS GROUP .................................................................................................................................8
TAB - 6 EEPROM DATA FORMAT EXAMPLE .......................................................................................................................9
TAB - 7 CSR ADDRESS MAPPING .....................................................................................................................................10
TAB - 8 LOCAL MEMORY MAPPING ..................................................................................................................................10
TAB - 9 INTERNAL SRAM MAP 00H ~ 1FH.....................................................................................................................10
TAB - 10 INTERNAL SRAM MAP 0400H ~ 040FH ...........................................................................................................10
TAB - 11 BYTE LANE MAPPING ........................................................................................................................................27
TAB - 12 POWER MANAGEMENT STATUSES......................................................................................................................28
TAB - 13 PAGE 0 OF MAC CORE REGISTERS MAPPING ....................................................................................................31
TAB - 14 PAGE 1 OF MAC CORE REGISTERS MAPPING ....................................................................................................32
TAB - 15 PAGE 2 OF MAC CORE REGISTERS MAPPING ....................................................................................................33
TAB - 16 PAGE 3 OF MAC CORE REGISTERS MAPPING ....................................................................................................34
TAB - 17 THE EMBEDDED PHY REGISTERS ......................................................................................................................53
TAB - 18 SMI MANAGEMENT FRAME FORMAT.................................................................................................................61
TAB - 19 MII MANAGEMENT FRAMES- FIELD DESCRIPTION.............................................................................................61
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
1.0 Introduction
1.1 General Description:
The AX88796B provides industrial standard NE2000 registers level compatible instruction set. Various drivers are
easily acquired, maintained, and used and no much additional effort is required. Software is easily port to various
embedded systems with no pain and tears. AX88796B also provides transmit queuing function to enhance standard
NE2000 of transmitting performance.
The AX88796B Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet
Controller with embedded 10/100Mbps PHY/Transceiver and 8K*16 bit SRAM. The AX88796B supports both
8/16-bit local CPU interfaces including MCS-51 series, 80186 series, ISA bus and high-performance SRAM-like
interface. The simple host interface provides a glue-less connection to most common microprocessors and
microcontrollers. The AX88796B provides both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 /
IEEE802.3u LAN standard.
1.2 AX88796B Block Diagram:
(Optional)
Fig - 1 AX88796B Block Diagram
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
1.3 AX88796B Pin Connection Diagram
The AX88796B is housed in the 64-pin plastic light quad flat pack. Fig - 2 shows the AX88796B pinout
diagram.
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
SA1 49
SA0 50
32 SD10
31 SD11
30 SD12
29 SD13
28 SD14
27 SD15
26 GND
25 VCC3IO
24 VCCK
23 IRQ
AEN,PSEN 51
CSn 52
RDn 53
WRn 54
IOIS16 55
TCLK 56
AX88796B
TEST_CK_EN 57
GND 58
VCCK 59
22 PME
VCC18A 60
XTALIN 61
XTALOUT 62
GND18A 63
RSET_BG 64
o
21 EECS
20 EECK
19 EEDIO
18 GND
17 RSTn
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16
Fig - 2 AX88796B Pin Out Diagram
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
2.0 Signal Description
The following abbreviations are used in AX88796B pinout:
All pin names with the “n” suffix are low-active signals.
The following abbreviations are used in following Tables.
I
O
I5
Input 1.8V
Output 1.8V
Input 3.3V with 5V tolerant
8m 8mA driving strength
S Schmitt trigger
PU Internal Pull Up 75Kohm
PD Internal Pull Down 75kohm
O5 Output 3.3V with 5V tolerant
T5
B5
Tri-state with 5V tolerant
Bi-directional I/O, 3.3V with 5V tolerant
P
A
Power Pin
Analog
4m 4mA driving strength
2.1 Local CPU Bus Interface Signals Group
Signal
SA[4:0]
Type
I5
Pin No.
Description
46, 47, 48, 49, System Address: Signals SA[4:0] are address bus input lines. Used to
50
45
select internal CSR’s.
System Address or FIFO Select: When driven high, all accesses to the
AX88796B are to the RX or TX data buffer FIFO (DP).
SA[5] or
FIFO_SEL
I5/PD
AX88796B supports two kinds of Data Port for receiving/transmitting
packets from/to AX88796B. One is the PIO Data Port (offset 10h);
the other one is the SRAM-like Data Port (e.g. offset 800h ~ FFFh for
Samsung2440 processor as described in Appendix A4 of AX88796B
datasheet). The SRAM-like Data Port address range depends on
which address line of host processor is being connected to the address
line SA5/FIFO_SEL of AX88796B.
Software on host CPU can issue Single Data Read/Write command to
both PIO Data Port and SRAM-like Data Port. However, to use Burst
Data Read/Write commands, one has to use SRAM-like Data Port,
which requires SA5/FIFO_SEL (pin 45) of AX88796B connecting to
an upper address line of host CPU. Our reference schematic has
SA5/FIFO_SEL pin connected to upper address line for supporting
Burst Data Read/Write commands.
SD[15:0]
IRQ
B5/8m
27, 28, 29, 30, System Data Bus: Signals SD[15:0] constitute the bi-directional data
31, 32, 33, 34, bus.
35, 36, 37, 38,
39, 40, 41, 42
O5/T5/8m
23
Programmable Interrupt request. Programmable polarity, source and
buffer types.
Can be configure by EEPROM auto-loader or BTCR (offset 15h)
Chip Select: Active low.
CSn
RDn
WRn
I5
I5
I5
52
53
54
Read: Active low strobe to indicate a read cycle.
Write: Active low strobe to indicate a write cycle. This signal also
used to wakeup the AX88796B when it is in reduced power state.
16 Bit Port: For ISA bus used. The IOIS16n is asserted when the
address at the range corresponds to an I/O address to which the chip
responds, and the I/O port addressed is capable of 16-bit access.
Address Enable: When 186, ISA mode, this signal is active low to
access AX88796B.
IOIS16n
T5/8m
I5
55
51
AEN or PSEN
PSEN: When 51 modes, this signal is active high to access
AX88796B.
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
PME
O5/T5/8m
22
Wakeup Indicator: When programmed to do so, is asserted when the
AX88696B detects a wake event and is requesting the system to wake
up from the D1 sleep state. The polarity and buffer type of this signal
is programmable by BTCR (offset 15h)
Tab - 1 Local CPU bus interface signals group
2.2 10/100Mbps Twisted-Pair Interface pins group
Signal
Type
AB
Pin No.
Description
Twisted Pair Receive Input, Positive
TPI+
TPI-
3
AB
AB
AB
4
6
7
Twisted Pair Receive Input, Negative
Twisted Pair Transmit Output, Positive
Twisted Pair Transmit Output, Negative
TPO+
TPO-
RSET_BG
AO
64
Off-chip resister. Must be connected 12.1K ohm ±1% to ground.
Tab - 2 10/100Mbps Twisted-Pair Interfaces pins group
2.3 Built-in PHY LED indicator pins group
Signal
Type
Pin No.
Description
I_FULL/COL
O5/8m
16
Full-Duplex/Collision Status. If this signal is low, it indicates
full-duplex link established, and if it is high, then the link is in
half-duplex mode. When in half-duplex and collision occurrence, the
output will be driven low for 80ms and driven high at minimum 80ms.
Speed Status: If this signal is low, it indicates 100Mbps, and if it is
high, then the speed is 10Mbps.
Link Status/Active: If this signal is low, it indicates link, and if it is
high, then the link is fail. When in link status and line activity
occurrence, this signal is pulsed high (LED off) for 80ms whenever
transmit or receive activity is detected. This signal is then driven low
again for a minimum of 80ms, after which time it will repeat the
process if TX or RX activity is detected.
I_SPEED
O5/8m
O5/8m
15
14
I_LK/ACT
Tab - 3 Built-in PHY LED indicator pins group
2.4 EEPROM Signals Group
Signal
Type
B5/4m/PD
B5/4m/PD
Pin No.
21
Description
EECS
EECK
EEPROM Chip Select: EEPROM chip select signal.
EEPROM Clock: Signal connected to EEPROM clock pin.
EECS, EECK can load BUS type setting during power on reset cycle.
20
EECS
EECK
BUS TYPE
0
0
1
1
0
1
0
1
ISA BUS / SRAM-Like
80186
Reserved
MCS-51 (805X)
EEDIO
B5/4m/PU
19
EEPROM Data In/Out: Signal connected to EEPROM data input and
data output pin.
Tab - 4 EEPROM bus interface signals group
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
2.5 Miscellaneous pins group
Signal
XTALIN
Type
I
Pin No.
Description
61
Crystal/Oscillator Input: A 25Mhz crystal, +/- 50 PPM can be
connected across XTALIN and XTALOUT.
CMOS Local Clock: A 25Mhz clock, +/- 50 PPM, 40%-60% duty
cycle. Note that the pin does not support 3.3V or 5V voltage supply.
Crystal/Oscillator Output: A 25Mhz crystal, +/- 50 PPM can be
connected across XTALIN and XTALOUT. If a single-ended external
clock (LCLK) is connected to XTALIN, the crystal output pin should
be left floating.
XTALOUT
RSTn
O
62
17
I5/S
Reset:
Reset is active low then place AX88796B into reset mode. During the
rising edge the AX88796B loads the power on setting data.
Test Clock Pins: As a clock input for ASIC testing only
No connection when normal operation
Enable TCLK in to ASIC as a main clock for test only.
No connection when normal operation
TEST mode select
Connect to ground when normal operation
TEST mode select
TCLK
I5/PD
I5/PD/S
I5/S
56
57
12
13
TCLK_EN
TEST2
TEST1
I5/S
Connect to ground when normal operation
VCC3A3
GND3A3
VCC18A
P
P
P
1
2
5, 60
Power Supply for Analog Circuit: +3.3V DC.
Power Supply for Analog Circuit: +0V DC or Ground Power.
Analog power for oscillator, PLL, and Ethernet PHY differential I/O
pins, 1.8V
GND18A
P
8, 63
Analog ground for oscillator, PLL, and Ethernet PHY differential I/O
pins.
V18F
P
P
P
P
P
P
9
10
11
On-chip 3.3V to 1.8V Regulator output +1.8V DC.
On-chip 3.3V to 1.8V Regulator power supply: +3.3V DC.
On-chip 3.3V to 1.8V Regulator ground.
VCC3R3
GND3R3
GND
VCC3IO
VCCK
18, 26, 58 Ground.
25, 44
24, 43, 59 Power Supply for core logic: +1.8V DC.
Power Supply for IO: +3.3V DC.
Tab - 5 miscellaneous pins group
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
3.0 Memory and CSR Mapping
1. EEPROM Memory Mapping
2. CSR Mapping
3. Local Memory Mapping
3.1 EEPROM Memory Mapping
EEPROM interface can access via CSR offset 14h SMI/EEPROM registers when auto load operation completed.
The content of EEPROM data will be auto-loaded to internal memory from 0000h to 001Fh and from 0400h to
040Fh automatically when hardware reset. It is similar to NE2000 PROM store Ethernet address. The real MAC
address must configured by PAR0 ~ PAR5 (CR page1 offset1 ~ offset6). The auto-loader only write to internal
SRAM not write to PAR0 ~ PAR5. An example as below, if the desired Ethernet physical address is
10-32-54-76-98-BA
It is a programmed EEPROM if auto-load value is 5AA5h from EEPROM address 0h. After hardware reset the
EEPROM loader will read first word and check pattern 5AA5h. If the first word value not equal to 5AA5h then the
EEPROM loader proclaimed that no external EEPROM or external EEPROM is a non-programmed EEPROM.
Addr Bits
D[15:8]
BAh
D[7:0]
98h
Description
5h
4h
3h
2h
[15:0]
[15:0]
[15:0]
[15:11]
MAC address 6th, 5th
MAC address 4th, 3rd
76h
54h
32h
10h
MAC address 2nd, 1st (multicast bit is 1st of bit_0)
No define
Always zero
[10:8] PHY_CONFIG
Configure internal PHY in different ways, such as 10BASE_T
half-duplex mode. If EEPROM auto loader not found 5AA5h
pattern in first word then internal PHY will be not been manual
configuration. (Default is Auto-negotiation enable with all
capabilities)
[10:8]
000
001
Function
Auto-negotiation enable with all capabilities
Auto-negotiation with 100BASE-TX FDX / HDX
ability
010
Auto-negotiation with 10BASE-T FDX / HDX
ability
011
100
101
110
111
Reserved
Manual selection of 100BASE-TX FDX
Manual selection of 100BASE-TX HDX
Manual selection of 10BASE-T FDX
Manual selection of 10BASE-T HDX
[7:6]
[5]
No define
Always zero
IRQ_TYPE_EEP This bit will logic OR with BTCR (15h) bit-5 and will been
clear when host write BTCR. (Offset 15h)
[4]
IRQ_POL_EEP This bit will logic OR with BTCR (15h) bit-4 and will been
clear when host write BTCR. (Offset 15h)
[3]
[2]
No define
Always zero
NE2000_PROM When set, AX88796B internal memory map of 1Ch ~ 1Fh will
be configured to 57h. An ASCII code “W”. Otherwise
configured to 42h. An ASCII code “B”.
[1:0]
No define
Always zero
1h
0h
[15:0]
[15:0]
00h
06h
Indicates the total of word counts for auto loading
Programmed pattern
5Ah
A5h
Tab - 6 EEPROM data format example
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
3.2 CSR Mapping
System I/O Offset
0000H ~ 001FH
Function
AX88796B Command Status Register
Tab - 7 CSR Address Mapping
3.3 Internal SRAM Memory Mapping
Offset
Function
Load from EEPROM
Reserved
Load from EEPROM
Reserved
NE2000 compatible mode
8K x 16 SRAM Buffer
Reserved
0000H ~ 001FH
0020H ~ 03FFH
0400H ~ 040FH
0410H ~ 3FFFH
4000H ~ 7FFFH
8000H ~ FFFFH
Tab - 8 Local Memory Mapping
SRAM Address
1EH
1CH
1AH ~ 10H
0AH
D[15:8]
57H / 42H
57H / 42H
00H
D[7:0]
57H / 42H
57H / 42H
00H
BAH
98H
76H
54H
32H
10H
BAH (E’NET ADDRESS 5)
98H (E’NET ADDRESS 4)
76H (E’NET ADDRESS 3)
54H (E’NET ADDRESS 2)
32H (E’NET ADDRESS 1)
10H (E’NET ADDRESS 0)
08H
06H
04H
02H
00H
Tab - 9 Internal SRAM Map 00H ~ 1FH
SRAM Address
40EH
0406H ~ 040DH
0404H
D[15:8]
57H
00H
D[7:0]
57H
00H
BAH (E’NET ADDRESS 5) 98H (E’NET ADDRESS 4)
0402H
0400H
76H (E’NET ADDRESS 3)
32H (E’NET ADDRESS 1)
54H (E’NET ADDRESS 2)
10H (E’NET ADDRESS 0)
Tab - 10 internal SRAM Map 0400H ~ 040FH
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
AX88796B internal memory address mapping
0h ~ 1Fh, Auto load MAC address
from external EEPROM
(0000h)
20h ~ 03FFh, Reserved
0400h ~ 040Fh, Auto load MAC
address from external EEPROM
0410h ~ 3FFFh, Reserved
(3FFFh)
TX Page Start Address (Page 0x40)
Page 0x40
(4000h)
Transmit
buffer
Page Start (Page 0x4C)
(4C00h)
Boundary Page Start (Page 0x4C)
Page 0x4C
(4C00h)
Current Page (Page 0x4D)
ꢀ Every page equal to 256 Bytes
ꢀ Address of first BYTE in packet buffer
Receive buffer
SRAM is Page 0x40, offset 0
ꢀ Address of last BYTE in packet buffer
SRAM is Page 0x7F, offset 0xff
Page 0x7F
Page Stop (Page 0x80)
(8000h)
Page 0x80
(8000h)
Fig - 3 Internal SRAM map
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ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
4.0 Basic Operation
4.1 Receiver Filtering
The address filtering logic compares the Destination Address Field (first 6 bytes of the received packet) to the
Physical address registers stored in the Address Register Array. If any one of the six bytes does not match the
pre-programmed physical address, the Protocol Control Logic rejects the packet. This is for unicast address filtering.
All multicast destination addresses are filtered using a hashing algorithm. (See following description.) If the
multicast address indexes a bit that has been set in the filter bit array of the Multicast Address Register Array the
packet is accepted, otherwise the Protocol Control Logic rejects it. Each destination address is also checked for all
1’s, which is the reserved broadcast address.
4.1.1 Unicast Address Match Filter
The physical address registers are used to compare the destination address of incoming packets for rejecting or
accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the
sequence in PAR0-PAR5 to the bit sequence of the received packet.
D7
D6
D5
D4
D3
D2
D1
D0
PAR0
PAR1
PAR2
PAR3
PAR4
PAR5
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA9
DA17
DA25
DA33
DA41
DA0
DA8
DA16
DA24
DA32
DA40
DA15
DA23
DA31
DA39
DA47
DA14
DA22
DA30
DA38
DA46
DA13
DA21
DA29
DA37
DA45
DA12
DA20
DA28
DA36
DA44
DA11
DA19
DA27
DA35
DA43
DA10
DA18
DA26
DA34
DA42
Note: The bit sequence of the received packet is DA0, DA1, … DA7, DA8 ….
4.1.2 Multicast Address Match Filter
The Multicast Address Registers provide filtering of multicast addresses hashed by the CRC logic. All destination
addresses are fed through the 32 bits CRC generation logic and as the last bit of the destination address enters the
CRC, the 6 most significant bits of the CRC generator are latched. These 6 bits are then decoded by a 1 of 64 decode
to index a unique filter bit (FB0-63) in the Multicast Address Registers. If the filter bit selected is set, the multicast
packet is accepted. The system designer would use a program to determine which filter bits to set in the multicast
registers. All multicast filter bits that correspond to Multicast Address Registers accepted by the node are then set to
one. To accept all multicast packets all of the registers are set to all ones.
D7
D6
D5
D4
D3
D2
D1
D0
MAR0
MAR1
MAR2
MAR3
MAR4
MAR5
MAR6
MAR7
FB7
FB6
FB5
FB4
FB3
FB2
FB1
FB9
FB0
FB8
FB15
FB23
FB31
FB39
FB47
FB55
FB63
FB14
FB22
FB30
FB38
FB46
FB54
FB62
FB13
FB21
FB29
FB37
FB45
FB53
FB61
FB12
FB20
FB28
FB36
FB44
FB52
FB60
FB11
FB19
FB27
FB35
FB43
FB51
FB59
FB10
FB18
FB26
FB34
FB42
FB50
FB58
FB17
FB25
FB33
FB41
FB49
FB57
FB16
FB24
FB32
FB40
FB48
FB56
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32-bit CRC Generator
X=31 to X=26
Clock
Latch
1 of 64-bit decoder
Filter bit array
Selected bit
0 = reject, 1= accept
If address Y is found to hash to the value 32 (20H), then FB32 (ref. 4.1.2) in MAR2 should be initialized to ``1''. This
will cause the AX88796B to accept any multicast packet with the address Y.
Although the hashing algorithm does not guarantee perfect filtering of multicast address, it will perfectly filter up to
64 logical address filters if these addresses are chosen to map into unique locations in the multicast filter.
Note: The first bit of received packet sequence is 1’s stands by Multicast Address.
4.1.3 Broadcast Address Match Filter
The Broadcast check logic compares the Destination Address Field (first 6 bytes of the received packet) to all 1’s,
which is the values are “FF FF FF FF FF FF FF” in Hex format. If any bit of the six bytes does not equal to 1’s, the
Protocol Control Logic rejects the packet.
4.1.4 VLAN Match Filter
AX88796B compares the thirteenth and fourteenth bytes of receive frames. If not match with VLAN_ID1,
VLAN_ID_0 (offset 1dh, 1ch) then reject current frame. The VLAN filter will always accept VLAN_ID is zero of
receive frames due to it is 802.1q (for priority purpose) frames. The maximum length of the good packet is thus
change from 1518 bytes to 1522 bytes.
802.1Q
VLAN tagging
7 Bytes
1 Byte
SFD
6 Bytes
6 Bytes
2 B 2 B
2 B
L/T
46-1500 Bytes
Data
4 Bytes
FCS
Destination
Address
Source
Address
Layer 2
Preamble
8100 TCI
Pad
3 bits
1 bit
12 bits
VLAN ID
Priority CFI
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4.1.5 Aggregate Address Filter with Receive Configuration Setup
The final address filter decision depends on the destination address types, identified by the above 4 address match
filters, and the setup of parameters of Receive Configuration Register.
Definitions of address match filter result are as following:
Signal
Phy
Value
=1
=0
=1
=0
=1
=0
=1
=0
Description
Unicast Address Match
Unicast Address not Match
Multicast Address Match
Multicast Address not Match
Broadcast Address Match
Broadcast Address not Match
VLAN ID Match
VLAN ID not Match
Aggregate Address Match
Aggregate Address not Match
Mul
Bro
VID
AGG
=1
=0
The meaning of AB, AM and PRO signals, please refer to “Receive Configuration Register” RCR (offset 0Ch)
The meaning of VLANE signal, Please refer to “MAC Configure Register” MCR (offset 1Bh)
Aggregate Address Filter function will be:
Bro
AB
/Bro
/Mul
PRO
/Bro
Mul
AM
AGG
Phy
VID
VLANE
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4.2 Buffer Management Operation
There are four buffer memory access types used in AX88796B.
1. Packet Reception (Write data to memory from MAC)
2. Packet Transmission (Read data from memory to MAC)
3. Filling Packets to Transmit Buffer (Host fill data to memory)
4. Removing Packets from the Receive Buffer Ring (Host read data from memory)
The type 1 and 2 operations act as Local DMA. Type 1 does Local DMA write operation and type 2 does Local
DMA read operation. The type 3 and 4 operations act as Remote DMA. Type 3 does Remote DMA write operation
and type 4 does Remote DMA read operation.
4.2.1 Packet Reception
The Local DMA receives channel uses a Buffer Ring Structure comprised of a series of contiguous fixed length 256
byte (128 word) buffers for storage of received packets. The location of the Receive Buffer Ring is programmed in
two registers, a Page Start and a Page Stop Register. Ethernet packets consist of minimum packet size (64 bytes) to
maximum packet size (1522 bytes), the 256 byte buffer length provides a good compromise between short packets
and longer packets to most efficiently use memory. In addition these buffers provide memory resources for storage
of back-to-back packets in loaded networks. Buffer Management Logic in the AX88796B controls the assignment
of buffers for storing packets. The Buffer Management Logic provides three basic functions: linking receive buffers
for long packets, recovery of buffers when a packet is rejected, and recalculation of buffer pages that have been read
by the host.
At initialization, a portion of the 16k byte (or 8k word) address space is reserved for the receiver buffer ring. Two
eight bit registers, the Page Start Address Register (PSTART) and the Page Stop Address Register (PSTOP) define
the physical boundaries of where the buffers reside. The AX88796B treats the list of buffers as a logical ring;
whenever the DMA address reaches the Page Stop Address, the DMA is reset to the Page Start Address.
4000h
4
…
3
n-2
Page Start
Buffer #1
Buffer #2
Buffer #3
…
…
…
n-1
2
1
n
…
Buffer #n
Page Stop
8000h
Physical Memory Map
Logic Receive Buffer Ring
Fig - 4 Receive Buffer Ring
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Initialization Of The Buffer Ring
Two static registers and two working registers control the operation of the Buffer Ring. These are the Page Start
Register, Page Stop Register (both described previously), the Current Page Register and the Boundary Pointer
Register. The Current Page Register points to the first buffer used to store a packet and is used to restore the DMA
for writing status to the Buffer Ring or for restoring the DMA address in the event of a Runt packet, a CRC, or
Frame Alignment error. The Boundary Register points to the first packet in the Ring not yet read by the host. If the
local DMA address ever reaches the Boundary, reception is aborted. The Boundary Pointer is also used to initialize
the Remote DMA for removing a packet and is advanced when a packet is removed. A simple analogy to remember
the function of these registers is that the Current Page Register acts as a Write Pointer and the Boundary Pointer acts
as a Read Pointer.
4000h
4
…
3
n-2
Page Start
Buffer #1
Buffer #2
Buffer #3
…
Boundary Page
Current Page
n-1
2
…
…
…
1
n
Buffer #n
Page Stop
8000h
Physical Memory Map
Logic Receive Buffer Ring
Fig - 5 Receive Buffer Ring At Initialization
Beginning Of Reception
When the first packet begins arriving the AX88796B and begins storing the packet at the location pointed to by the
Current Page Register. An offset of 4 bytes is reserved in this first buffer to allow room for storing receives status
corresponding to this packet.
Linking Receive Buffer Pages
If the length of the packet exhausts the first 256 bytes buffer, the DMA performs a forward link to the next buffer to
store the remainder of the packet. For a maximal length packet the buffer logic will link six buffers to store the entire
packet. Buffers cannot be skipped when linking; a packet will always be stored in contiguous buffers. Before the
next buffer can be linked, the Buffer Management Logic performs two comparisons. The first comparison tests for
equality between the DMA address of the next buffer and the contents of the Page Stop Register. If the buffer
address equals the Page Stop Register, the buffer management logic will restore the DMA to the first buffer in the
Receive Buffer Ring value programmed in the Page Start Address Register. The second of comparison test between
the DMA address of the next buffer address and the contents of the Boundary Pointer Register. If the two values are
equal the reception is aborted. The Boundary Pointer Register can be used to protect against overwriting any area in
the receive buffer that has not yet been read. When linking buffers, buffer management will never cross this pointer,
effectively avoiding any overwrites. If the buffer address does not match either the Boundary Pointer or Page Stop
Address, the link to the next buffer is performed.
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Linking Buffers
Before the DMA can enter the next contiguous 256 bytes buffer, the address is checked for equality to PSTOP and
to the Boundary Pointer. If neither is reached, the DMA is allowed to use the next buffer.
Buffer Ring Overflow
If the Buffer Ring has been filled and the DMA reaches the Boundary Pointer Address, reception of the current
incoming packet will be discard by the AX88796B. Thus, the packets previously received and still contained in the
Ring will not be destroyed.
End Of Packet Operations
At the end of the packet the AX88796B determines whether the received packet is to be accepted or rejected. It
either branch to a routine to store the or to another routine that recovers the buffers used to store the packet.
If current of packet is accepted then AX88796B write two words of buffer header on receive buffer.
Buffer Header
NPR, Status
Description
D[15:8]: Next Page Pointer
D[7:6]: always zero
D[5]: multicast or broadcast
D[4]: runt packet
D[3]: MII error
D[2]: alignment error
D[1]: CRC error
D[0]: good packet
Length
D[15:11]: always zero
D[10:0]: packet length
Successful Reception
If the packet is successfully received as shown, the DMA is restored to the first buffer used to store the packet
(pointed to by the Current Page Register). The DMA then stores the Receive Status, a Pointer to where the next
packet will be stored and the number of received bytes. Note that the remaining bytes in the last buffer are discarded
and reception of the next packet begins on the next empty 256 byte buffer boundary. The Current Page Register is
then initialized to the next available buffer in the Buffer Ring. (The location of the next buffer had been previously
calculated and temporarily stored in an internal scratchpad register.)
Buffer Recovery For Rejected Packets
If the packet is a runt packet or contains CRC or Frame Alignment errors, it is rejected. The buffer management
logic resets the DMA back to the first buffer page used to store the packet (pointed to by CPR), recovering all
buffers that had been used to store the rejected packet. This operation will not be performed if the AX88796B is
programmed to accept either runt packets or packets with CRC or Frame Alignment errors. The received CRC is
always stored in buffer memory after the last byte of received data for the packet.
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4.2.2 Packet Transmission
The Local DMA Read is also used during transmission of a packet. Three registers control the DMA transfer during
transmission, a Transmit Page Start Address Register (TPSR) and the Transmit Byte Count Registers (TBCR0, 1).
When the AX88796B receives a command to transmit the packet pointed to by these registers, buffer memory data
will be moved into the FIFO as required during transmission. The AX88796B Controller will generate and append
the preamble, synch and CRC fields. AX88796B supports options of transmit queue function to enhance transmit
performance.
Original NE2000 Of Transmit Buffer
AX88796B remote DMA
write default operation is
continue to write next address
even over transmit buffer
area. Host can do whole
memory read / write testing.
And host must handle the
transmit data do not overwrite
receive buffer area when
performing fill transmit data
to transmit buffer.
TX Page Start Address (0x40)
Transmit buffer
Rx Page Start Register,
PSTART (CR page0, offset
01h)
Receive buffer
Options Of Transmit Buffer As A Ring
When active Transmit Buffer
Ring Enable (CR page3 of
TX Page Start Address (0x40)
offset 0Dh). AX88796B
remote DMA write operation
will role over from last
transmit page to first transmit
page. Host no need reassign
RSAR0, RSAR1 again to fill
transmit data for first page.
Transmit buffer
Rx Page Start Register,
PSTART (CR page0, offset
01h)
Receive buffer
Options Back-To-Back Transmission (TX Command Queue)
When active TX Queue Enable
TX Command Queue
(offset 1Bh), Host can continue
Pop Out
Push In
TPSR
TBCR
1, 0
Writing TXP (bit 2 of CR
register) to push TPSR and
TBCR1, 0 into AX88796B TX
command queue as long as
Transmit buffer has enough
vacancy and CTEPR (offset
1Ch) bit7 is ‘0’(Not full). After
current packet transmitted
completely, MAC TX will pop
out next TPSR and TBCR1, 0
from TX Command Queue
then transmit this packet
following CSMA/CD protocol.
It is recommended to enable
this function to enhance TX
performance.
MAC TX
function block
AX88796B will report Current of Transmit End Page
CTEPR (offset 1Ch) when every packet transmits
completed.
Host can understand AX88796B current of transmitting
buffer point by reading CTEPR.
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Transmit Packet Assembly
The AX88796B requires a contiguous assembled packet with the format shown below. The transmit byte count
includes the Destination Address, Source Address, Length Field and Data. It does not include preamble and CRC.
When transmitting data smaller than 64 bytes, AX88796B can auto padding to a minimum length of 64 bytes
Ethernet frame. The packets are placed in the buffer RAM by the system. System programs the AX88796B Core's
Remote DMA to move the data from the system buffer RAM to internal transmit buffer RAM.
The data transfer must be 16-bits (1 word) when in 16-bit mode, and 8-bits when the AX88796B Controller is set in
8-bit mode. The data width is selected by setting the WTS bit in the Data Configuration Register.
Destination Address
Source Address
Length / Type
Data
6 Bytes
6 Bytes
2 Bytes
46 Bytes
Min.
(Pad if < 46 Bytes)
General Transmit Packet Format
Transmission
Prior to transmission, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count
Registers) must be initialized. To initiate transmission of the packet the TXP bit in the Command Register is set. The
Transmit Status Register (TSR) is cleared and the AX88796B begins to pre-fetch transmit data from memory. If the
Inter-packet Gap (IPG) has timed out the AX88796B will begin transmission.
Conditions Required To Begin Transmission
In order to transmit a packet, the following three conditions must be met:
1. The Inter-packet Gap Timer has timed out
2. At least one byte has entered the FIFO.
3. If a collision had been detected then before transmission the packet back-off time must have timed out.
Collision Recovery
During transmission, the Buffer Management logic monitors the transmit circuitry to determine if a collision has
occurred. If a collision is detected, the Buffer Management logic will reset the FIFO and restore the Transmit DMA
pointers for retransmission of the packet. The COL bit will be set in the TSR and the NCR (Number of Collisions
Register) will be incremented. If 15 retransmissions each result in a collision the transmission will be aborted and
the ABT bit in the TSR will be set.
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Transmit Packet Assembly Format
The following diagrams describe the format for how packets must be assembled prior to transmission for different
byte ordering schemes. The various formats are selected in the Data Configuration Register.
D15
D8 D7
D0
D[15:8]
D[7:0]
Destination Address 1
Destination Address 3
Destination Address 5
Source Address 1
Source Address 3
Source Address 5
Type / Length 1
Data 1
Destination Address 0
Destination Address 2
Destination Address 4
Source Address 0
Source Address 2
Source Address 4
Type / Length 0
Data 0
…
…
WTS = 1 in Data Configuration Register.
This format is used with ISA or 80186 Mode.
D7
D0
Destination Address 0 (DA0)
Destination Address 1 (DA1)
Destination Address 2 (DA2)
Destination Address 3 (DA3)
Destination Address 4 (DA4)
Destination Address 5 (DA5)
Source Address 0 (SA0)
Source Address 1 (SA1)
Source Address 2 (SA2)
Source Address 3 (SA3)
Source Address 4 (SA4)
Source Address 5 (SA5)
Type / Length 0
Type / Length 1
Data 0
Data 1
…
WTS = 0 in Data Configuration Register.
This format is used with ISA or MCS-51 Mode.
Note: All examples above will result in a transmission of a packet in order of DA0 (Destination Address 0), DA1,
DA2, DA3 and so on in byte. Bits within each byte will be transmitted least significant bit first.
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4.2.3 Filling Packet to Transmit Buffer (Host fill data to memory)
The Remote DMA channel is used to both assembles packets for transmission, and to remove received packets from
the Receive Buffer Ring. It may also be used as a general-purpose slave DMA channel for moving blocks of data or
commands between host memory and local buffer memory. There are two modes of operation, Remote Write and
Remote Read Packet.
Two register pairs are used to control the Remote DMA, a Remote Start Address (RSAR0, RSAR1) and a Remote
Byte Count (RBCR0, RBCR1) register pair. The Start Address Register pair points to the beginning of the block to
be moved while the Byte Count Register pair is used to indicate the number of bytes to be transferred. Full
handshake logic is provided to move data between local buffer memory (Embedded Memory) and a bi-directional
data port.
Remote Write
A Remote Write transfer is used to move a block of data from the host into local buffer memory. The Remote DMA
will read data from the I/O port and sequentially write it to local buffer memory beginning at the Remote Start
Address. The DMA Address will be incremented and the Byte Counter will be decremented after each transfer. The
DMA is terminated when the Remote Byte Count Register reaches a count of zero.
4.2.4 Removing Packets from the Ring (Host read data from memory)
Remote Read
A Remote Read transfer is used to move a block of data from local buffer memory to the host. The Remote DMA
will sequentially read data from the local buffer memory, beginning at the Remote Start Address, and write data to
the I/O port. The DMA Address will be incremented and the Byte Counter will be decremented after each transfer.
The DMA is terminated when the Remote Byte Count Register reaches zero.
Packets are removed from the ring using the Remote DMA or an external device. When using the Remote DMA.
The Boundary Pointer can also be moved manually by programming the Boundary Register. Care should be taken to
keep the Boundary Pointer at least one buffer behind the Current Page Pointer. The following is a suggested method
for maintaining the Receive Buffer Ring pointers.
1. At initialization set up a software variable (next_pkt) to indicate where the next packet will be read. At the
beginning of each Remote Read DMA operation, the value of next_pkt will be loaded into RSAR0 and RSAR1.
2. When initializing the AX88796B set:
BNRY
= PSTART
CPR
= PSTART + 1
= PSTART + 1
next_pkt
3. After a packet is DMAed from the Receive Buffer Ring, the Next Page Pointer (second byte in AX88796B
receive packet buffer header) is used to update BNRY and next_pkt.
next_pkt
= Next Page Pointer
BNRY
= Next Page Pointer - 1
If BNRY < PSTART then BNRY = PSTOP – 1
Note the size of the Receive Buffer Ring is reduced by one 256-byte buffer; this will not, however, impede the
operation of the AX88796B. The advantage of this scheme is that it easily differentiates between buffer full and
buffer empty.
It is full when BNRY = CPR.
It is empty when BNRY = CPR-1.
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Storage Format For Received Packets
The following diagrams describe the format for how received packets are placed into memory by the local DMA
channel. These modes are selected in the Data Configuration Register.
D15
D8 D7
D0
Next Packet Pointer
Receive Status
Receive Byte Count 1
Destination Address 1
Destination Address 3
Destination Address 5
Source Address 1
Source Address 3
Source Address 5
Type / Length 1
Data 1
Receive Byte Count 0
Destination Address 0
Destination Address 2
Destination Address 4
Source Address 0
Source Address 2
Source Address 4
Type / Length 0
Data 0
…
…
WTS = 1 in Data Configuration Register.
This format is used with ISA or 80186 Mode.
D7
D0
Receive Status
Next Packet Pointer
Receive Byte Count 0
Receive Byte Count 1
Destination Address 0
Destination Address 1
Destination Address 2
Destination Address 3
Destination Address 4
Destination Address 5
Source Address 0
Source Address 1
Source Address 2
Source Address 3
Source Address 4
Source Address 5
Type / Length 0
Type / Length 1
Data 0
Data 1
…
WTS = 0 in Data Configuration Register.
This format is used with ISA or MCS-51 Mode.
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4.2.5 Other Useful Operations
Memory Diagnostics
Memory diagnostics can be achieved by Remote Write/Read DMA operations. The following is a suggested step for
memory test and assume the AX88796B has been well initialized.
1.
2.
Issue the STOP command to the AX88796B. This is accomplished be setting the STP bit in the AX88796B's
Command Register. Writing 21H to the Command Register will stop the AX88796B.
Wait for at least 1.5 ms. Since the AX88796B will complete any reception that is in progress, it is necessary
to time out for the maximum possible duration of an Ethernet reception. This action prevents buffer memory
from written data through Local DMA Write.
3.
4.
5.
6.
Write data pattern to MUT (memory under test) by Remote DMA write operation.
Read data pattern from MUT (memory under test) by Remote DMA read operation.
Compare the read data pattern with original write data pattern and check if it is equal.
Repeat step 3 to step 5 with various data pattern.
Loop-back Diagnostics
1.
2.
Issue the STOP command to the AX88796B. This is accomplished be setting the STP bit in the AX88796B's
Command Register. Writing 21h to the Command Register will stop the AX88796B.
Wait for at least 1.5 ms. Since the AX88796B will complete any reception that is in progress, it is necessary
to time out for the maximum possible duration of an Ethernet reception. This action prevents buffer memory
from written data through Local DMA Write.
3.
4.
Place the AX88796B in mode 1 loop-back. (MAC internal loop-back) This can be accomplished by setting
LB1 and LB0, of the Transmit Configuration Register to ``0,1''.
Issue the START command to the AX88796B. This can be accomplished by writing 22h to the Command
Register. This is necessary to activate the AX88796B's Remote DMA channel.
Write data that want to transmit to transmit buffer by Remote DMA write operation.
Issue the TXP command to the AX88796B. This can be accomplished by writing 26h to the Command
Register.
5.
6.
7.
8.
9.
Read data current receive buffer by Remote DMA read operation.
Compare the received data with original transmit data and check if it is equal.
Repeat step 5 to step 8 for more packets test.
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4.3 Wake-up Detection
Setting wake up Control and Status WUCS (CR page3, offset 0Ah) and D1 power saving in Power Management
Register PMR (CR page3, offset 0Bh), place the AX88796B in wake on LAN detection mode. In this mode, normal
data reception is disabled. And detection logic within the MAC examines receive data for three kinds of WOL
events.
-
-
-
Examines receive data for the pre-programmed wake-up frame patterns
Examines receive data for the Magic Packet frame patterns
Examines PHY link status change
4.3.1 Wake-up frame
AX88796B supports four programmable filters that support many different receive packet patterns. If the remote
wakeup mode is enable (in D1 sleep state). The remote wakeup function receives all frames and checks each frame
against the enabled filter and recognizes the frame as a remote wake-up frame if it passes the MAC address filtering
and CRC value match. In order to determine which bytes of the frames should be checked by the CRC-16 (x16 +x15
+x2 +1) module. AX88796B use a programmable byte mask and a programmable pattern offset for each of the four
supported filters. AX88796B also provide last byte match check and options cascade four programmable filters.
Make the four of detectors can operate simultaneously or sequentially.
The byte mask is a 32-bit field that specifies whether or not each of the 32 contiguous bytes within the frame,
beginning in the pattern offset, should be checked. If bit j in the byte mask is set, the diction logic checks byte offset
+j in the frame.
The pattern offset define on Offset 3 ~ 0 for each wake-up filter 3 ~ 0 and the real offset value equal to Offset
register multiplied by 2. (For example, The real offset value equal to 12 if set 6 on Offset register field)
Last bytes 3 ~ 0 for each wake-up filter 3 ~ 0 also. The contents of Last Byte register must equal to the last of Byte
Mask bit indicates of byte value. For example, if set Byte Mask [31:0] as 00C30003h then Byte Mask [23] is the last
byte. Thus, The contents of Last byte register must equal to byte value of offset + 23.
In order to load the 32-bits of wake up control register host driver software must perform 4 writes for every 32 bit of
registers.
The first write of 8-bit is located at [31:24]. The second write will also occupy [31:24] and shift the first write of data
to [23:16]. The first write of data will be located at [7:0] after continue 4 times of write data.
2nd
[15:8]
3rd
[23:16]
1st
[7:0]
4th
[31:24]
3
2
4
1
0
8 7 6 5 4 3 2 1 0 8
7
6
5
3 2 1 0 8 7 6 5 4 3 2 1 0 8 7 6 5 4 3 2 1 0
Byte Mask 0
Byte Mask 1
Byte Mask 2
Byte Mask 3
Wakeup Frame 1 CRC
Wakeup Frame 3 CRC
Wakeup Frame 0 CRC
Wakeup Frame 2 CRC
Offset 3
Offset 2
Offset 1
Offset 0
Last Byte 3
Last Byte 2
Last Byte 1
Last Byte 0
Cascade Command 3 Command 2 Command 1 Command 0
Command
Reserved
[2:0]
Wake-Up frame Byte Mask Register Structure
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.
For Example.
A Ping packet is configured as a Wakeup frame and AX88196B MAC address is 00 A0 0C C4 7D 69.
00 A0 0C C4 7D 69 00 0E C6 12 34 56 08 00 45 00
00 3C 01 8C 00 00 80 01 27 1E C0 09 C9 02 C0 09
C9 01 08 00 47 5C 05 00 01 00 61 62 63 64 65 66
67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76
77 61 62 63 64 65 66 67 68 69 CRC (4 bytes)
Host configure Wakeup frame registers sequences
// Go to gape3
Write CR(Offset 0h) C2h
; page3
// Set Byte Mask 0 = 00 40 08 07
Write WFBM0 (Page3, Offset 01H) 07h
Write WFBM0 (Page3, Offset 01H) 08h
Write WFBM0 (Page3, Offset 01H) 40h
Write WFBM0 (Page3, Offset 01H) 00h
; WFBM0 = 07 00 00 00h
; WFBM0 = 08 07 00 00h
; WFBM0 = 40 08 07 00h
; WFBM0 = 00 40 08 07h
// Set {Wakeup Frame 1 CRC, Wakeup Frame 0 CRC} = 00 00 2B 42h
Write WF10CRC (Offset 05H) 42h
Write WF10CRC (Offset 05H) 2Bh
Write WF10CRC (Offset 05H) 00h
Write WF10CRC (Offset 05H) 00h
// Set {Offset 3 2 1 0} = 00 00 00 06h
Write WFOFST (Offset 07H) 06h
Write WFOFST (Offset 07H) 00h
Write WFOFST (Offset 07H) 00h
Write WFOFST (Offset 07H) 00h
// Set {Last Byte 3 2 1 0} = 00 00 00 08h
Write WFLB (Page3, Offset 08H) 08h
Write WFLB (Page3, Offset 08H) 00h
Write WFLB (Page3, Offset 08H) 00h
Write WFLB (Page3, Offset 08H) 00h
; WF10CRC = 42 00 00 00h
; WF10CRC = 2B 42 00 00h
; WF10CRC = 00 2B 42 00h
; WF10CRC = 00 00 2B 42h
; WFOFST = 06 00 00 00h
; WFOFST = 00 06 00 00h
; WFOFST = 00 00 06 00h
; WFOFST = 00 00 00 06h (Offset = 6*2 = 12)
; {Last Byte 3 2 1 0} = 08 00 00 00h
; {Last Byte 3 2 1 0} = 00 08 00 00h
; {Last Byte 3 2 1 0} = 00 00 08 00h
; {Last Byte 3 2 1 0} = 00 00 00 08h
// Set {Cascade, Command 3 2 1 0} = 00 00 00 03h
Write WFCMD (Offset 09H) 03h
Write WFCMD (Offset 09H) 00h
Write WFCMD (Offset 09H) 00h
Write WFCMD (Offset 09H) 00h
match is required)
; WFCMD = 03 00 00 00h
; WFCMD = 00 03 00 00h
; WFCMD = 00 00 03 00h
; WFCMD = 00 00 00 03h (enabled wake-up frame filter 0, and DA
// Set PME and IRQ pin I/O Buffer Type (Please Ref. Datasheet Offset 15 descriptions)
Write BTCR (Offset 15H)
// Host enables wakeup frame detection then enter D1 sleep
;
Write WUCSR (Page3, Offset 0AH) 02h
Write PMR (Offset 0BH) 01h
; (Wakeup frame enable)
; (Enter D1 Sleep mode)
4.3.2 Magic Packet frame
AX88796B checks frame for 16 repetitions of the MAC address without any breaks or interruptions. The 16
repetitions may be anywhere in the frame but must be preceded by the synchronization stream
48’hFF_FF_FF_FF_FF_FF pattern. If the MAC address of a node is 00h 11h 22h 33h 44h 55h, then AX88796B
scans for the following data sequence in an Ethernet frame.
Destination Address (6 byte) Source Address (6 byte) . . . . . . . . . FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
. . . . . . . . . CRC (4 byte)
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4.4 Flow Control
The AX88796B supports Full-duplex flow control using the pause control frame. It also supports half-duplex flow
control using collision base of back-pressure method.
4.4.1 Full-Duplex Flow Control
The format of a PAUSE frame is illustrated below. It conforms to the standard Ethernet frame format but includes a
unique type field and other parameters as follows:
The destination address of the frame may be set to either the unique DA of the station to be paused, or to the globally
assigned multicast address 01-80-C2-00-00-01 (hex). The IEEE 802.3 standard for use in MAC control PAUSE
frames has reserved this multicast address. The "Type" field of the PAUSE frame is set to 88-08 (hex) to indicate the
frame is a MAC Control frame.
The MAC Control opcode field is set to 00-01 (hex) to indicate the type of MAC Control frame being used is a
PAUSE frame. The PAUSE frame is the only type of MAC Control frame currently defined.
The MAC Control Parameters field contains a 16-bit value that specifies the duration of the PAUSE event in units of
512-bit times. Valid values are 00-00 to FF-FF (hex). If an additional PAUSE frame arrives before the current
PAUSE time has expired, its parameter replaces the current PAUSE time, so a PAUSE frame with parameter zero
allows traffic to resume immediately.
A 42-byte reserved field (transmitted as all zeros) is required to pad the length of the PAUSE frame to the minimum
Ethernet frame size.
Dest. MAC
Start Frame Address
Length/Type
(2-bytes)
= 802.3 MAC
Control
MAC Control
Opcode
(2-bytes)
= PAUSE
(00-01)
MAC Control
Parameters
(2-bytes)
= (00-00 to
FF-FF)
Source
MAC
Address
(6-bytes)
Frame
Check
Sequence
(4-bytes)
Reserved
(42-bytes)
= all zeros
Preamble
(7-bytes)
Delimiter
(1-byte)
(6-bytes)
= (01-80-C2-
00-00-01)
(88-08)
AX88796B will inhibit transmit frames for a specified period of time if a PAUSE frame received and CRC is
correct. If a PAUSE request is received while a transmit frame is in progress, then the pause will take effect after the
transmitting is completed.
AX88796B base on “Rx Page Start Register” (CR page0 Offset 01h) and “Rx Page Stop Register”(CR page0 Offset
02h) to calculate and got the total of free page count can be used for store received packets. (One page equal to 256
bytes) The total of free page count will decrease when packets received. A programmable of high water
free-page-count in “Flow Control Register” (Offset 1Ah) used to measure the water level of receive buffer.
AX88796B use XOFF / XON flow-control method to avoid missing packet if receive buffer almost full. A XON
transmitting when the total of free page count equal to or less then “high water free-page-count”. A XOFF
transmitting when the total of free page count equal to or greater then (“high water free-page-count” + 6 pages).
Programmable of free-page-count
Start to generate XON
frame packet
STOP
High water mark
Packet
TX
The total of
free pages count
generate XOFF frame
6 pages
HOST
packet
Low water mark
RX
AX88796B
Packets in RX buffer
PAUSE frame
TX Flow Control
RX Flow Control
Fig - 6 TX / RX Flow control
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4.4.2 Half-Duplex Flow Control
Whenever the receive buffer becomes full crosses a certain threshold level, The MAC starts sending a Jam signal,
which will result in a collision. After sensing the collision, the remote station will back off its transmit ion.
AX88796B only generate this collision-based of back-pressure when it receives a new frame, in order to avoid any
late collisions.
A programmable of “Back-pressure Jam Limit count” (Offset 17h) is used for avoid HUB port partition due to many
continues of collisions. AX88796B will reset the “Back-pressure Jam Limit count” when either a transmitted or
received frame without collision. A back-pressure leakage allow when senses continue of collisions count up to
“Back-pressure Jam Limit count”, it will be no jamming one of receive frame even receive buffer is full.
4.5 Big- and Little-endian Support
AX88796B supports “Big-“ or “Little-endian” processor. To support big-endian processors, the hardware designer
must explicitly invert the layout of the byte lanes. In addition, for a 16-bit interface, the big-endian register must be
set correctly following the table below.
Additionally, please refer to Big-endian register (offset 1Eh), for additional information on status indication on big-
or little-endian modes.
MODE OFOPERATION AX88796B DATA PINS
DESCRIPTION
SD[15:8]
SD[7:0]
Mode 0 Big-endian register (offset 1Eh) not equal to 0x0000h
Even access
Odd access
Byte3
Byte1
Byte2
Byte0
This mode can be used by 32-bit processors
operating with an external 16-bit bus.
Mode 0 Little-endian register (offset 1Eh) equal to 0x0000h (default)
Even access
Odd access
Byte1
Byte3
Byte0
Byte2
This mode can also be used by native 16-bit
processors.
Tab - 11 Byte Lane Mapping
AX88796B’s 16-bit Data Port (DP) read/write like a FIFO not rely on address pin. The “Even access” means the
first of access Data Port (DP) behind of remote read/write Command Register (CR). The second time access Data
Port (DP) is “Odd access” and then next is “Even access”, and so on.
Host can read bit-7 in “Device Status Register” (Offset 17h) to know the current of big- or little-endian types. The
default is Little-endian mode.
4.6 General Purpose Timer (GP Timer)
The programmable General Purpose Timer can be used to generate periodic host interrupts and the resolution of this
timer is 100us.
The GP timer is a 16-bit of register. GPT1 (CR page3 offset 0Fh) and GPT0 (CR page3 offset 0Eh) to compost this
16-bit of General Purpose Timer. This GP timer field of default value is FFFFh. Once set the General Purpose
Timer Enable (CR page3 Offset 0Dh) the GPT counts down until it reaches 0000h then update the a new pre-load
value into GPT, and continues counting.
The GPT interrupt has no status indicate in Interrupt Status Register (CR page0 offset 07h). The interrupt event will
keep active until host driver read Interrupt Status Register (CR page0 offset 07h) then clear GPT interrupt event.
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4.7 EEPROM Interface
AX88796B can optionally load its MAC address from an external serial EEPROM. If a properly configured
EEPROM is detected by AX88796B at power-up, hard reset or host set a reload EEPROM request (CR page3 offset
0Ch), the constants of EEPROM data will be auto loading to internal memory from 0000h to 001Fh and from 0400h
to 040Fh automatically. It is similar NE2000 PROM store MAC address field. A detailed explanation of the
EEPROM data format in section 3.1 “EEPROM Memory Mapping”. After auto load EEPROM completed not
indicate AX88796B knew its MAC address. Host driver can get MAC address from internal memory (0000h ~
001Fh) or (0400h ~ 040Fh) and write “Physical Address Registers” (CR page1 offset 01h ~ 06h).
The AX88796B EEPROM use 3 PIN to connect to a most “93C46” type EEPROM configured for x16-bit operation.
A connect diagram as below
93C46
AX88796B
EECS
EECK
EECS
EECK
EEDI
EEDIO
EEDO
Fig - 7 EEPROM connections
After EEPROM loader has finished reading the MAC after power-on, hard reset or host set a reload EEPROM
request (CR page3 offset 0Ch), the Host is free to perform EECS, EECK and EEDIO as General Purpose I/O pin.
4.8 Power management
AX88796B supports power-down modes to allow applications to minimize power consumption. There is one
normal operation power state, D0 and there are two power saving states: D1, and D2. The “Power Management
Register”(CR Page3 Offset 0Bh) controls those of power management modes. In D1 power saving state, AX88796B
supports Wake on LAN function. In D2 power saving state, AX88796B will off all function block and clocks to
minimize power consumption. After wakeup event, the “Power Management Register” will be cleared and state at
normal operation power state. When AX88796B in either D1 or D2 power saving mode, host can write “Host Wake
Up Register” (Offset 1Fh) return the AX88796B to the D0 state. Power is reduced to various modules by disabling
the clocks as outlined in table as below.
AX88796B
BLOCK
D0
(Normal
operation)
On
D1
(WOL)
D2
Internal
clock
MAC and
Host
MAC power
management
PHY
On
Off
Off
Off
Off
On
On
On
Off
Rx Block
On
On
Tab - 12 Power Management Statuses
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4.8.1 Power Management Event Indicators
The external PME signal can be setup as Push-Pull driver or open-drain buffer. And also can be set as active high or
active low. When set the PME_IND bit to a ‘1’, (offset 15h) the external PME signal will be driven active for 60ms
upon detection of a wake-up event. When the PME_IND bit is cleared, the PME signal will be driven continuously
upon detection of a wake-up event. Host can checks which kind of wake-up event activity by reads “Wake up
Control and Status Register”(CR page3 offset 0Ah). Host can writing “Power Management Register”(CR page3
offset 0Bh) or writing a ‘1’ to clear wake-up event activity flags on “Wake up Control and Status Register”(CR
page3 offset 0Ah) to deactivated PME signal.
IRQ_POL (offset 15h)
IRQ_POL (from EEPROM)
IRQ_TYPE (offset 15h)
IRQ_TYPE (from EEPROM)
System interrupt event
logic
ENB
IREQ
PME_IRQ_EN (offset 15h)
MPEN (CR page3 offset 0Ah)
Magic Packet Detect event
WUEN (CR page3 offset 0Ah)
Wakeup Frame Detect event
logic
60ms
PME_IND (offset 15h)
PME_POL (offset 15h)
PME_TYPE (offset 15h)
ENB
PME
Fig - 8 PME and IRQ signal generation
4.9 Device Ready or Busy
There are three kinds of device ready indicator in “Device Status Register” (Offset 17h). Those are indicates
AX88796B internal operation busy. In order to prevent the host access AX88796B in the busy stage, host can to
check the “Device Status Register” before doing some key operations.
When a “0” at the bit-4 (D-RDY) in “Device Status Register” (Offset 17h), indicate the AX88796B in reset state or
power saving state or EEPROM loading state or loop-back mode swapping.
When a “0” at the bit-5 (RD-RDY) in “Device Status Register” (Offset 17h), indicate the remote-DMA-read data
not ready yet, host must not read data port (DP) in this period. The non-ready period only happen when host set a
remote-read command on “Command Register”(CR), and it will be go to ready state when a valid data pop out for
host to reading. Host driver can back-to-back read data port (DP) since checked the RD-RDY was ready. The
maximum of remote-read non-ready period only spend 60ns. Host can ignore to check RD_RDY if host access time
not faster then it.
When a “0” at the bit-6 (RDMA-RDY) in “Device Status Register” (Offset 17h), indicate the remote DMA not
completed yet. This RDMA-RDY will be cleared when host write “Remote Byte Count 0” RBCR0 (CR page0
Offset 0Ah) or “Remote Byte Count 1” RBCR1 (CR page0 Offset 0Bh). The byte counter will down counting when
every data port (DP) access. This RDMA-RDY will be set when byte counter count to zero.
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5.0 Registers Operation
5.1 MAC Control and Status Registers (CSR)
All registers of MAC Core are 8-bit wide except data port (DP). Data Port is optional 8 or 16-bit wide by WTS
(DCR). Offset 01h to 0Fh mapped into pages, which are selected by PS (Page Select) in the Command Register.
Offset
00H
Page0
Page1
Page2
Command Register (CR)
Page3
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H, 11H
12H
Data Port (DP)
Inter-frame Gap Segment 1 (IFGS1)
Inter-frame Gap Segment 2 (IFGS2)
MII/EEPROM Access
13H
14H
15H
16H
Buffer Type Configure Register (BTCR)
Inter-frame Gap (IFG)
17H
18H
Device Status Register (DSR) / Back-pressure Jam Limit Count (BJLC)
Max Frame Size [7:0]
19H
Max Frame Size [11:8]
1AH
1BH
1CH
1DH
1EH
1FH
Flow Control Register (FCR)
MAC Configure Register (MCR)
Current TX End Page Register (CTEPR) / VLAN_ID_0
Reserved / VLAN_ID_1
Reserved / Big-Endian Register (BER)
Software Reset / Host Wake up (HWAKE)
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PAGE 0 (PS1=0,PS0=0)
Offset
00H
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
Read
Write
Command Register (CR)
Command Register (CR)
Page Start Register (PSTART)
Page Stop Register (PSTOP)
Rx Page Start Register (PSTART)
Rx Page Stop Register (PSTOP)
Boundary Pointer (BNRY)
Transmit Status Register (TSR)
Number of Collisions Register (NCR)
Current Page Register (CPR)
Interrupt Status Register (ISR)
Current Remote DMA Address 0 (CRDA0) Remote Start Address Register 0 (RSAR0)
Current Remote DMA Address 1 (CRDA1) Remote Start Address Register 1 (RSAR1)
Reserved
Boundary Pointer (BNRY)
Transmit Page Start Address (TPSR)
Transmit Byte Count Register 0 (TBCR0)
Transmit Byte Count Register 1 (TBCR1)
Interrupt Status Register (ISR)
Remote Byte Count 0 (RBCR0)
Remote Byte Count 1 (RBCR1)
Receive Configuration Register (RCR)
Transmit Configuration Register (TCR)
Reserved
Receive Status Register (RSR)
Frame Alignment Error Tally Register
(CNTR0)
0EH
0FH
CRC Error Tally Register (CNTR1)
Frames Lost Tally Register (CNTR2)
Data Configuration Register (DCR)
Interrupt Mask Register (IMR)
Data Port (DP)
11H, 10H Data Port (DP)
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Inter-frame Gap Segment 1 (IFGS1)
Inter-frame Gap Segment 2 (IFGS2)
MII/EEPROM Access
Buffer Type Configure Register (BTCR)
Inter-frame Gap (IFG)
Device Status Register (DSR)
Max Frame Size [7:0]
Inter-frame Gap Segment 1 (IFGS1)
Inter-frame Gap Segment 2 (IFGS2)
MII/EEPROM Access
Buffer Type Configure Register (BTCR)
Inter-frame Gap (IFG)
Back-pressure Jam Limit count (BJLC)
Max Frame Size [7:0]
Max Frame Size [11:8]
Flow Control Register (FCR)
MAC Configure Register (MCR)
VLAN_ID_0
VLAN_ID_1
Big-Endian Register (BER)
Host Wake up (HWAKE)
Max Frame Size [11:8]
Flow Control Register (FCR)
MAC Configure Register (MCR)
Current TX End Page Register (CTEPR)
Reserved
Reserved
Software Reset
Tab - 13 Page 0 of MAC Core Registers Mapping
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PAGE 1 (PS1=0,PS0=1)
Offset
01H
Read
Write
Physical Address Register 0
(PAR0)
Physical Address Register 0
(PAR0)
02H
03H
04H
05H
06H
Physical Address Register 1
(PAR1)
Physical Address Register 2
(PAR2)
Physical Address Register 3
(PAR3)
Physical Address Register 4
(PAR4)
Physical Address Register 1
(PAR1)
Physical Address Register 2
(PAR2)
Physical Address Register 3
(PAR3)
Physical Address Register 4
(PAR4)
Physical Address Register 5
(PAR5)
Physical Address Register 5
(PAR5)
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Current Page Register
(CPR)
Multicast Address Register 0
(MAR0)
Multicast Address Register 1
(MAR1)
Multicast Address Register 2
(MAR2)
Multicast Address Register 3
(MAR3)
Multicast Address Register 4
(MAR4)
Multicast Address Register 5
(MAR5)
Multicast Address Register 6
(MAR6)
Current Page Register
(CPR)
Multicast Address Register 0
(MAR0)
Multicast Address Register 1
(MAR1)
Multicast Address Register 2
(MAR2)
Multicast Address Register 3
(MAR3)
Multicast Address Register 4
(MAR4)
Multicast Address Register 5
(MAR5)
Multicast Address Register 6
(MAR6)
Multicast Address Register 7
(MAR7)
Multicast Address Register 7
(MAR7)
Tab - 14 Page 1 of MAC Core Registers Mapping
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PAGE 2 (PS1=1,PS0=0)
Offset
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Read
Write
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Total Receive Buffer Free Page (TFP) Reserved
Chip version (00h) Reserved
Receive Configuration Register (RCR) Reserved
Transmit Configuration Register (TCR) Reserved
Data Configuration Register (DCR)
Interrupt Mask Register (IMR)
Reserved
Reserved
Tab - 15 Page 2 of MAC Core Registers Mapping
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PAGE 3 (PS1=1,PS0=1)
Offset
01H
02H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
Read
Write
WFBM0
WFBM1
WFBM2
WFBM3
WF10CRC
WF32CRC
WFOFST
WFLB
WFCMD
WUCSR
PMR
Reserved
MISC
WFBM0
WFBM1
WFBM2
WFBM3
WF10CRC
WF32CRC
WFOFST
WFLB
WFCMD
WUCSR
PMR
REER
MISC
GPT0
GPT1
GPT0
GPT1
Tab - 16 Page 3 of MAC Core Registers Mapping
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5.1.1 Command Register (CR)
Offset 00H (Read/Write)
Field
7:6
Name
PS1, PS0 PS1, PS0: Page Select
The two bits select which register’s page is to be accessed.
It will be reset to default value when set PMR to D1 to D2 sleep state.
Description (Default = 21h)
PS1
0
PS0
0
1
page 0 (default)
page 1
0
1
0
page 2
1
1
page 3
5:3
RD2,
RD1,
RD0
RD2, RD1, RD0: Remote DMA Command
These three encoded bits control operation of the Remote DMA channel. RD2 could be set
to abort any Remote DMA command in process. RD2 is reset by AX88796B when a
Remote DMA has been completed. The Remote Byte Count should be cleared when a
Remote DMA has been aborted. The Remote Start Address is not restored to the starting
address if the Remote DMA is aborted.
It will be reset to default value when set PMR to D1 to D2 sleep state.
RD2 RD1 RD0
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
Not allowed
Remote Read
Remote Write
Not allowed
Abort / Complete Remote DMA (default)
2
1
TXP
TXP: Transmit Packet
This bit could be set to initiate transmission of a packet
START START:
This bit is used to active AX88796B operation.
This bit always read high when Host set once. It only clear by hardware or software reset.
STOP: Stop AX88796B
0
STOP
This bit is used to stop the AX88796B operation.
It will be reset to default value when set PMR to D1 to D2 sleep state.
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5.1.2 Rx Page Start Register (PSTART)
Page0 Offset 01H (Read/Write)
Field
7:0
Name
Description (Default = 00h)
PSTART Receive Buffer Ring Page Start Register
5.1.3 Rx Page Stop Register (PSTOP)
Page0 Offset 02H (Read/Write)
Field
7:0
Name
Description (Default = 00h)
PSTOP Receive Buffer Ring Page Stop Register
5.1.4 Boundary Pointer (BNRY)
Page0 Offset 03H (Read/Write)
Field
7:0
Name
BNRY
Description (Default = 4Ch)
Boundary Page Pointer
5.1.5 Transmit Page Start Address (TPSR)
Page0 Offset 04H (Write)
Field
7:0
Name
TPSR
Description
Transmit Page Start Address
5.1.6 Transmit Status Register (TSR)
Page0 Offset 04H (Read)
Field
7
6:4
3
Name
OWC
-
Description (Default = 00h)
Out of window collision
Reserved
ABT
Transmit Aborted
Indicates the AX88796 aborted transmission because of excessive collision.
2
COL
Transmit Collided
Indicates that the transmission collided at least once with another station on the network.
1
0
-
Reserved
Packet Transmitted
PTX
Indicates transmission without error.
5.1.7 Transmit Byte Count Register (TBCR0)
Page0 Offset 05H (Write)
Field
7:0
Name
Description
TBCR0 Transmit Byte Count Register. The bit assignment is shown below
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5.1.8 Number Of Collisions Register (NCR)
Page0 Offset 05H (Read)
Field
7:4
Name
-
Description (Default = 00h)
Always zero
3:0
NCR
If no collisions are experienced during a transmission attempt, the COL bit of the TSR will
not be set and the contents of NCR will be zero. If there are excessive collisions, the ABT bit
in the TSR will be set and the contents of NCR will be zero. The NCR is cleared after the
TXP bit in the CR is set.
5.1.9 Transmit Byte Count Register (TBCR1)
Page0 Offset 06H (Write)
Field
7:0
Name
Description
TBCR1 Transmit Byte Count Register.
5.1.10 Current Page Register (CPR)
Page0 Offset 06H (Read)
Field
7:0
Name
CPR
Description (Default = 4Dh)
The Buffer Management Logic as a backup register for reception uses this register
internally. CURR contains the address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive errors. This register is initialized
to the same value as PSTART and should not be written to again unless the controller is
Reset.
5.1.11 Interrupt Status Register (ISR)
Page0 Offset 07H (Read/Write)
Field
7
Name
RST
Description (Default = 80h)
Reset Status:
Set when AX88796B enters reset state (or a wake-up event) and cleared when a start
command is issued to the CR. Writing to this bit is no effect.
Remote DMA Complete
Set when remote DMA operation has been completed. Write this bit to high then reset it.
Counter Overflow
6
5
RDC
CNT
Set when MSB of one or more of the Tally Counters has been set. Write this bit to high
then reset its.
4
3
OVW
TXE
OVERWRITE: Set when receive buffer ring storage resources have been exhausted.
Write this bit to high then reset it.
Transmit Error
Set when packet transmitted with one or more of the following errors
Excessive collisions, Transmit over size and late collision.
Write this bit to high then reset it.
2
RXE
Receive Error
Indicates that a packet was received with one or more of the following errors
CRC error
Frame Alignment Error
Missed Packet
Write this bit to high then reset it.
1
0
PTX
PRX
Packet Transmitted
Indicates packet transmitted with no error
Write this bit to high then reset it.
Packet Received
Indicates packet received with no error.
Write this bit to high then reset it.
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Remote DMA operations are programmed via the Remote Start Address (RSAR0, 1) and Remote Byte Count
(RBCR0, 1) registers.
5.1.12 Remote Start Address Register (RSAR0)
Page0 Offset 08H (Write)
Field
7:0
Name
Description
RSAR0 The Remote Start Address is used to point to the start of the block of data to be transferred.
5.1.13 Remote Start Address Register (RSAR1)
Page0 Offset 09H (Write)
Field
7:0
Name
Description
RSAR1 The Remote Start Address is used to point to the start of the block of data to be transferred.
5.1.14 Remote Byte Count Register (RBCR0)
Page0 Offset 0AH (Write)
Field
7:0
Name
Description
RBCR0 The Remote Byte Count is used to indicate the length of the block (in bytes).
5.1.15 Remote Byte Count Register (RBCR1)
Page0 Offset 0BH (Write)
Field
7:0
Name
Description
RBCR1 The Remote Byte Count is used to indicate the length of the block (in bytes).
5.1.16 Current Remote DMA Address (CRDA0)
Page0 Offset 08H (Read)
Field
7:0
Name
Description (Default = 00h)
CRDA0 The Current Remote DMA Registers contain the current address of the Remote DMA. The
bit assignment is shown below:
5.1.17 Current Remote DMA Address (CRDA1)
Page0 Offset 09H (Read)
Field
7:0
Name
Description (Default = 00h)
CRDA1 The Current Remote DMA Registers contain the current address of the Remote DMA. The
bit assignment is shown below:
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5.1.18 Receive Configuration Register (RCR)
Page0 Offset 0CH (Write)
Field
Name
Description
7
6
5
-
-
Reserved
Reserved
Monitor Mode
0: Normal Operation. (Default)
MON
1: Monitor Mode, the input packet will be checked on NODE ADDRESS and CRC but not
buffered into memory.
4
3
PRO
AM
PRO: Promiscuous Mode
Enable the receiver to accept all packets with a physical address.
AM: Accept Multicast
Enable the receiver to accept packets with a multicast address. That multicast address must
pass the hashing array.
2
1
0
AB
AR
SEP
AB: Accept Broadcast
Enable the receiver to accept broadcast packet.
AR: Accept Runt
Enable the receiver to accept runt packet.
SEP: Save Error Packet
Enable the receiver to accept and save packets with error.
5.1.19 Receive Status Register (RSR)
Page0 Offset 0CH (Read)
Field
Name
-
DIS
PHY
MPA
-
FAE
CR
PRX
Description (Default = 00h)
Reserved
Receiver Disabled
Multicast Address Received.
Missed Packet
Always Zero
Frame alignment error.
CRC error.
7
6
5
4
3
2
1
0
Packet Received Intact
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5.1.20 Transmit Configuration Register (TCR)
Page0 Offset 0DH (Write)
Field
Name
Description
7
FDU
Full Duplex
This bit configure MAC media mode is Full Duplex or not.
0: Half duplex (Default)
1: Full duplex
This duplex setting was wire or with MCR bit-7. Each one goes high then configures MAC
as full-duplex. AX88796B will ignore this bit and MCR bit-7 when using internal PHY.
Pad Disable
0: Pad will be added when packet length less than 60. (Default)
1: Pad will not be added when packet length less than 60.
Retry of late collision
0: Don’t retransmit packet when late collision happens. (Default)
1: Retransmit packet when late collision happens.
Reserved
6
5
PD
RLO
-
4:3
2:1
LB1, LB0 Encoded Loop-back Control
These encoded configuration bits set the type of loop-back that is to be performed.
LB1 LB0
Mode0
Mode 1
Mode 2
No Define 1
Inhibit CRC
0
0
1
0
1
0
1
Normal operation (Default)
Internal AX88796B loop-back
PHY loop-back
Reserved
0
CRC
0: CRC appended by transmitter. (Default)
1: CRC inhibited by transmitter.
5.1.21 Frame Alignment Error Tally Register (CNTR0)
Page0 Offset 0DH (Read)
Field
Name
Description (Default = 00h)
7:0
CNTR0 This counter is incremented every time a packet is received with a Frame Alignment Error.
The packet must have been recognized by the address recognition logic. The counter is
cleared after the processor reads it.
5.1.22 Data Configuration Register (DCR)
Page0 Offset 0EH (Write)
Field
7:2
1
Name
-
-
Description
Reserved
Reserved
0
WTS
Word Transfer Select (Data Port Only)
0: Selects Data Port with byte-wide transfers. (Default)
1: Selects Data Port with word-wide transfers.
5.1.23 CRC Error Tally Register (CNTR1)
Page0 Offset 0EH (Read)
Field
Name
Description (Default = 00h)
7:0
CNTR1 This counter is incremented every time a packet is received with a CRC error. The packet
must first be recognized by the address recognition logic. The counter is cleared after the
processor reads it.
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5.1.24 Interrupt mask register (IMR)
Page0 Offset 0FH (Write)
Field
Name
Description
7
6
5
4
3
2
1
0
Reserved
RDCE
CNTE
DMA Complete Interrupt Enable. Default “low” disabled.
Counter Overflow Interrupt Enable. Default “low” disabled.
OVWE Overwrite Interrupt Enable. Default “low” disabled.
TXEE
RXEE
PTXE
PRXE
Transmit Error Interrupt Enable. Default “low” disabled.
Receive Error Interrupt Enable. Default “low” disabled.
Packet Transmitted Interrupt Enable. Default “low” disabled.
Packet Received Interrupt Enable. Default “low” disabled.
5.1.25 Frames Lost Tally Register (CNTR2)
Page0 Offset 0FH (Read)
Field
Name
Description (Default = 00h)
7:0
CNTR2 This counter is incremented if a packet cannot be received due to lack of buffer resources. In
monitor mode, this counter will count the number of packets that pass the address
recognition logic.
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5.1.26 Physical Address Register 0 (PAR0)
Page1 Offset 01H (Read/Write)
Field
7:0
Name
PAR0
Description (Default = 00h)
Physical Address Register 0
5.1.27 Physical Address Register 1 (PAR1)
Page1 Offset 02H (Read/Write)
Field
7:0
Name
PAR1
Description (Default = 00h)
Physical Address Register 1
5.1.28 Physical Address Register 2 (PAR2)
Page1 Offset 03H (Read/Write)
Field
7:0
Name
PAR2
Description (Default = 00h)
Physical Address Register 2
5.1.29 Physical Address Register 3 (PAR3)
Page1 Offset 04H (Read/Write)
Field
7:0
Name
PAR3
Description (Default = 00h)
Physical Address Register 3
5.1.30 Physical Address Register 4 (PAR4)
Page1 Offset 05H (Read/Write)
Field
7:0
Name
PAR4
Description (Default = 00h)
Physical Address Register 4
5.1.31 Physical Address Register 5 (PAR5)
Page1 Offset 06H (Read/Write)
Field
7:0
Name
PAR5
Description (Default = 00h)
Physical Address Register 5
The physical address registers are used to compare the destination address of incoming packets for rejecting or
accepting packets. Comparisons are performed on a byte wide basis. The bit assignment shown below relates the
sequence in PAR0 ~ PAR5 to the bit sequence of the received packet.
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5.1.32 Current Page Register (CPR)
Page1 Offset 07H (Read/Write)
Field
7:0
Name
CPR
Description (Default = 4Dh)
The Buffer Management Logic as a backup register for reception uses this register
internally. CURR contains the address of the first buffer to be used for a packet reception
and is used to restore DMA pointers in the event of receive errors. This register is initialized
to the same value as PSTART and should not be written to again unless the controller is
Reset.
5.1.33 Multicast Address Register 0 (MAR0)
Page1 Offset 08H (Read/Write)
Field
7:0
Name
MAR0
Description (Default = 00h)
Multicast Address Register 0
5.1.34 Multicast Address Register 1 (MAR1)
Page1 Offset 09H (Read/Write)
Field
7:0
Name
MAR1
Description (Default = 00h)
Multicast Address Register 1
5.1.35 Multicast Address Register 2 (MAR2)
Page1 Offset 0AH (Read/Write)
Field
7:0
Name
MAR2
Description (Default = 00h)
Multicast Address Register 2
5.1.36 Multicast Address Register 3 (MAR3)
Page1 Offset 0BH (Read/Write)
Field
7:0
Name
MAR3
Description (Default = 00h)
Multicast Address Register 3
5.1.37 Multicast Address Register 4 (MAR4)
Page1 Offset 0CH (Read/Write)
Field
7:0
Name
MAR4
Description (Default = 00h)
Multicast Address Register 4
5.1.38 Multicast Address Register 5 (MAR5)
Page1 Offset 0DH (Read/Write)
Field
7:0
Name
MAR5
Description (Default = 00h)
Multicast Address Register 5
5.1.39 Multicast Address Register 6 (MAR6)
Page1 Offset 0EH (Read/Write)
Field
7:0
Name
MAR6
Description (Default = 00h)
Multicast Address Register 6
5.1.40 Multicast Address Register 7 (MAR7)
Page1 Offset 0FH (Read/Write)
Field
7:0
Name
MAR7
Description (Default = 00h)
Multicast Address Register 7
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5.1.41 Total Receive Buffer Free Page Register (TFP)
Page2 Offset 0AH (Read)
Field
7:0
Name
TFP
Description (Default = 7Fh)
Indicate total free page in receive buffer ring. A default value 7Fh after hardware / software
reset. It will be update the real free page when every frame received.
5.1.42 Receive Configuration Register (RCR)
Page2 Offset 0CH (Read)
Field
7:0
Name
RCR
Description (Default = 00h)
Reference Page0 Offset 0CH for bits deifications.
5.1.43 Transmit Configuration Register (TCR)
Page2 Offset 0DH (Read)
Field
7:0
Name
TCR
Description (Default = 00h)
Reference Page0 Offset 0DH for bits deifications.
5.1.44 Data Configuration Register (DCR)
Page2 Offset 0EH (Read)
Field
7:0
Name
DCR
Description (Default = 00h)
Reference Page0 Offset 0EH for bits deifications.
5.1.45 Interrupt Mask Register (IMR)
Page2 Offset 0FH (Read)
Field
7:0
Name
IMR
Description (Default = 00h)
Reference Page0 Offset 0FH for bits deifications.
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5.1.46 Wakeup Frame Byte Mask (WFBM0)
Page3 Offset 01H (Read/Write)
Field
31:0
Name
Description (Default = 00h)
WFBM0 Byte mask for wake-up frame filter 0. Host continue write 4 times to completed 32-bits of
Byte Mask 0.
5.1.47 Wakeup Frame Byte Mask (WFBM1)
Page3 Offset 02H (Read/Write)
Field
31:0
Name
Description (Default = 00h)
WFBM1 Byte mask for wake-up frame filter 1. Host continue write 4 times to completed 32-bits of
Byte Mask 1.
5.1.48 Wakeup Frame Byte Mask (WFBM2)
Page3 Offset 03H (Read/Write)
Field
31:0
Name
Description (Default = 00h)
WFBM2 Byte mask for wake-up frame filter 2. Host continue write 4 times to completed 32-bits of
Byte Mask 2.
5.1.49 Wakeup Frame Byte Mask (WFBM3)
Page3 Offset 04H (Read/Write)
Field
31:0
Name
Description (Default = 00h)
WFBM3 Byte mask for wake-up frame filter 3. Host continue write 4 times to completed 32-bits of
Byte Mask 3.
5.1.50 Wakeup Frame 1,0 CRC (WF10CRC)
Page3 Offset 05H (Read/Write)
Field
7:0
Name
Description (Default = 00h)
WF0_0CRC Byte mask CRC for wake-up frame filter 0. Host continue write 4 times to completed
32-bits of Byte Mask 1 CRC and Byte Mask 0 CRC.
CRC-16 Polynomials = X^16 + X^15 + X^2 + 1
15:8
23:16
31:24
WF0_1CRC Byte mask CRC for wake-up frame filter 0.
WF1_0CRC Byte mask CRC for wake-up frame filter 1.
WF1_1CRC Byte mask CRC for wake-up frame filter 1.
5.1.51 Wakeup Frame 3,2 CRC (WF32CRC)
Page3 Offset 06H (Read/Write)
Field
7:0
Name
Description (Default = 00h)
WF2_0CRC Byte mask CRC for wake-up frame filter 2. Host continue write 4 times to completed
32-bits of Byte Mask 3 CRC and Byte Mask 2 CRC.
CRC-16 Polynomials = X^16 + X^15 + X^2 + 1
15:8
23:16
31:24
WF2_1CRC Byte mask CRC for wake-up frame filter 2.
WF3_0CRC Byte mask CRC for wake-up frame filter 3.
WF3_1CRC Byte mask CRC for wake-up frame filter 3.
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5.1.52 Wakeup Frame Offset (WFOFST)
Page3 Offset 07H (Read/Write)
Field
7:0
Name
Description (Default = 00h)
WF0OFST Byte mask Offset for wake-up frame filter 0. Host continue write 4 times to completed
32-bits of Byte Mask 3, 2, 1, 0 Offset. The unit is 16-bit. (2bytes)
WF1OFST Byte mask Offset for wake-up frame filter 1.
15:8
23:16
31:24
WF2OFST Byte mask Offset for wake-up frame filter 2.
WF3OFST Byte mask Offset for wake-up frame filter 3.
5.1.53 Wakeup Frame Last Byte (WFLB)
Page3 Offset 08H (Read/Write)
Field
7:0
Name
WFLB0
Description (Default = 00h)
Mask Last Byte for wake-up frame filter 0. Host continue write 4 times to completed
32-bits of Last Byte of 3, 2, 1, 0 filter.
15:8
23:16
31:24
WFLB1
WFLB2
WFLB3
Mask Last Byte for wake-up frame filter 1.
Mask Last Byte for wake-up frame filter 2.
Mask Last Byte for wake-up frame filter 3.
5.1.54 Wakeup Frame Command (WFCMD)
Page3 Offset 09H (Read/Write)
Field
3:0
Name
Description (Default = 00h)
WFCMD0 Byte Mask Command for wake-up frame filter 0. Host continue write 4 times to completed
32-bits of Byte Mask Command of 3, 2, 1, 0 filter and Mask cascade commend.
Bit0: wake-up frame filter enable
Bit1: destination match enable
Bit2: Multicast match enable
Bit3: Reserved
7:4
WFCMD1 Byte Mask Command for wake-up frame filter 1.
WFCMD2 Byte Mask Command for wake-up frame filter 2.
WFCMD3 Byte Mask Command for wake-up frame filter 3.
WFCSCD Byte Mask Cascade Command for wake-up frame filter
Bit-0: cascade wake-up filter 1 and 0
11:8
15:12
19:16
Bit-1: cascade wake-up filter 2 and 1
Bit-2: cascade wake-up filter 3 and 2
31:18
-
Reserved. Always zero.
5.1.55 Wakeup Control and Status Register (WUCSR)
Page3 Offset 0AH (Read/Write)
Field
Name
-
LSC
WUFR
Description (Default = 00h)
Reserved
Link status change event flag. This bit will be clear when Host write PMR or set this bit.
Wake-up Frame Received event flag. This bit will be clear when Host write PMR or set
7
6
5
this bit.
4
MPR
Magic Packet Received event flag. This bit will be clear when Host write PMR or set this
bit.
3
2
-
Reserved
LSCWE
Link status change wakeup enable
0: disable (Default)
1: enable
1
WUEN
Wake-up frame enable
0: disable (Default)
1: enable
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0
MPEN
Magic Packet wake-up enables.
0: disable (Default)
1: enable
5.1.56 Power Management Register (PMR)
Page3 Offset 0BH (Read/Write)
Field
7:5
4
Name
-
Description (Default = 00h)
Reserved
REGSTB 0: Regulator in normal mode (Default)
1: Regulator in standby mode
3:2
1:0
-
Reserved
PMM
Power Management Mode, Self clear when wake-up
00: Normal Operation (Default)
01: D1 power saving. Supported Link status change, Wake-up and Magic frame for
remote wake-up
10: D2 power saving. Only write host wake-up register (offset 1Fh) to leave D2 state.
11: Reserved. Do not set this mode.
5.1.57 Reload EEPROM Register (REER)
Page3 Offset 0CH (Write)
Field
7:1
0
Name
-
REER
Description
Reserved
Reload EEPROM
Host set this bit to active reload EEPROM process. And it will auto clear by it self.
5.1.58 Misc. Control Register (MISC)
Page3 Offset 0DH (Write/Read)
Field
7:3
2
Name
-
GPTE
Description (Default = 00h)
Reserved
General Purpose Timer Enable
0: Disable (Default)
1: Enable
1
0
BCB1
TBR
Burst Cycle Base On SA1 or SA0
0: Base on SA0 (Default)
1: Base on SA1
Transmit Buffer Ring Enable
0: Remote DMA write can write any where of embedded memory. (Default)
1: Remote DMA write transmit buffer as a Ring from page 40h to PSTART –1.
5.1.59 General Purpose Timer0 Register (GPT0)
Page3 Offset 0EH (Write/Read)
Field
7:0
Name
-
Description (Default = FFh)
General Purpose Timer [7:0]
5.1.60 General Purpose Timer1 Register (GPT1)
Page3 Offset 0FH (Write/Read)
Field
7:0
Name
-
Description (Default = FFh)
General Purpose Timer [15:8]
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5.1.61 Data Port (DP)
Offset 10H (Read/Write)
Field
15:8
7:0
Name
DP
DP
Description (Default = 00h)
Data Port High byte
Data Port Low byte
5.1.62 Inter-frame gap Segment 1(IFGS1)
Offset 12H (Read/Write)
Field
7
Name
-
Description (Default = 0Ch)
Reserved
6:0
IFGS1
Inter-frame Gap Segment 1.
5.1.63 Inter-frame gap Segment 2(IFGS2)
Offset 13H (Read/Write)
Field
7
Name
-
Description (Default = 12h)
Reserved
6:0
IFGS2
Inter-frame Gap Segment 2.
5.1.64 MII/EEPROM Management Register (MEMR)
Offset 14H (Read/Write)
Field
Name
Description (Default = 00h)
7
EECK
EECK
EEPROM Clock. It output to Pin-20
6
5
4
3
2
1
EEO
EEI
EEO: (Read only)
EEPROM Data Out value. It reflects Pin-19 EEDIO value.
EEI
EEPROM Data In. It output to Pin-19 EEDIO as EEPROM data input value.
EECS
EEPROM Chip Select. It output to Pin-21
MDO
MII Data Out. It connects to internal PHY of MDO.
MDI (Read only)
MII Data In. It connects to internal PHY of MDI.
Signal Direction: for both of SMI (MDIO) and EEPROM (EEDIO)
0: output direction, MDIO and EEDIO as push-pull drive out
1: input direction, MDIO and EEDIO as Z state for source from external signals
MDC
EECS
MDO
MDI
DIR
0
MDC
MII Clock. It connect to internal PHY of MDC
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5.1.65 I/O Buffer Type Configure Register (BTCR)
Offset 15H (Read/Write)
Field
Name
Description (Default = 00h)
7
6
-
Always write zero
PME_IQR_EN PME interrupt enable
0: PME interrupt disable (Default)
1: PME interrupt enable
5
4
IRQ_TYPE
IRQ_POL
Interrupt I/O Buffer Type
0: Enable IRQ to function as an open-drain buffer for use in a wired-OR interrupt
configuration. And ignored INTP field, the interrupt output is always active low.
(Default)
1: IRQ output is a Push-Pull driver
Interrupt Polarity
0: Low active (Default)
1: High active
3
2
-
Reserved
PME indication
PME_IND
0: A static signal active when detect wake-up event. (Default)
1: A 60ms pulse active when detect wake-up event.
PME I/O Type. When cleared, PME_POL is ignored, and the output is always active
low.
0: PME to function as an open-grain buffer for use in a wired-or configuration.
(Default)
1
0
PME_TYPE
PME_POL
1: PME output is a Push-Pull driver.
PME Polarity.
0: PME active Low (Default)
1: PME active high (ignore when PME_TYPE is low)
IRQ_POL (offset 15h)
IRQ_POL (from EEPROM)
IRQ_TYPE (offset 15h)
IRQ_TYPE (from EEPROM)
System interrupt event
logic
ENB
IREQ
PME_IRQ_EN (offset 15h)
MPEN (CR page3 offset 0Ah)
Magic Packet Detect event
WUEN (CR page3 offset 0Ah)
Wakeup Frame Detect event
logic
60ms
PME_IND (offset 15h)
PME_POL (offset 15h)
PME_TYPE (offset 15h)
ENB
PME
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5.1.66 Inter-frame gap (IFG)
Offset 16H (Read/Write)
Field
7
Name
-
Description (Default = 15h)
Reserved, Always zero.
6:0
IFG
Inter-frame Gap for Back-To-Back Transmission without collision
IFG
15h – n
15h (default)
15h + n
Bit-time of Frame gap
96 – (4*n)
96
96 + (4*n)
5.1.67 Back-pressure Jam Limit Count (BJLC)
Offset 17H (Write)
Field
7:6
Name
-
Description
Reserved, Always zero.
5:0
BJLC
Back-pressure Jam Limit count, Default value is 19H.
5.1.68 Device Status Register (DSR)
Offset 17H (Read)
Field
Name
Description
7
6
B_ENDIAN When set indicates big-endian mode. (The Big-endian Register’s value not all zero)
RDMA_RDY Remote DMA completed. It is same as ISR bit 6.
When set, it indicates the remote DMA process was completed.
5
4
RD_RDY
D_RDY
Read Data Port Ready, When set, indicates data was ready from SRAM to data port for
host reading.
Device Ready. When set, this bit indicates that AX88796B is ready to be accessed. This
register can be read when AX88796B in any power management mode.
When cleared, indicate AX88796B in reset, power saving or load EEPROM state.
Always zero
3
2
-
I_SPEED
PHY Link Speed:
0: indicate the link speed is 10Mb/s
1: indicate the link speed is 100Mb/s
1
0
I_DUPLEX PHY Duplex mode:
0: half-duplex
1: full-duplex
I_LINK
Link Status:
0: Link off
1: Link up
5.1.69 MAX Frame Size Register (MFSR0)
Offset 18H (Read/Write)
Field
Name
Description (Default = 00h)
7:0
MFSR0 MAX Frame size [7:0], default {MFSR1, MFSR0} = 1536 bytes
5.1.70 MAX Frame Size Register (MFSR1)
Offset 19H (Read/Write)
Field
7:3
Name
-
Description (Default = 06h)
Reserved
2:0
MFSR1 MAX Frame size [10:8]
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5.1.71 Flow Control Register (FCR)
Offset 1AH (Read/Write)
Field
7
Name
FLWC
Description (Default = 07h)
Flow-control
0: Flow-control disable (Default)
1: Flow-control enable
6
BPEN
Back Pressure in half-duplex flow-control (AX88796B will ignore this bit when running at
full-duplex mode)
0: Back Pressure disable (Default)
1: Back Pressure enable
5:0
HWPC
High Water free Page Count. Default value is 7 (7 * 256 = 1792 bytes).
5.1.72 MAC Configure Register (MCR)
Offset 1BH (Read/Write)
Field
Name
Description
7
DUPX
MAC duplex mode setting
When read, this bit is indicates the real duplex setting in MAC operation.
0: half-duplex
1: full-duplex
When write, this duplex setting was wire or with TCR bit-7. Each one goes high then
configures MAC as full-duplex mode. AX88796B will ignore this bit and TCR bit-7 when
using internal PHY.
6
5
BPLE
BBTC
Back-pressure leakage enable when continuous of collision N times.
N number is reference register 17H of Back-pressure Jam Limit count.
0: Allow flow-control leakage to avoid HUB port going partition state due to too many of
collision (Default)
1: No flow-control leakage
Back-To-Back Transmission Control:
0: Disable (Default)
1: Enable Back-To-Back Transmission, Host can continue set TXP without check transmit
completed
Host can ignore Number of Collisions Register (NCR)
4
3
MPSEL Media Select by Program
0: internal PHY is selected (Default)
1: external MII PHY is selected.
VLANE VLAN enable
0: No supported VLAN frame tagged (Default)
1: Only accept Tag frames. AX88796 will reject packet if Tag x8100 and VID not match
whit setting by host. Null VID (VID = 0) is acceptable.
2
CPTEFF Capture effect.
0: always write low (Default)
1: for MAC test only. Force first collision of back off is 2 slot-time and second collision of
back off is 0 slot time. Others as normal.
1
0
SPMAC Super MAC.
0: always write low (Default)
1: for MAC test only. Back-off only 0 ~ 3 slot-time
ZEROBF Zero Back Off Time.
0: always write low (Default)
1: for MAC test only. Back Off Time always zeros.
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5.1.73 VLAN ID 0 Register (VIDR0)
Offset 1CH (Write)
Field
Name
Description
7:0
VIDR0
VLAN ID [7:0]
5.1.74 Current TX End Page Register (CTEPR)
Offset 1CH (Read)
Field
7
Name
TXCQF TX Command Queue full
When set, indicate the TX Command queue was full. Host must check this status before
Description (Default = 00h)
queuing next transmit page and byte count.
6:0
CTEPR AX88796B will update CTEPR (current TX end page)
After every transmitting completed without collision.
It is for Host to conform how many free page can reuse for next transmitting.
The value is from 40h to 7Fh. It will be 00h when reset or STP.
5.1.75 VLAN ID 1 Register (VIDR1)
Offset 1DH (Write)
Field
7:5
4
Name
PRI
CFI
Description
Frame’s priority
Canonical Address Frame Indicator
VLAN ID [11:8]
3:0
VIDR1
5.1.76 Big-Endian Register (BER)
Offset 1EH (Write)
Field
Name
Description (Default = 00h)
7:0
-
All zero, (Default): little-endian
If not all zero means set data byte order as big-endian mode.
Note: This mode can be used by 32-bit big-endian mode of processors operating with an
external 16-bit bus only.
5.1.77 Host Wake Up Register (HWUR)
Offset 1FH (Write)
Field
7:1
0
Name
-
Description
Reserved
HWAKE Host write one to wake up AX88796B from D2 power saving. It will be auto clear when
(SC) wake up.
5.1.78 Software Reset
Offset 1FH (Read)
Field
Name
Description
7:0
-
Don’t care this read value.
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5.2 The Embedded PHY Registers
The MII management 16-bit register set implemented is as follows. And the following sub-section will describes each
field of the registers.
Address
Name Description
MR0 Control
MR1 Status
MR2 PHY Identifier 1
Default value
3100H
7809H
003BH
1841H
01E1H
0
1
2
3
4
5
6
MR3 PHY Identifier 2
MR4 Autonegotiation Advertisement
MR5 Autonegotiation Link Partner Ability
MR6 Autonegotiation Expansion
0000H
0000H
Tab - 17 The Embedded PHY Registers
Key to default:
Reset value
1: Bit set to logic one
0: Bit set to logic zero
X: No set value
Access type
RO: Read only
RW: Read or write
Attribute
SC: Self-clearing
PS: Value is permanently set
LL: Latch low
LH: Latch high
53
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
5.2.1 MR0 -- Control Register Bit Descriptions
Field
Type
Description (Default = 3100h)
0.15 (SW_RESET)
0, RW / SC 1 = Software reset
0 = Normal operation
0.14 (LOOPBACK)
0.13(SPEED100)
0, RW
1, RW
1, RW
1 = Loop-back enabled
0 = Normal operation
1 = 100Mbits/s
0 = 10Mbits/s
0.12 (NWAY_ENA)
1 = Auto negotiation enabled. Bits 8 and 13 of this register are ignored
when this bit is set.
0 = Auto negotiation disabled. Bits 8 and 13 of this register determine the
link speed and mode.
1 = Power down
0.11 (POWER DOWN) 0, RW
0 = Normal operation
1 = Isolate
0.10 (ISOLATE)
0, R/W
0 = Normal operation
0.9 (REDONWAY)
0, RW / SC Restart Autonegotiation.
1 = Restart auto negotiation
0 = Normal operation
0.8 (FULL_DUP)
0.7 (COLTST)
1, RW
0, RW
X, RO
Duplex Mode.
1 = Full duplex operation
0 = Normal operation
Collision Test.
1 = Collision test enabled
0 = Normal operation
Reserved.
0.6:0 (RESERVED)
Write as 0, read as “don’t care”
54
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
5.2.2 MR1 -- Status Register Bit Descriptions
Field
Type
Description (Default = 7809h)
1.15 (T4ABLE)
0, RO / PS
100Base-T4 Ability. This bit will always be a 0.
0 = AX88796B is not able to perform in 100BASE-T4 mode
100Base-TX Full-Duplex Ability.
1 = AX88796B is able to perform in 100BASE-TX full duplex mode
100Base-TX Half-Duplex Ability.
1 = AX88796B is able to perform in 100BASE-TX half duplex mode
10Base-T Full-Duplex Ability.
1 = AX88796B is able to perform in 10BASE-T full duplex mode
10Base-T Half-Duplex Ability.
1 = AX88796B is able to perform in 10BASE-T half duplex mode
Reserved.
1.14 (TXFULDUP)
1.13 (TXHAFDUP)
1.12 (ENFULDUP)
1.11 (ENHAFDUP)
1.10:7 (RESERVED)
1, RO /PS
1, RO / PS
1, RO / PS
1, RO / PS
0, RO
Write as 0, read as “don’t care”
1.6 (MF preamble
suppression)
0, RO
Management frame preamble suppression:
0 = AX88796B will not accept management frames with preamble
suppressed.
1.5 (NWAYDONE)
1.4 (REM_FLT)
0, RO
Autonegotiation Complete.
1= Auto negotiation process complete
0 = Auto negotiation process not complete
Remote Fault.
0, RO / LH
1 = Remote fault condition detected (cleared on read or by a chip reset)
0 = No remote fault condition detected
Autonegotiation Ability.
1 = AX88796B is able to perform auto-negotiation
Link Status.
1.3 (NWAYABLE)
1.2 (LSTAT_OK)
1, RO / PS
0, RO / LL
1 = Valid link established (100Mb/s or 10Mb/s operation)
0 = Link not established
1.1 (JABBER)
0, RO / LH
1, RO / PS
Jabber Detect.
1 = Jabber condition detected
0 = No Jabber condition detected
Extended Capability.
1.0 (EXT_ABLE)
1 = Extended register capable
0 = Basic register capable only
55
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
5.2.3 MR2 -- Identification 1 Registers
Field
Type
Description (Default = 003Bh)
2.15:0 (OUI[3:18])
RO
Organizationally Unique Identifier. The third through the twenty-fourth
bit of the OUI assigned to the PHY manufacturer by the IEEE are to be
placed in bits. 2.15:0 and 3.15:10.
5.2.3 MR3 – Identification 2 Registers
Field
3.15:10 (OUI[19:24]) RO
3.9:4 (MODEL[5:0]) RO
3.3:0 (VERSION[3:0]) RO
Type
Description (Default = 1841h)
Organizationally Unique Identifier. The remaining 6 bits of the OUI.
Model Number. 6-bit model number of the device.
Revision Number. The value of the present revision number
5.2.4 MR4 – Autonegotiation Advertisement Register
Field
Type
Description (Default = 01E1h)
4.15 (NEXT_PAGE)
0, RO / PS
Next Page.
0 = No next page available
AX88796B does not support the next page function.
4.14 (ACK)
0, RO
0, RW
Acknowledge.
1 = Link partner ability data reception acknowledged
0 = Not acknowledged
4.13 (REM_FAULT)
Remote Fault.
1= Fault condition detected and advertised
0 = No fault detected
4.12:11 (RESERVED) X, RW
Reserved.
Write as 0, read as “don’t care”
4.10 (PAUSE)
0, RW
Pause.
1 = Pause operation is enabled for full-duplex links
0 = Pause operation is not enabled
100Base-T4.
0 = 100BASE-T4 is not supported
100Base-TX Full Duplex.
4.9 (100BASET4)
0, RO / PS
1, RW
4.8 (100BASET_FD)
1 = 100BASE-TX full-duplex is supported by this device
0 = 100BASE-TX full-duplex is not supported by this device
100Base-TX Half Duplex.
1 = 100BASE-TX half-duplex is supported by this device
0 = 100BASE-TX half-duplex is not supported by this device
10Base-T Full Duplex.
1 = 10BASE-T full-duplex is supported by this PHY
0 = 10BASE-T full-duplex is not supported by this PHY
10Base-T Half Duplex.
4.7 (100BASETX)
4.6 (10BASET_FD)
4.5 (10BASET)
1, RW
R/W
R/W
1 = 10BASE-T half-duplex is supported by this PHY
0 = 10BASE-T half-duplex is not supported by this PHY
Selector Field. Reset with the value 00001 for IEEE 802.3.
4.4:0 (SELECT)
[0 0001],
RW
56
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
5.2.5 MR5 – Autonegotiation Link Partner Ability (Base Page) Register
Field
Type
Description (Default = 0000h)
5.15
0, RO
Link Partner Next Page.
(LP_NEXT_PAGE)
1 = Link partner is next page able
0 = Link partner is not next page able
5.14 (LP_ACK)
0, RO
0, RO
Link Partner Acknowledge.
1 = Link partner reception of data word acknowledged
0 = Not acknowledged
5.13
Remote Fault.
(LP_REM_FAULT)
1 = Remote fault indicated by link partner
0 = No remote fault indicated by link partner
Reserved.
5.12:11 (RESERVED) X, RO
Write as 0, read as “don’t care”
5.10 (LP_PAUSE)
5.9 (LP_T4)
0, RO
0, RO
0, RO
0, RO
0, RO
0, RO
Pause.
1 = Pause operation is supported by link partner
0 = Pause operation is not supported by link partner
Link Partner 100BASE-T4 supports.
1 = 100BASE-T4 is supported by link partner
0 = 100BASE-T4 is not supported by link partner
100BASE-TX full-duplex support.
1 = 100BASE-TX full-duplex is supported by link partner
0 = 100BASE-TX full-duplex is not supported by link partner
100BASE-TX half-duplex support.
1 = 100BASE-TX half-duplex is supported by link partner
0 = 100BASE-TX half-duplex is not supported by link partner
10BASE-T full-duplex support.
1 = 10BASE-T full-duplex is supported by link partner
0 = 10BASE-T full-duplex is not supported by link partner
10BASE-T half-duplex support.
1 = 10BASE-T half-duplex is supported by link partner
0 = 10BASE-T half-duplex is not supported by link partner
Selector Field.
5.8 (LP_ TX_FD)
5.7 (LP_ TX_HD)
5.6 (LP_ 10_FD)
5.5 (LP_ 10_HD)
5.4:0 (LP_SELECT)
[0 0000],
RO
Link partner’s binary encoded protocol selector
57
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
5.2.6 MR6 – Autonegotiation Expansion Register
Field
Type
Description (Default = 0000h)
6.15:5 (RESERVED)
0, RO
Reserved.
Write as 0, read as “don’t care”
6.4
0, RO / LH
0, RO
Parallel Detection Fault.
1 = Fault detected via the parallel detection function
0 = No fault detected
Link Partner Next Page Able.
1 = Link partner is next page able
0 = Link partner is not next page able
Next Page Able.
(PAR_DET_FAULT)
6.3
(LP_NEXT_PAGE_AB
LE)
6.2
(NEXT_PAGE_ABLE)
6.1 (PAGE_REC)
0, RO / PS
0, RO / LH
0 = PHY is not next page able
Page Received.
1 = New page received
0 = New page not received
Link Partner Autonegotiation Capable.
1 = Link partner auto-negotiation supported
6.0
0, RO
(LP_NWAY_ABLE)
58
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
6.0 CPU Read and Write Functions
6.1 ISA bus type access functions.
ISA bus Read function
Function Mode
Standby Mode
Byte Access
(For all of CSR
except DP)
CSn
H
L
AEN A0
RDn
X
L
WRn
X
H
SD[15:8]
High-Z
Not Valid
Not Valid
SD[7:0]
High-Z
Even-Byte
Odd-Byte
X
L
L
X
L
H
L
L
H
Word Access
(Only for DP
and WTS=1)
L
L
L
L
H
Odd-Byte
Even-Byte
ISA bus Write function
Function Mode
Standby Mode
Byte Access
(For all of CSR
except DP)
CSn
H
L
AEN A0
RDn
X
H
WRn
X
L
SD[15:8]
SD[7:0]
X
Even-Byte
Odd-Byte
X
L
L
X
L
H
X
X
X
L
H
L
Word Access
(Only for DP
and WTS=1)
L
L
L
H
L
Odd-Byte
Even-Byte
6.2 80186 CPU bus type access functions.
80186 CPU bus Read function
Function Mode
Standby Mode
Byte Access
(For all of CSR
except DP)
CSn
H
L
A0
X
L
RDn
X
L
WRn
X
H
SD[15:8]
SD[7:0]
High-Z
Even-Byte
Not Valid
High-Z
Not Valid
Odd-Byte
L
H
L
H
Word Access
(Only for DP
and WTS=1)
L
L
L
H
Odd-Byte
Even-Byte
80186 CPU bus Write function
Function Mode
Standby Mode
Byte Access
(For all of CSR
except DP)
CSn
H
L
A0
X
L
RDn
X
H
WRn
X
L
SD[15:8]
SD[7:0]
X
X
X
Even-Byte
X
L
H
H
L
Odd-Byte
Word Access
(Only for DP
and WTS=1)
L
L
H
L
Odd-Byte
Even-Byte
59
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
6.3 MCS-51 CPU bus type access functions.
8051 bus Read function
Function Mode
Standby Mode
CSn
H
X
L
L
PSEN SA0
RDn
X
X
L
L
WRn
X
X
H
H
SD[15:8]
High-Z
High-Z
Not Valid
Not Valid
SD[7:0]
High-Z
High-Z
Even-Byte
Odd-Byte
X
L
H
H
X
X
L
Byte Access
H
8051 bus Write function
Function Mode
Standby Mode
CSn
H
X
L
L
PSEN SA0
RDn
X
X
H
H
WRn
X
X
L
L
SD[15:8]
SD[7:0]
X
X
L
H
H
X
X
L
X
X
X
X
X
Byte Access
Even-Byte
Odd-Byte
H
60
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
6.5 CPU Access MII Serial Management Interface
Basic Operation
The primary function of station management is to transfer control and status information about the PHY to a
management entity. This function is accomplished by the MDC clock input from MAC entity. The maximum
frequency is 2.5 MHz.
The Internal PHY address is fixed to 10h and the equivalent circuit is shown as below:
From Register
Offset 14h
(Internal PHY)
MDIO-OUT MDIO-IN
MDC
MDC
MDO
MDI
Fig - 9 SMI connections
A specific set of registers and their contents (described in Tab - 19 MII Management Frames- field Description)
defines the nature of the information transferred across the MDIO interface. Frames transmitted on the MII
management interface will have the frame structure shown in Tab - 18 SMI Management Frame Format. The
order of bit transmission is from left to right. Note that reading and writing the management register must be
completed without interruption.
Read/Write Pre
(R/W)
ST
OP
PHYAD REGAD TA
DATA
IDLE
R
W
1. . .1
1. . .1
01
01
10
01
AAAAA RRRRR Z0
AAAAA RRRRR 10
DDDDDDDDDDDDDDDD
DDDDDDDDDDDDDDDD
Z
Z
Tab - 18 SMI Management Frame Format
Field
Pre
ST
Descriptions
Preamble. The PHY will accept frames with no preamble. This is indicated by a 1 in MR1 1, bit 6.
Start of Frame. The start of frame is indicated by a 01 pattern.
OP
Operation Code. The operation code for a read transaction is 10. The operation code for a write
transaction is a 01.
PHYADD
PHY Address. The PHY address is 5 bits, allowing for 32 unique addresses. The first PHY address
bit transmitted and received is the MSB of the address. A station management entity that is
attached to multiple PHY entities must have prior knowledge of the appropriate PHY address for
each entity.
REGAD
TA
Register Address. The register address is 5 bits, allowing for 32 unique registers within each PHY. The
first register address bit transmitted and received is the MSB of the address.
Turnaround. The turnaround time is a 2-bit time spacing between the register address field, and
the data field of a frame, to avoid drive contention on MDIO during a read transaction. During a
write to the PHY, these bits is driven to 10 by the station. During a read, the MDIO is not
driven during the first bit time and is driven to a 0 by the PHY during the second bit time.
Data. The data field is 16 bits. The first bit transmitted and received will be bit 15 of the register
being addressed.
DATA
IDLE
Idle Condition. The IDLE condition on MDIO is a high-impedance state. All three state drivers will be
disabled and the PHY’s pull-up resistor will pull the MDIO line to logic 1.
Tab - 19 MII Management Frames- field Description
61
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
7.0 Electrical Specification and Timings
7.1 Absolute Maximum Ratings
Description
VCCK (Core power supply)
VCCIO (power supply for 3.3V I/O)
VCCIO (Input voltage of 3.3V I/O with 5V tolerance)
Storage Temperature
Rating
-0.3 to 2.16
-0.3 to 4.0
-0.3 to 5.8
-65 to 150
20
Units
V
V
V
°C
mA
IIN (DC input current)
IOUT (Output short circuit current)
20
mA
7.2 General Operation Conditions
Description
Symbol
Min
0
Typ
Max
70
Units
°C
Operating Temperature
Ta
-40
85
Junction Temperature
Tj
Vcc18
Vcc3
-40
+1.62
+25
+1.8
+125
+1.98
°C
V
V
Supply Voltage for core (VCCK, VCC18A)
Supply Voltage (VCC3A3, VCC3IO, VCC3R3)
10BASE-T operation
+2.97 +3.30 +3.63
VCC3IO + VCC3A3 (3.3V)
VCCK + VCC18A (1.8V)
VCC3IO + VCC3A3 (3.3V)
VCCK + VCC18A (1.8V)
VCC3IO + VCC3A3 (3.3V)
VCCK + VCC18A (1.8V)
VCC3IO + VCC3A3 (3.3V)
VCCK + VCC18A (1.8V)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
30
20
30
88
24
17
0.04
0.26
mA
100BASE-TX operation
PHY power down
mA
mA
mA
D2 power saving mode
ꢀThermal Characteristics
Description
Thermal resistance of junction to case
Symbol
ΘJC
Rating
13.47
45.28
Units
°C/W
°C/W
Thermal resistance of junction to ambient
ΘJA
7.3 DC Characteristics
7.3.1 DC Characteristics of 3.3V with 5V Tolerance
Description
Symbol
Vil
Vih
Vol
Voh
Vt
Min
-
2.0
-
Typ
Max
0.8
-
0.4
-
Units
V
V
V
V
V
V
V
Low Input Voltage
High Input Voltage
Low Output Voltage
High Output Voltage
2.4
Switch threshold
1.5
1.1
1.6
75
Schmitt trigger negative going threshold voltage
Schmitt trigger positive going threshold voltage
Input pull-up resistance
Vt-
0.8
Vt+
Rpu
Rpd
2.0
190
190
10
40
40
KΩ
KΩ
uA
Input pull-down resistance
75
-10
±1
Input Leakage
Current
Iin
with pull-up resistance (Vin=0)
with pull-down
-15
15
-45
45
-85
85
uA
uA
resistance(Vin=VCC3I)
Tri-state Output Leakage Current
Ioz
62
-10
±1
10
uA
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
7.3.2 Power Consumption
ꢀ Device only
Power measurements base on 3.3V/25 °C condition.
Item
Symbol
Operating at Operating at PHY power
D2 power Units
saving
10BASE-T 100BASE-T
X
down
1
2
3
VCC3IO
VCC3A3
VCC3R3 (include VCCK,
VCC18A)
10
20
20
10
20
88
8
16
17
0.04
0
0.2
mA
mA
mA
4
VCC3IO + VCC3A3 + VCC3R3
50
165
118
390
41
135
0.24
0.8
mA
mW
ꢀ Device and system components
This is the total of Ethernet connectivity solution, which includes external components supporting the AX88796B
Ethernet controller as shown in the schematic as below.
Power measurements base on 3.3V/25 °C condition.
Total Power
(Typical)
462
Item
Test Conditions
Units
1
2
3
4
5
6
7
10BASE-T operation
100BASE-TX operation
mW
mW
mW
mW
mW
mW
mW
495
587
448
468
140
0.9
Cable unplug and non power saving mode
D1 power saving mode at 10BASE-T Link
D1 power saving mode at 100BASE-TX Link
PHY power down
D2 power saving mode
SD[0..15]
SA[0..5]
WAKE UP
J1 HEADER 1
U1
R1
SA1
SA0
AEN
CSN
RDN
WRN
SD10
SD11
SD12
SD13
SD14
SD15
GND
VCC33
VCC18
IRQ
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
SA1
SA0
AEN,PSEN
CSn
RDn
WRn
IOIS16
TCLK
TEST_CK_EN
GND
VCCK
VCC18A
XTALIN
XTALOUT
GND18A
RSET_BG
SD10
SD11
SD12
SD13
SD14
SD15
GND
VCC3IO
VCCK
IRQ
4.7K
CSN
RDN
WRN
ASIX
RESETN
IRQ
RESETN
IRQ
GND
LINK
D1
D2
D3
GREEN LED
YELLOW LED
ORANGE LED
R2
R3
R4
330
330
330
VCC18
VCC18A
XIN
XOUT
GND
PME
PME
PME
EECS
EECK
EEDIO
GND
SPEED
FULL
VCC33
AX88796B
PME
EECS
EECK
EEDIO
GND
VCC33
Y1 25.000MHZ
VCC33
GND
RESETN
RSTn
GND
R5
C1
1M
R6
C2
AX88796B
12.1K 1%
Place C10,C11 close to Pin 10: VCC3R3
Place C8,C9 close to Pin 9:V18F
VCC33
VCC33
VCC3A
L1
C3
C12
C4
0.1uF
F.B.
C5
10uF 10V
C6
0.1uF
C7
C13
C14
C15
0.1uF
+
0.1uF
C8
C9
C10
C11
22uF/16V
0.1uF
0.1uF
0.1uF
10uF 10V
0.1uF
10uF 10V
0.1uF
R7
49.9
R8
49.9
VCC18
VCC18
VCC18A
C21
CON1
TPI-
TPI+
L2
8
7
6
5
4
3
2
1
RX-
RX+
NC
NC
NC
CT
TX-
TX+
C18
C19
C20
0.1uF
C26 F.B.
0.1uF
C28
C27
C22
VCC3A
0.1uF
0.1uF
10uF 10V 0.1uF
0.1uF
0.1uF
TPO-
TPO+
LU1S041X
R9
49.9
R10
49.9
C16
0.1uF
C17
1uF
OptionVCC33
VCC33
R11
C23
U2
EECS
EECK
EEDIO
EEDIO
R12
R13
4.7K
4.7K
1
2
3
4
8
7
6
5
CS
SK
DI
VCC
NC
NC
C25
0.1uF
C24
0.1uF
1M
0.1uF
DO
GND
93C46
63
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
7.4 AC Timing Characteristics
7.4.1 Reset Timing
Trst
RSTn
Configuration Signals
Output Drive
Is
Ih
Oen
Symbol
Trst
Is
Description
Min
200
80
Typ.
-
Max
-
Units
us
ns
ns
ns
Reset pulse width
Configuration input setup to RSTn rising
Configuration input hold after RSTn rising
Output driver after RSTn rising
Ih
10
Oen
80
64
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
7.4.2 ISA Bus Access Timing
(1) Read cycle:
AEN, CSn, SA[5:0]
Tah
Tcycle
Tasu
Trdl
Trdh
RDn
Tdv
Tdon
Tdoh
Tdoff
SD[15:0]
IOIS16n
Tonis16
Tof fis16
Symbol
Tasu
Description
ADDRESS SETUP TIME
Min
Typ.
Max
-
-
11
Units
ns
ns
ns
ns
0
0
-
-
-
-
-
-
-
-
Tah
ADDRESS HOLD TIME
Tonis16
Toffis16
Tdv
IOIS16n VALID FROM SA[5:0], CSn AND AEN
IOIS16n VALID FROM SA[5:0], CSn AND AEN
DATA VALID TIME FROM RDn
6
33*1
ns
35*2
Tdoh
Trdl
DATA OUTPUT HOLD TIME
RDn LOW REQUIRE TIME
RDn HI REQUIRE TIME
0
35
13
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Trdh
Tdon
Tdoff
Tcycle
DATA BUFFER TURN ON TIME
DATA BUFFER TURN OFF TIME
READ CYCLE TIME
7
48
*1 : Base on SD bus output load 25pF
*2 : Base on SD bus output load 50pF
65
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
(2) Write cycle:
CSn, SA[5:0]
Tah
Tcycle
Tasu
Twrl
Twrh
WRn
SD[15:0]
IOIS16
Tds
Tdh
Tonis16
Toffis16
Symbol
Tasu
Description
ADDRESS SETUP TIME
Min
0
Typ.
-
Max
-
Units
ns
Tah
ADDRESS HOLD TIME
0
ns
Tonis16
Toffis16
Tds
IOIS16n VALID FROM SA[5:0], CSn AND AEN
IOIS16n DISABLE FROM SA[5:0], CSn AND AEN
DATA STABLE TIME
-
-
-
0
45
13
48
-
-
-
-
-
-
-
11
6
15
-
-
-
ns
ns
ns
ns
ns
ns
ns
Tdh
DATA HOLD TIME
Twrl
WRn WIDTH TIME
Twrh
Tcycle
WRn HI REQUIRE TIME
WRITE CYCLE TIME
-
66
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
7.4.3 80186 Type I/O Access Timing
(1) Read cycle:
CSn, SA[5:0]
Tah
Tcycle
Tas u
Trdl
Trdh
RDn
Tdv
Tdon
Tdoh
Tdoff
SD[15:0]
Symbol
Tasu
Description
ADDRESS SETUP TIME
Min
Typ.
Max
-
Units
ns
ns
0
0
-
-
-
-
Tah
ADDRESS HOLD TIME
-
33*1
ns
Tdv
DATA VALID TIME FROM RDn
35*2
Tdoh
Trdl
DATA OUTPUT HOLD TIME
RDn LOW REQUIRE TIME
RDn HI REQUIRE TIME
0
35
13
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Trdh
Tdon
Tdoff
Tcycle
DATA BUFFER TURN ON TIME
DATA BUFFER TURN OFF TIME
READ CYCLE TIME
7
48
*1 : Base on SD bus output load 25pF
*2 : Base on SD bus output load 50pF
67
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
(2) Write Cycle
CSn, SA[5:0]
Tah
Tcycle
Tas u
Tw rl
Tw rh
WRn
Tds
Tdh
SD[15:0]
Symbol
Tasu
Tah
Description
ADDRESS SETUP TIME
Min
0
0
-
0
35
13
48
Typ.
Max
-
-
15
-
-
Units
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
ADDRESS HOLD TIME
DATA STABLE TIME
DATA HOLD TIME
Tds
Tdh
Twrl
Twrh
Tcycle
WRn WIDTH TIME
WRn HI REQUIRE TIME
WRITE CYCLE TIME
-
-
68
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
7.4.4 8051 Bus Access Timing
(1) Read cycle
PSEN, CSn, SA [5:0]
Tah
Tcycle
Tasu
Trdl
Trdh
RDn
Tdv
Tdon
Tdoh
Tdoff
SD[15:0]
Symbol
Tasu
Description
ADDRESS SETUP TIME
Min
Typ.
Max
-
Units
ns
ns
0
0
-
-
-
-
Tah
ADDRESS HOLD TIME
-
33*1
ns
Tdv
DATA VALID TIME FROM RDn
35*2
Tdoh
Trdl
DATA OUTPUT HOLD TIME
RDn LOW REQUIRE TIME
RDn HI REQUIRE TIME
0
35
13
0
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
Trdh
Tdon
Tdoff
Tcycle
DATA BUFFER TURN ON TIME
DATA BUFFER TURN OFF TIME
READ CYCLE TIME
7
48
*1 : Base on SD bus output load 25pF
*2 : Base on SD bus output load 50pF
69
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
ꢀ
(2) Write cycle
PSEN, CSn, SA [5:0]
Tah
Tcycle
Tasu
Tw rl
Tw rh
WRn
Tds
Tdh
SD[15:0]
Symbol
Tasu
Description
ADDRESS SETUP TIME
Min
0
0
-
0
35
13
48
Typ.
Max
-
-
15
-
-
Units
ns
ns
ns
ns
ns
ns
ns
-
-
-
-
-
-
-
Tah
ADDRESS HOLD TIME
Tds
DATA STABLE TIME
DATA HOLD TIME
WRn WIDTH TIME
Tdh
Twrl
Twrh
Tcycle
WRn HI REQUIRE TIME
WRITE CYCLE TIME
-
-
70
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
7.4.5 Burst Reads Access Timing
Burst read access is enabled when set FIFO_SEL(SA5) is driven high during a read access. This is normally
accomplished by connecting the FIFO_SEL(SA5) signal to a high-order address line. This mode is useful when
the host processor must increment its address when accessing the AX88796B.
In this mode, performance is improved by allowing an unlimited number of back-to-back WORDS read cycles.
AX88796B base on SA0 or SA1 address toggles to identify WORD access cycle time. Host can set burst cycle
base on SA0 or SA1 toggle by BCB1 (CR page3 Offset 0Dh).
FIFO_SEL(SA5)
Tacyc
Tacy c
Tacyc
SA1 or SA0
CSn, RDn
SD[15:0]
Trdh
Tah
Tas u
Tdon
Tdv
Tdoff
Tdoh
Tadv
Tadv
Tadv
Symbol
Tasu
Description
ADDRESS SETUP TIME
Min
Typ.
Max
-
-
Units
ns
ns
0
0
-
-
-
-
Tah
ADDRESS HOLD TIME
33*1
35*2
33*1
35*2
-
ns
Tdv
DATA VALID TIME FROM RDn
Tadv
DATA VALID TIME FROM ADDRESS
ns
Tdoh
Trdh
DATA OUTPUT HOLD TIME
RDn HI REQUIRE TIME
READ CYCLE TIME
0
13
48
0
-
-
ns
ns
ns
ns
ns
-
Tacyc
Tdon
Tdoff
DATA BUFFER TURN ON
DATA BUFFER TURN OFF
7
*1 : Base on SD bus output load 25pF
*2 : Base on SD bus output load 50pF
71
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
8.0 Package Information
He
E
A
A2 A1
e
pin 1
b
θ
Symbol
Dimension
(mm)
MIN.
0.05
TYP
MAX
0.15
A1
A2
A
1.35
1.40
1.45
1.60
b
0.13
0.18
7.00
7.00
0.40
9.00
9.00
0.60
1.00
3.5°
0.23
D
E
e
Hd
He
L
0.45
0°
0.75
7°
L1
θ
72
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
9.0 Ordering Information
Model NO
AX88796BLF
Description
64 PIN, LQFP Package, Commercial grade 0°C to +70 °C (Green,
Lead-Free)
AX88796BLI
64 PIN, LQFP Package, Industrial grade -40°C to +85 °C (Green,
Lead-Free)
73
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
Appendix A1: MCS51-like (8-bit)
An example, AX88796B’s bus setting as MCS-51 mode. (Two external pull-up resister connect to EECS and
EECK)
AX88796B
MCS-51
A0
A1
A2
A3
A4
A5
SA0
SA1
SA2
SA3
SA4
SA5/FIFO_SEL
AEN/PSEN
SD[7:0]
RDn
SD[15:8]
PSEN
DATA[7:0]
RDn
WRn
INT
WRn
IRQ
Read
Write
SD[7:0]
Host Addr
SD[15:8]
SD[7:0]
AX88796B Host Addr
CSR Offset A[5:0]
SD[15:8]
AX88796B
A[5:0]
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
CSR Offset
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Offset 1
Offset 1
Offset 3
Offset 3
Offset 5
Offset 5
Offset 7
Offset 7
Offset 9
Offset 9
Offset B
Offset B
Offset D
Offset D
Offset F
Offset F
(DP)
Offset 0
Offset 1
Offset 2
Offset 3
Offset 4
Offset 5
Offset 6
Offset 7
Offset 8
Offset 9
Offset A
Offset B
Offset C
Offset D
Offset E
Offset F
(DP)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
X
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
To Offset 0
To Offset 1
To Offset 2
To Offset 3
To Offset 4
To Offset 5
To Offset 6
To Offset 7
To Offset 8
To Offset 9
To Offset A
To Offset B
To Offset C
To Offset D
To Offset E
To Offset F
(DP)
(DP)
X
(DP)
X
X
X
X
Offset 13
Offset 13
Offset 15
Offset 15
Offset 17
Offset 17
Offset 19
Offset 19
Offset 1B
Offset 1B
Offset 1D
Offset 1D
No effect
(Reset) *1
Offset 12
Offset 13
Offset 14
Offset 15
Offset 16
Offset 17
Offset 18
Offset 19
Offset 1A
Offset 1B
Offset 1C
Offset 1D
Offset 1E
(Reset) *1
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
To Offset 12 12
To Offset 13 13
To Offset 14 14
To Offset 15 15
To Offset 16 16
To Offset 17 17
To Offset 18 18
To Offset 19 19
To Offset 1A 1A
To Offset 1B 1B
To Offset 1C 1C
To Offset 1D 1D
To Offset 1E 1E
To Offset 1F 1F
*1 Read offset 1Fh register will reset AX88796B
74
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
Appendix A2: ISA-like (8/16-bit)
An example, AX88796B’s bus setting as ISA mode. (No external resister connect to EECS and EECK)
AX88796B
SA0
ISA
A0
A1
A2
A3
A4
SA1
SA2
SA3
SA4
SA5/FIFO_SEL
AEN/PSEN
SD[15:0]
RDn
A5
AEN
DATA[15:0]
IORDn
IOWRn
INT
WRn
IRQ
CSR Read
CSR Write
SD[7:0]
Host Addr
SD[15:8]
SD[7:0]
AX88796B Host Addr
CSR Offset A[5:0]
SD[15:8]
AX88796B
A[5:0]
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
CSR Offset
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Offset 1
Offset 1
Offset 3
Offset 3
Offset 5
Offset 5
Offset 7
Offset 7
Offset 9
Offset 9
Offset B
Offset B
Offset D
Offset D
Offset F
Offset F
(DP)
Offset 0
Offset 1
Offset 2
Offset 3
Offset 4
Offset 5
Offset 6
Offset 7
Offset 8
Offset 9
Offset A
Offset B
Offset C
Offset D
Offset E
Offset F
(DP)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
(DP)
To Offset 0
To Offset 1
To Offset 2
To Offset 3
To Offset 4
To Offset 5
To Offset 6
To Offset 7
To Offset 8
To Offset 9
To Offset A
To Offset B
To Offset C
To Offset D
To Offset E
To Offset F
(DP)
(DP)
X
(DP)
X
X
X
X
X
Offset 13
Offset 13
Offset 15
Offset 15
Offset 17
Offset 17
Offset 19
Offset 19
Offset 1B
Offset 1B
Offset 1D
Offset 1D
No effect
(Reset) *1
Offset 12
Offset 13
Offset 14
Offset 15
Offset 16
Offset 17
Offset 18
Offset 19
Offset 1A
Offset 1B
Offset 1C
Offset 1D
Offset 1E
(Reset) *1
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
To Offset 12 12
To Offset 13 13
To Offset 14 14
To Offset 15 15
To Offset 16 16
To Offset 17 17
To Offset 18 18
To Offset 19 19
To Offset 1A 1A
To Offset 1B 1B
To Offset 1C 1C
To Offset 1D 1D
To Offset 1E 1E
To Offset 1F 1F
*1 Read offset 1Fh register will reset AX88796B
75
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
Appendix A3: 186-like (16-bit)
An example, AX88796B’s bus setting as 186 mode. (One external pull-up resister connect to EECK)
AX88796B
16-bit processor
A0
A1
A2
A3
A4
A5
SA0
SA1
SA2
SA3
SA4
SA5/FIFO_SEL
AEN/PSEN
SD[15:0]
RDn
WRn
IRQ
DATA[15:0]
RDn
WRn
INT
Read
Write
SD[7:0]
Host Addr
SD[15:8]
SD[7:0]
AX88796B Host Addr
CSR Offset A[5:0]
SD[15:8]
no effect
AX88796B
CSR Offset
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
A[5:0]
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
Offset 1
Offset 1
Offset 3
Offset 3
Offset 5
Offset 5
Offset 7
Offset 7
Offset 9
Offset 9
Offset B
Offset B
Offset D
Offset D
Offset F
Offset F
(DP)
Offset 0
Offset 0
Offset 2
Offset 2
Offset 4
Offset 4
Offset 6
Offset 6
Offset 8
Offset 8
Offset A
Offset A
Offset C
Offset C
Offset E
Offset E
(DP)
0
0
To Offset 0
1
1
To Offset 1 no effect
no effect To Offset 2
To Offset 3 no effect
no effect To Offset 4
To Offset 5 no effect
no effect To Offset 6
To Offset 7 no effect
no effect To Offset 8
To Offset 9 no effect
To Offset A
To Offset B no effect
To Offset C
To Offset D no effect
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
A
A
no effect
B
B
C
C
no effect
D
D
E
E
no effect
To Offset E
To Offset F no effect
F
F
(DP)
X
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
(DP)
X
no effect
(DP)
X
(DP)
X
X
X
Offset 13
Offset 13
Offset 15
Offset 15
Offset 17
Offset 17
Offset 19
Offset 19
Offset 1B
Offset 1B
Offset 1D
Offset 1D
No effect
(Reset) *1
Offset 12
Offset 12
Offset 14
Offset 14
Offset 16
Offset 16
Offset 18
Offset 18
Offset 1A
Offset 1A
Offset 1C
Offset 1C
Offset 1E
(Reset) *1
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
To Offset 12 12
13
To Offset 14 14
To Offset 15 no effect 15
no effect To Offset 16 16
To Offset 17 no effect 17
no effect To Offset 18 18
To Offset 19 no effect 19
no effect To Offset 1A 1A
To Offset 1B no effect 1B
no effect To Offset 1C 1C
To Offset 1D no effect 1D
no effect To Offset 1E 1E
To Offset 1F no effect 1F
To Offset 13 no effect
no effect
*1 Read offset 1Fh register will reset AX88796B
76
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
Appendix A4: co-work with 32-bit processor
An example, AX88796B co-work with Samsung 2440 processor. (32-bit processor with external 16-bit bus)
AX88796B’s bus setting as ISA mode. (Without external resister connect to EECS and EECK) Host can use burst
read mode, it is useful host processor increment its address when moving AX88796B received data.
AX88796B supports two kinds of Data Port for receiving/transmitting packets from/to AX88796B. One is the PIO
Data Port (offset 10h); the other one is the SRAM-like Data Port (e.g. offset 800h ~ FFFh for Samsung2440
processor as described in below figure). The SRAM-like Data Port address range depends on which address line of
host processor is being connected to the address line SA5/FIFO_SEL of AX88796B.
Software on host CPU can issue Single Data Read/Write command to both PIO Data Port and SRAM-like Data Port.
However, to use Burst Data Read/Write commands, one has to use SRAM-like Data Port, which requires
SA5/FIFO_SEL (pin 45) of AX88796B connecting to an upper address line of host CPU. AX88796B with Samsung
2440 processor reference schematic has SA5/FIFO_SEL pin connected to upper address line (i.e. A11 of Samsung
2440) for supporting Burst Data Read/Write commands.
AX88796B
A0
A1
A2
A3
A4
A5
A0
A1
A2
A3
A4
A11
CSn
RDn
WRn
INT
A5/FIFO_SEL
CSn
RDn
WRn
IRQ
AEN/PSEN
Samsung2440
Read
Write
SD[7:0]
Host Addr
SD[15:8]
SD[7:0]
AX88796B Host Addr
CSR Offset A[11:0]
SD[15:8]
AX88796B
A[11:0]
0
2
4
6
8
A
C
E
10
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
2E
CSR Offset
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
Offset 1
Offset 1
Offset 3
Offset 3
Offset 5
Offset 5
Offset 7
Offset 7
Offset 9
Offset 9
Offset B
Offset B
Offset D
Offset D
Offset F
Offset F
10 (DP)
X
Offset 0
Offset 1
Offset 2
Offset 3
Offset 4
Offset 5
Offset 6
Offset 7
Offset 8
Offset 9
Offset A
Offset B
Offset C
Offset D
Offset E
Offset F
10 (DP)
X
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
2
4
6
8
A
C
E
10
12
14
16
18
1A
1C
1E
20
22
24
26
28
2A
2C
2E
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
10 (DP)
X
To Offset 0
To Offset 1
To Offset 2
To Offset 3
To Offset 4
To Offset 5
To Offset 6
To Offset 7
To Offset 8
To Offset 9
To Offset A
To Offset B
To Offset C
To Offset D
To Offset E
To Offset F
10 (DP)
F
10 (DP)
X
10 (DP)
X
X
Offset 13
Offset 13
Offset 15
Offset 15
Offset 17
Offset 17
Offset 12
Offset 13
Offset 14
Offset 15
Offset 16
Offset 17
12
13
14
15
16
17
no effect
no effect
no effect
no effect
no effect
no effect
To Offset 12 12
To Offset 13 13
To Offset 14 14
To Offset 15 15
To Offset 16 16
To Offset 17 17
77
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
30
32
34
36
38
3A
3C
3E
Offset 19
Offset 19
Offset 1B
Offset 1B
Offset 1D
Offset 1D
No effect
(Reset) *1
No used
Offset 18
Offset 19
Offset 1A
Offset 1B
Offset 1C
Offset 1D
Offset 1E
(Reset) *1
No used
18
19
1A
1B
1C
1D
1E
1F
30
32
34
36
38
3A
3C
3E
no effect
no effect
no effect
no effect
no effect
no effect
no effect
no effect
No used
(DP)
To Offset 18 18
To Offset 19 19
To Offset 1A 1A
To Offset 1B 1B
To Offset 1C 1C
To Offset 1D 1D
To Offset 1E 1E
To Offset 1F 1F
40 ~7FF
800 ~ FFF
No used
10 (DP)
40 ~7FF
800 ~ FFF
No used
(DP)
No used
10 (DP)
(DP)
(DP)
*1 Read offset 1Fh register will reset AX88796B
78
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
Appendix A5: big-endian processor of Data Byte Lands
An example, AX88796B co-work with big-endian processor like Renesas H8/SH2 MCU, etc.. (To support
big-endian processors, the hardware designer must explicitly swap the connection of data byte lanes.)
AX88796B
ADDR
D[7:0]
ADDR
D[7:0]
D[15:8]
D[15:8]
CSn
RDn
WRn
INT
CSn
RDn
WRn
IRQ
Big-endian
Processor
79
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
Appendix B: Disable AX88796B voltage regulator
AX88796B integrates an on-chip 3.3V to 1.8V voltage regulator for single-power supply system design. If the
system have 1.8V power source already, user may like to disable AX88796B voltage regulator and use the existing
1.8V power source (probably a higher efficiency version). In that case, user can connect VCC3R3 (pin-10) and
GND3R3 (pin-11) to ground, keep V18F (pin-9) open, and set REGSTB bit of PMR register (see Page3 Offset 0BH
bit-4 in section 5.1.56 Power Management Register (PMR)) to 0 (i.e. logic "low") to avoid the leakage current.
Please refer to below picture for details.
AX88796B
Keep NC without loading
V18F
REGSTB
Logic “low”
Supply Analog 1.8V from existing power
source on system
VCC18A
Supply Digital 1.8V from existing power source
on system
VCCK
VCC3R3
GND3R3
Note: If user connects the VCC3R3 to 3.3V VCC and wants to disable the internal voltage regulator of AX88796B,
the REGSTB bit of PMR register should be set to 1 to set the regulator in standby mode to reduce the leakage
current.
80
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
Reversion History
Revision
V1.0
V1.1
Date
2006/03/01
2006/03/31
Comment
Initial Release.
1. Correct some typo errors.
2. Change page3 offset 0Dh register name from P30D to MISC.
3. Change the name of bit 5 of MCR register from TQCE to BBTC.
4. Define a short name “TXCQF” for bit 7 of CTEPR register.
5. Add the default values of PHY registers into Section 5.2.
1. Correct the pin descriptions of pin 60 and 63 in Figure 2 and Section
2-5.
V1.2
2006/09/08
2. Correct the Wakeup Frame registers configuration information in
Section 4.3.1.
3. Update the reference schematics in Section 7.3.2, Appendix A1.
4. Remove Demonstration Circuit A, B, C reference schematics.
1. Modify the resistance value of pin 64 (RSET_BG) from 11.8 ±1% K
ohm to 12.1 ±1% K ohm.
V1.3
V1.4
2006/09/20
2006/10/05
1. Add Thermal Resistance values (ΘJc, ΘJA) of Junction in Section
7.3.2.
2. Correct the SD[7:0] values of Read cycle in Appendix A3 “186-like
(16-bit)”.
3. Correct the SD[7:0] and SD[15:8] values of offset 1Fh register Read
cycle in Appendix A1~A4.
V1.5
2007/3/19
1. Add US patent approved (NO 6799231) and VLAN in the Features
page.
2. Change the product name in the Features page.
3. Correct the TPI+/TPI- pin name of AX88796B Pin Out Diagram in
Section 1.3.
4. Modify some pin descriptions in Section 2.2 and 2.5.
5. Modify the Wake-up Configuration descriptions in Section 4.3.1 and
5.1.54.
6. Change the Storage Temperature to –65 to 150 °C in Section 7.1.
7. Add Appendix A5 to indicate the reference connection for big-endian
processor.
8. Add Appendix B to indicate how to disable the internal regulator.
1. Modify the description of SA5/FIFO_SEL pin in Section 2.1 and
Appendix A4.
2. Swapped the pin name of XTALIN and XTALOUT in Section 2.5
and Figure 2.
V1.6
V1.7
2007/4/27
2007/8/18
1. Correct a typo in Revision History table.
2. Add some information into Section 7.2.
81
ASIX ELECTRONICS CORPORATION
AX88796BLF / AX88796BLI
4F, No.8, Hsin Ann Rd., Hsinchu Science Park,
Hsinchu, Taiwan, R.O.C.
TEL: +886-3-5799500
FAX: +886-3-5799558
Email: support@asix.com.tw
Web: http://www.asix.com.tw
82
ASIX ELECTRONICS CORPORATION
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