AS6VA5128-TC [ALSC]
Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32;
| 型号： | AS6VA5128-TC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 512KX8, 55ns, CMOS, PDSO32, 8 X 20 MM, TSOP1-32 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总11页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2000
AS6VA5128
®
2.7V to 3.3V 512K × 8 Intelliwatt™ low-power CMOS SRAM with one chip enable
Features
• AS6VA5128
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 36(48)-ball FBGA
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 524,288 words × 8 bits
• 2.7V to 3.3V at 55 ns
• Low power consumption: ACTIVE
- 132 mW at 3.3V and 55 ns
• Low power consumption: STANDBY
- 66 µW max at 3.3V
- 32-pin TSOP I (available September 2000)
- 32-pin sTSOP I (available September 2000)
- 32-pin TSOP II (forward) (available September 2000)
- 32-pin TSOP II (reverse) (available September 2000)
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
• 1.2V data retention
• Equal access and cycle times
Pin arrangement
Logic block diagram
V
CC
A18
A16
A14
1
2
3
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
32
31
30
29
28
27
26
25
24
V
A18
A16
A14
A12
A7
A6
A5
A4
A3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
V
CC
CC
GND
A15
A17
WE
A13
A8
A15
A17
WE
A13
A8
Input buffer
A12
4
A7
A6
A5
A4
A3
A2
A1
A0
5
6
7
8
9
10
11
12
13
14
15
16
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A11
A9
I/ O8
I/ O1
32-pin TSOPII
(Forward)
32-pin TSOPII
(Reverse)
A11
OE
A10
CS
I/ O8
I/ O7
I/ O6
I/ O5
OE
A10
512K
× 8
A2
A1
A0
23
22
21
Array
(4,194,304)
CS
I/ O8
I/ O7
I/ O6
I/ O5
20 I/ O1
19
18 I/ O3
17
I/ O1
I/ O2
I/ O3
I/ O2
V
I/ O4
V
SS
I/ O4
SS
WE
OE
CS
Column decoder
Control
circuit
A11
A9
A8
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
OE
A10
CS
I/ O8
I/ O7
I/ O6
I/ O5
I/ O4
A13
48-CSP BGA Package (shading indicates no ball)
WE
A17
A15
1
2
3
4
5
6
32-pin TSOPII
32-pin sTSOPI
(Forward)
V
CC
A
B
C
D
E
A
A
NC
WE
NC
A
A
A
9
10
11
0
1
3
6
8
A18
A16
A14
A12
V
SS
I/ O3
I/ O2
I/ O1
A0
A1
A2
I/ O5
I/ O6
A
A
A
7
I/ O1
I/ O2
VCC
2
4
12
13
14
15
16
A
A7
A6
A5
A4
20
19
18
17
5
V
SS
A3
VCC
I/ O7
I/ O8
VSS
F
A
A
I/ O3
I/ O4
18
17
G
H
OE
CS
A
A
15
16
A
A
A
A
A
A
14
9
10
11
12
13
Selection guide
VCC Range
Power Dissipation
Operating (ICC1
)
Standby (ISB2)
Min
(V)
Typ2
(V)
Max
(V)
Speed
(ns)
Product
Max (mA)
2
Max (µA)
AS6VA5128
2.7
3.0
3.3
55
20
7/ 14/ 00
ALLIANCE SEMICONDUCTOR
1
Copyright ©2000 Alliance Semiconductor. All rights reserved.
AS6VA5128
®
Functional description
The AS6VA5128 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 524,288
words × 8 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip
selects (CS) permit easy memory expansion with multiple-bank memory systems.
When CS is high, the device enters standby mode: the AS6VA5128 is guaranteed not to exceed 66 µW power consumption at
3.3V and 55ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low. Data on the input pins I/ O1–I/ O8 is
written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive
I/ O pins only after outputs have been disabled with output enable ( OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), with write enable (WE) High. The chip drives
I/ O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Thedevice is available in
the JEDEC standard 32-pin TSOP I, 32-pin sTSOP I, 400-mL TSOP II, and 36(48)-ball FBGA packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
–0.5
–0.5
–
Max
Unit
V
Voltage on VCC relative to V
V
VCC + 0.5
SS
tIN
Voltage on any I/ O pin relative to GND
Power dissipation
V
V
tI/ O
PD
1.0
+150
+125
20
W
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
Tstg
Tbias
IOUT
–65
–55
–
°C
°C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specificati on is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
CS
H
L
WE
X
OE
X
Supply Current
I/ O1–I/ O8
High Z
High Z
High Z
DOUT
Mode
Standby (ISB)
Standby (ISB)
Output disable (ICC)
Read (ICC)
ISB
ISB
ICC
ICC
ICC
X
X
L
H
H
L
H
L
L
L
X
D
Write (ICC)
IN
Key: X = Don’t care, L = Low, H = High.
2
ALLIANCE SEMICONDUCTOR
7/ 14/ 00
AS6VA5128
®
Recommended operating condition (over the operating range)
Parameter
Description
Test Conditions
Min
2.4
Max
Unit
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Load Current
IOH = –2.1mA
IOL = 2.1mA
VCC = 2.7V
OH
V
VCC = 2.7V
VCC = 2.7V
VCC = 2.7V
0.4
VCC + 0.5
0.8
V
OL
V
2.2
–0.5
–1
V
IH
V
V
IL
IIX
GND < VIN < VCC
GND < V < VCC; Outputs High Z
+1
µA
µA
IOZ
–1
+1
O
CS = V ,
IOUT = 0mA, f = 0,
IL
VCC Operating Supply
Current
ICC
VCC = 3.3V
VCC = 3.3V
2
2
mA
mA
V
IN = V or V
IL IH
CS < 0.2V, V < 0.2V,
or VIN > VCC – 0.2V,
f = 1 mS
IN
ICC1
@
Average VCC Operating
1 MHz Supply Current at 1 MHz
Average VCC Operating CS ≠ V , VIN = V or
IL
IL
ICC2
ISB
VCC = 3.3V (55 ns)
VCC = 3.3V
40
mA
Supply Current
V , f = fMax
IH
CS Power Down Current; CS > V , other inputs
IH
100
µA
TTL Inputs
= 0V – VCC
CS > VCC – 0.2V,
other inputs = 0V –
VCC, f = fMax
CS Power Down Current;
CMOS Inputs
ISB1
VCC = 3.3V
VCC = 1.2V
20
2
µA
µA
CS > VCC – 0.1V,
f = 0
ISBDR
Data Retention
Capacitance (f = 1 MHz, T = Room temperature, V = NOMINAL)
a
CC
Signals
Parameter
Input capacitance
Symbol
Test conditions
IN = 0V
IN = VOUT = 0V
Max
5
Unit
C
A, CS, WE, OE
I/ O
V
pF
pF
IN
I/ O capacitance
C
V
7
I/ O
7/ 14/ 00
ALLIANCE SEMICONDUCTOR
3
AS6VA5128
®
Read cycle (over the operating range)
Parameter
Read cycle time
Symbol
tRC
Min
55
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Address access time
tAA
55
55
25
–
3
3
Chip select (CS) access time
Output enable (OE) access time
Output hold from address change
CS low to output in low Z
CS high to output in high Z
OE low to output in low Z
OE high to output in high Z
Power up time
tACS
tOE
–
–
tOH
10
10
0
5
tCLZ
tCHZ
tOLZ
tOHZ
tPU
–
4, 5
4, 5
4, 5
4, 5
4, 5
4, 5
20
–
5
0
20
–
0
Power down time
tPD
–
55
Shaded areas indicate preliminary information.
Key to switching waveforms
Rising input
Falling input
Undefined/ don’t care
Read waveform 1 (address controlled)
t
RC
Address
t
AA
t
t
OH
OH
D
Previous data valid
Data valid
OUT
Read waveform 2 (CS, OE controlled)
t
RC1
CS
t
OE
OE
t
t
OHZ
OLZ
t
t
ACE
CHZ
D
OUT
Data valid
t
CLZ
t
PD
I
CC
t
Supply
current
PU
I
SB
50%
50%
4
ALLIANCE SEMICONDUCTOR
7/ 14/ 00
AS6VA5128
®
Write cycle (over the operating range)
Parameter
Symbol
tWC
tCW
tAW
tAS
Min
55
40
40
0
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
Write cycle time
Chip select to write end
Address setup to write end
Address setup time
–
–
–
12
Write pulse width
tWP
tAH
tDW
tDH
tWZ
tOW
35
0
–
Address hold from end of write
Data valid to write end
Data hold time
–
25
0
–
–
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
Shaded aread indicate preliminary information.
0
20
–
5
Write waveform 1 (WE controlled)
t
WC
t
t
t
AW
AH
DH
Address
WE
t
WP
t
AS
t
DW
D
Data valid
IN
t
t
WZ
OW
D
OUT
Write waveform 2 (CS controlled)
t
WC
t
t
AH
AW
Address
t
t
CW
AS
CS
t
WP
WE
t
t
t
DH
WZ
DW
D
Data valid
IN
D
OUT
7/ 14/ 00
ALLIANCE SEMICONDUCTOR
5
AS6VA5128
®
Data retention characteristics (over the operating range)
Parameter
Symbol
Test conditions
Min
1.2V
–
Max
3.3
2
Unit
V
V
CC for data retention
VDR
VCC = 1.2V
CS ≥ VCC – 0.1V or
Data retention current
ICCDR
tCDR
tR
µA
ns
V
≥ VCC – 0.1V or
Chip deselect to data retention time
Operation recovery time
0
–
IN
V
≤ 0.1V
IN
tRC
–
ns
Data retention waveform
Data retention mode
1.2V
V
V
V
CC
V
≥
CC
CC
DR
t
t
R
CDR
V
DR
V
V
IH
CS
IH
AC test loads and waveforms
Thevenin equivalent:
R1
R1
V
R
CC
V
TH
CC
V
OUTPUT
OUTPUT
OUTPUT
30 pF
5 pF
ALL INPUT PULSES
V
Typ
R2
CC
R2
90%
10%
90%
10%
INCLUDING
JIG AND
INCLUDING
JIG AND
SCOPE
< 5 ns
(c)
GND
(a)
SCOPE
(b)
Parameters
VCC = 3.0V
1105
VCC = 2.5V
16670
15380
8000
VCC = 2.0V
15294
Unit
R1
R2
Ohms
Ohms
Ohms
Volts
1550
11300
RTH
645
6500
V
1.75V
1.2V
0.85V
TH
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CS is required to meet I specification.
This parameter is sampled, but not 100% tested.
CC CC SB
For test conditions, see AC Test Conditions.
t
and t are specified with C = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
CHZ L
CLZ
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CS and OE are LOW for read cycle.
Address valid prior to or coincident with CS transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/ A.
13 1.2V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
6
ALLIANCE SEMICONDUCTOR
7/ 14/ 00
AS6VA5128
®
Typical DC and AC characteristics
Normalized supply current
vs. supply voltage
1.4
Normalized access time
vs. supply voltage
Normalized standby current
vs. ambient temperature
1.0
3.0
2.5
2.0
1.2
1.0
0.8
V
= V typ
CC
CC
0.75
0.5
V
= V typ
IN
CC
1.5
1.0
0.5
T = 25° C
A
V
= V typ
CC
0.6
0.4
0.2
0.0
IN
T = 25° C
A
0.0
0.25
0.0
–0.5
1.7
2.2
2.7
3.2
3.7
1.7
2.2
2.7
3.2
3.7
–55
25
105
Supply voltage (V)
Supply Voltage (V)
Ambient temperature (°C)
Normalized standby current
vs. supply voltage
Normalized I
CC
vs. Cycle Time
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.5
1.0
I
SB2
V
= 3.6V
IN
T = 25
°
C
A
0.50
0.10
V
= V typ
CC
IN
T = 25° C
A
1
5
10
15
2.8
1
1.9
3.7
Supply voltage (V)
Supply voltage (V)
7/ 14/ 00
ALLIANCE SEMICONDUCTOR
7
AS6VA5128
®
Package diagrams and dimensions
20.00+0.20
+0.10
0.787+0.008
0.20
0.008
-0.05
+0.004
-0.002
#1
#32
0.25
(
)
0.010
8.40
0.331
MAX
0.50
0.0197
#16
#17
+0.10
+0.004
18.40
0.528
0.05
0.002
0.25
0.010
+0.10
-0.05
1.00+0.10
MIN
TYP
0.15
0.039+0.004
+0.004
0.006
-0.002
1.20
MAX
0.047
0~8o
0.45 ~0.75
0.018 ~0.030
0.50
0.020
)
(
32-pin Thin Small Outline Package Type I (Forward) (ST)
+0.10
13.40
0.528
+0.008
+0.10
+0.004
-0.002
0.20
-0.05
0.008
#1
# 32
0.25
)
(
0.010
8.40
0.331
MAX
0.50
0.0197
# 16
# 17
0.05
0.002
1.00+0.10
MIN
+0.10
+0.004
11.80
0.465
0.039+0.004
0.25
0.010
+0.10 1.20
TYP
MAX
0.15
-0.05
0.047
+0.004
-0.002
0.006
0~8o
0.45 ~0.75
0.018 ~0.030
0.50
0.020
)
(
8
ALLIANCE SEMICONDUCTOR
7/ 14/ 00
AS6VA5128
®
0~8o
32-pin Thin Small Outline Package Type II (Forward) (HF)
# 32
# 17
0.25
0.010
(
)
11.76+0.20
0.463+0.008
0.45~0.75
0.018~0.030
# 1
# 16
1.00+0.10
0.039+0.004
21.35
0.841
MAX
1.20
0.047
MAX
+0.10
+0.10
20.95
0.15 -0.05
0.006
+0.004
+0.004
0.825
-0.002
0.50
)
(
0.020
1.10 MAX
0.004 MAX
0.05
0.002
MIN
0.95
0.037
1.27
0.050
+0.10
+0.004
0.40
0.016
(
)
0~8o
0.25
0.010
32-pin Thin Small Outline Package Type II (Reverse) (HR)
(
)
# 1
# 16
0.45~0.75
0.018~0.030
11.76+0.20
0.463+0.008
# 32
# 17
+0.10
-0.05
0.15
0.006
+0.004
1.00+0.10
-0.002
0.50
0.020
(
)
0.039+0.004
21.35
MAX
0.841
1.20
0.047
MAX
+0.10
20.95
0.825
+0.004
1.10 MAX
0.004 MAX
0.05
0.002
MIN
0.95
0.037
+0.10
+0.004
1.27
0.050
0.40
0.016
(
)
7/ 14/ 00
ALLIANCE SEMICONDUCTOR
9
AS6VA5128
®
36(48)-ball FBGA
Top View
Bottom View
Ball # A1 index
6
5
4
3
2
1
Ball # A1
A
B
C
D
E
SRAM Die
C
C1
F
A
G
H
Elastomer
A
B
B1
Detail View
Side View
A
E2
D
E
Y
E2
E
Die
Die
E1
0.3/ Typ
Minimum
Typical
0.75
7.00
3.75
11.00
5.25
0.35
–
Maximum
–
A
B
–
6.90
–
Notes
7.10
–
1. Bump counts: 36(48) (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
B1
C
10.90
–
11.10
–
C1
D
4. All tolerances are ±0.050, unless otherwise specified.
5. Typ: typical.
0.30
–
0.40
1.20
–
E
6. Y is coplanarity: 0.08 (max).
E1
E2
Y
–
0.68
0.25
–
0.22
–
0.27
0.08
10
ALLIANCE SEMICONDUCTOR
7/ 14/ 00
AS6VA5128
®
Ordering codes
Speed (ns)
Ordering Code
AS6VA5128-TC
AS6VA5128-STC
AS6VA5128-HFC
AS6VA5128-HRC
AS6VA5128-BC
AS6VA5128-TI
AS6VA5128-STI
AS6VA5128-HFI
AS6VA5128-HRI
AS6VA5128-BI
Package Type
Operating Range
32-pin 8×20 TSOP I
32-pin 8×13.4 TSOP I
32-pin TSOP II (forward)
32-pin TSOP II (reverse)
48-ball fine pitch BGA
32-pin 8×20 TSOP I
55
55
Commercial
32-pin 8×13.4 TSOP I
32-pin TSOP II (forward)
32-pin TSOP II (reverse)
48-ball fine pitch BGA
Industrial
Part numbering system
AS6VA
5128
T, ST, HF, HR, B
C, I
Package:
T: TSOP I
ST: sTSOPI
Temperature range:
C: Commercial: 0° C to 70° C
I: Industrial: –40°C to 85° C
SRAM Intelliwatt™ prefix
Device number
HF: TSOP2 Forward
HR: TSOP2 Reverse
B: CSP BGA
7/ 14/ 00
ALLIANCE SEMICONDUCTOR
11
Copyright © 2000. Alliance Semiconductor Corporation (Alliance)'s three-point logo, our name, and Intelliwatt™ are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of
their respective companies. Alliance reserves the right to make changes to thisweb site and its products at any time withoutnotice. Alliance assumes no responsibility for any errors that may appear in thisweb site. Alliance does not
assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to fitness for a particular purpose, merchantability, or infringement
of any intellectual property rights, except as expressly agreed to in Alliance's Terms and Conditions of Sale (available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of
Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not
authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-
supporting systems implies that themanufacturer assumes all risk of such use andagrees to indemnify Alliance against all claims arising from such use.
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