AS6VB51216-70BI [ALSC]
Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 7 X 9 MM, CSP, FBGA-48;
| 型号： | AS6VB51216-70BI |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 512KX16, 70ns, CMOS, PBGA48, 7 X 9 MM, CSP, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总10页 (文件大小：158K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2002
Advance information
AS6VB51216
&
TM
2.7V to 3.3V 512K X 16 Intelliwatt Super Low-Power CMOS SRAM
Features
• AS6VB51216
• 1.5V data retention
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 524,288 words × 16 bits
• 2.7V to 3.3V power supply range
• Fast access time of 55 ns
• Equal access and cycle times
• Easy memory expansion with CS1, CS2, OE inputs
• Smallest footprint packages
- 48-ball FBGA; 7.0 x 9.0 mm
• ESD protection ≥ 2000 volts
• Low power consumption: ACTIVE
- 132 mW max at 3.3V and 55 ns
• Low power consumption: STANDBY
- 66 µW max at 3.3V
• Latch-up current ≥ 200 mA
Pin arrangement (top view)
Logic block diagram
48-CSP Ball-Grid-Array Package
V
V
1
2
3
4
5
6
DD
A
B
LB
OE
A0
A3
A1
A4
A2
CS2
512K × 16
Array
(8,388,608)
SS
I/O8 UB
CS I/O0
C
D
E
I/O9 I/O10 A5
VSS I/O11 A17
VCC I/O12 VSS
A6 I/O1 I/O2
A7 I/O3 VCC
A16 I/O4 VSS
I/O0–I/O7
I/O8–I/O15
I/O
Control circuit
buffer
F
I/O14 I/O13 A14 A15 I/O5 I/O6
I/O15 NC A12 A13 WE I/O7
A18 A8 A9
A10 A11 DNU1
G
H
Column decoder
WE
ꢀꢁꢂꢃꢄꢁꢅꢁꢂꢆꢁꢃꢆꢇꢁꢄꢈꢉ
A9~A18
UB
OE
LB
CS1
CS2
ꢀꢁꢂꢁꢃꢄꢅꢆꢇꢈꢉꢊꢅꢋꢁ
VCC Range
Power Dissipation
Operating (ICC1 Standby (ISB2
)
)
Min
(V)
Ty p 2
(V)
Max
Speed
(ns)
Product
(V)
3.3
3.3
3.3
Max (mA)
Max (µA)
AS6VB51216-55
AS6VB51216-70
AS6VB51216-85
2.7
2.7
2.7
3.0
3.0
3.0
55
4
4
4
25
25
25
70
85
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Copyright © Alliance Semiconductor. All rights reserved.
AS6VB51216
&
Functional description
The AS6VB51216 is a low-power CMOS 8,388,608-bit Static Random Access Memory (SRAM) device organized as 524,288
words × 16 bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55/70/85 ns are ideal for low-power applications. Active high and low
chip enables (CS1 and CS2) permit easy memory expansion with multiple-bank memory systems.
When CS1 is high or CS2 is low, or UB and LB are high, the device enters standby mode: the AS6VB51216 is guaranteed not to
exceed 66 µW power consumption at 3.3V. The device also retains data when VCC is reduced to 1.5V for even lower power
consumption.
The device can also be put into standby mode when deselected (CS1 is high or CS2 is low, or UB and LB are high). The input/
output pins (I/O0 through I/O15) are placed in a high-impedance state when: deselected ( CS1 is high or CS2 is low, or UB and
LB are high), outputs are disabled (OE High), UB and LB are disabled (UB, LB High), or during a write operation ( CS1 is low or
CS2 is high and WE Low).
Writing to the device is accomplished by taking Chip Enables CS1 Low, CS2 High and Write Enable (WE) input Low. If Byte Low
Enable (LB) is Low, then data from I/O pins (I/O0 through I/O7), is written into the location specified on the address pins (A0
through A18). If Byte High Enable (UB) is Low, then data from I/O pins (I/O8 through I/O15) is written into the location spec-
ified on the address pins (A0 through A18). To avoid bus contention, external devices should drive I/O pins only after outputs
have been disabled with output enable (OE) or write enable (WE).
Reading from the device is accomplished by taking Chip Enable CS1 Low, CS2 High and Output Enable (OE) Low while forcing
the Write Enable (WE) High. If Byte Low Enable (LB) is Low, then data from the memory location specified by the address pins
will appear on I/O0 to I/O7. If Byte High Enable (UB) is Low, then data from memory will appear on I/O8 to I/O15.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 2.7V to 3.3V supply. Device is available in the
JEDEC 48-ball FBGA package.
ꢌꢍꢎꢆꢂꢊꢄꢁꢈꢏꢐꢑꢅꢏꢊꢏꢈꢒꢐꢄꢅꢇꢉꢎ
Parameter
Voltage on VCC relative to VSS
Voltage on any I/O pin relative to GND
Power dissipation
Symbol
VtIN
Min
–0.5
–0.5
–
Max
VCC + 0.5
VCC + 0.5
1.0
Unit
V
VtI/O
PD
V
W
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
Tstg
–65
–55
–
+150
°C
°C
mA
Tbias
IOUT
+125
20
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional oper-
ation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
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AS6VB51216
&
ꢓꢒꢊꢄꢔꢈꢄꢐꢍꢂꢁ
Supply
CS1
H
CS2
X
WE
X
OE
X
LB
X
H
X
X
L
UB
X
H
X
X
H
L
Current I/O0–I/O7 I/O8–I/O15
Mode
Standby
X
X
X
X
ISB
ICC
ICC
High Z
High Z
X
L
X
X
L
X
H
H
High Z
DOUT
High Z
DOUT
DIN
High Z
High Z
DOUT
DOUT
High Z
DIN
Output disable
Read
L
L
H
H
H
L
L
H
L
L
L
H
L
X
H
L
ICC
High Z
DIN
Write
L
DIN
Key: X = Don’t care, L = Low, H = High.
ꢕꢖꢈꢗꢁꢃꢆꢏꢏꢁꢇꢋꢁꢋꢈꢆꢘꢁꢒꢐꢄꢅꢇꢉꢈꢃꢆꢇꢋꢅꢄꢅꢆꢇꢈꢙꢆꢚꢁꢒꢈꢄꢔꢁꢈꢆꢘꢁꢒꢐꢄꢅꢇꢉꢈꢒꢐꢇꢉꢁꢛ
Parameter
Vcc
Description
Test Conditions
Min
Max
Unit
V
Supply voltage
-
2.7
2.4
3.3
VOH
VOL
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Load Current
IOH = –1.0mA
V
IOL = 2.1mA
0.4
VCC + 0.2
0.6
V
VIH
-
2.2
–0.2
–1
V
VIL
-
V
IIX
GND < VIN < VCC
+1
µA
µA
IOZ
GND < VO < VCC; Outputs High Z
–1
+1
IOUT = 0mA,
f = 0
ICC
VCC Operating Supply Current
3
4
mA
mA
ICC1
@
Average VCC Operating Supply
Current at 1 MHz
IOUT = 0mA,
f =1MHz
1 MHz
40 mA at 55ns
30 mA at 70ns
25 mA at 85ns
Average VCC Operating Supply
Current
ICC2
IOUT = 0mA, f = fMax
mA
CS1 > VCC – 0.2V or CS2< 0.2V
or UB = LB. > Vcc -0.2V.
[Other inputs = VIL or VIH, f = 0]
CS Power Down Current; TTL
Inputs
ISB
300
20
µA
µA
CS1 > VCC – 0.2V or CS2< 0.2V or
UB = LB > VCC – 0.2V.
[Other inputs = 0V – VCC, f = fMax
CS Power Down Current;
CMOS Inputs
ISB1
]
1/21/02; V.0.9.6
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AS6VB51216
&
ꢅꢆ
Capacitance (f = 1 MHz, T = Room temperature, V = NOMINAL)
a
CC
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
Signals
A, CS, CS2, WE, OE, LB, UB
I/O
Test conditions
Max
5
Unit
pF
VIN = 0V
CI/O
VIN = VOUT = 0V
7
pF
ꢀꢁꢄ
Read cycle (over the operating range)
–55
–70
–85
Parameter
Symbol
tRC
Min
Max
–
Min
70
–
Max
–
Min
85
–
Max
–
Unit
Notes
Read cycle time
55
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
tAA
55
55
25
–
70
70
35
–
85
85
35
–
3
3
Chip enable (CS) access time
Output enable (OE) access time
Output hold from address change
CSꢁꢊꢆꢋꢁꢇo output in low Z
CS high to output in high Z
OE low to output in low Z
UB/LB access time
tACS
tOE
–
–
–
–
–
–
tOH
tCLZ
tCHZ
tOLZ
tBA
10
10
0
10
10
0
10
10
0
5
–
–
–
4, 5
4, 5
4, 5
20
–
25
–
25
–
5
5
5
–
55
–
–
70
–
–
85
–
UB/LB low to low Z
tBLZ
tBHZ
tOHZ
tPU
10
0
10
0
10
0
4, 5
4, 5
4, 5
4, 5
4, 5
UB/LB high to high Z
OE high to output in high Z
Power up time
20
20
–
25
25
–
25
25
–
0
0
0
0
0
0
Power down time
tPD
–
55
–
70
–
85
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
ꢀꢁꢂꢁꢃꢁꢄ
Read waveform 1 (address controlled)
(CS1
=
OE
=
LB
=
UB=Low, CS2=High)
t
RC
Address
t
AA
t
t
OH
OH
D
Previous data valid
Data valid
OUT
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AS6VB51216
&
ꢀꢁꢂꢁꢇꢁꢄ ꢆ
Read waveform 2 (CS1, CS2, OE, UB, LB controlled)
[WE=High]
t
RC
Address
t
AA
OE
t
OE
t
t
OH
OLZ
CS1
t
OHZ
t
ACS
CS2
t
t
HZ
LZ
LB, UB
t
t
BA
BHZ
t
BLZ
D
Data valid
OUT
ꢈꢈ
Write cycle (over the operating range)
–55
–70
–85
Parameter
Symbol
Min
55
45
45
0
Max
–
Min
Max
–
Min
85
60
60
0
Max
–
Unit
ns
Notes
12
Write cycle time
tWC
tCW
tAW
tAS
70
60
60
0
Chip enable to write end
Address setup to write end
Address setup time
–
–
–
ns
–
–
–
ns
–
–
–
ns
ns
12
Write pulse width
tWP
tAH
tDW
tDH
tWZ
tOW
tBW
40
0
–
50
0
–
50
0
–
Address hold from end of write
Data valid to write end
Data hold time
–
–
–
ns
ns
25
0
–
30
0
–
30
0
–
–
–
–
ns
ns
ns
ns
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
UB/LB low to end of write
0
20
–
0
20
–
0
20
–
5
5
5
45
–
60
–
60
–
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AS6VB51216
&
ꢈꢉꢁꢈꢈ
Write waveform 1 (WE controlled)
t
t
WC
Address
CS1
t
AH
CW
t
BW
CS2
LB, UB
t
AW
t
t
WP
AS
WE
t
t
DH
DW
Data valid
D
IN
t
WZ
t
OW
D
Data undefined
OUT
High Z
ꢈꢉꢁꢈꢈ
Write waveform 2 (CS controlled)
t
WC
Address
t
t
AH
AS
t
CW
CS1
CS2
LB, UB
WE
t
AW
t
BW
t
WP
t
t
DH
DW
Data valid
High Z
D
IN
t
t
CLZ
WZ
t
OW
D
Data undefined
OUT
High Z
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AS6VB51216
&
ꢈꢀꢁꢊ
Data retention characteristics (over the operating range)
Parameter
Symbol
Test conditions
Min
1.5
–
Max
3.3
10
–
Unit
V
VCC for data retention
VDR
VCC = 1.5V
CS ≥ VCC – 0.1V or
UB = LB = > VCC – 0.1V
VIN ≥ VCC – 0.1V or
VIN ≤ 0.1V
Data retention current
ICCDR
tCDR
µA
ns
Chip deselect to data retention time
Operation recovery time
0
tR
tRC
–
ns
Data retention waveform
CS1 controlled
t
t
R
CDR
Data retention mode
V
CC
1.65V
1.4V
V
DR
CS1,
LB/UB
GND
CS1≥VCC -0.2, LB=UB ≥VCC -0.2V
CS2 controlled
Data retention mode
V
CC
1.65V
CS2
t
t
CDR
R
V
DR
CS2≤0.2V
0.4V
GND
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AS6VB51216
&
AC test loads and waveforms
Thevenin equivalent:
R1
R1
V
R
CC
V
TH
CC
V
OUTPUT
OUTPUT
OUTPUT
30 pF
5 pF
ALL INPUT PULSES
90%
V
Typ
R2
CC
R2
90%
10%
10%
INCLUDING
JIG AND
INCLUDING
JIG AND
SCOPE
< 5 ns
GND
(a)
SCOPE
(b)
(c)
Parameters
VCC = 2.7V
Unit
Ohms
Ohms
Ohms
Volts
R1
R2
992
1842
645
Ω
Ω
RTH
VTH
Ω
1.755V
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CS is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
and t are specified with C = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage.
CHZ L
CLZ
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CS and OE are LOW for read cycle.
Address valid prior to or coincident with CS transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 1.5V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
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AS6VB51216
&
Package diagrams and dimensions
48-ball FBGA
Top View
Bottom View
Ball #A1 Index
6
5
4
3
2
1
Ball #A1
A
B
SRAM Die
C
D
E
C1
C
F
A
G
H
Elastomer
A
B
B1
Detail View
A
Side View
D
Ε2
Ε
E2
Y
E
Die
Die
Ε1
0.3/Typ
Minimum Ty pi c a l Maximum
Notes
A
–
6.90
–
0.75
7.00
3.75
9.0
–
1. Bump counts: 48 (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
B
B1
C
7.10
–
8.4
–
8.6
–
4. All tolerance are 0.050 unless otherwise specified.
5. Typ: typical.
C1
D
5.25
0.35
–
0.30
–
0.40
1.20
–
6. Y is coplanarity: 0.08 (max).
E
E1
E2
Y
–
0.68
0.25
–
0.22
–
0.27
0.08
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AS6VB51216
&
Ordering codes
Speed (ns)
Ordering Code
AS6VB51216-55BI
AS6VB51216-70BI
AS6VB51216-85BI
AS6VB51216-55BC
AS6VB51216-70BC
AS6VB51216-85BC
Package Type
Operating Range
55
70
85
55
70
85
48-ball fine pitch BGA
48-ball fine pitch BGA
48-ball fine pitch BGA
48-ball fine pitch BGA
48-ball fine pitch BGA
48-ball fine pitch BGA
Industrial
Commercial
Part numbering system
AS6UA
51216
-55/70/85
B
C or I
Temperature range:
C: Commercial: 0° C to 70° C
I: Industrial: –40° C to 85° C
SRAM Intelliwatt™
Package:
B: CSP BGA
Device number
Nano-seconds
prefix
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© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks
of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,
any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties
related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in
Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not
convey a license under any patent rights, copyrights, mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-
supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes
all risk of such use and agrees to indemnify Alliance against all claims arising from such use.
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