AS6WA25616 [ETC]
3.0V to 3.6V 256K?6 IntelliwattTM low-power CMOS SRAM with one chip enable; 3.0V至3.6V 256K ？ 6 IntelliwattTM低功耗CMOS SRAM有一个芯片使能
| 型号： | AS6WA25616 |
| 厂家： | 
ETC |
| 描述： | 3.0V to 3.6V 256K?6 IntelliwattTM low-power CMOS SRAM with one chip enable |
| 文件： | 总9页 (文件大小：208K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 2001
AS6WA25616
&
3.0V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable
• 1.5V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
- 48-ball FBGA
- 400-mil 44-pin TSOP 2
• ESD protection ≥ 2000 volts
Features
• AS6WA25616
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words × 16 bits
• 3.0V to 3.6V at 55 ns
• Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
• Latch-up current ≥ 200 mA
• Low power consumption: STANDBY
Pin arrangement (top view)
- 72 µW max at 3.6V
Logic block diagram
A0
44-pin 400-mil TSOP 2
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
A2
3
A7
V
A1
A2
A1
4
OE
CC
A0
5
UB
256K × 16
Array
(4,194,304)
V
A3
CS
6
LB
SS
I/ O16
I/ O15
I/ O14
I/ O13
I/ O1
I/ O2
I/ O3
I/ O4
7
A4
8
A6
9
A7
10
11
12
13
14
15
16
17
18
19
20
21
22
A8
V
V
CC
SS
CC
A12
A13
V
V
SS
I/ O5
I/ O6
I/ O7
I/ O8
WE
I/ O12
I/ O1
1
I/ O1–I/ O8
I/ O9–I/ O16
I/ O
Control circuit
I/ O10
I/ O9
NC
buffer
A17
A16
A15
A14
A13
A8
Column decoder
WE
A9
A10
A11
A12
UB
OE
LB
CS
48-CSP Ball-Grid-Array Package
1
2
3
4
5
6
A
B
C
D
E
LB
OE
A0
A3
A1
A4
A2
NC
I/ O9 UB
CS I/ O1
I/ O10 I/ O11 A5
I/ O12 A17
A6 I/ O2 I/ O3
A7 I/ O4 VCC
V
SS
VCC I/ O13 NC A16 I/ O5
I/ O15 I/ O14 A14 A15 I/ O6 I/ O7
I/ O16 NC A12 A13 WE I/ O8
A10 A11 NC
V
SS
F
G
H
NC
A8
A9
Selection guide
VCC Range
Power Dissipation
Operating (ICC)
Standby (ISB1)
Min
(V)
Typ2
(V)
Max
(V)
Speed
(ns)
Product
Max (mA)
2
Max (µA)
AS6WA25616
3.0
3.3
3.6
55
20
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Copyright ©Alliance Semiconductor. All rights reserved.
AS6WA25616
&
Functional description
The AS6WA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16 bits.
It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (t , t , t ) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS) permit
AA RC WC
easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6WA25616 is guaranteed not to exceed 72 µW power
consumption at 3.6V and 55 ns. The device also returns data when V is reduced to 1.5V for even lower power consumption.
CC
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/ or LB low. Data on the input pins
I/ O1–O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip drives
I/ O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, or
(UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/ O1–I/ O8, and UB controls the higher bits, I/ O9–I/ O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. Device is available in the JEDEC standard
400-mm, TSOP 2, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter
Device
Symbol
Min
–0.5
–0.5
–
Max
Unit
V
Voltage on VCC relative to V
V
VCC + 0.5
SS
tIN
Voltage on any I/ O pin relative to GND
Power dissipation
V
V
tI/ O
PD
1.0
+150
+125
20
W
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
Tstg
Tbias
IOUT
–65
–55
–
°C
°C
mA
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Supply
CS
H
L
WE
X
OE
X
LB
X
H
X
L
UB
X
H
X
H
L
Current I/ O1–I/ O8 I/ O9–I/ O16
Mode
ISB
High Z
High Z
Standby (ISB)
X
X
L
H
H
ICC
High Z
DOUT
High Z
High Z
DOUT
Output disable (ICC)
L
L
H
L
L
H
L
ICC
High Z
DOUT
Read (ICC)
Write (ICC)
L
DOUT
L
H
L
D
High Z
IN
X
H
L
ICC
High Z
D
IN
L
D
D
IN
IN
Key: X = Don’t care, L = Low, H = High.
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AS6WA25616
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Recommended operating condition (over the operating range)
Parameter
Description
Test Conditions
Min
2.4
Max
Unit
V
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Load Current
IOH = –2.1mA
IOL = 2.1mA
VCC = 3.0 - 3.6V
OH
V
VCC = 3.0 - 3.6V
VCC = 3.0 - 3.6V
VCC = 3.0 - 3.6V
0.4
VCC + 0.5
0.8
V
OL
V
2.2
–0.5
–1
V
IH
V
V
IL
IIX
GND < VIN < VCC
GND < V < VCC; Outputs High Z
+1
µA
µA
IOZ
–1
+1
O
CS = V , VIN = V
IL
IL
VCC Operating Supply
Current
ICC
or V , IOUT = 0mA,
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
2
5
mA
mA
mA
µA
IH
f = 0
CS < 0.2V, V < 0.2V
or VIN > VCC – 0.2V,
f = 1 mS
IN
ICC1
@
Average VCC Operating
Supply Current at 1 MHz
1 MHz
Average VCC Operating CS ≠ V , VIN = V or
IL
IL
ICC2
40
100
20
Supply Current
V , f = fMax
IH
CS > VIH or UB = LB
> V , other inputs =
CS Power Down Current;
TTL Inputs
ISB
IH
V or V , f = 0
IL
IH
CS > VCC – 0.2V or
UB = LB > VCC – 0.2V,
other inputs = 0V – VCC,
f = 0
CS Power Down Current;
CMOS Inputs
ISB1
VCC = 3.6V
µA
ꢀꢁ
Capacitance (f = 1 MHz, T = Room temperature, V = NOMINAL)
a
CC
Signals
Parameter
Input capacitance
I/ O capacitance
Symbol
Test conditions
IN = 0V
IN = VOUT = 0V
Max
5
Unit
pF
C
A, CS, WE, OE, LB, UB
I/ O
V
IN
C
V
7
pF
I/ O
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AS6WA25616
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ꢂꢃꢄ
Read cycle (over the operating range)
Parameter
Symbol
tRC
Min
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
55
–
Address access time
tAA
55
55
25
–
3
3
Chip select (CS) access time
Output enable (OE) access time
Output hold from address change
CS low to output in low Z
CS high to output in high Z
OE low to output in low Z
UB/ LB access time
tACS
tOE
–
–
tOH
10
10
0
5
tCLZ
tCHZ
tOLZ
tBA
–
4, 5
4, 5
4, 5
20
–
5
–
55
–
UB/ LB low to low Z
tBLZ
tBHZ
tOHZ
tPU
10
0
4, 5
4, 5
4, 5
4, 5
4, 5
UB/ LB high to high Z
20
20
–
OE high to output in high Z
Power up time
0
0
Power down time
tPD
–
55
Shaded areas indicate preliminary information.
Key to switching waveforms
Rising input
Falling input
Undefined/ don’t care
ꢂꢃꢅꢃꢆꢃꢄ
Read waveform 1 (address controlled)
t
RC
Address
t
AA
t
t
OH
OH
D
Previous data valid
Data valid
OUT
ꢂꢃꢅꢃꢇꢃꢄ ꢁ
Read waveform 2 (CS, OE, UB, LB controlled)
t
RC
Address
OE
t
AA
t
OE
t
t
OH
OLZ
CS
t
OHZ
t
ACS
t
t
HZ
LZ
LB, UB
t
t
BA
BHZ
t
BLZ
D
Data valid
OUT
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AS6WA25616
&
ꢈꢈ
Write cycle (over the operating range) .
Parameter
Symbol
tWC
tCW
tAW
Min
55
40
40
0
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
Write cycle time
Chip select to write end
Address setup to write end
Address setup time
–
–
tAS
–
12
Write pulse width
tWP
tWR
tAH
35
0
–
Write recovery time
–
Address hold from end of write
Data valid to write end
Data hold time
0
–
tDW
tDH
25
0
–
–
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
UB/ LB low to end of write
tWZ
tOW
tBW
0
20
–
5
35
–
ꢈꢉꢃꢈꢈ
Write waveform 1 (WE controlled)
t
t
WC
CW
t
WR
Address
t
AH
CS
t
BW
LB, UB
t
AW
t
t
WP
AS
WE
t
t
DH
DW
Data valid
D
IN
t
WZ
t
OW
D
Data undefined
OUT
High Z
ꢈꢉꢃꢈꢈ
Write waveform 2 (CS controlled)
t
WC
t
WR
Address
t
t
t
AS
AH
CW
CS
t
AW
t
BW
LB, UB
WE
t
WP
t
t
DH
DW
Data valid
High Z
D
IN
t
t
CLZ
WZ
t
OW
D
Data undefined
OUT
High Z
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AS6WA25616
&
ꢈꢂꢃꢊ
Data retention characteristics (over the operating range)
Parameter
Symbol
Test conditions
Min
1.5V
–
Max
-
Unit
V
V
CC for data retention
VDR
VCC = 1.5V
CS ≥ VCC – 0.1V or
UB = LB = > VCC – 0.1V
Data retention current
ICCDR
tCDR
tR
10
–
µA
ns
Chip deselect to data retention time
Operation recovery time
0
V
≥ VCC – 0.1V or
IN
V
≤ 0.1V
tRC
–
ns
IN
Data retention waveform
Data retention mode
1.5V
V
V
V
V
≥
CC
CC
CC
DR
t
t
R
CDR
V
DR
V
V
CS
IH
IH
AC test loads and waveforms
Thevenin equivalent:
R1
R1
V
R
CC
V
TH
CC
V
OUTPUT
TH
OUTPUT
OUTPUT
30 pF
5 pF
ALL INPUT PULSES
V
Typ
R2
CC
R2
90%
10%
90%
10%
INCLUDING
JIG AND
INCLUDING
JIG AND
SCOPE
< 5 ns
(c)
GND
(a)
SCOPE
(b)
Parameters
V
CC = 3.6V
Unit
Ohms
Ohms
Ohms
Volts
R1
R2
1523
1142
476
R
TH
VTH
1.4V
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CS is required to meet I specification.
CC CC SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
and t are specified with C = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
CHZ L
CLZ
This parameter is guaranteed, but not tested.
WEis HIGH for read cycle.
CSand OE are LOW for read cycle.
Address valid prior to or coincident with CS transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/ A.
13 1.5V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
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AS6WA25616
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Typical DC and AC characteristics
Normalized supply current
vs. supply voltage
1.4
Normalized access time
vs. supply voltage
Normalized standby current
vs. ambient temperature
1.0
3.0
2.5
2.0
1.2
V
= V typ
CC
IN
V
= V typ
CC
CC
1.0
0.8
0.6
0.4
0.2
0.0
0.75
0.5
T = 25
°
C
A
V
= V typ
IN
CC
1.5
1.0
0.5
0.0
T = 25° C
A
0.25
0.0
–0.5
1.7
2.2
2.7
3.2
3.7
1.7
2.2
2.7
3.2
3.7
–
55
25
Ambient temperature (°C)
105
Supply voltage (V)
Supply Voltage (V)
Normalized standby current
vs. supply voltage
Normalized I
CC
vs. Cycle Time
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.5
I
SB2
V
= 3.6V
T = 25° C
CC
1.0
A
0.50
0.10
V
= V typ
CC
IN
T = 25° C
A
1
5
10
15
2.8
1.9
Supply voltage (V)
1
3.7
Supply voltage (V)
Package diagrams and dimensions
44-pin TSOP 2
c
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
Min
Max
(mm)
(mm)
A
1.2
H
e
44-pin TSOP 2
e
A
0.05
0.95
0.25
1
A
1.05
0.45
2
b
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
c
d
0.15 (typical)
d
18.28
10.06
11.56
18.54
10.26
11.96
e
l
A
2
A
0–5°
He
E
l
A
1
0.80 (typical)
b
E
0.40
0.60
7/ 9/ 02; v.1.3
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AS6WA25616
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48-ball FBGA
Top View
Bottom View
Ball #A1 Index
6
5
4
3
2
1
Ball # A1
A
B
C
D
E
SRAM Die
C1
C
F
A
G
H
Elastomer
A
B
B1
Detail View
A
Side View
D
E2
E
E2
Y
E
Die
Die
E1
0.3/ Typ
Minimum
Typical
0.75
7.00
3.75
11
Maximum
–
A
B
–
6.90
–
Notes
1. Bump counts: 48 (8 row × 6 column).
7.10
–
B1
C
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
10.90
–
11.10
–
C1
D
5.25
0.35
–
4. All tolerance are ±0.050 unless otherwise specified.
5. Typ: typical.
0.30
–
0.40
1.20
–
E
6. Y is coplanarity: 0.08 (max).
E1
E2
Y
–
0.68
0.25
–
0.22
–
0.27
0.08
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AS6WA25616
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Ordering codes
Speed (ns)
Ordering Code
AS6WA25616-TC
AS6WA25616-BC
AS6WA25616-TI
AS6WA25616-BI
Package Type
44-pin TSOP 2
Operating Range
55
55
Commercial
Industrial
48-ball fine pitch BGA
44-pin TSOP 2
48-ball fine pitch BGA
Part numbering system
AS6WA
25616
T, B
C, I
Package:
Temperature range:
SRAM Intelliwatt™ prefix
Device number
T: TSOP 2
B: CSP/ BGA
C: Commercial: 0° C to 70° C
I: Industrial: –40° C to 85° C
7/ 9/ 02; v.1.3
Alliance Semiconductor
P. 9 of 9
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of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/ or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
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