AS6WA25616-55BC [ALSC]
Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, CSP, FBGA-48;
| 型号： | AS6WA25616-55BC |
| 厂家： | 
ALLIANCE SEMICONDUCTOR CORPORATION |
| 描述： | Standard SRAM, 256KX16, 55ns, CMOS, PBGA48, CSP, FBGA-48 静态存储器 内存集成电路 |
| 文件： | 总9页 (文件大小：138K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 2001
AS6WA25616
®
3.0V to 3.6V 256K×16 Intelliwatt™ low-power CMOS SRAM with one chip enable
• 1.5V data retention
• Equal access and cycle times
• Easy memory expansion with CS, OE inputs
• Smallest footprint packages
Features
• AS6WA25616
• Intelliwatt™ active power circuitry
• Industrial and commercial temperature ranges available
• Organization: 262,144 words × 16 bits
• 3.0V to 3.6V at 55 ns
- 48-ball FBGA
- 400-mil 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Low power consumption: ACTIVE
- 144 mW at 3.6V and 55 ns
• Latch-up current ≥ 200 mA
• Low power consumption: STANDBY
Pin arrangement (top view)
- 72 µW max at 3.6V
Logic block diagram
A0
44-pin 400-mil TSOP 2
A4
A3
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
2
A6
A2
3
A7
V
V
A1
A2
A1
4
OE
CC
A0
5
UB
256K × 16
Array
(4,194,304)
A3
CS
6
LB
SS
I/O16
I/O15
I/O14
I/O13
I/O1
I/O2
I/O3
I/O4
7
A4
8
A6
9
A7
10
11
12
13
14
15
16
17
18
19
20
21
22
A8
V
V
V
CC
SS
CC
A12
A13
V
SS
I/O5
I/O6
I/O7
I/O8
WE
I/O12
I/O11
I/O10
I/O9
NC
I/O1–I/O8
I/O9–I/O16
I/O
Control circuit
buffer
A17
A16
A15
A14
A13
A8
Column decoder
WE
A9
A10
A11
A12
UB
OE
LB
48-CSP Ball-Grid-Array Package
CS
1
2
3
4
5
6
A
B
LB
OE
A0
A3
A1
A4
A2
CS
NC
I/O9 UB
I/O1
C
D
E
I/O10 I/O11 A5
VSS I/O12 A17
VCC I/O13 NC
A6 I/O2 I/O3
A7 I/O4 VCC
A16 I/O5 VSS
F
I/O15 I/O14 A14 A15 I/O6 I/O7
G
H
I/O16 NC
NC A8
A12 A13
A9
WE I/O8
NC
A10 A11
Selection guide
VCC Range
Power Dissipation
Operating (ICC)
Max (mA)
2
Standby (ISB1
Max (µA)
20
)
Min
(V)
Typ2
(V)
Max
(V)
Speed
(ns)
Product
AS6WA25616
3.0
3.3
3.6
55
5/25/01; v.1.2
Alliance Semiconductor
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Copyright ©Alliance Semiconductor. All rights reserved.
AS6WA25616
®
Functional description
The AS6WA25616 is a low-power CMOS 4,194,304-bit Static Random Access Memory (SRAM) device organized as 262,144 words × 16
bits. It is designed for memory applications where slow data access, low power, and simple interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 55 ns are ideal for low-power applications. Active high and low chip selects (CS)
permit easy memory expansion with multiple-bank memory systems.
When CS is high, or UB and LB are high, the device enters standby mode: the AS6WA25616 is guaranteed not to exceed 72 µW power
consumption at 3.6V and 55 ns. The device also returns data when VCC is reduced to 1.5V for even lower power consumption.
A write cycle is accomplished by asserting write enable (WE) and chip select (CS) low, and UB and/or LB low. Data on the input pins
I/O1–O16 is written on the rising edge of WE (write cycle 1) or CS (write cycle 2). To avoid bus contention, external devices should drive
I/O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE), chip select (CS), UB and LB low, with write enable (WE) high. The chip drives
I/O pins with the data word referenced by the input address. When either chip select or output enable is inactive, or write enable is active, or
(UB) and (LB), output drivers stay in high-impedance mode.
These devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be written and
read. LB controls the lower bits, I/O1–I/O8, and UB controls the higher bits, I/O9–I/O16.
All chip inputs and outputs are CMOS-compatible, and operation is from a single 3.0 to 3.6V supply. Device is available in the JEDEC standard
400-mm, TSOP 2, and 48-ball FBGA packages.
Absolute maximum ratings
Parameter
Voltage on VCC relative to VSS
Voltage on any I/O pin relative to GND
Power dissipation
Device
Symbol
VtIN
Min
–0.5
–0.5
–
Max
Unit
V
VCC + 0.5
VtI/O
PD
V
1.0
+150
+125
20
W
Storage temperature (plastic)
Temperature with VCC applied
DC output current (low)
Tstg
–65
–55
–
°C
°C
mA
Tbias
IOUT
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Truth table
Supply
CS
H
L
WE
X
OE
X
LB
X
H
X
L
UB
X
H
X
H
L
Current I/O1–I/O8 I/O9–I/O16
Mode
ISB
High Z
High Z
Standby (ISB)
X
X
L
H
H
ICC
High Z
DOUT
High Z
DOUT
DIN
High Z
High Z
DOUT
DOUT
High Z
DIN
Output disable (ICC)
L
L
H
L
L
H
L
ICC
Read (ICC)
L
L
H
L
X
H
L
ICC
High Z
DIN
Write (ICC)
L
DIN
Key: X = Don’t care, L = Low, H = High.
5/25/01; v.1.2
Alliance Semiconductor
P. 2 of 9
AS6WA25616
®
Recommended operating condition (over the operating range)
Parameter
VOH
VOL
Description
Test Conditions
Min
2.4
Max
Unit
V
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Load Current
Output Load Current
IOH = –2.1mA
IOL = 2.1mA
VCC = 3.0 - 3.6V
VCC = 3.0 - 3.6V
VCC = 3.0 - 3.6V
VCC = 3.0 - 3.6V
0.4
VCC + 0.5
0.8
V
VIH
2.2
–0.5
–1
V
VIL
V
IIX
GND < VIN < VCC
GND < VO < VCC; Outputs High Z
CS = VIL, VIN = VIL
+1
µA
µA
IOZ
–1
+1
VCC Operating Supply
Current
ICC
or VIH, IOUT = 0mA,
f = 0
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
VCC = 3.6V
2
5
mA
mA
mA
µA
CS < 0.2V, VIN < 0.2V
or VIN > VCC – 0.2V,
f = 1 mS
ICC1
@
Average VCC Operating
Supply Current at 1 MHz
1 MHz
Average VCC Operating CS ≠ VIL, VIN = VIL or
ICC2
40
100
20
Supply Current
VIH, f = fMax
CS > VIH or UB = LB
> VIH, other inputs =
VIL or VIH, f = 0
CS Power Down Current;
TTL Inputs
ISB
CS > VCC – 0.2V or
UB = LB > VCC – 0.2V,
other inputs = 0V –
VCC, f = fMax
CS Power Down Current;
CMOS Inputs
ISB1
µA
Capacitance (f = 1 MHz, T = Room temperature, V = NOMINAL)2
a
CC
Signals
Parameter
Input capacitance
I/O capacitance
Symbol
CIN
Test conditions
Max
5
Unit
pF
A, CS, WE, OE, LB, UB
I/O
VIN = 0V
CI/O
VIN = VOUT = 0V
7
pF
5/25/01; v.1.2
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P. 3 of 9
AS6WA25616
®
Read cycle (over the operating range)3,9
Parameter
Symbol
Min
55
–
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
Read cycle time
tRC
Address access time
tAA
55
55
25
–
3
3
Chip select (CS) access time
Output enable (OE) access time
Output hold from address change
CS low to output in low Z
CS high to output in high Z
OE low to output in low Z
UB/LB access time
tACS
tOE
–
–
tOH
tCLZ
tCHZ
tOLZ
tBA
10
10
0
5
–
4, 5
4, 5
4, 5
20
–
5
–
55
–
UB/LB low to low Z
tBLZ
tBHZ
tOHZ
tPU
10
0
4, 5
4, 5
4, 5
4, 5
4, 5
UB/LB high to high Z
20
20
–
OE high to output in high Z
Power up time
0
0
Power down time
tPD
–
55
Shaded areas indicate preliminary information.
Key to switching waveforms
Rising input
Falling input
Undefined/don’t care
Read waveform 1 (address controlled)3,6,7,9
t
RC
Address
t
AA
t
t
OH
OH
D
Previous data valid
Data valid
OUT
Read waveform 2 (CS, OE, UB, LB controlled)3,6,8,9
t
RC
Address
t
AA
OE
CS
t
OE
t
t
OH
OLZ
t
OHZ
t
ACS
t
t
HZ
LZ
LB, UB
t
t
BA
BHZ
t
BLZ
D
Data valid
OUT
5/25/01; v.1.2
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P. 4 of 9
AS6WA25616
®
Write cycle (over the operating range)11
Parameter
Symbol
tWC
tCW
tAW
tAS
Min
55
40
40
0
Max
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
12
Write cycle time
Chip select to write end
Address setup to write end
Address setup time
–
–
–
12
Write pulse width
tWP
tAH
tDW
tDH
35
0
–
Address hold from end of write
Data valid to write end
Data hold time
–
25
0
–
–
4, 5
4, 5
4, 5
Write enable to output in high Z
Output active from write end
UB/LB low to end of write
Shaded areas indicate preliminary information.
tWZ
tOW
tBW
0
20
–
5
35
–
Write waveform 1 (WE controlled)10,11
t
t
WC
Address
t
AH
CW
CS
t
BW
LB, UB
t
AW
t
t
WP
AS
WE
t
t
DH
DW
Data valid
D
IN
t
WZ
t
OW
D
Data undefined
OUT
High Z
Write waveform 2 (CS controlled)10,11
t
WC
Address
t
t
AS
AH
t
CW
CS
t
AW
t
BW
LB, UB
WE
t
WP
t
t
DH
DW
Data valid
High Z
D
IN
t
t
CLZ
WZ
t
OW
D
Data undefined
OUT
High Z
5/25/01; v.1.2
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AS6WA25616
®
Data retention characteristics (over the operating range)13,5
Parameter
Symbol
Test conditions
Min
1.5V
–
Max
-
Unit
V
VCC for data retention
VDR
VCC = 1.5V
CS ≥ VCC – 0.1V or
UB = LB = > VCC – 0.1V
VIN ≥ VCC – 0.1V or
VIN ≤ 0.1V
Data retention current
ICCDR
tCDR
tR
10
–
µA
ns
Chip deselect to data retention time
Operation recovery time
0
tRC
–
ns
Data retention waveform
Data retention mode
V
V
V
CC
V
≥ 1.5V
CC
CC
DR
t
t
R
CDR
V
DR
V
V
IH
CS
IH
AC test loads and waveforms
Thevenin equivalent:
R1
R1
V
R
CC
V
TH
CC
V
OUTPUT
TH
OUTPUT
OUTPUT
30 pF
5 pF
ALL INPUT PULSES
V
Typ
R2
CC
R2
90%
10%
90%
10%
INCLUDING
JIG AND
INCLUDING
JIG AND
SCOPE
< 5 ns
(c)
GND
(a)
SCOPE
(b)
Parameters
R1
VCC = 3.6V
1523
Unit
Ohms
Ohms
Ohms
Volts
R2
1142
RTH
476
VTH
1.4V
Notes
1
2
3
4
5
6
7
8
9
During V power-up, a pull-up resistor to V on CS is required to meet I specification.
CC
CC
SB
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions.
t
and t
are specified with C = 5pF as in Figure C. Transition is measured 500 mV from steady-state voltage.
CHZ L
CLZ
This parameter is guaranteed, but not tested.
WE is HIGH for read cycle.
CS and OE are LOW for read cycle.
Address valid prior to or coincident with CS transition LOW.
All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CS or WE must be HIGH during address transitions. Either CS or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 N/A.
13 1.5V data retention applies to commercial and industrial temperature range operations.
14 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
5/25/01; v.1.2
Alliance Semiconductor
P. 6 of 9
AS6WA25616
®
Typical DC and AC characteristics
Normalized supply current
vs. supply voltage
1.4
Normalized access time
vs. supply voltage
Normalized standby current
vs. ambient temperature
1.0
3.0
2.5
2.0
1.2
V
= V typ
CC
IN
V
V
= V typ
CC
CC
IN
1.0
0.8
0.6
0.4
0.2
0.0
0.75
0.5
T = 25
°
C
A
= V typ
CC
1.5
1.0
0.5
0.0
T = 25° C
A
0.25
0.0
–
0.5
1.7
2.2
2.7
3.2
3.7
1.7
2.2
2.7
3.2
3.7
–
55
25
Ambient temperature (°C)
105
Supply voltage (V)
Supply Voltage (V)
Normalized standby current
vs. supply voltage
Normalized I
CC
vs. Cycle Time
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0.0
1.5
I
SB2
V
= 3.6V
T = 25° C
CC
1.0
A
0.50
0.10
V
= V typ
CC
IN
T = 25° C
A
1
5
10
15
2.8
1.9
Supply voltage (V)
1
3.7
Supply voltage (V)
Package diagrams and dimensions
44-pin TSOP 2
c
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
Min
Max
(mm)
(mm)
A
A1
A2
b
1.2
H
e
44-pin TSOP 2
e
0.05
0.95
0.25
1.05
0.45
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22
c
0.15 (typical)
d
d
18.28
10.06
11.56
18.54
10.26
11.96
e
l
A
2
A
0–5°
He
E
A
1
0.80 (typical)
E
b
l
0.40
0.60
5/25/01; v.1.2
Alliance Semiconductor
P. 7 of 9
AS6WA25616
®
48-ball FBGA
Top View
Bottom View
Ball #A1 Index
6
5
4
3
2
1
Ball #A1
A
B
C
D
E
SRAM Die
C1
C
F
A
G
H
Elastomer
A
B
B1
Detail View
A
Side View
D
E2
E
E2
Y
E
Die
Die
E1
0.3/Typ
Minimum
Typical
0.75
7.00
3.75
11
Maximum
A
B
–
6.90
–
–
7.10
–
Notes
1. Bump counts: 48 (8 row × 6 column).
2. Pitch: (x,y) = 0.75 mm × 0.75 mm (typ).
3. Units: millimeters.
B1
C
10.90
–
11.10
–
C1
D
5.25
0.35
–
4. All tolerance are 0.050 unless otherwise specified.
5. Typ: typical.
0.30
–
0.40
1.20
–
E
6. Y is coplanarity: 0.08 (max).
E1
E2
Y
–
0.68
0.25
–
0.22
–
0.27
0.08
5/25/01; v.1.2
Alliance Semiconductor
P. 8 of 9
AS6WA25616
®
Ordering codes
Speed (ns)
Ordering Code
AS6WA25616-TC
AS6WA25616-BC
AS6WA25616-TI
AS6WA25616-BI
Package Type
44-pin TSOP 2
Operating Range
Commercial
55
55
48-ball fine pitch BGA
44-pin TSOP 2
Industrial
48-ball fine pitch BGA
Part numbering system
AS6WA
25616
T, B
C, I
Temperature range:
Package:
SRAM Intelliwatt™ prefix
Device number
T: TSOP 2
B: CSP/BGA
C: Commercial: 0° C to 70° C
I: Industrial: –40° C to 85° C
5/25/01; v.1.2
Alliance Semiconductor
P. 9 of 9
© Copyright Alliance Semiconductor Corporation. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be
the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may
appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the
product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential
customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use
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