A8698 [ALLEGRO]
Wide Input Voltage 3.0 A Step Down Regulator; 宽输入电压3.0降压稳压器
| 型号： | A8698 |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Wide Input Voltage 3.0 A Step Down Regulator |
| 文件： | 总12页 (文件大小：617K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A8698
Wide Input Voltage 3.0 A Step Down Regulator
Features and Benefits
Description
▪ 8 to 25 V input range
▪ Integrated DMOS switch
▪ Adjustable fixed off-time
▪ Highly efficient
The A8698 is a constant off-time current mode step-down
regulatorwithawideinputvoltagerange.Regulationvoltageis
set by external resistors, to output voltages as low as 0.8 V.
The A8698 includes an integrated power DMOS switch to
reduce the total solution footprint. It also features internal
compensation, allowing users to design stable regulators with
minimal design efforts.
▪ Adjustable 0.8 to 20 V output
The off-time can be set with an external resistor, allowing
flexibility in inductor selection. Additionally, the A8698 has
a logic level enable pin which can shut the device down and
put it into a low quiescent current mode for power sensitive
applications.
The A8698 is supplied in a low-profile 8-lead SOIC with
exposed pad (package LJ). Applications include:
Package: 8-Lead SOIC with exposed
thermal pad (suffix LJ)
▪ Applications with 8 to 25 V input
▪ Consumer electronics, networking equipment
▪ 12 V lighter-powered applications (portable DVD, etc.)
▪ Point of Sale (POS) applications
Approximate Scale 1:1
Typical Application
+8 to 24 V
Efficiency
VIN = 12.0 V
CBOOT
0.01 μF
92
CIN3
82 μF
CIN2
82 μF
35 V
CIN1
0.22 μF
VOUT = 5.0 V
90
35
V
88
BOOT
ENB
VIN
LX
VOUT = 3.3 V
86
84
82
L 1
33 μH
A8698
VOUT
3.3 V / 3 A
VOUT = 2.5 V
80
78
76
74
72
70
TSET
GND
VBIAS
FB
RTSET
30.1 k7
R1
6.34 k7
COUT
330 μF
6.3 V
ESR
R2
2 k7
D1
0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Circuit for 12 V step down to 3.3 V at 3 A.
Efficiency curves for circuit at left.
A8698-DS, Rev. 3
A8698
Wide Input Voltage 3.0 A Step Down Regulator
Absolute Maximum Ratings
Characteristic
Symbol
VIN
Conditions
Min.
–
Typ.
–
Max.
25
7
Units
V
VIN Supply Voltage
VBIAS Input Voltage
VBIAS
VS
–0.3
–1
–
V
Switching Voltage
–
–
V
ENB Input Voltage
VENB
TA
–0.3
–40
–
–
7
V
Operating Ambient Temperature Range
Junction Temperature
Storage Temperature
Range E
–
85
150
150
°C
°C
°C
TJ(max)
TS
–
–55
–
*Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any set of conditions, do not exceed
the specified current ratings, or a junction temperature, TJ, of 150°C.
Package Thermal Characteristics*
RθJA
Package
PCB
(°C/W)
LJ
35
4-layer
* Additional information is available on the Allegro website.
Ordering Information
Use the following complete part numbers when ordering:
Part Numbera
A8698ELJTR-T
A8698ELJ-T
Packingb
13 in. reel, 3000 pieces/reel
98 pieces/tube
Description
LJ package, SOIC surface mount with
exposed thermal pad
aLeadframe plating 100% matte tin.
bContact Allegro for additional packing options.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
Functional Block Diagram
VIN
BOOT
VIN
Boot Charge
V
IN
–
VOUT
LX
L1
ESR
D1
COUT
ENB
Switch PWM Control
Switch
μC
Disable
Clamp
Error
TSET
+
–
FB
–
I_Peak
I_Demand
VBIAS is connected to VOUT
when V target is between
3.3 and 5 V
COMP
OUT
Bias Supply
GND
VBIAS
VBB UVLO
TSD
Soft Start
Ramp Generation
0.8 V
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
ELECTRICAL CHARACTERISTICS1,2 at TA = 25°C, VIN = 8 to 25 V (unless noted otherwise)
Characteristics
Symbol
Test Conditions
Min.
Typ.
Max.
Units
VENB = LOW, VIN = 12 V, VBIAS = 3.2 V,
VFB = 1.5 V (not switching)
–
1.0
–
mA
VIN Quiescent Current
IVIN(Q)
VENB = LOW, VIN = 12 V, VBIAS < 3 V,
VFB = 1.5 V
–
4.1
–
mA
VENB = HIGH
–
–
–
3.8
180
–
100
5
μA
mA
mΩ
%
VBIAS Input Current
IBIAS
VBIAS = VOUT
Buck Switch On Resistance
Fixed Off-Time Proportion
Feedback Voltage
RDS(on)
TA = 25°C, IOUT = 3 A
Based on calculated value
–
–
–15
0.784
–3
–400
5
15
0.816
3
VFB
VOUT
IFB
0.8
–
V
Output Voltage Regulation
Feedback Input Bias Current
Soft Start Time
IOUT = 0 mA to 3 A
%
–100
10
–
100
15
5
nA
ms
A
tss
VFB > 0.4 V
3.5
–
Buck Switch Current Limit
ICL
VFB < 0.4 V
1.15
–
–
A
ENB Open Circuit Voltage
ENB Input Voltage Threshold
ENB Input Current
VOC
VENB(0)
IENB(0)
Output disabled
2.0
–
7
V
LOW level input (Logic 0), output enabled
VENB = 0 V
–
1.0
–1
7.2
1.1
–
V
–10
6.6
0.7
–
–
μA
V
VIN Undervoltage Threshold
VIN Undervoltage Hysteresis
Thermal Shutdown Temperature
Thermal Shutdown Hysteresis
VUVLO
VIN rising
6.9
–
VUVLO(hys)
TJTSD
VIN falling
V
Temperature increasing
Recovery = TJTSD – TJTSD(hys)
165
15
°C
°C
TJTSD(hys)
–
–
1Negative current is defined as coming out of (sourcing) the specified device pin.
2Specifications over the junction temperature range of 0ºC to 125ºC are assured by design and characterization.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
Performance Characteristics
VOUT; 2.00 V/div.
IOUT; 1.00 A/div.
VSW; 10.0 V/div.
VOUTAC; 500 mV/div.
VINAC; 1.00 V/div.
IOUT; 2.00 A/div.
t
t
t = 10.0 ms/div.
t = 5.00 μs/div.
VOUTAC; 200 mV/div.
VOUT; 2.00 V/div.
IOUT; 500 mA/div.
IOUT; 1.00 A/div.
t
t
t = 1.00 ms/div.
t = 1.00 ms/div.
VOUTAC; 500 mV/div.
VOUTAC; 500 mV/div.
IOUT; 500 mA/div.
IOUT; 500 mA/div.
t
t = 100 μs/div.
t
t = 100 μs/div.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
Load Regulation
Line Regulation
IOUT = 3.0 A
0.2
0.1
0.2
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.1
–0.2
–0.3
–0.4
0
0.5
1.0
1.5
2.0
2.5
3.0
9
11
13
15
17
19
21
23
25
Load Current (A)
VIN (V)
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
6
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
Functional Description
The A8698 is a fixed off-time, current-mode–controlled buck
switching regulator. The regulator requires an external clamping
diode, inductor, and filter capacitor, and operates in both continu-
ous and discontinuous modes. An internal blanking circuit is used
to filter out transients resulting from the reverse recovery of the
external clamp diode. Typical blanking time is 200 ns.
ON/OFF Control. The ENB pin is externally pulled to ground
to enable the device and begin the soft start sequence. When the
ENB is open circuited, the switcher is disabled and the output
decays to 0 V.
Protection. The buck switch will be disabled under one or more
of the following fault conditions:
The value of a resistor between the TSET pin and ground deter-
mines the fixed off-time (see graph in the tOFF section).
• VIN < 6 V
• ENB pin = open circuit
• TSD fault
VOUT. The output voltage is adjustable from 0.8 to 20 V, based on
When the device comes out of a TSD fault, it will go into a soft
start to limit inrush current.
the combination of the value of the external resistor divider and
the internal 0.8 V ±2% reference. The voltage can be calculated
with the following formula:
tOFF. The value of a resistor between the TSET pin and ground
determines the fixed off-time. The formula to calculate tOFF (μs)
is:
VOUT = VFB × (1 + R1/R2)
(1)
Light Load Regulation. To maintain voltage regulation during
light load conditions, the switching regulator enters a cycle-skip-
ping mode. As the output current decreases, there remains some
energy that is stored during the power switch minimum on-time.
In order to prevent the output voltage from rising, the regulator
skips cycles once it reaches the minimum on-time, effectively
making the off-time larger.
⎛
⎜
⎞
⎟
1–0.03 VBIAS
(2)
t
R
SET
=
10.2 × 109
OFF
⎝
⎠
where RTSET (kΩ) is the value of the resistor. Results with the
VBIAS pin connected are shown in the following graph (when
VBIAS is not connected, use VBIAS = 0 in equation 2):
Off-Time Setting versus Resistor Value
200
Soft Start. An internal ramp generator and counter allow the out-
put to slowly ramp up. This limits the maximum demand on the
external power supply by controlling the inrush current required
to charge the external capacitor and any dc load at startup.
Internally, the ramp is set to 10 ms nominal rise time. During soft
start, current limit is 3.5 A minimum.
180
160
140
VBIAS = 5 V
120
100
VBIAS = 3.3 V
80
60
40
20
0
The following conditions are required to trigger a soft start:
• VIN > 6 V
• ENB pin input falling edge
• Reset of a TSD (thermal shut down) event
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
tOFF (µs)
V
BIAS. To improve overall system efficiency, the regulator output,
tON. From the volt-second balance of the inductor, the turn-on
time, ton , can be calculated approximately by the equation:
VOUT, is connected to the VBIAS input to supply the operating
bias current during normal operating conditions. During startup
the circuitry is run off of the VIN supply. VBIAS should be con-
nected to VOUT when the VOUT target level is between 3.3 and
5 V. If the output voltage is less than 3.3 V, then the A8698 can
operate with an internal supply and pay a penalty in efficiency,
as the bias current will come from the high voltage supply, VIN.
VBIAS can also be supplied with an external voltage source. No
power-up sequencing is required for normal opperation.
(VOUT + Vf + IOUT RL) tOFF
(3)
tON
=
VIN – IOUT
RDS(on) – IOUT RL – VOUT
where
V is the voltage drop across the external Schottky diode,
f
RL is the winding resistance of the inductor, and
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
7
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
RDS(on) is the on-resistance of the switching MOSFET.
time is extended to prevent loss of control of the current limit due
to the minimum on-time of the switcher.
The switching frequency is calculated as follows:
The extension of the off-time is based on the value of the TSET
multiplier and the FB voltage, as shown in the following table:
1
(4)
fSW
=
tON + tOFF
VFB (V)
< 0.16
< 0.32
< 0.5
TSET Multiplier
8 × tOFF
Shorted Load. If the voltage on the FB pin falls below 0.4 V, the
regulator will invoke a 1.5 A typical overcurrent limit to handle
the shorted load condition at the regulator output. For low output
voltages at power up and in the case of a shorted output, the off-
4 × tOFF
2 × tOFF
Component Selection
L1. The inductor must be rated to handle the total load current.
The value should be chosen to keep the ripple current to a reason-
able value. The ripple current, IRIPPLE, can be calculated by:
Substituting into equation 8:
ON = 323 mA × 33 μH / 7.95 V = 1.34 μs
Substituting into equation 7:
fSW = 1 / (2.67 μs +1.34 μs) = 250 kHz
t
IRIPPLE = VL(OFF) × tOFF /L
(5)
(6)
VL(OFF) = VOUT + Vf + IL(AV) × RL
Higher inductor values can be chosen to lower the ripple cur-
rent. This may be an option if it is required to increase the total
maximum current available above that drawn from the switching
regulator. The maximum total current available, ILOAD(MAX) , is:
Example:
Given VOUT = 3.3 V, Vf = 0.55 V, VIN = 12 V, ILOAD = 3.0 A,
power inductor with L = 33 μH and RL = 0.05 Ω Rdc at 55°C,
tOFF = 2.67 μs, and RDS(on) = 0.2 Ω.
I
LOAD(MAX) = ICL(min) – IRIPPLE /2
(10)
where ICL(min) is 3.5 A, from the Electrical Chracteristics table.
Substituting into equation 6:
D1. The Schottky catch diode should be rated to handle 1.2 times
the maximum load current. The voltage rating should be higher
than the maximum input voltage expected during all operating
conditions. The duty cycle for high input voltages can be very
close to 100%.
VL(OFF) = 3.3 V + 0.55 V+ 3.0 A × 0.05 Ω = 4.0 V
Substituting into equation 5:
IRIPPLE = 4.0 V × 2.67 μs / 33 μH = 323 mA
COUT. The main consideration in selecting an output capacitor
is voltage ripple on the output. For electrolytic output capacitors,
a low-ESR type is recommended.
The switching frequency, fSW, can then be estimated by:
fSW = 1 / ( tON + tOFF
)
(7)
(8)
The peak-to-peak output voltage ripple is simply IRIPPLE × ESR.
Note that increasing the inductor value can decrease the ripple
current. The ESR should be in the range from 50 to 500 mΩ.
tON = IRIPPLE × L / VL(ON)
V
L(ON) = VIN – IL(AV) × RDS(on) – IL(AV) × RL– VOUT
(9)
If a low ESR capacitor is used, such as a POSCAP or SP, an extra
Rr, Cr circuit is needed to inject ripple into the feedback pin and
ensure stability. Please refer to the Application Circuit section for
Substituting into equation 9:
VL(ON) = 12 V – 3 A × 0.2 Ω – 3 A × 0.05 Ω – 3.3 V = 7.95 V
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
the connection. The Rr should be much larger than the feedback
resistor to prevent any potential offset in output voltage. For
example, if Rf < 10 kΩ, Rr should be 1 MΩ. Cr should be selected
based on the following equation:
Note. The curve represents the minimum RTSET value. When
calculating RTSET, be sure to use VIN(max) / VOUT(min). Resistor
tolerance should also be considered, so that under no operating
conditions the resistance on the TSET pin is allowed to go below
the minimum value.
(V (min) – VFB) × tON(min)
IN
(5)
Cr(max) =
0.05 × Rr
where Cr is in pF, tON(min) is in μs, and Rr is in MΩ.
FB Resistor Selection. The impedance of the FB network
should be kept low to improve noise immunity. Large value resis-
tors can pick up noise generated by the inductor, which can affect
voltage regulation of the switcher.
RTSET Selection. Correct selection of RTSET values will
ensure that minimum on-time of the switcher is not violated and
prevent the switcher from cycle skipping. For a given VIN to
VOUT ratio, the RTSET value must be greater than or equal to the
value defined by the curve in the plot below.
13.0
12.5
12.0
11.5
Violation of
11.0
Minimum On-Time
10.5
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
Safe Operating Area
10.0
12
.5
15
.0
17
.5
20
.0
2
25
.0
2
30
.0
32.5
35
.0
37
.5
40
.0
4
45
.0
4
50.0
5
5
57.5
6
62.5
65.0
67
.5
70
2.5
7.5
2.5
7.5
2.5
5.0
0.0
.
0
RTSET (k7)
Allegro MicroSystems, Inc.
9
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
Application Circuit
Circuit with Low ESR Capacitor
fSW = 500 kHz nominal at 12 V
Efficiency versus Load Current
Stabilized with low ESR capacitor
100
90
80
70
60
50
40
30
20
10
VIN
12 to 16.4 V
CBOOT
0.01 μF
CIN
22 μF
VIN
LX
BOOT
ENB
VOUT
5V /2.5 A
L
10 μH
A8698
COUT
D1
120 μF
TSET
GND
VBIAS
FB
R3
1MΩ
mΩ
18
RTSET
16.4 kΩ
R1
6.34 kΩ
Ratings:
R2
100 pF
L: CDRH104R-100NC
COUT: EEFUD0J121R
CIN: ECJ-4YB1E226M
1.2 kΩ
0
0
0.5
1.0
1.5
2.0
2.5
3.0
Load Current (A)
Evaluation Board
Silkscreen Layer
Bottom Layer
J1
8 to 24 Vdc
C1.2
C1.3
C1.1
J2
GND
C3
C2
J4
GND
C4.2
C4.1
BOOT
ENB
VIN
LX
J3
R4
R3
L1
3.3 V / 3.0 A
A8698
VOUT
C4.3
D1
TSET
GND
VBIAS
FB
EN
PAD
R2
R1
R5
P1
Top and Silkscreen Layers
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
Evaluation Board Bill of Materials
Designator Quantity
Description
Manufacturer
Panasonic
Rubycon
Footprint
Part Number
ECJ4YB1E226M
35V-ZAV-820-8 X 12
C1.1
1
2
Ceramic chip, 22 μF, 25 V, ±20%, X5R.
1210
C1.2, C1.3
Aluminum electrolytic capacitor, 35 V / 82 μF, 930
8 mm × 12 mm
mA ripple current
C2
C3
1
1
0
Ceramic capacitor, X7R, ±10%, 0.1 μF / 50 V
Ceramic capacitor, X7R, ±10%, 0.01 μF / 50 V
Special polymer cap, 120 μF / 6.3 V, 15 mꢀ
Murata
Kemet
0603
0603
GRM188R71H104KA93D
C0603C103K5RACTU
EEFUD0J121R
C4.2
Panasonic
7.3 mm × 4.3 mm
× 3.1 mm
C4.1
C4.3
0
1
Ceramic capacitor, X5R, ±20%, 47 μF / 6.3 V
Panasonic
Panasonic
1210
ECJ4YB0J476M
EEVFC0J331P
Aluminum electrolytic capacitor, 6.3 V / 330 μF, 450
mA ripple current, 300 mꢀ
8 mm × 10.2 mm
L1
1
Inductor, 33 μH, 53 mꢀ, 3.9 A, ±20%
Sumida
10.3 mm ×
CDRH127/LDNP-330MC
10.5 mm × 4 mm
D1
R1
R2
R3
R4
R5
1
1
3
1
1
1
4
Schottky diode, 40 V / 3.0 A
Chip resistor, 6.34 kꢀ, 1/16 W, 1%
Chip resistor, 2.0 kꢀ,1/16 W, 1%
Chip resistor, 30.1 kꢀ, 1/16 W, 1%
Chip resistor, 10 kꢀ, 1/16 W, 1%
Chip resistor, 0 ꢀ, 1/16 W, 1%
Header, 2-pin, 100 mil spacing
Diodes, Inc.
Std
SMA
0603
B340
Std.
Std
0603
Std.
Std
0603
Std.
Std
0603
Std.
Std
0603
Std.
J1, J2, J3,
J4
Sullins
0.100 in. × 2
PTC36SAAN
P1
EN
U1
1
1
1
Test point, Red, 1mm
Test point, Black, 1mm
Farnell
Farnell
Allegro
0.038 in.
0.038 in.
ESOIC8
240-345
240-333
A8698
Wide Input Voltage Step Down Regulator
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
11
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A8698
Wide Input Voltage 3.0 A Step Down Regulator
6.20 .244
5.80 .228
Package LJ 8-Pin SOIC
0.25 [.010] M B M
5.00 .197
4.80 .189
8º
0º
A
8
B
0.25 .010
0.17 .007
4.00 .157
3.80 .150
B
2.41 .095
NOM
1.27 .050
0.40 .016
A
1
2
3.30 .130
NOM
0.25 .010
C
8X
SEATING PLANE
GAUGE PLANE
SEATING
PLANE
0.10 [.004]
C
0.51 .020
0.31 .012
1.75 .069
1.35 .053
8X
0.25 [.010] M
C A B
0.25 .010
0.10 .004
1.27 .050
0.65 .026
MAX
1.27 .050
NOM
All dimensions reference, not for tooling use
(reference JEDEC MS-012 AA)
1.75 .069
NOM
Dimensions in millimeters
U.S. Customary dimensions (in.) in brackets, for reference only
Dimensions exclusive of mold flash, gate burrs, and dambar protrusions
Exact case and lead configuration at supplier discretion within limits shown
5.60 .220
NOM
A
B
C
Terminal #1 mark area
2.41 .095
NOM
2X 0.20 .008
MIN
Exposed thermal pad (bottom surface)
Reference land pattern layout (reference IPC7351
SOIC127P600X175-9AM); adjust as necessary to meet
application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal
vias at the exposed thermal pad land can improve thermal
dissipation (reference EIA/JEDEC Standard JESD51-5)
C
1
2
6X 0.20 .008
MIN
3.30 .130
NOM
Pin-out Diagram
Terminal List Table
Number
Name
Description
1
2
3
4
5
6
7
8
–
BOOT Gate drive boost node
ENB On/off control; logic input
TSET Off-time setting
GND Ground
BOOT
ENB
1
2
3
4
8
7
6
5
VIN
LX
Pad
TSET
GND
VBIAS
FB
FB
Feedback for adjustable regulator
VBIAS Bias supply input
LX
VIN
Pad
Buck switching node
Supply input
Exposed pad for enhanced thermal dissipation
(Top View)
The products described herein are manufactured under one or more patents pending.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reli-
ability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the information being relied upon is current.
Allegro products are not authorized for use as critical components in life-support appliances, devices, or systems without express written approval.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use; nor for any infringements of patents or
other rights of third parties that may result from its use.
Copyright © 2006 Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
12
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
相关型号：
A8731
The Allegro A8731 Xenon photoflash charger IC is designed to meet the needs of ultra-low power, small form factor cameras, particularly camera-phones.
ALLEGRO
A8731EEJTR-T
The Allegro A8731 Xenon photoflash charger IC is designed to meet the needs of ultra-low power, small form factor cameras, particularly camera-phones.
ALLEGRO
©2020 ICPDF网 联系我们和版权申明