A8731EEJTR-T [ALLEGRO]
The Allegro A8731 Xenon photoflash charger IC is designed to meet the needs of ultra-low power, small form factor cameras, particularly camera-phones.; 快板A8731氙气闪光灯充电器IC是专为满足超低功耗，小型摄像机，特别是拍照手机的需求。
| 型号： | A8731EEJTR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | The Allegro A8731 Xenon photoflash charger IC is designed to meet the needs of ultra-low power, small form factor cameras, particularly camera-phones. |
| 文件： | 总16页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A8731
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
Features and Benefits
Description
TheAllegro® A8731 Xenon photoflash charger IC is designed
tomeettheneedsofultra-lowpower,smallformfactorcameras,
particularly camera-phones.
▪ Low quiescent current draw (0.01 μA in shutdown mode)
▪ Primary-side output voltage sensing; no resistor divider
required
The charge time is adjustable by setting the charge current
limit from 0.4 to 1.2 A maximum. By using primary-side
voltagesensing, theneedforasecondary-sideresistivevoltage
divideriseliminated.Thishastheadditionalbenefitofreducing
leakage currents on the secondary side of the transformer. To
extend battery life, theA8731 features very low supply current
draw—typically 0.01 μA in shutdown mode and 10 μA in
standby mode.
TheA8731hasaflashdualtriggerIGBTdriver.TheIGBTdriver
alsohasinternalgateresistorsforminimumexternalcomponent
count. The charge and trigger voltage logic thresholds are set
at 1.1 VHI (min) to support applications implementing low
voltage control logic.
▪ User-adjustable current limit from 0.4 to 1.2 A
▪ 1.1 V logic (VHI(min)) compatibility
▪ Integrated IGBT driver with internal gate resistors
▪ Flexible dual trigger inputs for IGBT driver
▪ Optimized for mobile phone, 1-cell Li+ battery applications
▪ No primary-side Schottky diode needed
▪ Zero-voltage switching for lower loss
▪ >75% efficiency
▪ Charge complete indication
▪ Integrated 40 V DMOS switch
Applications
▪ Mobile phone flash
▪ Digital and film camera flash
The A8731 is available in a 10-contact 3 mm × 3 mm DFN
package with a 0.75 nominal overall package height, and an
exposed pad for enhanced thermal performance.
Package: 10-contact DFN with exposed
thermal pad (package EJ)
Approximate Scale 1:1
Typical Applications
1 : 10
1 : 10
+
+
Battery Input
2.3 to 5.5 V
Battery Input
2.3 to 5.5 V
C1
C1
COUT
100 μF
315 V
C2
C2
COUT
100 μF
VIN
VIN
315 V
VOUT Detect
VOUT Detect
SW
SW
ISET
ISET
Control
Block
Control
Block
I
SW sense
ISW sense
RSET
RSET
VPULLUP
VPULLUP
100 kΩ
100 kΩ
DONE
DONE
CHARGE
CHARGE
DONE
GATE
DONE
GATE
V
V
IN
IGBT Driver
IN
IGBT Driver
TRIGGER1
TRIGGER2
TRIGGER1
TRIGGER2
IGBT Gate
IGBT Gate
GND
GND
Figure 1. Typical application with separate trigger inputs.
A8731-DS, Rev. 1
Figure 2. Typical application with single trigger input.
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
Selection Guide
Part Number
Package
10-contact DFN
Packing
A8731EEJTR-T
Tape and reel, 1500 pieces per reel
*Contact Allegro for additional ordering information.
Absolute Maximum Ratings
Characteristic
Symbol
VSW
Notes
Rating
Units
DC voltage.
(VSW is self-clamped by internal active clamp
and is allowed to exceed 40 V during flyback
spike durations. Maximum repetitive energy
during flyback spike: 0.5 μJ at frequency
≤ 400 kHz.)
SW Pin
VIN Pin
–0.3 to 40
V
VIN
–0.3 to 6.0
V
V
Care should be taken to limit the current when
–0.6 V is applied to these pins.
¯¯¯¯¯¯¯¯
CHARGE, TRIGGERx, DONE Pins
–0.6 to VIN + 0.3 V
Remaining Pins
–0.3 to VIN + 0.3 V
–40 to 85
V
Operating Ambient Temperature
Maximum Junction
TA
TJ(max)
Tstg
Range E
ºC
ºC
ºC
150
Storage Temperature
–55 to 150
Thermal Characteristics
Characteristic
Symbol
Test Conditions*
Value Units
On 2-layer PCB with 0.88 in.2 area of 2 oz. copper each side,
based on JEDEC standard
65
45
ºC/W
ºC/W
Package Thermal Resistance
RθJA
On 4-layer PCB based on JEDEC standard
*Additional thermal information available on Allegro website.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
2
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
Functional Block Diagram
SW
VIN
VSW – VBAT
ISET Buffer
DCM
Detector
Control Logic
DMOS
t
off(max)
18 μs
ISET
S
R
Q
Q
H m L
VDSref
OCP
Triggered Timer
ton(max)
18 μs
Enable
S
R
Q
Q
DONE
One Shot
CHARGE
V
IN
IGBT Driver
GATE
TRIGGER1
TRIGGER2
GND
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
3
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
Pin-out Diagram
ISET
GATE
1
2
3
4
5
10 NC
9
8
7
6
DONE
PAD
VIN
TRIGGER1
SW
GND
CHARGE
TRIGGER2
(Contacts Down View)
Terminal List Table
Number
Name
Function
1
ISET
Sets the maximum switch current; connect an external resistor to GND to
set the desired peak current
2
3
4
5
6
7
GATE
VIN
IGBT gate drive – sink/source
Input voltage; connect to a 2.3 to 5.5 V battery supply
Ground connection
GND
CHARGE
TRIGGER2
SW
Pull high to initiate charging; pull low to enter low-power standby mode
IGBT input trigger 2
Drain connection of internal power MOSFET switch; connect to
transformer primary winding
8
9
TRIGGER1
IGBT input trigger 1
¯¯¯¯¯¯¯¯
DONE
Pulls low when output reaches target value and CHARGE pin is high;
goes high during charging or whenever CHARGE pin is low
10
–
NC
No connection , electrically floating pin
PAD
Exposed pad for enhanced thermal dissipation; connect to ground plane
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
4
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
ELECTRICAL CHARACTERISTICS typical values valid at VIN = 3.6 V, RSET= 33 kΩ, ISWlim = 1.0 A, and TA=25°C, unless otherwise noted
Characteristics
VIN Voltage Range
Symbol
VIN
Test Conditions
Min.
2.3
–
Typ.
–
Max.
5.5
2.2
–
Unit
V
UVLO Enable Threshold
UVLO Hysteresis
VINUV
VIN rising
2.05
150
V
VINUVhys
–
mV
Shutdown (CHARGE = 0 V,
TRIGGER1 and TRIGGER2 = 0 V)
–
–
–
0.01
10
2
0.5
50
–
μA
μA
VIN Supply Current
IIN
Charging complete
Charging (CHARGE = VIN,
TRIGGER1 and TRIGGER2 = 0 V)
mA
Current Limits
ISWlimMAX RSET = 26.7 kΩ
ISWlimMIN RSET = 85 kΩ
1.08
–
1.2
0.4
28
1.32
–
A
A
Switch Current Limit1
SW / ISET Current Ratio
I
SW/ISET CHARGE = high
VSET CHARGE = high
RSET(INT)
–
–
kA/A
V
ISET Pin Voltage While Charging
ISET Pin Internal Resistance
Switch On-Resistance
–
1.2
1000
0.25
–
–
–
–
Ω
RSWDS(on) VIN = 3.6 V, ID = 800 mA, TA = 25°C
VSW = VIN(max), over temperature range
–
–
Ω
–
2
μA
Switch Leakage Current2
ISWlk
Combined VIN and SW leakage current at TA=25°C
–
–
0.5
μA
VIN= 5.5 V in Shutdown
ICHARGE VCHARGE = VIN
CHARGE Input Current
CHARGE Input Voltage2
–
1.1
–
36
–
–
–
μA
V
High, over input supply range
VCHARGE
Low, over input supply range
–
0.4
–
V
CHARGE Pull-Down Resistor Value
CHARGE ON/OFF Delay
Maximum Switch-Off Timeout
Maximum Switch-On Timeout
2
RCHPD
–
100
20
18
18
kΩ
us
μs
μs
tCH
Time between CHARGE = 1 and charging enabled
–
–
toffMAX
tonMAX
IDONElk
VDONEL
–
–
–
–
¯¯¯¯¯¯¯¯
DONE Output Leakage Current
–
–
1
μA
2
¯¯¯¯¯¯¯¯
DONE Output Low Voltage
¯¯¯¯¯¯¯¯
32 μA into DONE pin
–
31
–
–
100
32
mV
V
Output Comparator Trip Voltage2
Output Comparator Overdrive
dV/dt Threshold of ZVS Comparator
IGBT Driver
VOUTTRIP Measured as VSW – VIN
31.5
200
20
VOUTOV Pulse width = 200 ns (90% to 90%)
400
–
mV
V/ꢀs
dV/dt
Measured at SW pin
–
VTRIG(H) Input = logic high, over input supply range
VTRIG(L) Input = logic low, over input supply range
1.1
–
–
–
0.4
–
V
V
TRIGGER, TRIGGER2 Input Voltage2
–
TRIGGER, TRIGGER2 Pull-Down Resistor RTRIGPD
–
100
23
kΩ
Ω
GATE Resistance to VIN
GATE Resistance to GND
Propagation Delay (Rising)
Propagation Delay (Falling)
Output Rise Time
RSrcDS(on) VIN = 3.6 V, VGATE =1.8 V
–
–
RSnkDS(on) VIN = 3.6 V, VGATE = 1.8 V
–
30
–
Ω
tDr
tDf
–
110
140
290
360
–
ns
ns
ns
ns
–
–
Measurement taken at pin, CL= 6500 pF, VIN= 3.6 V
tr
tf
–
–
Output Fall Time
–
–
1Current limit guaranteed by design and correlation to static test. Refer to application section for peak current in actual circuits.
2Specifications over the range TA= –40°C to 85°C; guaranteed by design and characterization.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
5
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
IGBT Drive Timing Definition
50%
50%
TRIGGER
GATE
t
Dr
t
r
t
Df
t
f
90%
90%
10%
10%
IGBT Drive Timing Characteristic Performance
CGATE = 6200 pF. VIN = 3.6 V, Time = 200 ns/div; CH1 = TRIGGER input, 2 V/div,
CH2 = Gate driver output, 1 V/div
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
6
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
A8731 Operation Timing Diagram
UVLO
VIN
CHARGE
SW
Target V
OUT
VOUT
DONE
T2
T3
T1
TRIGGER1 and
TRIGGER2
IGBTDRV
A
B
C
D
E
F
Explanation of Events
A: Start charging by pulling CHARGE to high, provided that VIN is above UVLO level.
B: Charging stops when VOUT reaches the target voltage.
C: Start a new charging process with a low-to-high transition at the CHARGE pin.
D: Pull CHARGE to low to put the controller in low-power standby mode.
E: Charging does not start, because VIN is below UVLO level when CHARGE goes high.
F: After VIN goes above UVLO, another low-to-high transition at the CHARGE pin is required to
start the charging.
T1, T2, T3(Trigger instances): IGBT driver output pulled high whenever both TRIGGER pins are
logic high. It is recommended to avoid applying any trigger pulses during charging.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
7
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
Performance Characteristics
Charging Time at Various Peak Current Levels
Common Parameters
Parameter Units/Division
Symbol
C1
C2
C3
t
VOUT
VBAT
IIN
50 V
1 V
100 mA
200 ms
Value
3.6 V
VOUT
C1
time
Conditions Parameter
VBATT
COUT
VBAT
C2
20 μF
IIN
Conditions Parameter
Value
26.7 kΩ
≈1.2 A
C1
C2
C3
C3
RSET
ISWlim
t
VOUT
C1
VBAT
C2
IIN
Conditions Parameter
Value
33.2 kΩ
≈1.0 A
C1
C2
C3
C3
RSET
ISWlim
t
VOUT
C1
VBAT
C2
IIN
Conditions Parameter
Value
39 kΩ
≈0.9 A
C1
C2
C3
C3
RSET
ISWlim
t
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
8
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
Efficiency versus Battery Voltage
Charge Time versus Battery Voltage
Transformer Lp= 8 μH, N = 10.2; COUT= 20 μF / 330 V UCC; TA=25°
Transformer Lp= 8 μH, N = 10.2; COUT= 20 μF / 330 V UCC; TA=25°
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
RSET
(kΩ)
55
IP
(A)
≈ 0.65
45
39
≈ 0.8
≈ 0.9
33.2
26.7
≈ 1.0
≈ 1.2
RSET
(kΩ)
55
IP
(A)
≈ 0.65
45
39
≈ 0.8
≈ 0.9
33.2
26.7
≈ 1.0
≈ 1.2
2.0
2.5
3.0
3.5
4.0
BAT (V)
4.5
5.0
5.5
6.0
2.0
2.5
3.0
3.5
4.0
VBAT (V)
4.5
5.0
5.5
6.0
V
COUT= 20 μF. For larger or smaller capacitances, charging time
Special low-profile transformer with relatively low inductance
scales proportionally.
(Lp= 8 μH) and high winding resistance (Rp = 0.37 Ω). Higher efficien-
cy can be achieved by using transformers with higher Lp, which reduces
switching frequency and therefore switching loses, and lower resistance,
which reduces conduction losses.
Average Input Current versus Battery Voltage
XFM Lp= 8 μH, N = 10.2, COUT= 20 μF 330 V UCC, TA=25°
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
RSET
(kΩ)
26.7
IP
(A)
≈ 1.2
33.2
39
≈ 1.0
≈ 0.9
≈ 0.8
≈ 0.65
45
55
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
VBAT (V)
An increase in ISWlim with respect to VBAT actually keeps the average input current
roughly constant throughout the battery voltage range. Normally, if ISWlim is kept
constant, the average current will drop as VBAT goes higher.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
9
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
Application Information
transformer primary inductance, Lp. If necessary, the
General Operation Overview
following expressions can be used to determine ISWlim
more accurately:
The CHARGE pin enables the part and starts charging.
¯¯
¯¯
¯¯
¯
¯¯¯¯
The DONE open-drain indicator is pulled low when
CHARGE is high and target output voltage is reached.
Pulling the CHARGE pin low stops charging and
forces the chip into low-power standby mode.
I
SET = VSET /(RSET + RSET(INT) – K × RGND(INT)), (2)
where:
Selection of Switching Current Limit
R
SET(INT) is the internal resistance of the ISET pin
The A8731 features continuously adjustable peak
switching current between 0.4 and 1.2A. This is done
by selecting the value of an external resistor RSET,
connected from the ISET pin to GND, which deter-
mines the ISET bias current, and therefore the switch-
(1 kꢀ typical),
R
GND(INT) is the internal resistance of the bonding
wire for the GND pin (27 mꢀ typical), and
ing current limit, ISWlim
.
K = (K′ + VIN × K″), with K′ = 24350 and
K″ ≈ 1040 at TA = 25°C. Then,
To the first order approximation, ISWlim is related to
ISET and RSET according to the following equations:
I
SWlim = ISET × K + VBAT / LP × tD ,
(3)
(1)
ISWlim = ISET × K = VSET /RSET × K ,
where tD is the delay in SW turn-off (0.1 ꢁs typical).
where K = 28000 when battery voltage is 3.6 V.
Figure 3 can be used to determine the relationship
between RSET and ISWlim at various battery voltages.
In real applications, the actual switching current
limit is affected by input battery voltage, and also the
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
VIN = 5.5 V
VIN = 4.5 V
VIN = 3.6 V
VIN = 3.0 V
VIN = 2.3 V
25
30
35
40
45
50
55
60
65
70
75
80
85
90
RSET (kΩ)
Figure 3. Peak Current Limit versus ISET Resistance. VIN = VBAT, transformer LP = 8 μH, TA = 25°C.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
10
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
relationship of Timer Mode and Fast Charging Mode
is shown in figure 5.
Smart Current Limit (Optional)
With the help of some simple external logic, the user
can change the charging current according to the bat-
tery voltage. For example, assume that ISET is nor-
The IC operates in Timer Mode when beginning to
charge a completely discharged photoflash capaci-
mally 36 μA (for ISWlim = 1.0 A). Referring to figure 4, tor, usually when the output voltage, VOUT, is less
when the battery voltage drops below 2.5 V, the signal
at BL (battery-low) goes high. The resistor RBL, con-
necting BL to the ISET pin, then injects 10 μA into
RSET. This effectively reduces ISET current to 26 μA
(for ISWLIM = 0.73 A).
than approximately 15 to 20 V. Timer Mode is a fixed
period, 18 ꢁs, off-time control. One advantage of
having Timer Mode is that it limits the initial battery
current surge and thus acts as a “soft-start.” A time-
expanded view of a Timer Mode interval is shown in
figure 6.
Timer Mode and Fast Charging Mode
The A8731 achieves fast charging times and high effi- As soon as a sufficient voltage has built up at the
ciency by operating in discontinuous conduction mode
(DCM) through most of the charging process The
output capacitor, the IC enters Fast-Charging Mode.
In this mode, the next switching cycle starts after the
secondary side current has stopped flowing, and the
switch voltage has dropped to a minimum value. A
proprietary circuit is used to allow minimum-voltage
switching, even if the SW pin voltage does not drop to
0 V. This enables Fast-Charging Mode to start earlier
BL
RBL
ISET
RSET
Figure 4. Smart Current Limit reference circuit
VOUT
Timer Mode
Fast Charging Mode
VBAT
VSW
VBAT
VOUT
IIN
ISW
Figure 5. Timer Mode and Fast Charging Mode. t =200 ms/div,
VOUT =50 V/div, VBAT =1 V/div., IIN =100 mA/div., VBAT =3.6 V,
COUT =20 μF/330 V, RSET=46 kΩ (ISWlim≈0.75 A).
Figure 6. Timer Mode expanded view. VOUT ≤ 14 V, t = 2 μs / div.,
VBAT = 3.6 V, RSET = 33.2 kΩ.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
11
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
than previously possible, thereby reducing the overall
charging time. Minimum-voltage switching is shown
in figure 7.
sufficient ambient light (for example, during daylight
outdoor photographing), a current of about 30 μA
can flow through the phototransistor. This forces the
voltage at TRIGGER2 pin to fall to 0.8 V or lower,
so it prohibits TRIGGER1 from firing the flash. The
exact threshold of ambient light required to prohibit
flash firing can be adjusted by RTGR1. The smaller this
resistance, the brighter the ambient light must be to
prohibit flash firing.
During Fast-Charging Mode, when VOUT is high
enough (over 50 V), true zero-voltage switching
(ZVS) is achieved. This further improves efficiency
as well as reduces switching noise. A ZVS interval is
shown in figure 8.
IGBT Gate Driver Inputs
When ambient conditions are dark, the current flow-
ing through the phototransistor is in less than 1 μA.
Because the TRIGGER2 pin is biased at 1.4 V or
higher, TRIGGER1 is allowed to activate the IGBT
gate driver (and thereby fire the flash).
The TRIGGER1 and TRIGGER2 pins are ANDed
together inside the IC to control the IGBT gate driver.
If only one trigger signal is needed, tie both trigger
pins together and use as a single input.
Ambient Light Sensing
The capacitor CTGR1 and resistor RTGR1 form an
integrator for light exposure. When the flash fires,
bright light bounces back from subject and enters the
phototransistor. In example A in figure 10, the flash
terminates after just 30 μs, without fully discharging
the photoflash capacitor.
Ambient Light Sensing (ALS) can be easily imple-
mented for the A8731 using the TRIGGER2 pin plus
three external components. This configuration is
shown in figure 9.
The phototransistor current is proportional to the
intensity of the light that it receives. When there is
VOUT
Minimum Voltage
Switching
Zero Voltage
VSW
Switching
VSW
VBAT
VBAT
VOUT
ISW
ISW
Figure 7. Minimum voltage switching. VOUT ≥ 15 V; t =1 μs/div.,
VBAT = 3.6 V, RSET = 33.2 kΩ.
Figure 8. Zero voltage switching. VOUT = 120 V. t = 0.2 μs/div.,
VBAT = 3.6 V, RSET = 33.2 kΩ.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
12
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
Battery Input
2.5 to 5.5 V
If the subject is far away, the reflected
light intensity is lower, so the phototransis-
tor current is also lower. In example B, the
flash stays on for longer time (60 μs) and
discharges more energy from the photo-
flash capacitor.
1 : 10
+
C1
C2
COUT
100 μF
315 V
VIN
VOUT Detect
SW
ISET
Control
Block
Using a larger CTGR1 causes the time
constant of the integrator to increase, so a
longer pulse is required before the flash is
terminated.
ISW sense
RSET
VPULLUP
DONE
CHARGE
DONE
GATE
V
IN
IGBT Driver
TRIGGER1
TRIGGER2
A
IGBT Gate
RTGR1
100 kΩ
CTGR1
1 μF
GND
It is recommend to use a regulated system voltage for the bias. If battery
voltage is used, the ALS sensitivity will vary with battery voltage, and there
would be a small leakage current even when the camera is turned off.
A
PNZ121S
Phototransistor
Figure 9. ALS typical application
VOUT
C1
VOUT
VTRIGGER2
VTRIGGER1
C1
C2
C3
VTRIGGER2
C2
C3
C2
C3
C2
C3
VTRIGGER1
VGATE
VGATE
C1
C4
C1
C4
C4
C4
Common Parameters
t
t
Symbol
C1
C2
C3
C4
Parameter Units/Division
(B)
VOUT
VTRIGGER2
VTRIGGER1
VGATE
50 V
1 V
5 V
(A)
5 V
t
time
20 μs
Figure 10. Adaptive timing of photoflash. (A) Subject near to camera, and (B) subject far from camera.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
13
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
The minimum pulse width for toff determines what
is the minimum LP required for the transformer. For
example, if ISWlim = 0.7 A, N = 10, and VOUT = 315 V,
then LP must be at least 9 μH in order to keep toff at
200 ns or longer. These relationships are illustrated in
figure 11.
Transformer Selection
1. The transformer turns ratio, N, determines the out-
put voltage:
N = NS / NP ,
(4)
(5)
VOUT = 31.5 × N – Vd ,
where 31.5 is the typical value of VOUTTRIP, and Vd is
the forward drop of the output diode.
In general, choosing a transformer with a larger LP
results in higher efficiency (because a larger LP means
lower switch frequency and hence lower switching
loss). But transformers with a larger LP also require
more windings and larger magnetic cores. Therefore, a
trade-off must be made between transformer size and
efficiency.
2. The primary inductance, LP, determines the on-time
of the switch:
ton = (–LP/R)×ln(1 – ISWlim × R/V ) ,
(6)
IN
where R is the total resistance in the primary current
path (including RSWDS(on) and the DC resistance of the
transformer).
Component Selection
If VIN is much larger than ISWlim ×R, then ton can be
approximated by:
Selection of the flyback transformer should be based
on the peak current, according to the following table:
ton = ISWlim ×LP /VIN
.
(7)
IPeak Range
(A)
LP
(μH)
14.5
10.5
8.2
3. The secondary inductance, LS, determines the off-
time of the switch. Given:
Supplier
TDK
Part Number
LDT565630T-002
LDT565630T-003
LDT565620ST-203
C5-KT2.2L
0.4 to 1.0
0.5 to 1.2
0.7 to 1.0
0.7 to 1.2
0.8 to 1.2
TDK
LS/LP = N×N , then
TDK
toff = (ISWlim /N)×LS /VOUT
= (ISWlim ×LP×N)/VOUT
(8)
(9)
Mitsumi
Tokyo Coil
8.0
T-19-243
6.5
.
toff
ton
VSW
ISW
V
r
tf
V
V
IN
IN
VSW
ISW
tneg
Figure 11. Pulse width relationship definitions.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
14
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
Package EJ, 3 mm x 3 mm 10-Contact DFN
with Exposed Thermal Pad
0.30
3.00 ±0.15
0.85
0.50
10
10
3.00 ±0.15
1.64 3.10
A
1
2
1
2.38
D
C
11X
SEATING
PLANE
0.08
C
+0.05
–0.07
C
PCB Layout Reference View
0.25
0.75 ±0.05
0.50
1
2
For Reference Only
(reference JEDEC MO-229WEED)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.40 ±0.10
A
B
Terminal #1 mark area
1.64
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
B
C
Reference land pattern layout (reference
IPC7351 SON50P300X300X80-11WEED3M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
10
2.38
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
15
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
Mobile Phone Xenon Photoflash Capacitor Charger
With IGBT Driver
A8731
Revision History
Revision
Revision Date
Description of Revision
Miscellaneous format changes
Rev. 1
April 19, 2012
Copyright ©2008-2012, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
16
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
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