A8740EEETR-T [ALLEGRO]
Analog Circuit, 1 Func, PDSO8, 2 X 2 MM, 0.60 MM HEIGHT, LEAD FREE, MO-229UCCD, DFN-8;
| 型号： | A8740EEETR-T |
| 厂家： | 
ALLEGRO MICROSYSTEMS |
| 描述： | Analog Circuit, 1 Func, PDSO8, 2 X 2 MM, 0.60 MM HEIGHT, LEAD FREE, MO-229UCCD, DFN-8 CD 光电二极管 |
| 文件： | 总18页 (文件大小：484K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
A8740
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
Discontinued Product
This device is no longer in production. The device should not be
purchased for new design applications. Samples are no longer available.
Date of status change: August 27, 2012
Recommended Substitutions:
For existing customer transition, and for new customers or new appli-
cations, contact Allegro Sales.
NOTE: For detailed information on purchasing options, contact your
local Allegro field applications engineer or sales representative.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, revisions to the anticipated product life cycle plan
for a product to accommodate changes in production capabilities, alternative product availabilities, or market demand. The
information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no respon-
sibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use.
A8740
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
Description
Features and Benefits
▪ Ultra small 2 × 2 DFN/MLP-8 package
TheAllegro®A8740isaXenonphotoflashchargerICdesigned
tomeettheneedsofultralowpower,smallformfactorcameras,
particularly camera phones. By using primary-side voltage
sensing, the need for a secondary-side resistive voltage divider
is eliminated. This has the additional benefit of reducing
leakage currents on the secondary side of the transformer. To
extend battery life, theA8740 features very low supply current
draw (0.5 μA max in shutdown mode). The IGBT driver also
has internal gate resistors for minimum external component
count. The charge and trigger voltage logic thresholds are set
at 1.3 VHI(min) to support applications implementing low-
voltage control logic.
▪ Low quiescent current draw (0.5 μA max. in shutdown mode)
▪ Primary-side output voltage sensing; no resistor divider required
▪ Fixed 1.5 A peak current limit
▪ 1.3 V logic (VHI(min)) compatibility
▪ Integrated IGBT driver with internal gate resistors
▪ Optimized for mobile phone, 1-cell Li+ battery applications
▪ Zero-voltage switching for lower loss
▪ >75% efficiency
▪ Charge complete indication
▪ Integrated 50 V DMOS switch with self-clamping protection
The A8740 is available in an 8-contact 2 mm × 2 mm
DFN/MLP package with a 0.60 maximum overall package
height, andanexposedpadforenhancedthermalperformance.
It is lead (Pb) free with 100% matte tin leadframe plating.
Package: 8-pin DFN/MLP (suffix EE)
2 mm×2 mm, 0.60 mm height
Not to scale
Typical Applications
+
+
Battery Input
C1
Battery Input
2.3 to 5.5 V
C1
1.5 to 5.5 V
COUT
COUT
100F
315 V
100F
VBAT
VBAT
315 V
VOUT Detect
VOUT Detect
SW
SW
VIN_VDRV
C2
VIN_VDRV
C2
Control
Block
Control
Block
I
SW sense
ISW sense
VPULLUP
VPULLUP
100 kΩ
100 kΩ
CHARGE
CHARGE
DONE
DONE
DONE
DONE
V
V
IN_VDRV
IN_VDRV
IGBT Driver
IGBT Driver
TRIG
TRIG
IGBT Gate
GATE
IGBT Gate
GATE
GND
GND
(A)
(B)
Figure 1. Typical applications: (A) with single battery supply and (B) with separate bias supply
8740-DS
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Selection Guide
Part Number
Packing
Package
A8740EEETR-T
3000 pieces per reel
8-contact DFN/MLP with exposed thermal pad
Absolute Maximum Ratings
Characteristic
Symbol
Notes
Rating
Units
DC voltage.
(VSW is self-clamped by internal active clamp
and is allowed to exceed 50 V during flyback
spike durations. Maximum repetitive energy
during flyback spike: 0.5 μJ at frequency
≤ 400 kHz.)
VSW
–0.3 to 50
V
SW Pin
ISW
VIN
DC current, pulse width = 1 ms
3
A
V
VIN_DRV, VBAT Pins
–0.3 to 6.0
Care should be taken to limit the current when
–0.6 V is applied to these pins.
¯¯¯¯¯¯¯¯
CHARGE, TRIG, DONE Pins
–0.6 to VIN + 0.3 V
V
Remaining Pins
–0.3 to VIN + 0.3 V
–40 to 85
V
Operating Ambient Temperature
Maximum Junction
TA
TJ(max)
Tstg
Range E
ºC
ºC
ºC
150
Storage Temperature
–55 to 150
THERMAL CHARACTERISTICS may require derating at maximum conditions
Characteristic
Symbol
Test Conditions*
Value Units
RθJA
Package Thermal Resistance
4-layer PCB, based on JEDEC standard
49 ºC/W
*Additional thermal information available on Allegro Web site.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
2
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Functional Block Diagram
SW
VBAT
VSW – VBAT
DCM
Detector
Control Logic
DMOS
t
off(max)
ILIM
Reference
18 μs
S
R
Q
Q
H m L
VDSref
OCP
Triggered Timer
t
on(max)
18 μs
Enable
VIN_DRV
S
R
Q
Q
DONE
CHARGE
TRIG
V
IN_DRV
IGBT Driver
GATE
GND
Terminal List
Number
Name
Function
Pin-out Diagram
Open collector output, pulls low when output reaches target value and CHARGE is
high. Goes high during charging or whenever CHARGE is low.
¯¯¯¯¯¯¯¯
DONE
1
2
3
4
5
6
TRIG
GATE
GND
SW
IGBT trigger input.
DONE
TRIG
GATE
GND
1
2
3
4
8
7
6
5
CHARGE
IGBT gate drive output.
VIN_DRV
VBAT
PAD
Ground connection.
SW
Drain connection of internal DMOS switch. Connect to transformer primary winding.
Battery voltage.
VBAT
(Top View)
Input voltage. Connect to 3 to 5.5 V bias supply. Decouple VIN voltage with 0.1 ꢀF
ceramic capacitor placed close to this pin.
7
VIN_DRV
8
–
CHARGE Charge enable pin. Set this pin low to shut down the chip.
PAD
Exposed pad for enhanced thermal dissipation. Connect to ground plane.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
3
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
ELECTRICAL CHARACTERISTICS Typical values are valid at VIN = VBAT = 3.6 V; TA = 25°C, except indicates specifications
guaranteed from −40°C to 85°C ambient, unless otherwise noted
Characteristics
VBAT Voltage Range1
Symbol
Test Conditions
Min.
Typ. Max. Unit
VBAT
1.5
–
5.5
V
VIN_DRV Voltage Range1
UVLO Enable Threshold
UVLO Hysteresis
VIN
2.3
–
–
5.5
2.2
–
V
VINUV
VIN rising
2.05
150
0.02
50
V
VINUV(hys)
–
mV
ꢀA
ꢀA
mA
ꢀA
Shutdown (CHARGE = 0 V, TRIG = 0 V)
Charging complete
–
0.5
100
–
VIN Supply Current
IIN
–
Charging (CHARGE = VIN, TRIG = 0 V)
Shutdown (CHARGE = 0 V, TRIG = 0 V)
–
2
–
0.01
1
VBAT Pin Supply Current
Charging done (CHARGE = VIN
¯¯¯¯¯¯¯¯
DONE = 0 V)
,
IBAT
–
–
–
–
5
ꢀA
ꢀA
Charging (CHARGE = VIN, TRIG = 0 V)
50
Current Limit
Primary-Side Current Limit2
Switch On-Resistance
Switch Leakage Current1
CHARGE Pull-down Resistance
ISWLIM
RSWDS(on)
ISWLK
1.35
–
1.5
0.4
–
1.65
A
ꢁ
VIN_DRV = 3.6 V, ID = 600 mA, TA = 25°C
VSW = 5.5, over full temperature range
–
2
–
–
–
ꢀA
kꢁ
V
RCHGPD
–
130
–
High, over input supply range
Low, over input supply range
1.3
CHARGE Input Voltage1
CHARGE On/Off Delay
VCHARGE
–
–
–
0.5
–
V
Time between CHARGE = 1 and charging
enabled
tCH
20
us
Switch-Off Timeout
toff(max)
ton(max)
–
–
18
18
–
–
ꢀs
ꢀs
V
Switch-On Timeout
Output Comparator Trip Voltage3
VOUTTRIP
VOUTOV
IDONELK
Measured as VSW – VBAT
31.0
–
31.5
200
–
32.0
400
1
Output Comparator Voltage Overdrive
Pulse width = 200 ns (90% to 90%)
mV
μA
1
¯¯¯¯¯¯¯¯
DONE Output Leakage Current
–
1
¯¯¯¯¯¯¯¯
¯¯¯¯¯¯¯¯
DONE Output Low Voltage
VDONEL
dV/dt
32 ꢀA into DONE pin
–
–
–
100
–
mV
dV/dt Threshold for ZVS Comparator
Measured at SW pin
20
V/μs
IGBT Driver
VTRIG(H)
VTRIG(L)
Input = logic high, over input supply range
Input = logic low, over input supply range
1.3
–
–
–
–
0.5
–
V
V
TRIG Input Voltage1
TRIG Pull-Down Resistor
GATE Resistance to VIN_DRV
GATE Resistance to GND
RTRIGPD
–
130
6.6
50
kꢁ
ꢁ
RSrcDS(on)
RSnkDS(on)
VGATE = 1.8 V
VGATE = 1.8 V
–
–
–
–
ꢁ
¯¯¯¯¯¯¯¯
Measurement taken at DONE pin,
CL= 6500 pF
Propagation Delay (Rising)4,5
tDr
–
25
–
ns
Propagation Delay (Falling)4,5
Output Rise Time4,5
tDf
–
–
–
–
60
80
–
–
–
–
ns
ns
ns
kꢁ
tr
tf
Output Fall Time4,5
700
20
GATE Pull-Down Resistor
RGTPD
1Specifications throughout the range TA = –40°C to 85°C guaranteed by design and characterization.
2Current limit guaranteed by design and correlation to static test.
3Specifications throughout the range TA = –20°C to 85°C guaranteed by design and characterization.
4Guaranteed by design and characterization.
5See IGBT Drive Timing Definition diagram for further information.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
4
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
IGBT Drive Timing Definition
50%
50%
TRIG
t
t
r
t
Df
t
f
Dr
90%
90%
GATE
10%
10%
Operation Timing Diagram
VBAT
UVLO
V
IN
CHARGE
SW
Target V
OUT
V
OUT
DONE
T2
T3
T1
TRIG
GATE
A
B
C
D
E
F
Explanation of Events
A: Start charging by pulling CHARGE to high, provided that V is above UVLO level.
IN
B: Charging stops when V
reaches the target voltage.
OUT
C: Start a new charging process with a low-to-high transition at the CHARGE pin.
D: Pull CHARGE to low to put the controller in low-power standby mode.
E: Charging does not start, because V is below UVLO level when CHARGE goes high.
IN
F: After V goes above UVLO, another low-to-high transition at the CHARGE pin is required to
IN
start the charging.
T1, T2, T3 (Trigger instances): IGBT driver output pulled high whenever the TRIG pin is at logic
high. It is recommended to avoid applying any trigger pulses during charging.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
5
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Characteristic Performance
IGBT Drive Performance
IGBT drive waveforms are measured at pin, with capacitive load of 6800 pF
tr
Rising Signal
VIN
Symbol
Parameter Units/Division
C1
C2
C3
t
VTRIGGER
VGATE
VIN
1 V
1 V
1 V
20 ns
Value
21 ns
85 ns
6.8 nF
time
VGATE
Conditions Parameter
tDr
tr
CLOAD
C2,C3
VTRIGGER
C1
t
tf
Falling Signal
VIN
Symbol
Parameter Units/Division
C1
C2
C3
t
VTRIGGER
VGATE
VIN
1 V
1 V
1 V
200 ns
Value
time
Conditions Parameter
VGATE
tDf
tf
CLOAD
80 ns
765 ns
6.8 nF
C2,C3
VTRIGGER
C1
t
Allegro MicroSystems, Inc.
115 Northeast Cutoff
6
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Characteristic Performance
Charge Time versus Battery Voltage
Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, COUT = 100 μF / 330 V UCC, at room temperature
16
14
12
10
8
6
4
2
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Battery Voltage (V)
Efficiency versus Battery Voltage
Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature
85%
80%
75%
70%
65%
60%
55%
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Allegro MicroSystems, Inc.
115 Northeast Cutoff
7
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Final Output Voltage versus Battery Voltage
Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature
328
327
326
325
324
323
322
321
320
319
318
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Battery Voltage (V)
Average Input Current versus Battery Voltage
Transformer LPRIMARY = 12.8 μH, N =10.25, VIN =3.6 V, at room temperature
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
Battery Voltage (V)
Note: Peak switch current is limited by the maximum on-time and di/dt of the transformer
primary current; therefore, average input current drops at very low battery voltage.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
8
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Charging Waveforms
Output Capacitor Charging at Various Battery Voltages
Test conditions: VIN = 3.6 V, COUT = 100 μF / 330 V UCC, transformer = T-16-024A (LPRIMARY =12.8 μH, N = 10.25), at room temperature
¯¯¯¯¯¯¯¯
Oscilloscope settings: Ch1 = DONE (5 V / div), Ch2 = Battery Voltage (1 V / div), Ch3 = Output Voltage (50 V / div), Ch4 = Input Current (200 mA V / div),
Time scale = 1 sec / div
VOUT
VBAT = 2.5 V
VBAT
IIN
C2,C3,C4
VDONE
C1
t
VOUT
VBAT
VBAT = 3.7 V
IIN
C2,C3,C4
VDONE
C1
t
VOUT
VBAT
VBAT = 5.0 V
IIN
C2,C3,C4
VDONE
C1
t
Allegro MicroSystems, Inc.
115 Northeast Cutoff
9
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Functional Description
General Operation Overview
Timer Mode and Fast Charging Mode
The A8740 achieves fast charging times and high efficiency by
operating in discontinuous conduction mode (DCM) through
most of the charging process. The relationship of Timer mode and
Fast Charging mode is shown in figure 2.
The charging operation is started by a low-to-high signal on the
CHARGE pin, provided that VIN is above the VUVLO level. It is
strongly recommended to keep the CHARGE pin at logic low
during power-up. After VIN exceeds the UVLO level, a low-
to-high transition on the CHARGE pin is required to start the
The IC operates in Timer mode when beginning to charge a com-
pletely discharged photoflash capacitor, usually when the output
voltage, VOUT, is less than approximately 30 V (depending on
transformer used). Timer mode is a fixed period, 18 μs, off-time
control. One advantage of having Timer mode is that it limits the
initial battery current surge and thus acts as a “soft-start.” A time-
expanded view of a Timer mode interval is shown in figure 3.
¯¯
¯
¯¯
¯
¯¯¯¯
charging. The DONE open-drain indicator is pulled low when
CHARGE is high and target output voltage is reached.
When a charging cycle is initiated, the transformer primary side
current, IPRIMARY, ramps-up linearly at a rate determined by the
combined effect of the battery voltage, VBAT, and the primary
side inductance, LPRIMARY. When IPRIMARY reaches the current
limit, ISWLIM , the internal MOSFET is turned off immediately,
allowing the energy to be pushed into the photoflash capacitor,
COUT, from the secondary winding. The secondary side current
drops linearly as COUT charges. The switching cycle starts again,
either after the transformer flux is reset, or after a predetermined
time period, tOFF(max) (18 μs), whichever occurs first.
VOUT
The A8740 senses output voltage indirectly on primary side. This
eliminates the need for high voltage feedback resistors required
for secondary sensing. Flyback converter stops switching when
output voltage reaches:
IIN
VOUT = K × N – Vd ,
Figure 2. Timer mode and Fast Charging mode: t = 1 s/div;
VOUT = 50 V/div; IIN = 150 mA/div., VIN = VBAT = 3.6 V;
COUT = 100 ꢀF/330 V; and ILIM = 1.0 A.
Where:
K = 31.5 V typically,
Vd is the forward drop of the output diode (approximately 2 V),
and
N is transformer turns ratio.
Switch On-Time and Off-Time Control
The A8740 implements an adaptive on-time/off-time control. On-
time duration, ton , is approximately equal to
ISW
C4
VSW
ton = ISWlim × LPRIMARY / VBAT
.
VBAT
Off-time duration, toff , depends on the operating conditions
during switch off-time. The A8740 applies two charging modes:
Fast Charging mode and Timer mode, according to the conditions
described in the next section.
C2,C3
VOUT
C1
Figure 3. Expanded view of Timer mode: VOUT ≤ 10 V, VBAT = 5.5 V,
Ch1: VOUT = 20 V/div., Ch2: VBAT = 5 V/div., Ch3: VSW = 5 V/div.,
Ch4: ISW = 750 mA/div., t = 5 ꢀs / div.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
10
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
As soon as a sufficient voltage has built up at the output capaci-
tor, the IC enters Fast-Charging mode. In this mode, the next
switching cycle starts after the secondary side current has stopped
flowing, and the switch voltage has dropped to a minimum value.
A proprietary circuit is used to allow minimum-voltage switch-
Fast-Charging mode to start earlier, thereby reducing the overall
charging time. Minimum-voltage switching is shown in figure 4.
During Fast-Charging mode, when VOUT is high enough (over
50 V), true zero-voltage switching (ZVS) is achieved. This
further improves efficiency as well as reduces switching noise. A
ing, even if the SW pin voltage does not drop to 0 V. This enables ZVS interval is shown in figure 5.
ISW
ISW
C4
C4
VSW
VSW
VBAT
VBAT
C2,C3
C1
C2,C3
C1
VOUT
VOUT
Figure 4. Minimum-voltage switching: VOUT ≥ 35 V, VBAT = 5.5 V,
Ch1: VOUT = 20 V/div., Ch2: VBAT = 5 V/div., Ch3: VSW = 5 V/div.,
Ch4: ISW = 750 mA/div., t = 1 ꢀs / div.
Figure 5. True zero-voltage switching (ZVS): VOUT = 75 V, VBAT = 5.5 V,
Ch1: VOUT = 20 V/div., Ch2: VBAT = 5 V/div., Ch3: VSW = 5 V/div.,
Ch4: ISW = 750 mA/div., t = 0.5 ꢀs / div.
Allegro MicroSystems, Inc.
115 Northeast Cutoff
11
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Applications Information
The minimum pulse width for toff determines what is the mini-
Transformer Design
1. The transformer turns ratio, N, determines the output voltage:
mum LPRIMARY required for the transformer. For example, if
ILIM = 1.5 A, N = 10, and VOUT = 315 V, then LPRIMARY must
be at least 4.2 μH in order to keep toff at 200 ns or longer. These
relationships are illustrated in figure 6.
N = NS / NP
VOUT = 31.5 × N – Vd ,
where 31.5 is the typical value of VOUTTRIP, and Vd is the for-
ward drop of the output diode.
In general, choosing a transformer with a larger LPRIMARY results
in higher efficiency (because a larger LPRIMARY corresponds to
a lower switch frequency and hence lower switching loss). But
transformers with a larger LPRIMARY also require more windings
and larger magnetic cores. Therefore, a trade-off must be made
between transformer size and efficiency.
2. The primary inductance, LPRIMARY, determines the on-time of
the switch:
ton = (–LPRIMARY/R)×ln(1 – ISWlim × R/V ) ,
IN
where R is the total resistance in the primary current path (includ-
ing RSWDS(on) and the DC resistance of the transformer).
Leakage Inductance and Secondary Capacitance
The transformer design should minimize the leakage induc-
tance to ensure the turn-off voltage spike at the SW node does
not exceed the absolute maximum specification on the SW pin
(refer to the Absolute Maximum Ratings table). An achievable
minimum leakage inductance for this application, however, is
usually compromised by an increase in parasitic capacitance.
Furthermore, the transformer secondary capacitance should be
minimized. Any secondary capacitance is multiplied by N2 when
reflected to the primary, leading to high initial current swings
when the switch turns on, and to reduced efficiency.
If VIN is much larger than ISWlim ×R, then ton can be approxi-
mated by:
ton = ISWlim ×LPRIMARY /VIN .
3. The secondary inductance, LSECONDARY, determines the off-
time of the switch. Given:
LSECONDARY/LPRIMARY = N×N , then
toff = (ISWlim /N)×LSECONDARY/VOUT
= (ISWlim ×LPRIMARY×N)/VOUT
.
toff
ton
VSW
ISW
V
r
tf
V
V
IN
IN
VSW
ISW
tneg
Figure 6. Transformer Selection Relationships
Allegro MicroSystems, Inc.
115 Northeast Cutoff
12
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Effects of Input Filters
Input Capacitor Selection
VOUT
Ceramic capacitors with X5R or X7R dielectrics are recom-
mended for the input capacitor, CIN. During initial Timer mode
the device operates with 18 ꢀs off-time. The resonant period
caused by input filter inductor and capacitor should be at least
2 times greater or smaller than the 18 ꢀs Timer period, to reduce
input ripple current during this period. The typical input LC filter
is shown in figure 7.
VBAT
C2
C3
IBAT
C1
The resonant period is given by:
T
res = 2 ꢁ (L × CIN)1/2
.
Figure 8. Input current waveforms with Li+ battery connected by
5-in. wire and decoupled by 4.7 ꢀF capacitor, COUT = 100 μF,
VIN = VBAT = 3.6 V, Ch1: VOUT = 50 V/div, Ch2: VBAT = 2 V/div,
Ch3: IBAT = 750 mA/div, t = 1 s/div
The effects of input filter components are shown in figures 8, 9,
and 10. It is recommended to use at least 10 μF / 6.3 V to decou-
ple the battery input, VBAT , at the primary of the transformer.
Decouple the VIN pin using 0.1 μF / 6.3 V bypass
capacitor.
VOUT
VBAT
Output Diode Selection
C2
C3
Choose rectifying diodes, D1, to have small parasitic capacitance
(short reverse recovery time) while satisfying the reverse voltage
and forward current requirements. The peak reverse voltage of
the diodes, VDPeak , occurs when the internal MOSFET switch is
closed. It can be calculated as:
IBAT
C1
VDPeak = VOUT + N × VBAT
.
Figure 9. Input current waveforms with Li+ battery connected through
4.7 ꢀH inductor and 4.7 ꢀF capacitor, COUT = 100 μF, VIN = VBAT = 3.6 V,
Ch1: VOUT = 50 V/div, Ch2: VBAT = 2 V/div, Ch3: IBAT = 300 mA/div,
t = 1 s/div
The peak current of the rectifying diode, IDPeak, is calculated as:
IDPeak = IPRIMARY_Peak / N .
VOUT
L
VBAT
IN
C2
IBAT
+
A8740
C3
V
C
BAT
IN
C1
Figure 10. Input current waveforms with Li+ battery connected through
4.7 ꢀH inductor and 10 ꢀF capacitor, COUT = 100 μF, VIN = VBAT = 3.6 V,
Ch1: VOUT = 50 V/div, Ch2: VBAT = 2 V/div, Ch3: IBAT = 300 mA/div,
t = 1 s/div
Figure 7. Typical input section with input inductance (inductance, LIN, may
be an input filter inductor or inductance due to long wires in test setup)
Allegro MicroSystems, Inc.
115 Northeast Cutoff
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Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Layout Guidelines
Key to a good layout for the photoflash capacitor charger circuit
is to keep the parasitics minimized on the power switch loop
(transformer primary side) and the rectifier loop (secondary side).
Use short, thick traces for connections to the transformer primary
breakdown failure of the circuit board.
Avoid placing any ground plane area underneath the transformer
secondary and diode, to minimize parasitic capacitance.
¯¯
¯
¯¯
¯
¯¯¯¯
and SW pin. It is important that the DONE signal trace and other
signal traces be routed away from the transformer and other
switching traces, in order to minimize noise pickup. In addition,
high voltage isolation rules must be followed carefully to avoid
Connect the EE package PAD to the ground pad for better ther-
mal performance. Use ground planes on the top and bottom layers
below the IC and connect them through multiple thermal vias.
Refer to the figures on page 18 for recommended layout.
Recommended Components
Component
C1, Input Capacitor
C2
Rating
Part Number
Source
Taiyo Yuden
10 ꢀF, ±10%, 6.3 V, X5R ceramic
capacitor (0805)
JMK212BJ106K
0.1 μF, 6.3 V X5R ceramic capacitor
COUT, Photoflash
Capacitor
100 ꢀF / 330 V
EPH-31ELL101B131S Chemi-Con
Philips Semiconductor,
Fairchild Semiconductor
D1, Output Diode
2 x 250 V, 225 mA, 5 pF
BAV23S
LPRIMARY = 12.8 μH, N= 10.25,
6.5 × 8 × 4 mm
T-16-024A
Tokyo Coil Electric
TDK
T1, Transformer
LPRIMARY = 6 μH, N= 10.4,
5.6 × 5.6 × 3 mm
LDT565630T-001
Allegro MicroSystems, Inc.
115 Northeast Cutoff
14
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Recommended Layout
VBAT
VOUT
D1
COUT
100 μF
T1
6
7
VBAT
5
VIN_DRV
SW
Schematic
RG
12 ꢁ
R10
2 kꢁ
A8740
C2
10 μF
3
2
1
8
GATE
TRIG
DONE
C4
0.1 μF
CHARGE
C5
1 nF
GND
4
C6
1 nF
Top side
Bottom side
Top components
Allegro MicroSystems, Inc.
115 Northeast Cutoff
15
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Package EE
8-Contact DFN with Exposed Thermal Pad
0.30
0.50
8
2.00 ±0.15
8
0.83
2.00 ±0.15
0.90
2.13
A
1
2
1
1.60
D
C
9X
SEATING
PLANE
0.08
C
C
PCB Layout Reference View
+0.05
–0.04
0.25 ±0.05
0.55
0.50 BSC
1
2
All dimensions nominal, not for tooling use
(reference JEDEC MO-229UCCD)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown
0.325 ±0.050
A
B
Terminal #1 mark area
0.90
Exposed thermal pad (reference only, terminal #1
identifier appearance at supplier discretion)
B
C
Reference land pattern layout (reference IPC7351
SON50P200X200X100-9M);
All pads a minimum of 0.20 mm from all adjacent pads; adjust as
necessary to meet application process requirements and PCB layout
tolerances; when mounting on a multilayer PCB, thermal vias at the
exposed thermal pad land can improve thermal dissipation (reference
EIA/JEDEC Standard JESD51-5)
8
1.60
D
Coplanarity includes exposed thermal pad and terminals
Allegro MicroSystems, Inc.
115 Northeast Cutoff
16
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
Ultra Small Mobile Phone Xenon Photoflash
Capacitor Charger with IGBT Driver
A8740
Copyright ©2011, Allegro MicroSystems, Inc.
Allegro MicroSystems, Inc. reserves the right to make, from time to time, such departures from the detail specifications as may be required to per-
mit improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in life support devices or systems, if a failure of an Allegro product can reasonably be expected to cause the
failure of that life support device or system, or to affect the safety or effectiveness of that device or system.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems, Inc. assumes no responsibility for its use;
nor for any infringement of patents or other rights of third parties which may result from its use.
For the latest version of this document, visit our website:
www.allegromicro.com
Allegro MicroSystems, Inc.
115 Northeast Cutoff
17
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
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