AD768ARCHIPS [ADI]
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| 型号： | AD768ARCHIPS |
| 厂家： | 
ADI |
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16-Bit, 30 MSPS
D/A Converter
a
AD768
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
30 MSPS Update Rate
16-Bit Resolution
Linearity: 1/ 2 LSB DNL @ 14 Bits
1 LSB INL @ 14 Bits
Fast Settling: 25 ns Full-Scale Settling to 0.025%
SFDR @ 1 MHz Output: 86 dBc
THD @ 1 MHz Output: 71 dBc
Low Glitch Im pulse: 35 pV-s
Pow er Dissipation: 465 m W
On-Chip 2.5 V Reference
V
DD
DCOM
(MSB)
DB15
AD768
MSBs: SEGMENTED
CURRENT SOURCES
AND SWITCHES
MSB
DECODER
AND
EDGE-
TRIGGERED
BIT
LSBs:
IOUTA
IOUTB
CURRENT SOURCES,
SWITCHES, AND
1kΩ R-2R
1k
1k
LADDERS
LATCHES
LADCOM
Edge-Triggered Latches
Multiplying Reference Capability
2.5V
BANDGAP
REFERENCE
CONTROL
AMP
V
EE
DB0
APPLICATIONS
(LSB)
Arbitrary Waveform Generation
Com m unications Waveform Reconstruction
Vector Stroke Display
NR
CLOCK
IREFIN
NC REFCOM REFOUT
P RO D UCT D ESCRIP TIO N
P RO D UCT H IGH LIGH TS
T he AD768 is a 16-bit, high speed digital-to-analog converter
(DAC) that offers exceptional ac and dc performance. T he
AD768 is manufactured on ADI’s Advanced Bipolar CMOS
(ABCMOS) process, combining the speed of bipolar transistors,
the accuracy of laser-trimmable thin film resistors, and the effi-
ciency of CMOS logic. A segmented current source architecture
is combined with a proprietary switching technique to reduce
glitch energy and maximize dynamic accuracy. Edge triggered
input latches and a temperature compensated bandgap reference
have been integrated to provide a complete monolithic DAC
solution.
1. T he low glitch and fast settling time provide outstanding
dynamic performance for waveform reconstruction or digital
synthesis requirements, including communications.
2. T he excellent dc accuracy of the AD768 makes it suitable for
high speed A/D conversion applications.
3. On-chip, edge-triggered input CMOS latches interface
readily to CMOS logic families. T he AD768 can support up-
date rates up to 40 MSPS.
4. A temperature compensated, 2.5 V bandgap reference is
included on-chip allowing for generation of the reference
input current with the use of a single external resistor. An ex-
ternal reference may also be used.
T he AD768 is a current-output DAC with a nominal full-scale
output current of 20 mA and a 1 kΩ output impedance. Differ-
ential current outputs are provided to support single-ended
or differential applications. T he current outputs may be tied
directly to an output resistor to provide a voltage output, or fed
to the summing junction of a high speed amplifier to provide a
buffered voltage output. Also, the differential outputs may be
interfaced to a transformer or differential amplifier.
5. T he current output(s) of the AD768 may be used singly or
differentially, either into a load resistor, external op amp
summing junction or transformer.
6. Proper selection of an external resistor and compensation
capacitor allow the performance-conscious user to optimize
the AD768 reference level and bandwidth for the target
application.
T he on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. T he AD768 can be driven by
the on-chip reference or by a variety of external reference volt-
ages based on the selection of an external resistor. An external
capacitor allows the user to optimally trade off reference band-
width and noise performance.
T he AD768 operates on ±5 V supplies, typically consuming
465 mW of power. T he AD768 is available in a 28-pin SOIC
package and is specified for operation over the industrial tem-
perature range.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
(T to TMAX , V = +5.0 V, V = –5.0 V, LADCOM, REFCOM, DCOM = 0 V, IREFIN = 5 mA,
MIN
DD
EE
CLOCK = 10 MHz, unless otherwise noted)
AD768–SPECIFICATIONS
P aram eter
Min
Typ
Max
Units
RESOLUT ION
16
Bits
DC ACCURACY1
Linearity Error
TA = +25°C
TMIN to TMAX
Differential Nonlinearity
–8
–8
±4
±2
+8
+8
LSB
LSB
TA = +25°C
TMIN to TMAX
–6
–8
+6
+8
LSB
LSB
Monotonicity (13-Bit)
GUARANT EED OVER RAT ED SPECIFICAT ION T EMPERAT URE RANGE
ANALOG OUT PUT
Offset Error
–0.2
–1.0
+0.2
+1.0
% of FSR
% of FSR
mA
V
kΩ
pF
Gain Error
Full-Scale Output Current2
Output Compliance Range
Output Resistance
Output Capacitance
20
–1.2
0.8
+5.0
1.2
1.0
3
REFERENCE OUT PUT
Reference Voltage
2.475
1
2.5
+5.0
2.525
+15
V
mA
Reference Output Current3
REFERENCE INPUT
Reference Input Current
5
7
mA
Reference Bandwidth4
Small Signal, IREF = 5 mA ± 0.1 mA
Large Signal, IREF = 4 mA ± 2 mA
28
9
MHz
MHz
T EMPERAT URE COEFFICIENT S
Unipolar Offset Drift
Gain Drift5
–5
+5
ppm of FSR/oC
ppm of FSR/oC
ppm of FSR/oC
ppm/oC
–20
–40
–30
+20
+40
+30
Gain Drift6
Reference Voltage Drift
DYNAMIC PERFORMANCE7
Maximum Output Update Rate
Output Settling T ime (tST) (to 0.025%)
30
40
25
10
35
5
5
3
MSPS
ns
ns
pV-s
ns
ns
nV/√Hz
%
Degree
35
Output Propagation Delay (tPD
Glitch Impulse
)
Output Rise T ime (10% to 90%)
Output Fall T ime (10% to 90%)
Output Noise (DB0–DB15 High, into 50 Ω)
Differential Gain Error
0.01
0.01
Differential Phase Error
DIGIT AL INPUT S
Logic “1” Voltage
Logic “0” Voltage
Logic “1” Current
Logic “0” Current
Input Capacitance
Input Setup T ime (tS)
Input Hold T ime (tH)
3.5
V
V
1.5
+10
+10
–10
–10
µA
µA
pF
ns
ns
ns
10
10
5
10
Latch Pulse Width (tLPW
)
AC LINEARIT Y7
Spurious-Free Dynamic Range (SFDR Within a Window)
FOUT = 1.002 MHz; CLOCK = 10 MHz; 2 MHz Span
FOUT = 1.002 MHz; CLOCK = 20 MHz; 2 MHz Span
FOUT = 5.002 MHz; CLOCK = 30 MHz; 10 MHz Span
Spurious-Free Dynamic Range (SFDR to Nyquist)
FOUT = 1.002 MHz; CLOCK = 10 MHz
86
85
78
79
dB
dB
dB
74
73
67
70
dB
dB
dB
FOUT = 1.002 MHz; CLOCK = 20 MHz
FOUT = 5.002 MHz; CLOCK = 30 MHz
T otal Harmonic Distortion (T HD)
FOUT = 1.002 MHz; CLOCK = 10 MHz
FOUT = 1.002 MHz; CLOCK = 20 MHz
FOUT = 5.002 MHz; CLOCK = 30 MHz
–71
–66
–61
–68
dB
dB
dB
–2–
REV. B
AD768
P aram eter
Min
Typ
Max
Units
POWER SUPPLY
Positive Voltage Range
4.75
–5.25
5
5.25
–4.75
40
73
600
+0.2
V
V
mA
mA
mW
Negative Voltage Range
Positive Supply Current
Negative Supply Current
Nominal Power Dissipation
Power Supply Rejection Ratio (PSRR)
–5
30
63
465
–0.2
–40
% of FSR/V
OPERAT ING RANGE
+85
°C
NOT ES
1Measured at IOUT A, driving a virtual ground.
2Nominal FS output current is 4× the current at IREFIN. T herefore, nominal FS current is 20 mA when IREFIN = 5 mA.
3Output current is defined as total current available for IREFIN and any external load.
4Reference bandwidth is a function of external cap at NR pin. Refer to compensation section of data sheet for details.
5Excludes internal reference drift.
6Includes internal reference drift.
7Measured as unbuffered voltage output (1 V range) with FS current into 50 Ω load at IOUT B.
Specifications subject to change without notice.
ABSO LUTE MAXIMUM RATINGS*
P aram eter
with Respect to
Min Max
Units
Positive Supply Voltage (VDD
Negative Supply Voltage (VEE
)
)
DCOM, REFCOM, LADCOM –0.5 +6.0
DCOM, REFCOM, LADCOM –6.0 +0.5
V
V
Analog-to-Other Grounds (REFCOM) DCOM, LADCOM
–0.5 +0.5
–0.5 +0.5
V
V
V
Digital-to-Other Grounds (DCOM)
Reference Output (REFOUT )
LADCOM, REFCOM
REFCOM
VDD + 0.5
Reference Input Current (IREFIN)
Digital Inputs (DB0–DB15, CLOCK) DCOM
Analog Outputs (IOUT A, IOUT B)
Maximum Junction T emperature
Storage T emperature
+7.5
–0.5 VDD + 0.5
–2.0 +5.0
+150
mA
V
V
°C
°C
°C
LADCOM
–65
+150
+300
Lead T emperature
*Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. T his is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating for extended periods may affect device
reliability.
DB0–DB15
O RD ERING GUID E
tS
tH
P ackage
O ption
CLOCK
Model
P ackage D escription
tLPW
tPD
AD768AR
AD768ACHIPS
AD768-EB
28-Pin 300 mil SOIC
Die
AD768 Evaluation Board
R-28
tST
0.025%
IOUTA
OR
IOUTB
0.025%
Tim ing Diagram
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD768 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD768
1
(T = +25؇C, V = +5.0 V, V = –5.0 V, IREFIN = 5 mA, unless otherwise noted)
WAFER TEST LIMITS
A
DD
EE
P aram eter
AD 768ACH IP S Lim it
Units
Integral Nonlinearity2
Differential Nonlinearity2
Offset Error
±8
±6
±0.2
±1.0
±1.0
40
LSB max
LSB max
% FSR max
% FSR max
% of nom. 2.5 V max
mA max
Gain Error
Reference Voltage
Positive Supply Current
Negative Supply Current
Power Dissipation
73
600
mA max
mW max
NOT ES
1Electrical test are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal
yield loss, yield after packaging is not guaranteed for standard product dice.
2Limits extrapolated from testing of individual bit errors.
3Die offers latch control pad. Edge triggered latches become level triggered when latch control and clock pads are high.
4Die substrate is connected to VEE.
P IN D ESCRIP TIO NS
P in No.
Sym bol
Type
Nam e and Function
1
2
3
4
5
6
7
IOUT A
NR
REFOUT
NC
REFCOM
IREFIN
DB0
DB1–DB7
DCOM
CLOCK
DB8–DB14
DB15
AO
AI
AO
NC
P
AI
DI
DI
P
DI
DI
DI
P
DAC Current Output. Full-scale current when all data bits are 1s.
Noise Reduction Node. Add capacitor for noise reduction.
Reference Output Voltage. Nominal value is 2.5 V.
No Connect. Reserved for internal use.
Reference Ground.
Reference Input Current. Nominal is 5 mA. DAC full-scale is 4× this current.
Data Bit 0 (LSB).
Data Bits 1–7.
8–14
15
16
17–23
24
25
26
27
28
Digital Ground.
Clock Input. Data latched on positive edge of clock.
Data Bits 8–14.
Data Bit 15 (MSB).
VDD
VEE
IOUT B
LADCOM
Positive Supply Voltage. Nominal is +5 V.
Negative Supply Voltage. Nominal is –5 V.
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
DAC Ladder Common.
P
AO
P
T ype: AI = Analog Input; DI = Digital Input; AO = Analog Output; P = Power.
D ICE CH ARACTERISTICS3, 4
P IN CO NFIGURATIO N
V
V
DD
DB15
DB14 DB13 DB12 DB11 DB10
DD
LADCOM
IOUTB
IOUTA
NR
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DB9
DB8
V
V
EE
REFOUT
NC
3
V
V
(–5V)
(+5V)
EE
EE
4
DD
REFCOM
IREFIN
(LSB) DB0
DB15 (MSB)
5
IOUTB
CLOCK
6
DB14
DB13
DB12
AD768
TOP VIEW
(Not to Scale)
LATCH CONTROL
DCOM
7
LADCOM
IOUTA
8
DB1
DB2
DB3
9
DB11
DB10
DB9
DB7
DB6
DB5
NR
10
11
12
13
14
DB4
DB5
DB6
DB7
REFOUT
DB8
NC
CLOCK
DCOM
REFCOM IREFIN
DB0
DB1
DB2
DB3 DB4
NC = NO CONNECT
Die Size:
0.1106 × 0.1417 inch, 15,672 sq. m ils
(2.81 × 3.60 m m , 10.116 sq. m m )
–4–
REV. B
AD768
D EFINITIO NS O F SP ECIFICATIO NS
Tem per atur e D r ift
Linear ity Er r or (Also Called Integr al Nonlinear ity or INL)
Linearity error is defined as the maximum deviation of the ac-
tual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
T emperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either TMIN or TMAX. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is re-
ported in ppm per degree C.
D iffer ential Nonlinear ity (or D NL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input code.
P ower Supply Rejection
T he maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Settling Tim e
T he time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
O ffset Er r or
T he deviation of the output current from the ideal of zero is
called offset error. For IOUT A, 0 mA output is expected when
the inputs are all 0s. For IOUT B, 0 mA output is expected
when all inputs are set to 1s.
Spur ious-Fr ee D ynam ic Range
T he difference, in dB, between the rms amplitude of the
input signal and the peak spurious signal over the specified
bandwidth.
Gain Er r or
T he difference between the actual and ideal output span. T he
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s. T he ideal
output current span is 4× the current applied to the IREFIN pin.
Total H ar m onic D istor tion
T HD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal. It is ex-
pressed as a percentage or in decibels (dB).
O utput Com pliance Range
T he range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Glitch Im pulse
Asymmetrical switching times in a DAC give rise to undesired
output transients which are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-sec.
C
REFCOMP
R
500Ω
REF
1µF
4
3
6
NC
REFOUT
REFIN
IOUTA
V
1
IOUTA
DD
+2.5V REF
25
+5V
5mA
IOUTB
27
IOUTB
LOAD
1µF
1µF
REFCOM
NR
R
R
1kΩ
5
2
LAD
1kΩ
R
LAD
50Ω
1µF
50Ω
LADCOM
28
C
V
NR
EE
26
15
–5V
SEGMENTED
CURRENT
SOURCES
DCOM
AD768
CURRENT SOURCES
AND R-2R LADDER
CLOCK
MSB DECODE
& LATCHES
CLOCK
16
LATCHES – LOWER 12 BITS
24
23
22
21
20
19 18
17
14
13 12
11 10
9
8
7
Figure 1. Functional Block Diagram and Basic Hookup
FUNCTIO NAL D ESCRIP TIO N
T he digital interface offers CMOS compatible edge-triggered
input latches that interface readily to CMOS logic and supports
clock rates up to 40 MSPS. A temperature compensated 2.5 V
bandgap reference is integrated on-chip to drive the AD768 ref-
erence input current with the use of a single external resistor.
T he functional block diagram in Figure 1 is a simple representa-
tion of the internal circuitry to aid the understanding of the
AD768’s operation. T he DAC transfer function is described,
and followed by a detailed description of each key portion of the
circuit. T ypical circuit configurations are shown in the section
APPLYING T HE AD768.
T he AD768 is a current-output DAC with a nominal full-scale
current of 20 mA and a 1 kΩ output impedance. Differential
outputs are provided to support single-ended or differential
applications. T he DAC architecture combines segmented cur-
rent sources for the top four bits (MSBs) and a 1 kΩ R-2R lad-
der for the lower 12 bits (LSBs). T he DAC current sources are
implemented with laser-trimmable thin film resistors for excel-
lent dc linearity. A proprietary switching technique is utilized to
reduce glitch energy and maximize dynamic accuracy.
REV. B
–5–
AD768
D AC TRANSFER FUNCTIO N
550
500
450
400
350
300
T he AD768 may be used in either current-output mode with the
output connected to a virtual ground, or voltage-output mode
with the output connected to a resistive load.
In current output mode,
IOUT = (DAC CODE/65536) × (IREFIN × 4)
In voltage output mode,
VOUT = IOUT × RLOADʈRLAD
where:
DAC CODE is the decimal representation of the DAC inputs;
an integer between 0 and 65535.
IREFIN is the current applied at the IREFIN pin, determined by
1.0
2.0
3.0
4.0
– mA
5.0
6.0
7.0
VREF/RREF
.
I
REFIN
Substituting for IOUT and IREFIN
,
Figure 3. Power Dissipation vs. IREFIN Current
VOUT = –VREF × (DAC CODE/65536) × 4 × [(RLOADʈRLAD)/RREF
]
Note the AD768 is optimized for operation at an input current
of 5 mA. Both linearity and dynamic performance at other input
currents may be somewhat degraded. Figure 4 shows typical dc
linearity over a range of input currents. Figure 5 shows typical
SFDR (to Nyquist) performance over a range of input currents
and CLOCK input rates for a 1 MHz output frequency.
T hese equations clarify an important aspect of the AD768
transfer function; the full-scale current output of the DAC is
proportional to a current input. T he voltage output is then a
function of the ratio of (RLOADʈRLAD)/RREF, allowing for cancel-
lation of resistor drift by selection of resistors with matched
characteristics.
10
9
REFERENCE INP UT
T he IREFIN pin is a current input node with low impedance to
REFCOM. T his input current sets the magnitude of the DAC
current sources such that the full-scale output current is exactly
four times the current applied at IREFIN. For the nominal in-
put current of 5 mA, the nominal full-scale output current is
20 mA.
8
7
6
5
INL
T he 5 mA reference input current can be generated from the
on-chip 2.5 V reference with an external resistor of 500 Ω from
REFOUT to IREFIN. If desired, a variety of external reference
voltages may be used based on the selection of an appropriate
resistor. However, to maintain stability of the reference ampli-
fier, the external impedance at IREFIN must be kept below
1 kΩ.
4
3
2
DNL
1
0
1.0
2.0
3.0
4.0
– mA
5.0
6.0
7.0
I
REFIN
5
6
REFCOM
IREFIN
Figure 4. INL/DNL vs. IREFIN Current
–85
–80
–75
–70
–65
IFB
5mA
CLOCK = 10 MSPS
CLOCK = 20 MSPS
V
V
EE
EE
Figure 2. Equivalent Reference Input Circuit
T he IREFIN current can be varied from 1 mA to 7 mA which
subsequently will result in a proportional change in the DAC
full-scale. Since the operating currents within the DAC vary
with IREFIN, so does the power dissipation. Figure 3 illustrates
that relationship.
CLOCK = 30 MSPS
CLOCK = 40 MSPS
–60
–55
1.0
2.0
3.0
4.0
– mA
5.0
6.0
7.0
I
REFIN
Figure 5. SFDR (to Nyquist) vs. IREFIN @ FOUT = 1 MHz
–6–
REV. B
AD768
REFERENCE O UTP UT
100M
10M
T he internal 2.5 V bandgap reference is provided for generation
of the IREFIN current, and must be compensated externally with
a capacitor of 0.1 µF or greater from REFOUT to REFCOM. If
an external reference is used, REFOUT should be tied directly
to the positive supply voltage, VDD. T his effectively turns off the
internal reference, eliminating the need for the external capaci-
tor at REFOUT . T he reference is specified to drive a nominal
load of 5 mA with a maximum of 15 mA. Operation with a
heavier load will result in degradation of supply rejection and
reference voltage accuracy. T herefore, the reference output
should be buffered with an amplifier when additional load cur-
rent is required. A properly sized pull-up resistor can also be
used to source additional current to the load. T he resistors value
should be selected such that REFOUT will always source a
minimum of 5 mA to IREFIN and the additional load.
1M
100k
10k
1k
10p
100p
1n
10n
100n
1µ
NOISE REDUCTION CAPACITOR – F
Figure 7. External Noise Reduction Capacitor vs. –3 dB
Bandwidth
AD768
IREFIN
500Ω
6
3
T he sensitivity of the NR node requires that care be taken in
capacitor placement. T he capacitor should be located as physi-
cally close to the package pins as possible and lead lengths
should be minimized. For this purpose, the use of a chip
capacitor is recommended. For applications that do not require
high frequency modulation at IREFIN, it is recommended that
REFOUT
C
REFCOMP
1µF
5
REFCOM
a capacitor on the order of 1 µF be connected from NR to VEE
.
Figure 6. Typical Reference Hookup
TEMP ERATURE CO NSID ERATIO NS
If the reference input is purely dc, noise may be minimized with
multiple capacitors, such as 1 µF and 0.1 µF, to more effectively
filter both high and low frequency disturbances.
Note that the reference plays a key role in the overall tempera-
ture performance of the AD768. Any drift of IREFIN shows up
directly in IOUT . When the output is taken as a current, the drift
of IREFIN (which depends on both VREF and RREF) must be mini-
mized. T his can be done by using the internal temperature com-
pensated reference for VREF and a low temperature coefficient
resistor for RREF. If the output is taken as a voltage, it is a func-
tion of a resistor ratio, not an absolute resistor value. By select-
ing resistors with matched temperature coefficients for RREF
and RLOAD, the drift in the resistor values will cancel, providing
optimal drift performance.
ANALO G O UTP UTS
T he AD768 offers two analog outputs; IOUT A is trimmed for
optimal INL and DNL performance and has a full-scale output
when all bits are high. For applications that require the specified
dc accuracy, IOUT A should be used. IOUT B is the comple-
mentary output with full-scale output when all bits are low.
Both IOUT A and IOUT B provide similar dynamic perfor-
mance. Refer to Figures 8 and 9 for typical INL and DNL per-
formance curves. T he outputs can also be used differentially.
Refer to the section “Applying the AD768” for examples of vari-
ous output configurations.
REFERENCE NO ISE RED UCTIO N AND MULTIP LYING
BAND WID TH
8
6
For application flexibility and multiplying capabilities, the refer-
ence amplifier is designed to offer adjustable bandwidth that can
be reduced by connecting an external capacitor from the NR
node to the negative supply pin, VEE. T his capacitor limits the
bandwidth and acts as a filter to reduce the noise contribution
from the reference amplifier.
4
2
0
T he noise reduction capacitor, CNR, is not required for stability
and does not affect the settling time of the DAC output. With-
out this capacitor, the IREFIN bandwidth is 15 MHz allowing
high frequency modulation of the DAC full-scale range through
the reference input node. Figure 7 shows the relationship be-
tween the external noise reduction capacitor and the –3 dB
bandwidth of the reference amplifier.
–2
–4
–6
–8
0
5
10 15 20 25 30 35 40 45 50 55 60 65
DIGITAL INPUT CODE – k
Figure 8. Typical INL Perform ance
REV. B
–7–
AD768
8
6
LADCOM
28
IOUTB
27
IOUTA
1
1kΩ
1kΩ
4
3pF
3pF
2
I
I
OUT
OUT
IREFIN
x2.75
0
26
–2
–4
–6
–8
V
EE
Figure 10. Equivalent Analog Output Circuit
D IGITAL INP UTS
0
5
10 15 20 25 30 35 40 45 50 55 60 65
DIGITAL INPUT CODE – k
T he AD768 digital inputs consist of 16 data input pins and a
clock pin. T he 16-bit parallel data inputs follow standard posi-
tive binary coding, where DB15 is the most significant bit
(MSB) and DB0 is the least significant bit (LSB). IOUT A pro-
duces full-scale output current when all data bits are at logic 1.
IOUT B is the complementary output, with full-scale when all
data bits are at logic 0. T he full-scale current is split between
the two outputs as a function of the input code.
Figure 9. Typical DNL Perform ance
T he outputs have a compliance range of –1.2 V to +5.0 V with
respect to LADCOM. T he current steering output stages will
remain functional over this range. Operation beyond the maxi-
mum compliance limits may cause either output stage saturation
or breakdown, resulting in nonlinear performance. T he rated dc
and ac performance specifications are for an output voltage of
0 V to –1 V.
T he digital interface is implemented using an edge-triggered
master slave latch. T he DAC output is updated following the
rising edge of the clock, and is designed to support a clock rate
as high as 40 MSPS. T he clock can be operated at any duty
cycle that meets the specified minimum latch pulse width. T he
setup and hold times can also be varied within the clock cycle as
long as the specified minimums are met, although the location
of these transition edges may affect digital feedthrough. T he
digital inputs are CMOS compatible with logic thresholds set to
approximately half the positive supply voltage. T he small input
current requirements allow for easy interfacing to unbuffered
CMOS logic. Figure 11 shows the equivalent digital input
circuit.
T he current in LADCOM is proportional to IREFIN and has been
carefully configured to be independent of digital code when the
output is connected to a virtual ground. T his minimizes any det-
rimental effects of ladder ground resistance on linearity. For
optimal dc linearity, IOUT A should be connected directly to a
virtual ground, and IOUT B should be grounded. An example of
this configuration is provided in the section “Buffered Voltage
Output.” If IOUT A is driving a resistive load directly, then
IOUT B should be terminated with an equal impedance. T his
will ensure the current in LADCOM remains constant with digi-
tal code, and is recommended for improved dc linearity in the
unbuffered voltage output configuration.
V
CC
V
CC
As shown in Figure 10, there is an equivalent output impedance
of 1 kΩ in parallel with 3 pF at each output terminal. If the out-
put voltage deviates from the ladder common voltage, an error
current flows through this 1 kΩ impedance. T his is a linear effect
which does not change with input code, so it appears as a gain
error. With 50 Ω output termination, the resulting gain error is
approximately –5%. An example of this configuration is pro-
vided in the section Unbuffered Voltage Output.
DIGITAL
INPUT
DCOM
V
EE
Figure 11. Equivalent Digital Input Circuit
Digital input signals to the DAC should be isolated from the
analog output as much as possible. Interconnect distances to the
DAC inputs should be kept as short as possible. T ermination
resistors may improve performance if the digital lines become
too long. T o minimize digital feedthrough, the inputs should be
free from glitches and ringing, and may be further improved
with a reduction of edge speed.
–8–
REV. B
Typical Performance Curves––AD768
–0.470
–0.472
1.00
0.90
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
–0.9405
–0.9415
–0.9424
–0.9433
–0.9443
–0.9453
–0.9462
–0.9472
–0.9481
–0.9498
–0.9500
0.2
R
= 50Ω
= 0 TO –1V
R
= 50Ω
L
L
V
OUT
V
= 0 TO –1V
OUT
R
= 50Ω
= 0 TO –1V
L
0.0
V
OUT
–0.474
–0.476
–0.478
–0.480
–0.482
–0.2
–0.4
–0.6
–0.8
–1.0
0.05
0.025
TIME – 5ns/Div
12 14 16 18 20 22 24 26 28 30 32 34 36
TIME – ns
TIME – 2ns/Div
Figure 14. Rise and Fall
Characteristics
Figure 13. Glitch Im pulse at Major
Carry
Figure 12. Settling Tim e
0
0
–20
–80
CLOCK = 10MHz
R
V
= 50Ω
L
F
= 1.002MHz
CLOCK = 10MHz
OUT
= 0 TO –1V
OUT
–75
–70
–65
–60
–55
–50
–20
–40
F
= 1.002MHz
OUT
AMPLITUDE = 0dBm
AMPLITUDE = 0dBm
OUTPUT IOUTB
R
L
= 50Ω
–40
–60
–60
–80
–80
–100
–100
10k
1.0M
FREQUENCY – Hz
2.0M
4
5
6
7
8
9 10
20
30
40
0.1
1
2
3
4
5
FREQUENCY – MHz
FREQUENCY – MHz
Figure 15. THD vs. Clock Frequency
at FOUT = 1 MHz
Figure 16. Typical Spectral
Perform ance
Figure 17. Typical SFDR
(With a Window)
–80
0
–20
–86
CLOCK = 10 MHz
FOUT1 = 240 kHz
FOUT2 = 260 kHz
AMPLITUDE = –6.0 dB FS
PER TONE
OUTPUT IOUTB
CLOCK = 30MHz
CLOCK = 1MHz
CLOCK = 10MHz
–82
–75
–70
–65
–60
–78
RL = 50Ω
–74
–40
CLOCK = 10MHz
CLOCK = 20MHz
CLOCK = 30MHz
–70
–66
–62
–58
–60
CLOCK = 40MHz
–80
–55
–50
–54
CLOCK = 20MHz
–100
–50
0.01
0.1
1
10
150
190
230
270
310
350
10
1
FREQUENCY – MHz
FREQUENCY – Hz
FREQUENCY – MHz
Figure 18. SFDR (Within a Window)
vs. FOUT
Figure 19. THD vs. FOUT
Figure 20. Interm odulation
Distortion
REV. B
–9–
AD768
AP P LYING TH E AD 768
DAC output is the parallel combination of the AD768’s output
impedance, RL, and bias resistor RB. T he nominal output swing
with the values given in Figure 22 is ±0.5 V assuming RB >> RL.
T he gain of the circuit will be a function of the tolerances of the
impedances RLAD, RB, and RL.
O UTP UT CO NFIGURATIO NS
T he following sections illustrate some typical output configura-
tions for the AD768. While most figures take the output at
IOUT A, IOUT B can be interchanged in all cases. Unless other-
wise noted, it is assumed that IREFIN and full-scale currents are
set to nominal values.
Choosing the value of RB and C will depend primarily on the
desired –3 dB high pass cutoff frequency and the bias current,
IB, of the subsequent stage connected to RB. T he –3 dB fre-
quency can be approximated by the equation,
For application that require the specified dc accuracies, proper
resistor selection is required. In addition to absolute resistor tol-
erances, resistor self-heating can result in unexpected errors. For
optimal INL, the buffered voltage output is recommended as
shown in Figure 23. In this configuration, self-heating of RFB
may cause a change in gain, producing a bow in the INL curve.
T his effect can be minimized by selection of a low temperature
coefficient resistor.
f–3 dB = 1/[2 × π × (RB + RLʈRLAD) × C].
T he dc offset of the output is a function of the bias current of
the subsequent stage and the value of RB. For example, if
C = 390 pF, RB = 20 kΩ, and IB = 1.0 µA, the –3 dB frequency
is approximately 20.4 kHz and the dc offset would be 20 mV.
UNBUFFERED VO LTAGE O UTP UT CO NFIGURATIO NS
Figure 21 shows the AD768 configured to provide a unipolar
output range of approximately 0 V to –1 V. T he nominal full-
scale current of 20 mA flows through the parallel combination
of the 50 Ω RL resistor and the 1 kΩ DAC output resistance
(from the R-2R ladder), for a combined 47.6 Ω. T his produces
an ideal full-scale voltage of –0.952 V with respect to LADCOM.
In addition, the 1 kΩ DAC output resistance has a tolerance of
±20% which may vary the full-scale gain by ±1%. T his linear
variation results in a gain error which can be easily compensated
I
AD768
B
C
IOUTA
1
R
L
IOUTB
27
R
B
49.9Ω
R
49.9Ω
L
LADCOM
28
Figure 22. 0.5 V to –0.5 V Unbuffered AC-Coupled Output
BUFFERED VO LTAGE O UTP UT CO NFIGURATIO NS
Unipolar Configur ation
for by adjusting IREFIN
.
For positive output voltages, or voltage ranges greater than
allowed by output compliance limits, some type of external
buffer is needed. A wide variety of amplifiers may be selected
based on considerations such as speed, accuracy and cost. T he
AD9631 is an excellent choice when dynamic performance is
important, offering low distortion up to 10 MHz. Figure 23
shows the implementation of 0 V to +2 V full-scale unipolar
buffered voltage output. T he amplifier establishes a summing
node at ground for the DAC output. T he buffered output volt-
age results from the DAC output current flowing through the
amplifier’s feedback resistor, RFB. In this case, the 20 mA full-
scale current across RFB (100 Ω) produces an output voltage
range of 0 V through +2 V. T he same configuration using a pre-
cision amplifier such as the AD845 is recommended for optimal
dc linearity.
AD768
IOUTA
1
R
49.9Ω
L
VA
VB
LADCOM
IOUTB
28
27
R
L
49.9Ω
Figure 21. 0 V to –1 V Unbuffered Voltage Output
In this configuration, it is important to note the restrictions from
the output compliance limits. T he maximum negative voltage
compliance is –1.2 V, prohibiting use of a 100 Ω load to produce
a 0 V to –2 V output swing. One additional consideration for
operation in this mode is integral nonlinearity. As the voltage at
the output node changes, the finite output impedance of the
DAC current steering switches gives rise to small changes in the
output current that vary with output voltage, producing a bow
(up to 8 LSBs) in the INL. For optimal INL performance, the
buffered voltage output mode is recommended.
R
FB
100Ω
AD768
IOUTA
1
A1
IOUTB
27
28
T he INL is also slightly dependent on the termination of the
unused output (IOUT B) as described in the ANALOG OUT -
PUT section. T o eliminate this effect, IOUT B should be termi-
nated with the same impedance as IOUT A, so both outputs see
the same resistive divider to ground. T his will keep the current
in LADCOM constant, minimizing any code-dependent IR
drops within the DAC ladder that may give rise to additional
nonlinearities.
LADCOM
Figure 23. Unipolar 0 V to +2 V Buffered Voltage Output
Buffer ed O utput Using a Cur r ent D ivider
T he configuration shown in Figure 23 may not be possible in
cases where the amplifier cannot supply the requisite 20 mA
feedback current. As an alternative, Figure 24 shows amplifier
A1 in conjunction with a resistive current divider. T he values of
RFF and RL are chosen to limit the current, I3, which must be
supplied by A1. Current, I2, is shunted to ground through resis-
tor, RL. T he parallel combination of RFF and RL should not ex-
ceed 60 Ω to avoid exceeding the specified compliance voltage.
AC-Coupled O utput
Configuring the output as shown in Figure 22 provides a bipolar
output signal from the AD768 without requiring the use of a
summing amplifier. T he ac load impedance presented to the
–10–
REV. B
AD768
primary side is multiplied by a factor of 4 (i.e., in this case
200 Ω). T o avoid dc current from flowing into the R-2R ladder
of the DAC, the center tap of the transformer should be con-
nected to LADCOM.
For the values given in Figure 24, I3 equals 4 mA, which results
in a nominal unipolar output swing of 0 V to 2 V. Note, since
A1 has an inverting gain of approximately –4 and a noise gain of
+5, A1’s distortion and noise performance should be considered.
R
500Ω
In order to comply with the minimum voltage compliance of
–1.2 V, the maximum differential resistance seen between
IOUT A and IOUT B should not exceed 240 Ω. Note that the
differential resistance consists of the load RL, referred to the
primary side of the transformer in parallel with any added differ-
ential resistance, RDIFF, across the two outputs. RDIFF is typically
added to the primary side of the transformer to match the effec-
tive primary source impedance to the load (i.e., in this case
200 Ω).
FB
R
FF
100Ω
AD768
I
I
3
1
IOUTA
1
A1
I
2
R
24.9Ω
L
IOUTB
27
R
P
20Ω
LADCOM
28
Figure 24. 0 V to 2 V Buffered Unipolar Output Using a
Current Divider
AD768
IOUTA
1
Bipolar Configur ation
Bipolar mode is accomplished by providing an offset current,
R
DIFF
200Ω
R
50Ω
T1
L
I
BIPOLAR, to the I/V amplifier’s (A1) summing junction. By set-
ting IBIPOLAR to exactly half the full-scale current flowing
IOUTB
27
28
4:1 IMPEDANCE
RATIO
through RFB, the resulting output voltage will be symmetrical
about the summing junction voltage, typically ground. Figure 25
shows the implementation for a bipolar ±2.5 V buffered voltage
output. T he resistor divider sets the full-scale current for IDAC to
5 mA. T he internal 2.5 V reference generates a 2.5 mA IBIPOLAR
current across RBIP. An output voltage of 0 V is produced when
the DAC is set to half scale (100. . .0) such that the 2.5 mA cur-
rent, IDAC, is exactly offset by IBIPOLAR. As the DAC is varied
from zero to full-scale, the output voltage swings from –2.5 V to
+2.5 V. Note, in configurations that require more than 15 mA
of total current from REFOUT , an external buffer is required.
LADCOM
T1 = MINI-CIRCUITS T4-6T
Figure 26. Differential Output Using a Transform er
D C CO UP LING VIA AN AMP LIFIER
A dc differential to single-ended conversion can be easily ac-
complished using the circuit shown in Figure 27. T his circuit
will attenuate both ac and dc common-mode error sources due
to the differential nature of the circuit. T hus, common-mode
noise (i.e., clock feedthrough) as well as dc unipolar offset errors
will be significantly reduced. Also, excellent temperature stabil-
ity can be obtained by using temperature tracking, thin film
resistors for R and RREF. T he design equations for the circuit are
provided such that the voltage output swing and IREF can be
optimized for a given application.
Op amps such as the AD811, AD8001, and AD9631 are good
selections for superior dynamic performance. In dc applications,
op amps such as the AD845 or AD797 may be more appropriate.
R
BIP
1kΩ
AD768
REFOUT
3
R
FB
R*
C
1kΩ
I
BIPOLAR
AD768
I
IOUTA
1
DAC
75Ω
V
= ±4 I
R
OUT
REF
=
IOUTA
IOUTB
1
A1
V
2.5V
OUT
WHERE I
A1
REF
IOUTB
27
R
REF
24.9Ω
27
R*
R
P
V
± 2V
OUT
R = 200Ω
= 5 x 200Ω
20Ω
LADCOM
REFIN
28
6
LADCOM
28
R
REF
R
REF
*
I
*OHMTEK TDP-1403
REF
Figure 25. Bipolar ±2.5 V Buffered Voltage Output
REFOUT
3
D IFFERENTIAL O UTP UT CO NFIGURATIO NS
Figure 27. DC Differential to Single-Ended Conversion
AC Coupling via a Tr ansfor m er
Applications that do not require baseband operation typically
use transformer coupling. T ransformer coupling the comple-
mentary outputs of the AD768 to a load has the inherent benefit
of providing electrical isolation while consuming no additional
power. Also, a properly applied transformer should not degrade
the AD768’s output signal with respect to noise and distortion,
since the transformer is a passive device. Figure 26 shows a
center-tapped output transformer that provides the necessary dc
load conditions at the outputs IOUT A and IOUT B to drive a
±0.5 V signal into a 50 Ω load. In this particular circuit, the cen-
ter-tapped transformer has an impedance ratio of 4 that corre-
sponds to a turns ratio of 2. Hence, any load, RL, referred to the
P O WER AND GRO UND ING CO NSID ERATIO NS
In systems seeking to simultaneously achieve high speed and
high accuracy, the implementation and construction of the
printed circuit board design is often as important as the circuit
design. Proper RF techniques must be used in device selection,
placement and routing, and supply bypassing and grounding.
Maintaining low noise on power supplies and ground is critical
to obtaining optimum results from the AD768. Figure 28 pro-
vides an illustration of the recommended printed circuit board
ground plane layout which is implemented on the AD768 evalu-
ation board.
REV. B
–11–
AD768
Figure 28. Printed Circuit Board Ground Plane Layout
Figure 29. Printed Circuit Board Power Plane Layout
–12–
REV. B
AD768
If properly implemented, ground planes can perform a host of
functions on high speed circuit boards: bypassing, shielding,
current transport, etc. In mixed signal design, the analog and
digital portions of the board should be distinct from each other,
with the analog ground plane confined to the areas covering
analog signal traces and the digital ground plane confined to
areas covering the digital interconnects.
A clean digital supply may be generated using the circuit shown
in Figure 30. T he circuit consists of a differential LC filter with
separate power supply and return lines. Lower noise can be at-
tained using low ESR (Equivalent Series Resistance) type elec-
trolytic and tantalum capacitors.
FERRITE
BEADS
TTL/CMOS
LOGIC
CIRCUITS
All analog ground pins of the DAC, reference, and other analog
output components, should be tied directly to the analog ground
plane. T he two ground planes should be connected by a path
1/4 to 1/2 inch wide underneath or within 1/2 inch of the DAC
as shown in Figure 28. Care should be taken to ensure that the
ground plane is uninterrupted over crucial signal paths. On the
digital side, this includes the digital input lines running to the
DAC as well as any clock signals. On the analog side, this in-
cludes the DAC output signal, reference signal, and the supply
feeders.
V
DD
100µF
ELECT.
10–20µF
TANT.
0.1µF
CER.
DCOM
+5V
DGND
+5V
POWER SUPPLY
Figure 30. Differential LC Filter for Single +5 V
Applications
T he use of wide runs or planes in the routing of power lines is
also recommended. T his serves the dual role of providing a low
series impedance power supply to the part, as well as, providing
some “free” capacitive decoupling to the appropriate ground
plane. Figure 29 illustrates the power plane layout used in the
AD768 evaluation board. T he AD768 evaluation board uses a
four layer P.C. board which illustrates good layout practices as
discussed above.
AP P LICATIO NS
USING TH E AD 768 AS A MULTIP LYING D AC
T he AD768 can be easily configured as a multiplying DAC
since IREFIN can be modulated from 1 mA to 7 mA. T he refer-
ence amplifier sets the maximum multiplying bandwidth to 15
MHz, while any external capacitor to the NR node serves to
limit the bandwidth according to Figure 7. IREFIN can be easily
modulated by properly scaling and summing into the IREFIN
node the modulating signal. Figure 31 demonstrates how the
modulating signal VMOD can be properly scaled and converted
to a current via RREFMOD such that its peak current does not ex-
ceed 3.0 mA. Figure 32 shows the AD768’s typical distortion
versus the reference channel frequency.
It is essential that care be taken in the layout of signal and
power ground interconnects to avoid inducing extraneous volt-
age drops in the signal ground paths. It is recommended that all
connections be short, direct and as physically close to the pack-
age as possible, in order to minimize the sharing of conduction
paths between different currents. When runs exceed an inch in
length, some type of termination resistor should be considered.
T he necessity and value of this resistor will be dependent upon
the logic family used.
AD768
IREFIN
R
REFMOD
VMOD
6
3
R
REF
625Ω
For maximum ac performance, the DAC should be mounted
directly to the circuit board; sockets should be avoided since
they introduce unwanted capacitive coupling between adjacent
pins of the device.
REFOUT
1µF
VMOD
≤ ±3.0mA
R
REFMOD
P O WER SUP P LY AND D ECO UP LING
One of the most important external components associated with
high speed designs are the capacitors used to bypass the power
supplies. Both selection and placement of these capacitors can
be critical and, to a large extent, dependent upon the specifics of
the system configuration. T he dominant consideration in the
selection of bypass capacitors for the AD768 is the minimization
of the series resistance and inductance. Many capacitors will
begin to look inductive at 20 MHz and above. Ceramic and film
type capacitors generally feature lower series inductance than
tantalum or electrolytic types.
Figure 31. Typical Multiplying DAC Application
–75
–70
–65
–60
–55
–50
–45
–40
I
= 5.0+/–1 mA
= 4.0+/–2 mA
REF
I
REF
It is recommended that each power supply to the AD768 be de-
coupled by a 0.1 µF capacitor located as close to the device pins
as possible. Surface-mount chip capacitors, by virtue of their
low parasitic inductance, are preferable to through-hole types.
Some series inductance between the DAC supply pins and the
power supply plane may help to provide additional filtering of
high frequency power supply noise. T his inductance can be gen-
erated by using small ferrite beads.
I
= 4.0+/–3 mA
REF
250
500
750 1000 1250 1500 1750 2000 2250 2500
FREQUENCY – kHz
Figure 32. Reference Channel Distortion vs. Frequency
REV. B
–13–
AD768
1.5
1.0
AD 768 IN MULTITO NE TRANSMITTERS (FO R AD SL)
Communications applications frequently require aspects of
component performance that differ significantly from the
simple, single tone signals used in typical SNR and T HD tests.
T his is particularly true for spread-spectrum and frequency divi-
sion multiplexed (FDM) type signals, where information con-
tent is held in a number of small signal components spread
across the frequency band. In these applications, a combination
of wide dynamic range, good fine-scale linearity, and low inter-
modulation distortion is required. Unfortunately, a part’s full
scale SNR and T HD performance may not be a reliable indica-
tor of how it will perform in these multitone applications.
0.5
0
–0.5
–1.0
–1.5
One example of an FDM communications system is the DMT
(discrete multitone) ADSL (Asymmetrical Digital Subscriber
Line) standard currently being considered by ANSI. Figure 33
shows a block diagram of a transmitter function.
TIME – 25µs/DIV
Figure 34b. Tim e Dom ain Output Signal of ADSL Test
Vector
T he digital bits are used to QAM modulate each of approxi-
mately 200 discrete tones. An inverse FFT turns this modu-
lated frequency domain information into 512 time points at a
2.2 MSPS sample rate. T hese time points are then put through
an FIR interpolation filter to upsample (in this case to 4.4 MSPS).
The bit stream is run through the AD768, which is followed by
a 4th order analog smoothing filter, then run to the line-driving
circuitry
T able I and II show the available SNR and T HD at the output
of the filter vs. frequency bin for the ADSL application. T he
AD768’s combination of 16-bit dynamic range and 14-bit lin-
earity provides excellent performance for the DMT signal. Its
fast input rate would support even faster rates of oversampling,
if one were interested in trading off digital filter complexity in
the interpolator for a simplified analog filter.
1024 TIME
POINTS
@ 4.4MSPS
BIT
STREAM
512 TIME
POINTS
256
MODULATED
2X
INTERPOLATOR
FIR
INVERSE
FFT
QAM
ENCODER
FREQUENCY
BINS
@ 2.2MSPS
Table I. SNR vs. Frequency
Frequency
SNR
4TH ORDER
SMOOTHING
FILTER
AD768
+BUFFER
TO
TRANSMITTER
151 kHz
349 kHz
500 kHz
1 MHz
70.1 dB
69.7 dB
69.4 dB
69.8 dB
Figure 33. Typical DMT ADSL Transm it Chain
Figure 34a shows a frequency domain representation of a test
vector run through this system, while 34b shows the time do-
main representation. (Clearly the frequency domain picture is
more informative.) We wish to optimize the SINAD of each
4 kHz frequency band: this is a function of both noise
(wideband and quantization) and distortion (simple harmonic
and intermod).
Table II. TH D vs. Frequency
Frequency
TH D
160 kHz
418 kHz
640 kHz
893 kHz
–68.9 dBc
–64.0 dBc
–64.3 dBc
–63.8 dBc
0
–20
–40
–60
–80
1.1M
0
FREQUENCY – Hz
Figure 34a. Output Spectrum of ADSL Test Vector
–14–
REV. B
AD768
AD 768 EVALUATIO N BO ARD
JP1. Buffered op amp output “A”. Jumper JP1 should be
installed if the buffered op amp output is desired. When JP 1
is in stalled, JP 2 an d JP 3 m u st be r em oved for proper
operation. T he output, available on the “A” connector, has a
nominal voltage swing of 0 V to 2 V and is in-phase with the
digital input. T his is the factory default setting.
GENERAL D ESCRIP TIO N
T he AD768-EB is an evaluation board for the AD768 16-bit
30 Msps D/A converter. Careful attention to layout and circuit
design combined with analog and digital prototyping areas al-
lows the user to easily and effectively evaluate the AD768 in any
application where high resolution, high speed conversion is
required.
JP 2. Bipolar 50 Ω transformer output. If jumper JP2 is in-
stalled, a transformer coupled output is available on the “A”
connector. When JP 2 is installed, JP 1 and JP 3 m ust be r e-
m oved for proper operation. T he transformer acts both as a
differential-to-single-ended converter and as an impedance
transformer. For proper operation, the tr ansfor m er m ust be
ter m inated with a 50 Ω r esistor. R2 must be replaced with
the 100 Ω resistor, R7. An additional 100 Ω resistor and the
transformer are included with the AD768-EB. T he additional
100 Ω resistor must be soldered into the appropriate position la-
beled “R3” and the transformer must be inserted into the
socket labeled “T 1.” T he nominal output voltage into a 50 Ω
load is 1 V p-p centered on a common-mode voltage of 0 V.
T he digital inputs to the AD768-EB may be driven directly us-
ing the standard 40-pin IDC connector. An external clock is
also required. T hese signals may be applied from a user’s
bench, or they can be generated from a circuit built on the
prototyping area. T he analog outputs from the AD768-EB are
available on BNC connectors. T hese outputs may be configured
to use either resistors, op amps, or a transformer.
O P ERATING P RO CED URE AND FUNCTIO NAL
D ESCRIP TIO N
P ower
Power may be supplied to the AD768-EB by applying either
wires or banana plugs to the metal binding posts included on the
printed circuit board.
JP 3. Resistor output “A.” JP3 is used to connect the resistor
R2 to the “A” output. U2 should be removed from its socket.
Using a 24.9 Ω resistor for R2, the output is an unbuffered 0 V
to –0.5 V output that is out of phase with the digital input. Re-
sistor R2 may be replaced with other values, but careful atten-
tion to the recommended output compliance range should be
observed. When JP 3 is installed, JP 1 and JP 2 m ust be r e-
m oved for pr oper oper ation.
D GND . Digital Ground. T he digital ground and the analog
ground are connected together underneath the AD768. Optimal
performance can be obtained with separate analog and digital
supplies. For evaluation purposes, a single-supply which makes
a second analog and digital ground connection at the supply is
acceptable.
JP 4. Resistor output “B.” JP4 is used to connect the resistor
R3 to the “A” output. U3 should be removed from its socket.
T he AD768-EB is shipped from the factory with resistor R3
shorted to ground. A different value selected by the user can be
installed for R3 to generate an unbuffered output that is in-
phase with the digital input. Careful attention to the recom-
mended output compliance range should be observed when
selecting the value of R3. When JP 4 is installed, JP 5 m ust
be r em oved for pr oper oper ation.
+5D . T he +5 V (±5%) digital supply should be capable of sup-
plying 50 mA.
–5A. T he –5 V (±5%) analog supply should be capable of sup-
plying –75 mA.
AGND . Analog ground. T he analog ground and the digital
ground are connected together underneath the AD768. Optimal
performance can be obtained with separate analog and digital
supplies. For evaluation purposes, a single-supply which makes
a second analog and digital ground connection at the supply is
acceptable.
JP 5. Buffered op amp output “B.” Jumper JP5 should be in-
stalled if the buffered op amp output is desired. When JP 5 is
installed, JP 4 m ust be r em oved for pr oper oper ation.
T he output is available on the “B” connector and has a nominal
voltage swing determined by the combination of resistors R3,
R9, and R10. T his op amp is not provided with the AD768-EB.
–VEE. Negative analog supply; typically –5 V to –15 V. T his
supply is used as the negative supply rail for the external op
amps. For the AD811 supplied with the AD768-EB, a supply
capable of supplying –20 mA (excluding external load require-
ments) is required.
Refer ence
Either the internal reference of the AD768 or an external refer-
ence may be selected on the AD768-EB. R12 is used to adjust
the full-scale output current of the AD768.
+VCC
. Positive analog supply; typically +5 V to +15 V. T his
supply is used as the positive supply rail for the external op
amps. For the AD811 supplied with the AD768-EB, a supply
capable of supplying +20 mA (excluding external load require-
ments) is required.
SW2. Internal/External reference select switch. When SW2 is
in position 1, the internal reference of the AD768 is selected.
When SW2 is in position 2, an external reference must be pro-
vided by the user.
Analog O utputs
T he analog output(s) from the AD768-EB are available on BNC
jacks “A” and “B.” T he complementary current outputs from
the AD768 can be configured using either resistors, op amps, or
a transformer. Only the “A” portion of the AD768-EB is popu-
lated and shipped from the factory. T he “B” side, or comple-
mentary output, may be populated by the user if so desired.
Level-Shifting the Analog O utput
Resistor sockets R8 and R6 can be populated with an appropri-
ately valued resistor to add dc offset current to an output which
uses the op amp configuration. As an example, to generate a
bipolar output signal, a 1.25 kΩ resistor installed into the “R8”
socket level-shifts the normally unipolar output by –1 V. T he
factory defaults for R8 and R6 are open circuits.
REV. B
–15–
AD768
Clock Input
Table III. Sum m ary of Jum per Functionality
An external sample clock must be provided to either the BNC
connector labeled “CLOCK” or on Pin 33 of the IDC connec-
tor. T his clock must comply with the logic levels outlined in the
AD768 data sheet. T he “CLOCK” input is terminated with a
removable 51 Ω resistor. T he IDC connector clock connection
is unterminated.
Installed
Jum per Function
Jumper
JP1
JP2
JP3 (ST BY)
JP4
JP5
Buffered Output A
50 Ω T ransformer Output
Unbuffered Output A
Unbuffered Output B
Buffered Output B
SW1. Clock source select switch. When SW1 is in position 1, Pin
33 of the IDC connected is applied to the CLOCK input of the
AD768. When SW2 is in position 2, the “CLOCK” BNC connec-
tor is applied to the CLOCK input of the AD768.
Table IV. AD 768-EB P arts List
Value / P art Type P ackage
D igital Inputs
T he digital inputs of the AD768, DB0–DB15, are available via
J1, a 40-pin IDC connector. T hese inputs should comply with
the specifications given in the AD768 data sheet.
Reference
Qty/Bd
U1
U2
T 1
AD768
AD811
28-Pin SOIC
1
1
1
Layout Consider ations
8-Pin DIP
Figures 28 and 29 show the AD768-EB ground and power
plane layouts. Figures 35–38 show the schematic diagram, trace
routing, silk screening, and component layout for the AD768 4
layer evaluation board.
Mini-Circuits
T 4–6T
Not Installed
A, B, CLOCK BNC JACKs,
Small
Small, Vertical
3
Separate ground and power planes have several advantages for
high speed layouts. (For further information outlining these
advantages, see the application note “Design and Layout of a
Video Graphics System for Reduced EMI” [E1309] available
from Analog Devices [(617) 461-3392].) A solid ground plane
can be used if the digital return current can be routed such that
it does not modulate the analog ground plane. If this is not pos-
sible, it may be necessary to split the ground plane in order to
force currents to flow in a controlled direction. T his type of
grounding scheme is shown in the Figure 28. T he ground plane
is separated into analog and digital planes that are joined
together under the AD768. In any case, the AD768 should be
treated as an analog component and a common ground connec-
tion should be made underneath the AD768 despite some pins
being labeled “digital” ground and some as “analog” ground.
JP1–5
SW1, 2
J1
Header
2-Pin
5
2
1
SPDT , Secme
0.1" × 0.3"
40-Pin IDC
Connector
R.A., Male,
w/ Latches
R1
R2
500 Ω
1/4 W, 0.01%,
Vishay
1
1
25 Ω
1/4 W, 0.01%,
Vishay
R3, R13–21, &
R23–29
Wire Jumpers
17
1
A complete parts list for the AD768 evaluation board is given in
T able IV.
R5
500 Ω
1/4 W, 0.01%,
Vishay
R7
100 Ω
1/4 W, 0.01%,
Vishay
1
R11
51 Ω
1/8 W, 5%, Carbon
3266 W
1
1
4
R12
10 kΩ Pot.
C1–4
1 µF Ceram. Cap. Leaded
0.1 µF Chip Cap,
C5–8, C10, 12,
14, & C16–19
1206
11
4
C9, 11, 13, 15 22 µF T ant. Cap., T eardrop,
25 V 0.1" Spacing
–16–
REV. B
AD768
R5
499
A
B
50
JP5
1
1
R10
499
+V
CC
C5
0.1µF
2
2
U2
2
7
+V
CC
C7
50
JP1
JP2
A
6
0.1µF
AD811
4
U3
3
C6
0.1µF
2
3
7
A
6
AD811
4
A
T1
4:1
3
1
C8
0.1µF
A
A
–V
EE
A
4
5
6
JP3
JP4
–V
EE
A
R7
100
–V
R2
24.9
R3
24.9
EE
C9
C10
47µF, 25V
0.1µF
R9
100
R8
∞
R6
∞
A
+V
CC
C11
47µF, 25V
C12
0.1µF
A
–5A
+5D
C13
47µF, 25V
C14
0.1µF
U1
C17
0.1µF
A
C3
1µF
C2
1µF
C18
0.1µF
R12
10k
AD768
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
LADCOM
IOUTA
NR
A
A
IOUTB
A
3
C4
1µF
C19
0.1µF
C15
47µF, 25V
C16
0.1µF
(–5V) V
REFOUT
NC
EE
C1
1µF
4
1
2
(+5V) V
DD
5
R21
0
0
0
0
0
0
0
0
R1
499
SW2
J1
J1
J1
J1
J1
J1
J1
J1
1
3
REFCOM
IREFIN
DB0 (LSB)
DB1
(MSB) DB15
DB14
6
R23
R24
R25
R26
R27
R28
R29
TP1
7
R13
R14
R15
R16
R17
R18
R19
R20
0
0
0
0
0
0
0
0
J1 31
J1 29
J1 27
J1 25
J1 23
J1 21
J1 19
J1 17
5
DB13
8
7
DB12
9
9
DB2
DB11
10
11
12
13
14
11
13
15
DB3
DB10
DB4
DB9
DB5
DB8
DB6
CLOCK
DCOM
DB7
33
J1
1
2
SW1
CLOCK
1
R11
50
2
J1
J1
J1
J1
J1
J1
J1
J1 16
J1 18
J1 20
J1 22
J1 24
J1 26
J1 28
J1 30
J1 32
J1 34
J1 36
J1 38
J1 40
2
4
DGND
6
AGND CONNECTED TO DGND
ON GND PLANE UNDER U1
IN BETWEEN PINS 5 AND 25
8
10
12
14
AGND
A
Figure 35. AD768 Evaluation Board Schem atic
REV. B
–17–
AD768
Figure 36. Silkscreen Layer (Not to Scale)
–18–
REV. B
AD768
Figure 37. Com ponent Side PCB Layout (Not to Scale)
Figure 38. Solder Side PCB Layout (Not to Scale)
REV. B
–19–
AD768
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
R-28
300 Mil 28-P in SO IC
0.7125 (18.10)
0.6969 (17.70)
28
15
0.2992 (7.60)
0.2914 (7.40)
0.4193 (10.65)
0.3937 (10.00)
1
14
PIN 1
0.1043 (2.65)
0.0926 (2.35)
0.0291 (0.74)
x 45°
0.0098 (0.25)
0.0500 (1.27)
0.0157 (0.40)
8°
0°
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0118 (0.30)
0.0040 (0.10)
SEATING
PLANE
0.0125 (0.32)
0.0091 (0.23)
–20–
REV. B
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