AD76911 [ADI]
14-Bit, 500 kSPS PulSAR ADC in MSOP; 14位， 500 kSPS时的PulSAR ADC ，采用MSOP
| 型号： | AD76911 |
| 厂家： | 
ADI |
| 描述： | 14-Bit, 500 kSPS PulSAR ADC in MSOP |
| 文件： | 总24页 (文件大小：644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
14-Bit, 500 kSPS
PulSAR ADC in MSOP
AD7946
APPLICATION DIAGRAM
FEATURES
0.5V TO 5V
5V
14-bit resolution with no missing codes
Throughput: 500 kSPS
INL: 0.4 LSB typical, 1 LSB maximum ( 0.0061% of FSR)
SINAD: 85 dB @ 20 kHz
THD: −100 dB @ 20 kHz
Pseudo differential analog input range
0 V to REF with REF up to VDD
VIO
SDI
1.8V TO VDD
REF VDD
0V TO REF
IN+
IN–
SCK
SDO
CNV
AD7946
3- OR 4-WIRE INTERFACE
(SPI, DAISY CHAIN, CS)
GND
No pipeline delay
Single-supply 5 V operation with
1.8 V/2.5 V/3 V/5 V logic interface
Serial interface, SPI/QSPI/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs and BUSY indicator
Power dissipation
3.3 mW @ 5 V/100 kSPS
3.3 μW @ 5 V/100 SPS
Standby current: 1 nA
Figure 1.
GENERAL DESCRIPTION
The AD7946 is a 14-bit, charge redistribution, successive
approximation, analog-to-digital converter (ADC) that operates
from a single 5 V power supply, VDD. It contains a low power,
high speed, 14-bit sampling ADC with no missing codes, an
internal conversion clock, and a versatile serial interface port.
The part also contains a low noise, wide bandwidth, short
aperture delay track-and-hold circuit. On the CNV rising edge,
it samples an analog input IN+ between 0 V to REF with respect
to a ground sense IN−. The reference voltage, REF, is applied
externally and can be set up to the supply voltage.
10-lead MSOP (MSOP-8 size) and
3 mm × 3 mm QFN (LFCSP) (SOT-23 size)
Pin-for-pin compatible with the 16-bit AD7686
APPLICATIONS
Battery-powered equipment
Data acquisition
Its power scales linearly with throughput.
Instrumentation
Medical instruments
Process control
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus, or it provides an optional BUSY indicator. It is
compatible with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate
supply VIO.
The AD7946 is housed in a 10-lead MSOP or a 10-lead QFN
(LFCSP) with operation specified from −40°C to +85°C.
Table 1. MSOP, QFN (LFCSP) 14-/16-/18-Bit PulSAR® ADC
Type
14-Bit
16-Bit
100 kSPS
AD7940
AD7680
AD7683
AD7684
250 kSPS
AD79421
AD76851
AD76871
AD7694
400 kSPS to 500 kSPS
AD79461
≥1000 kSPS
ADC Driver
AD76861
AD79801
AD79831
ADA4941
ADA4841
AD76881
AD76931
18-Bit
AD76911
AD76901
AD79821
AD79841
ADA4941
ADA4841
1 Pin-for-pin compatible.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2005–2007 Analog Devices, Inc. All rights reserved.
AD7946
TABLE OF CONTENTS
Features .............................................................................................. 1
Voltage Reference Input ............................................................ 14
Power Supply............................................................................... 15
Supplying the ADC from the Reference.................................. 15
Single-Supply Application......................................................... 15
Digital Interface.......................................................................... 16
Applications....................................................................................... 1
Application Diagram........................................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 11
Theory of Operation ...................................................................... 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Typical Connection Diagram ................................................... 13
Analog Input ............................................................................... 13
Driver Amplifier Choice............................................................ 14
CS
CS
CS
CS
MODE 3-Wire, No BUSY Indicator .................................. 17
Mode 3-Wire with BUSY Indicator ................................... 18
Mode 4-Wire, No BUSY Indicator..................................... 19
Mode 4-Wire with BUSY Indicator ................................... 20
Chain Mode, No BUSY Indicator ............................................ 21
Chain Mode with BUSY Indicator........................................... 22
Application Guidelines .................................................................. 23
Layout .......................................................................................... 23
Evaluating the AD7946’s Performance.................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
12/07—Rev. 0 to Rev. A
QFN Package Available......................................................Universal
Changes to Table 1............................................................................ 1
Changes to Table 5............................................................................ 6
Changes to Ordering Guide .......................................................... 24
7/05—Revision 0: Initial Version
Rev. A | Page 2 of 24
AD7946
SPECIFICATIONS
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, TA = −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
14
Bits
ANALOG INPUT
Voltage Range
Absolute Input Voltage
IN+ − IN−
IN+
IN−
0
−0.1
−0.1
REF
VDD + 0.1
0.1
V
V
V
Analog Input CMRR
Leakage Current at 25°C
Input Impedance
fIN = 200 kHz
Acquisition phase
65
1
dB
nA
See the Analog Input section
ACCURACY
No Missing Codes
14
−0.7
−1
Bits
Differential Linearity Error
Integral Linearity Error
Transition Noise
Gain Error2, TMIN to TMAX
Gain Error Temperature Drift
Offset Error2, TMIN to TMAX
Offset Temperature Drift
Power Supply Sensitivity
THROUGHPUT
0.3
0.4
0.33
0.3
1
0.3
1
0.1
+0.7
+1
LSB1
LSB
LSB
LSB
ppm/°C
LSB
REF = VDD = 5 V
6
6
ppm/°C
LSB
VDD = 5 V 5ꢀ
Full-scale step
Conversion Rate
Transient Response
AC ACCURACY
0
500
400
kSPS
ns
Signal-to-Noise
fIN = 20 kHz, REF = 5 V
fIN = 20 kHz, REF = 2.5 V
fIN = 20 kHz
fIN = 20 kHz
fIN = 20 kHz, REF = 5 V
fIN = 20 kHz, REF = 5 V, −60 dB input
84.5
85
84
−100
−100
85
dB3
dB
dB
dB
dB
dB
dB
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
84.5
25
100
Intermodulation Distortion4
1 LSB means least significant bit. With the 5 V input range, one LSB is 305.2 μV.
2 See the Terminology section. These specifications do include full temperature range variation but do not include the error contribution from the external reference.
3 All specifications in dB are referred to a full-scale input, FS. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
4 fIN1 = 21.4 kHz, fIN2 = 18.9 kHz, each tone at −7 dB below full scale.
Rev. A | Page 3 of 24
AD7946
VDD = 4.5 V to 5.5 V, VIO = 2.3 V to VDD, REF = VDD, TA = −40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
Conditions
Min
Typ
Max
Unit
0.5
VDD + 0.3
V
μA
500 kSPS, REF = 5 V
VDD = 5 V
100
9
2.5
MHz
ns
−0.3
0.7 × VIO
−1
0.3 × VIO
VIO + 0.3
+1
V
V
μA
μA
VIH
IIL
IIH
−1
+1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Serial 14-bits straight binary
Conversion results available immediately
after completed conversion
VOL
VOH
ISINK = +500 μA
ISOURCE = −500 μA
0.4
V
V
VIO − 0.3
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current1, 2
Power Dissipation
Specified performance
Specified performance
4.5
2.3
1.8
5.5
V
V
V
nA
μW
mW
mW
VDD + 0.3
VDD + 0.3
50
VDD and VIO = 5 V, 25°C
1
3.3
3.3
VDD = 5 V, 100 SPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 500 kSPS throughput
3.8
19
TEMPERATURE RANGE3
Specified Performance
TMIN to TMAX
−40
+85
°C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact sales for extended the temperature range.
Rev. A | Page 4 of 24
AD7946
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 4.5 V to 5.5 V, VIO = 2.3 V to 5.5 V or VDD + 0.3 V, whichever is the lowest, unless otherwise stated.
See Figure 2 and Figure 3 for load conditions.
Table 4.
Parameter
Symbol
tCONV
tACQ
Min
0.5
400
2
Typ
Max
Unit
μs
ns
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
1.6
tCYC
μs
CNV Pulse Width (CS Mode)
tCNVH
tSCK
10
ns
SCK Period (CS Mode)
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
17
18
19
20
7
ns
ns
ns
ns
ns
ns
ns
tSCKL
tSCKH
tHSDO
tDSDO
7
5
14
15
16
17
ns
ns
ns
ns
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
VIO Above 4.5 V
tEN
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with Busy Indicator)
VIO Above 4.5 V
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
5
3
4
15
26
ns
ns
VIO Above 2.3 V
Rev. A | Page 5 of 24
AD7946
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Analog Inputs
IN+1, IN−1
Rating
GND − 0.3 V to VDD + 0.3 V or
130 mA
REF
GND − 0.3 V to VDD + 0.3 V
Supply Voltages
VDD, VIO to GND
VDD to VIO
−0.3 V to +7 V
7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
ESD CAUTION
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
θJA Thermal Impedance
10-Lead MSOP
200°C/W
48.7°C/W
10-Lead QFN
θJC Thermal Impedance
10-Lead MSOP
44°C/W
10-Lead QFN
2.96°C/W
Lead Temperature
Vapor Phase (60 sec)
Infrared (15 sec)
215°C
220°C
1 See the Analog Input section.
500µA
I
OL
TO
SDO
1.4V
C
L
50pF
500µA
I
OH
Figure 2. Load Circuit for Digital Interface Timing
70% OVDD
30% VIO
tDELAY
tDELAY
1
1
2V or OVDD – 0.5V
2V or VIO – 0.5V
2
2
0.8V or 0.5V
0.8V or 0.5V
NOTES
1
2
2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
Figure 3. Voltage Levels for Timing
Rev. A | Page 6 of 24
AD7946
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
VDD
IN+
VIO
1
2
3
4
5
10
9
REF
VDD
IN+
1
2
3
4
5
VIO
10
9
SDI
AD7946
TOP VIEW
(Not to Scale)
SDI
AD7946
TOP VIEW
(Not to Scale)
8
SCK
SDO
CNV
8
SCK
SDO
CNV
IN–
7
IN–
7
GND
6
6
GND
Figure 5. 10-Lead QFN (LFCSP) Pin Configuration
Figure 4. 10-Lead MSOP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD, and is referred to the GND pin. This pin
should be decoupled closely to the pin with a 10 μF capacitor.
2
3
VDD
IN+
P
AI
Power Supply.
Analog Input. It is referred to IN−. The voltage range, that is, the difference between IN+ and IN−,
is 0 V to REF.
4
5
6
IN−
GND
CNV
AI
P
DI
Analog Input Ground Sense. Connect to the analog ground plane or to a remote sense ground.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions and
selects the interface mode, chain, or CS. In CS mode, it enables the SDO pin when low. In chain mode,
the data should be read when CNV is high.
7
8
9
SDO
SCK
SDI
DO
DI
DI
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the
ADC as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a data
input to daisy-chain the conversion results of two or more ADCs onto a single SDO line. The digital
data level on SDI is output on SDO with a delay of 14 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV can
enable the serial output signals when low, and if SDI or CNV is low when the conversion is complete,
the BUSY indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V, 2.5 V,
3 V, or 5 V).
1 AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. A | Page 7 of 24
AD7946
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
1.0
0.8
POSITIVE INL = +0.17LSB
POSITIVE DNL = +0.20LSB
NEGATIVE DNL = –0.13LSB
0.8
NEGATIVE INL = –0.26LSB
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
4096
8192
12288
16384
0
4096
8192
12288
16384
CODE
CODE
Figure 6. Integral Nonlinearity vs. Code
Figure 9. Differential Nonlinearity vs. Code
300000
250000
200000
150000
150000
261120
VDD = REF = 5V
VDD = REF = 5V
131592
129528
125000
100000
75000
50000
25000
0
100000
50000
0
0
0
0
0
0
0
0
0
0
0
2009
200A
200B
200C
200D
200E
200F
2059
205A
205B
205C
205D
205E
CODE IN HEX
CODE IN HEX
Figure 7. Histogram of a DC Input at the Code Center
Figure 10. Histogram of a DC Input at the Code Transition
0
90
88
86
84
82
80
8192 POINT FFT
VDD = REF = 5V
fS = 500kSPS
fIN = 20.14kHz
SNR = 85.3dB
THD = –105.2dB
–20
–40
–60
SECOND HARMONIC = –106dB
THIRD HARMONIC = –110dB
–80
–100
–120
–140
–160
–180
0
20 40 60 80 100 120 140 160 180 200 220 240
FREQUENCY (kHz)
–10
–8
–6
–4
–2
INPUT LEVEL (dB)
Figure 8. FFT Plot
Figure 11. SNR vs. Input Level
Rev. A | Page 8 of 24
AD7946
90.0
87.5
85.0
82.5
80.0
–90
–95
15.0
14.5
14.0
13.5
13.0
–100
–105
–110
–115
–120
SNR
THD
SINAD
SFDR
ENOB
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 12. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 15. THD, SFDR vs. Reference Voltage
90.0
87.5
85.0
82.5
80.0
–90
–100
–110
–120
–130
REF = 5V
REF = 5V
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 13. SNR vs. Temperature
Figure 16. THD vs. Temperature
100
95
90
85
80
75
70
–60
–70
–80
REF = 5V, –10dB
–90
REF = 5V, –1dB
REF = 5V, –1dB
–100
–110
–120
REF = 5V, –10dB
0
50
100
150
200
0
50
100
FREQUENCY (kHz)
150
200
FREQUENCY (kHz)
Figure 14. SINAD vs. Frequency
Figure 17. THD vs. Frequency
Rev. A | Page 9 of 24
AD7946
3
2
1000
fS = 100kSPS
750
500
250
VDD
1
OFFSET ERROR
GAIN ERROR
0
–1
–2
–3
VIO
0
4.50
–55
–35
–15
5
25
45
65
85
105
125
4.75
5.00
SUPPLY (V)
5.25
5.50
TEMPERATURE (°C)
Figure 18. Operating Current vs. Supply
Figure 21. Offset and Gain Error vs. Temperature
1000
750
500
250
25
20
15
10
5
VDD = 5V, 85°C
VDD = 5V, 25°C
VDD+VIO
0
–55
0
0
20
40
60
80
100
120
–35
–15
5
25
45
65
85
105
125
SDO CAPACITIVE LOAD (pF)
TEMPERATURE (°C)
Figure 19. Power-Down Current vs. Temperature
Figure 22. tDSDO Delay vs. Capacitance Load and Supply
1000
750
500
250
0
fS = 100kSPS
VDD = 5V
VIO
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 20. Operating Current vs. Temperature
Rev. A | Page 10 of 24
AD7946
TERMINOLOGY
Integral Nonlinearity Error (INL)
Effective Number of Bits (ENOB)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (Figure 24).
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in dB.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in dB.
Offset Error
The first transition should occur at a level ½ LSB above analog
ground (152.6 μV for the 0 V to 5 V range). The offset error is
the deviation of the actual transition from that point.
Signal-to-(Noise + Distortion) Ratio (SINAD)
Gain Error
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in dB.
The last transition (from 111 … 10 to 111 … 11) should occur
for an analog voltage 1½ LSB below the nominal full scale
(4.999542 V for the 0 V to 5 V range). The gain error is the
deviation of the actual level of the last transition from the ideal
level after the offset has been adjusted out.
Aperture Delay
Aperture delay is the measurement of the acquisition perform-
ance and is the time between the rising edge of the CNV input
and when the input signal is held for a conversion.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Transient Response
Transient response is the time required for the ADC to accu-
rately acquire its input after a full-scale step function is applied.
Rev. A | Page 11 of 24
AD7946
THEORY OF OPERATION
IN+
SWITCHES CONTROL
CONTROL
MSB
LSB
LSB
SW+
SW–
8192C
8192C
4096C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
COMP
LOGIC
GND
OUTPUT CODE
4096C
MSB
CNV
IN–
Figure 23. ADC Simplified Schematic
The control logic toggles these switches, starting with the MSB,
in order to bring the comparator back into a balanced condition.
After completing this process, the part returns to the acquisition
phase, and the control logic generates the ADC output code and
a BUSY signal indicator.
CIRCUIT INFORMATION
The AD7946 is a fast, low power, single-supply, precise 14-bit
ADC using a successive approximation architecture.
The AD7946 can convert 500,000 samples per second (500 kSPS)
and powers down between conversions. When operating at
100 SPS, for example, it consumes 3.3 μW typically, ideal for
battery-powered applications.
Because the AD7946 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Transfer Functions
The AD7946 provides the user with an on-chip track-and-hold
and does not exhibit any pipeline delay or latency, making it
ideal for multiple multiplexed channel applications.
The ideal transfer characteristic for the AD7946 is shown in
Figure 24 and Table 7.
The AD7946 is specified from 4.5 V to 5.5 V and can be
interfaced to any of the 1.8 V to 5 V digital logic family. It is
housed in a 10-lead MSOP or a tiny 10-lead QFN (LFCSP) that
combines space savings and allows flexible configurations.
111...111
111...110
111...101
It is pin-for-pin compatible with the 16-bit ADC AD7686.
CONVERTER OPERATION
The AD7946 is a successive approximation ADC based on a
charge redistribution DAC. Figure 23 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 14 binary weighted capacitors, which are
connected to the two comparator inputs.
000...010
000...001
000...000
–FSR
–FSR + 1 LSB
+FSR – 1 LSB
+FSR – 1.5 LSB
–FSR + 0.5 LSB
During the acquisition phase, the terminals of the array that are
tied to the comparator’s input are connected to GND via SW+
and SW−. All independent switches are connected to the analog
inputs. Thus, the capacitor arrays are used as sampling capacitors
and acquire the analog signal on the IN+ and IN− inputs. When
the acquisition phase is complete and the CNV input goes high,
a conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
inputs IN+ and IN− captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary weighted voltage steps (REF/2, REF/4 … REF/16,384).
ANALOG INPUT
Figure 24. ADC Ideal Transfer Function
Table 7. Output Codes and Ideal Input Voltages
Analog Input
Description
REF = 5 V
Digital Output Code Hexa
FSR − 1 LSB
4.999695 V
3FFF1
2001
2000
1FFF
0001
00002
Midscale + 1 LSB 2.500305 V
Midscale 2.5 V
Midscale − 1 LSB 2.499695 V
−FSR + 1 LSB
−FSR
305.2 μV
0 V
1 This is also the code for an overranged analog input (VIN+ − VIN− above REF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
Rev. A | Page 12 of 24
AD7946
TYPICAL CONNECTION DIAGRAM
Figure 25 shows an example of the recommended connection diagram for the AD7946 when multiple supplies are available.
(NOTE 1)
V+
V+
REF
5V
10µF
(NOTE 2)
100nF
100nF
1.8V TO VDD
REF
VDD
VIO
SDI
33Ω
IN+
IN–
0V TO REF
SCK
SDO
CNV
3- OR 4-WIRE INTERFACE
(NOTE 5)
2.7nF
(NOTE 4)
AD7946
(ADA4841
OR NOTE 3)
V–
GND
NOTES
1. SEE REFERENCE SECTION FOR REFERENCE SELECTION.
2. C IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
REF
3. SEE DRIVER AMPLIFIER CHOICE SECTION.
4. OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
5. SEE DIGITAL INTERFACE FOR MOST CONVENIENT INTERFACE MODE.
Figure 25. Typical Application Diagram with Multiple Supplies
70
ANALOG INPUT
Figure 26 shows an equivalent circuit of the input structure of
the AD7946.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs IN+ and IN−. Care must be taken to ensure that
the analog input signal never exceeds the supply rails by more
than 0.3 V because this causes these diodes to begin to forward-
bias and start conducting current. These diodes can handle a
maximum forward-biased current of 130 mA. For instance,
these conditions could eventually occur when the input buffer’s
(U1) supplies are different from VDD. In such a case, an input
buffer with a short-circuit current limitation can be used to
protect the part.
60
50
40
VDD = 5V
1
10
100
FREQUENCY (kHz)
1k
10k
VDD
Figure 27. Analog Input CMRR vs. Frequency
D1
C
During the acquisition phase, the impedance of the analog
inputs (IN+ or IN−) can be modeled as a parallel combination
of capacitor, CPIN, and the network formed by the series connec-
tion of RIN and CIN. CPIN is primarily the pin capacitance. RIN is
typically 600 Ω and is a lumped component made up of some
serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
During the conversion phase, when the switches are opened, the
input impedance is limited to CPIN. RIN and CIN make a 1-pole,
low-pass filter, which reduces undesirable aliasing effects and
limits the noise.
IN
R
IN
IN+
OR IN–
C
PIN
D2
GND
Figure 26. Equivalent Analog Input Circuit
The analog input structure allows the sampling of the
differential signal between IN+ and IN−. By using this
differential input, small signals common to both inputs are
rejected, as shown in Figure 27, which represents the typical
CMRR over frequency. For instance, by using IN− to sense a
remote signal ground, ground potential differences between the
sensor and the local ADC ground are eliminated.
When the source impedance of the driving circuit is low, the
AD7946 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
Rev. A | Page 13 of 24
AD7946
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency, as shown in
Figure 28.
Table 8. Recommended Driver Amplifiers
Amplifier
ADA4841
AD8021
AD8655
AD8022
Typical Application
Very low noise, small and low power
Very low noise and high frequency
5 V single-supply, low noise, and low power
Low noise and high frequency
–80
–85
–90
OP184
AD8605, AD8615
AD8519
Low power, low noise, and low frequency
5 V single-supply, low power
Small, low power, and low frequency
High frequency and low power
R
= 250Ω
=100Ω
S
–95
–100
–105
–110
AD8031
R
S
VOLTAGE REFERENCE INPUT
R
R
= 50Ω
= 33Ω
S
S
The AD7946 voltage reference input REF has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
0
25
50
75
100
FREQUENCY (kHz)
When REF is driven by a very low impedance source, for
example, a reference buffer using the AD8031 or the AD8603, a
10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate for
optimum performance.
Figure 28. THD vs. Analog Input Frequency and Source Resistance
DRIVER AMPLIFIER CHOICE
Although the AD7946 is easy to drive, the driver amplifier
needs to meet the following requirements:
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
•
The noise generated by the driver amplifier needs to be
kept as low as possible to preserve the SNR and transition
noise performance of the AD7946. Note that the AD7946
has a noise much lower than most of the other 14-bit
ADCs and, therefore, can be driven by a noisier amplifier
to meet a given system noise specification. The noise
coming from the amplifier is filtered by the AD7946 analog
input circuit 1-pole, low-pass filter made by RIN and CIN or
by the external filter, if one is used.
If desired, smaller reference decoupling capacitor values down
to 2.2 μF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value ceramic
decoupling capacitor (for example, 100 nF) between the REF
and GND pins.
•
•
For ac applications, the driver should have a THD perform-
ance commensurate with the AD7946. Figure 17 shows the
THD vs. frequency that the driver should exceed.
For multichannel multiplexed applications, the driver
amplifier and the AD7946 analog input circuit must settle a
full-scale step onto the capacitor array at a 14-bit level
(0.006%). In the amplifier’s data sheet, settling at 0.1% to
0.01% is more commonly specified. This could differ
significantly from the settling time at a 14-bit level and
should be verified prior to driver selection.
Rev. A | Page 14 of 24
AD7946
POWER SUPPLY
SUPPLYING THE ADC FROM THE REFERENCE
The AD7946 is specified at 4.5 V to 5.5 V. It uses two power
supply pins: a core supply VDD and a digital input/output
interface supply VIO. VIO allows direct interface with any
logic between 1.8 V and VDD. To reduce the supplies needed,
the VIO and VDD can be tied together. The AD7946 is
independent of power supply sequencing between VIO and
VDD. Additionally, it is very insensitive to power supply
variations over a wide frequency range, as shown in Figure 29,
which represents PSRR over frequency.
For simplified applications, the AD7946, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 31. The reference line can be driven by one of
the following:
•
•
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
•
A reference buffer, such as the AD8031 or AD8603,
which can also filter the system power supply, as shown
in Figure 31.
90
80
5V
VDD = 5V
70
10kΩ
5V 1kΩ
10µF
1µF
AD8603
(NOTE 1)
60
50
40
30
1µF
47kΩ
REF
VDD
VIO
AD7946
NOTES
1. OPTIONAL REFERENCE BUFFER AND FILTER
1
10
100
1k
10k
Figure 31. Example of Application Circuit
FREQUENCY (kHz)
Figure 29. PSRR vs. Frequency
SINGLE-SUPPLY APPLICATION
The AD7946 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate, as shown in Figure 30. This makes the part
ideal for low sampling rate (even a few Hz) and low battery-
powered applications.
Figure 32 shows a typical 14-bit single-supply application. There
are different challenges to doing a single-supply, high resolution
design, and the ADA4841 addresses these nicely. The combina-
tion of low noise, low power, wide input range, rail-to-rail output,
and high speed make the ADA4841 a perfect driver solution for
low power, single-supply 14-bit ADCs, such as the AD7946. In a
single-supply system, one of the main challenges is to use the
amplifier in buffer mode to have the lowest output noise and
still preserve linearity compatible with the ADC. Rail-to-rail
input amplifiers usually have higher noise than the ADA4841
and cannot be used on their entire input range in buffer mode
because of the nonlinear region around the crossover point of
their input stage. The ADA4841, which has no crossover region
but has a wide linear input range from ground to 1 V below
positive rail, solves this issue, as shown in Figure 32, where it
can accept the 0 V to 4.096 V input range with a supply as low
as 5.2 V. This supply allows using a small, low dropout, low
temperature drift ADR364 reference voltage. Note that, like any
rail-to-rail output amplifier at the low end of its output range
close to ground, the ADA4841 can exhibit some nonlinearity on
a small region of approximately 25 mV from ground. The
ADA4841 drives a 1-pole, low-pass filter. This filter limits the
already very low noise contribution from the amplifier to the
AD7946.
1000
VDD = 5V
100
VIO
10
1
0.1
0.01
0.001
10
100
1k
10k
100k
1M
SAMPLING RATE (SPS)
Figure 30. Operating Currents vs. Sampling Rate
Rev. A | Page 15 of 24
AD7946
>5.2V
independent of the readback timing (SDI). This is useful in low
jitter sampling or simultaneous sampling applications.
100nF
ADR364
The AD7946, when in chain mode, provides a daisy chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
100nF
10µF
100nF
ADA4841
REF
VDD VIO
0V TO 4.096V
33Ω
The operating mode depends on the SDI level when the CNV
IN+
SDI
SCK
SDO
CNV
CS
rising edge occurs.
mode is selected if SDI is high, and chain
2.7nF
AD7946
mode is selected if SDI is low. The SDI hold time is such that
when SDI and CNV are connected, the chain mode is always
selected.
IN–
GND
In either mode, the AD7946 offers the flexibility to optionally
force a start bit in front of the data bits. This start bit can be
used as a BUSY signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a BUSY indicator,
the user must time out the maximum conversion time prior to
readback.
Figure 32. Example of a Single-Supply Application Circuit
DIGITAL INTERFACE
Although the AD7946 has a reduced number of pins, it offers
flexibility in its serial interface modes.
CS
The AD7946, when in
mode, is compatible with SPI, QSPI™,
BUSY indicator feature is enabled
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. This interface can use either 3-wire or 4-wire. A
3-wire interface using the CNV, SCK, and SDO signals mini-
mizes wiring connections useful, for instance, in isolated
applications. A 4-wire interface using the SDI, CNV, SCK, and
SDO signals allows CNV, which initiates the conversions, to be
CS
mode, if CNV or SDI is low when the ADC
•
In
conversion ends (see Figure 36 and Figure 40).
•
In chain mode, if SCK is high during the CNV rising edge
(see Figure 44).
Rev. A | Page 16 of 24
AD7946
are then clocked by subsequent SCK falling edges. The data is
valid on both SCK edges. Although the rising edge can be used
to capture the data, a digital host using the SCK falling edge
allows a faster reading rate, provided it has an acceptable hold
time. After the 14th SCK falling edge or when CNV goes high,
whichever is earlier, SDO returns to high impedance.
CS MODE 3-WIRE, NO BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 33 and the corresponding timing is given in
Figure 34.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
conversion, selects the
mode, and forces SDO to high
CONVERT
impedance. Once a conversion is initiated, it continues to
completion irrespective of the state of CNV. For instance, it
could be useful to bring CNV low to select other SPI devices,
such as analog multiplexers, but CNV must be returned high
before the minimum conversion time and held high until the
maximum conversion time to avoid the generation of the BUSY
signal indicator. When the conversion is complete, the AD7946
enters the acquisition phase and powers down. When CNV
goes low, the MSB is output onto SDO. The remaining data bits
DIGITAL HOST
CNV
VIO
DATA IN
SDI
SDO
AD7946
SCK
CLK
CS
Figure 33. Mode 3-Wire, No BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
12
13
14
D0
tHSDO
tSCKH
tDSDO
D11
tEN
tDIS
SDO
D13
D12
D1
CS
Figure 34. Mode 3-Wire, No BUSY Indicator Serial Interface Timing (SDI High)
Rev. A | Page 17 of 24
AD7946
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
15th SCK falling edge, or when CNV goes high, whichever is
earlier, SDO returns to high impedance.
CS MODE 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 35, and the
corresponding timing is given in Figure 36.
If multiple AD7946s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
conversion, selects the
mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV could be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time and
held low until the maximum conversion time to guarantee the
generation of the BUSY signal indicator. When the conversion
is complete, SDO goes from high impedance to low. With a
pull-up on the SDO line, this transition can be used as an
interrupt signal to initiate the data reading controlled by the
digital host. The AD7946 then enters the acquisition phase and
powers down. The data bits are then clocked out, MSB first, by
subsequent SCK falling edges. The data is valid on both SCK
CONVERT
VIO
DIGITAL HOST
CNV
VIO
47kΩ
DATA IN
IRQ
SDI
SDO
AD7946
SCK
CLK
CS
Figure 35. Mode 3-Wire with BUSY Indicator
Connection Diagram (SDI High)
SDI = 1
t
CYC
t
CNVH
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
t
SCK
t
SCKL
SCK
SDO
1
2
3
13
14
15
t
t
tSCKH
HSDO
t
DSDO
DIS
D13
D12
D1
D0
CS
Figure 36. Mode 3-Wire with BUSY Indicator Serial Interface Timing (SDI High)
Rev. A | Page 18 of 24
AD7946
time and held high until the maximum conversion time to
CS MODE 4-WIRE, NO BUSY INDICATOR
avoid the generation of the BUSY signal indicator. When the
conversion is complete, the AD7946 enters the acquisition
phase and powers down. Each ADC result can be read by
bringing its SDI input low, which consequently outputs the MSB
onto SDO. The remaining data bits are then clocked by subse-
quent SCK falling edges. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 14th SCK
falling edge, or when SDI goes high, whichever is earlier, SDO
returns to high impedance and another AD7946 can be read.
This mode is usually used when multiple AD7946s are
connected to an SPI-compatible digital host.
A connection diagram example using two AD7946s is shown in
Figure 37, and the corresponding timing is given in Figure 38.
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
DIGITAL HOST
CNV
CNV
SDI
SDO
SDI
SDO
AD7946
AD7946
SCK
SCK
DATA IN
CLK
CS
Figure 37. Mode 4-Wire, No BUSY Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI(CS1)
tHSDICNV
SDI(CS2)
SCK
tSCK
tSCKL
1
2
3
12
13
14
15
16
26
27
28
tHSDO
tSCKH
tDSDO
D11
tDIS
tEN
SDO
D13
D12
D1
D0
D13
D12
D1
D0
CS
Figure 38. Mode 4-Wire, No BUSY Indicator Serial Interface Timing
Rev. A | Page 19 of 24
AD7946
low. With a pull-up on the SDO line, this transition can be used
as an interrupt signal to initiate the data readback controlled by
the digital host. The AD7946 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
15th SCK falling edge or SDI going high, whichever is earlier, the
SDO returns to high impedance.
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7946 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
CS1
CONVERT
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI could
be used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the BUSY signal indicator. When
the conversion is complete, SDO goes from high impedance to
VIO
DIGITAL HOST
CNV
47kΩ
DATA IN
IRQ
SDI
SDO
AD7946
SCK
CLK
CS
Figure 39. Mode 4-Wire with BUSY Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
SCK
SDO
1
2
3
13
14
15
tHSDO
tDSDO
tSCKH
tDIS
tEN
D13
D12
D1
D0
CS
Figure 40. Mode 4-Wire with BUSY Indicator Serial Interface Timing
Rev. A | Page 20 of 24
AD7946
onto SDO, and the AD7946 enters the acquisition phase and
CHAIN MODE, NO BUSY INDICATOR
powers down. The remaining data bits stored in the internal
shift register are then clocked by subsequent SCK falling edges.
For each ADC, SDI feeds the input of the internal shift register
and is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 14 × N clocks are required to
readback the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. The maximum conver-
sion rate may be reduced due to the total readback time. For
instance, with a 3 ns digital host setup time and 3 V interface,
up to four AD7946s running at a conversion rate of 360 kSPS
can be daisy-chained on a 3-wire port.
This mode can be used to daisy-chain multiple AD7946s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7946s is shown in
Figure 41, and the corresponding timing is given in Figure 42.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the BUSY indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
readback. When the conversion is complete, the MSB is output
CONVERT
CNV
CNV
DIGITAL HOST
SDI
SDO
SDI
SDO
AD7946
AD7946
DATA IN
A
B
SCK
SCK
CLK
Figure 41. Chain Mode, No BUSY Indicator Connection Diagram
SDI = 0
A
tCYC
CNV
tACQ
t
CONV
ACQUISITION
CONVERSION
tSSCKCNV
ACQUISITION
tSCK
tSCKL
SCK
1
A
B
2
3
A
B
12
13
14
15
16
26
27
28
tHSCKCNV
tSSDISCK
tSCKH
tHSDISCK
tEN
D
D
13
D
12
D
D
11
11
D
1
1
D
0
SDO = SDI
A
A
A
A
B
tHSDO
tDSDO
13
D
12
D
B
D
0
D
13
D
12
A
D
1
D 0
A
SDO
B
B
A
A
B
Figure 42. Chain Mode, No BUSY Indicator Serial Interface Timing
Rev. A | Page 21 of 24
AD7946
Figure 43) SDO is driven high. This transition on SDO can
be used as a BUSY indicator to trigger the data readback
controlled by the digital host. The AD7946 then enters the
acquisition phase and powers down. The data bits stored in
the internal shift register are then clocked out, MSB first, by
subsequent SCK falling edges. For each ADC, SDI feeds the
input of the internal shift register and is clocked by the SCK
falling edge. Each ADC in the chain outputs its data MSB first,
and 14 × N + 1 clocks are required to readback the N ADCs.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7946s in the chain, provided the
digital host has an acceptable hold time. For instance, with a
3 ns digital host setup time and 3 V interface, up to four AD7946s
running at a conversion rate of 360 kSPS can be daisy-chained
to a single 3-wire port.
CHAIN MODE WITH BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7946s on a
3-wire serial interface while providing a BUSY indicator. This
feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7946s is shown
in Figure 43, and the corresponding timing is given in Figure 44.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the BUSY indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the near-end ADC (ADC C in
CONVERT
DIGITAL HOST
DATA IN
CNV
CNV
CNV
SDI
SDO
SDI
SDO
SDI
SDO
AD7946
AD7946
AD7946
A
B
C
SCK
SCK
SCK
IRQ
CLK
Figure 43. Chain Mode with BUSY Indicator Connection Diagram
tCYC
CNV = SDI
A
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSSCKCNV
tSCKH
SCK
1
2
3
A
4
13
14
15
16
17
27
28
29
30
31
41
42
43
tSSDISCK
tHSCKCNV
tSCKL
tDSDOSDI
tHSDISCK
tEN
SDO = SDI
D
13
D
12
D
11
D
1
D 0
A
A
B
A
A
A
tHSDO
tDSDO
tDSDOSDI
tDSDOSDI
tDSDOSDI
SDO = SDI
B
D
13
D
D
12
D
D
11
B
D
D
1
D
0
D
13
D
12
D 1
A
D 0
A
C
B
B
B
B
A
A
tDSDOSDI
SDO
D
13
12
11
1
D
0
D
13
D
12
D
1
D
0
D
13
D
12
D
1
D 0
A
C
C
C
C
C
C
B
B
B
B
A
A
A
Figure 44. Chain Mode with BUSY Indicator Serial Interface Timing
Rev. A | Page 22 of 24
AD7946
APPLICATION GUIDELINES
LAYOUT
The printed circuit board that houses the AD7946 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7946, with all its analog signals on the left side and all its
digital signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die, unless a ground plane under the
AD7946 is used as a shield. Fast switching signals, such as CNV
or clocks, should never run near analog signal paths. Crossover
of digital and analog signals should be avoided.
At least one ground plane should be used. It could be common
or split between the digital and analog sections. In the latter
case, the planes should be joined underneath the AD7946s.
Figure 45. Example of Layout of the AD7946 (Top Layer)
The AD7946 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, and ideally right up against, the REF
and GND pins and connecting it with wide, low impedance
traces.
Finally, the power supplies VDD and VIO of the AD7946
should be decoupled with ceramic capacitors (typically 100 nF)
placed close to the AD7946 and connected using short and wide
traces to provide low impedance paths and reduce the effect of
glitches on the power supply lines.
An example of layout following these rules is shown in
Figure 45 and Figure 46.
EVALUATING THE AD7946’S PERFORMANCE
Other recommended layouts for the AD7946 are outlined
in the documentation of the evaluation board for the AD7946
(EVAL-AD7946CB). The evaluation board package includes a
fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-CONTROL BRD3.
Figure 46. Example of Layout of the AD7946 (Bottom Layer)
Rev. A | Page 23 of 24
AD7946
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
6
5.15
4.90
4.65
3.10
3.00
2.90
1
5
PIN 1
0.50 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.05
0.33
0.17
SEATING
PLANE
0.23
0.08
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 47.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
0.30
0.23
0.18
3.00
BSC SQ
0.50 BSC
10
6
5
PIN 1 INDEX
1.74
1.64
1.49
*
EXPOSED
PAD
AREA
(BOTTOM VIEW)
0.50
0.40
0.30
1
PIN 1
INDICATOR
(R 0.19)
TOP VIEW
2.48
2.38
2.23
0.80 MAX
0.55 NOM
0.80
0.75
0.70
0.05 MAX
0.02 NOM
*
PADDLE CONNECTED TO GND.
THIS CONNECTION IS NOT
REQUIRED TO MEET THE
SEATING
PLANE
ELECTRICAL PERFORMANCES
0.20 REF
Figure 48. 10-Lead Lead Frame Chip Scale Package [QFN (LFCSP_WD)]
3 mm × 3 mm Body, Very Very Thin, Dual Lead (CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7946BRM
AD7946BRM-RL7
AD7946BRMZ1
AD7946BRMZRL71
AD7946BCPZRL71
AD7946BCPZRL1
EVAL-AD7946CBZ1, 2
EVAL-CONTROL BRD3Z1, 3
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead QFN (LFCSP_WD)
10-Lead QFN (LFCSP_WD)
Evaluation Board
Evaluation Board
Package Option
RM-10
RM-10
RM-10
RM-10
Ordering Quantity
Tube, 50
Reel, 1,000
Tube, 50
Reel, 1,000
Reel, 1,000
Reel, 5,000
Branding
C1E
C1E
C4X
C4X
CP-10-9
CP-10-9
C4X
C4X
1 Z = RoHS Compliant Part.
2 This board can be used as a standalone evaluation board or in conjunction with the EVAL-CONTROL BRD3Z for evaluation/demonstration purposes.
3 This board allows a PC to control and communicate with all Analog Devices, Inc. evaluation boards ending in the CB designator.
©2005–2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04656-0-12/07(A)
Rev. A | Page 24 of 24
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