AD7690BCPZRL7 [ADI]
18-Bit, 1.5 LSB INL, 400 kSPS PulSAR® Differential ADC in MSOP/QFN;
| 型号： | AD7690BCPZRL7 |
| 厂家： | 
ADI |
| 描述： | 18-Bit, 1.5 LSB INL, 400 kSPS PulSAR® Differential ADC in MSOP/QFN 光电二极管 转换器 |
| 文件： | 总25页 (文件大小：670K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
18-Bit, 1.5 LSB INL, 400 kSPS PulSAR®
Differential ADC in MSOP/LFCSP
Data Sheet
AD7690
FEATURES
APPLICATION EXAMPLE
+2.5V TO +5V
+5V
18-bit resolution with no missing codes
Throughput: 400 kSPS
INL: 0.7ꢀ LSB typical, 1.ꢀ LSB maximum ꢁ 6 ppm of FSRꢂ
Dynamic range: 102 dB at 400 kSPS
Oversampled dynamic range: 12ꢀ dB at 1 kSPS
Noise-free code resolution: 20 bits at 1 kSPS
Effective resolution: 22.7 bits at 1 kSPS
SINAD: 101.ꢀ dB at 1 kHz
VIO
SDI
+1.8V TO VDD
REF VDD
GND
IN+
IN–
3- OR 4-WIRE
SCK
SDO
CNV
INTERFACE
±10V, ±5V, ...
(SPI, DAISY CHAIN, CS)
ADA4941-1
AD7690
THD: −12ꢀ dB at 1 kHz
Figure 2.
True differential analog input range: VREF
0 V to VREF with VREF up to VDD on both inputs
No pipeline delay
Table 1. MSOP, LFCSP/SOT-23 14-/16-/18-Bit PulSAR ADC
400 kSPS
100
kSPS
2ꢀ0
kSPS
to
ꢀ00 kSPS kSPS
1000
ADC
Driver
Single-supply ꢀ V operation with
1.8 V/2.ꢀ V/3 V/ꢀ V logic interface
Proprietary serial interface
Type
18-Bit True
Differential
AD7691 AD7690
AD7982
AD7982 ADA4941
ADA4841
SPI/QSPI/MICROWIRE™/DSP compatible
Daisy-chain multiple ADCs and busy indicator
Power dissipation
4.2ꢀ μW at 100 SPS
4.2ꢀ mW at 100 kSPS
16-Bit True
Differential
AD7684 AD7687 AD7688
AD7693
ADA4941
ADA4841
16-Bit Pseudo AD7680 AD7685 AD7686
Differential AD7683 AD7694
AD7980 ADA4841
14-Bit Pseudo AD7940 AD7942 AD7946
Differential
ADA4841
Standby current: 1 nA
10-lead package: MSOP ꢁMSOP-8 sizeꢂ and
3 mm × 3 mm LFCSP ꢁSOT-23 sizeꢂ
Pin-for-pin compatible with LFCSP/MSOP PulSAR ADCs
GENERAL DESCRIPTION
The AD76901 is an 18-bit, successive approximation, analog-to-
digital converter (ADC) that operates from a single power supply,
VDD. It contains a low power, high speed, 18-bit sampling ADC
with no missing codes, an internal conversion clock, and a
versatile serial interface port. On the CNV rising edge, it
samples the voltage difference between the IN+ and IN− pins.
The voltages on these pins swing in opposite phase between 0 V
and REF. The reference voltage, REF, is applied externally and
can be set up to the supply voltage.
APPLICATIONS
Battery-powered equipment
Data acquisition
Seismic data acquisition systems
DVMs
Instrumentation
Medical instruments
1.5
POSITIVE INL = +0.42LSB
NEGATIVE INL = –0.6LSB
The power of the AD7690 scales linearly with the throughput.
1.0
0.5
The SPI-compatible serial interface also features the ability,
using the SDI input, to daisy-chain several ADCs on a single,
3-wire bus and provides an optional busy indicator. It is compatible
with 1.8 V, 2.5 V, 3 V, or 5 V logic, using the separate VIO supply.
0
The AD7690 is housed in a 10-lead MSOP or a 10-lead LFCSP
with operation specified from −40°C to +85°C.
–0.5
–1.0
–1.5
1 Protected by U.S. Patent 6,703,961.
0
65536
131072
CODE
196608
262144
Figure 1. Integral Nonlinearity vs. Code
Rev. C
Document Feedback
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Tel: 781.329.4700 ©2006–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD7690* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
View a parametric search of comparable parts.
REFERENCE MATERIALS
Technical Articles
• MS-1779: Nine Often Overlooked ADC Specifications
• MS-2210: Designing Power Supplies for High Speed ADC
Tutorials
EVALUATION KITS
• AD7690 Evaluation Kit
• Precision ADC PMOD Compatible Boards
• MT-074: Differential Drivers for Precision ADCs
DOCUMENTATION
Application Notes
DESIGN RESOURCES
• AD7690 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
• AN-931: Understanding PulSAR ADC Support Circuitry
• AN-932: Power Supply Sequencing
Data Sheet
• AD7690: 18-Bit, 1.5 LSB INL, 400 kSPS PulSAR® Differential
ADC in MSOP/QFN Data Sheet
DISCUSSIONS
View all AD7690 EngineerZone Discussions.
User Guides
• UG-340: Evaluation Board for the 10-Lead Family 14-/16-/
18-Bit PulSAR ADCs
SAMPLE AND BUY
Visit the product page to see pricing options.
• UG-682: 6-Lead SOT-23 ADC Driver for the 8-/10-Lead
Family of 14-/16-/18-Bit PulSAR ADC Evaluation Boards
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
SOFTWARE AND SYSTEMS REQUIREMENTS
• AD7690 FMC-SDP Interposer & Evaluation Board / Xilinx
KC705 Reference Design
• BeMicro FPGA Project for AD7690 with Nios driver
DOCUMENT FEEDBACK
Submit feedback for this data sheet.
TOOLS AND SIMULATIONS
• AD7685 IBIS Models
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AD7690
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Driver Amplifier Choice ........................................................... 14
Single-to-Differential Driver .................................................... 15
Voltage Reference Input ............................................................ 15
Power Supply............................................................................... 16
Supplying the ADC from the Reference.................................. 16
Digital Interface.......................................................................... 16
Applications....................................................................................... 1
Application Example ........................................................................ 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Specifications....................................................................... 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Terminology ...................................................................................... 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 12
Circuit Information.................................................................... 12
Converter Operation.................................................................. 12
Typical Connection Diagram.................................................... 13
Analog Inputs.............................................................................. 14
CS
CS
CS
CS
Mode, 3-Wire Without Busy Indicator ............................. 17
Mode, 3-Wire With Busy Indicator ................................... 18
Mode, 4-Wire Without Busy Indicator ............................. 19
Mode, 4-Wire With Busy Indicator ................................... 20
Chain Mode Without Busy Indicator ...................................... 21
Chain Mode with Busy Indicator............................................. 22
Application Hints ........................................................................... 23
Layout .......................................................................................... 23
Evaluating the AD7690 Performance...................................... 23
Outline Dimensions....................................................................... 24
Ordering Guide .......................................................................... 24
REVISION HISTORY
7/14—Rev. B to Rev. C
Changes to Gain Error in Table 2....................................................3
Change to Gain Error Temperature Drift in Table 2 ....................3
Change to Zero Temperature Drift in Table 2...............................3
Changes to Power Dissipation in Table 3.......................................4
Change to Conversion Time: CNV Rising Edge to Data
Available in Table 4............................................................................5
Change to Acquisition Time in Table 4..........................................5
Changes to Figure 12.........................................................................9
Change to Figure 22 Caption........................................................ 11
Changes to Circuit Information Section ..................................... 12
Change to Table 7 ........................................................................... 13
Change to Endnote 1 of Figure 26................................................ 13
Added Figure 29 ............................................................................. 14
Changes to Driver Amplifier Choice Section............................. 14
Change to Evaluating the AD7690’s Performance Section....... 23
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide.......................................................... 24
Changed QFN (LFCSP) to LFCSP .............................. Throughout
Changes to Features Section............................................................ 1
Added Patent Note, Note 1.............................................................. 1
Changes to Evaluating the AD7690 Performance Section........ 23
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
7/11—Rev. A to Rev. B
Changes to Common-Mode Input Range Min Parameter ......... 3
Added EPAD Note to Figure 6 and Table 6................................... 7
Updated Outline Dimensions....................................................... 24
Changes to Ordering Guide .......................................................... 24
3/07—Rev. 0 to Rev. A
Removed Endnote Regarding QFN Package ..................Universal
Changes to Features.......................................................................... 1
Changes to Table 1............................................................................ 1
Changes to Figure 2.......................................................................... 1
4/06—Revision 0: Initial Version
Rev. C | Page 2 of 24
Data Sheet
AD7690
SPECIFICATIONS
VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Conditions
Min
Typ
Max
Unit
RESOLUTION
18
Bits
ANALOG INPUT
Voltage Range
IN+ to IN−
−VREF
+VREF
V
Absolute Input Voltage
Common-Mode Input Range
Analog Input CMRR
Leakage Current at 25°C
Input Impedance1
THROUGHPUT
IN+, IN−
IN+, IN−
fIN = 250 kHz
Acquisition phase
−0.1
VREF/2 − 0.1
VREF + 0.1
VREF/2 + 0.1
V
V
dB
nA
VREF/2
65
1
Conversion Rate
Transient Response
ACCURACY
No Missing Codes
Integral Linearity Error
Differential Linearity Error
Transition Noise
Gain Error3
Gain Error Temperature Drift
Zero Error3
Zero Temperature Drift
Power Supply Sensitivity
0
400
400
kSPS
ns
Full-scale step
REF = VDD = 5 V
VDD = 5 V ± 5%
18
−1.5
−1
Bits
LSB2
LSB
LSB
LSB
ppm/°C
mV
ppm/°C
LSB
0.75
0.5
0.75
2
+1.5
+1.25
−40
+40
0.3
−0.8
+0.8
0.3
0.25
AC ACCURACY
Dynamic Range
Oversampled Dynamic Range5
Signal-to-Noise
VREF = 5 V
fIN= 1 kSPS
101
102
125
dB4
dB
dB
dB
dB
dB
dB
dB
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 2.5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 5 V
fIN = 1 kHz, VREF = 5 V
100
94.5
101.5
96
−125
−125
101.5
115
Spurious-Free Dynamic Range
Total Harmonic Distortion
Signal-to-(Noise + Distortion)
Intermodulation Distortion6
100
1 See the Analog Inputs section.
2 LSB means least significant bit. With the 5 V input range, one LSB is 38.15 µV.
3 See the Terminology section. These specifications include full temperature range variation but not the error contribution from the external reference.
4 All specifications in dB are referred to a full-scale input FSR. Tested with an input signal at 0.5 dB below full scale, unless otherwise specified.
5 Dynamic range obtained by oversampling the ADC running at a throughput fS of 400 kSPS, followed by postdigital filtering with an output word rate fO.
6 fIN1 = 21.4 kHz and fIN2 = 18.9 kHz, with each tone at −7 dB below full scale.
Rev. C | Page 3 of 24
AD7690
Data Sheet
VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
REFERENCE
Voltage Range
Load Current
SAMPLING DYNAMICS
−3 dB Input Bandwidth
Aperture Delay
DIGITAL INPUTS
Logic Levels
VIL
Conditions
Min
Typ
Max
Unit
0.5
VDD + 0.3
V
µA
400 kSPS, REF = 5 V
VDD = 5 V
100
9
2.5
MHz
ns
−0.3
0.7 × VIO
−1
+0.3 × VIO
VIO + 0.3
+1
V
V
µA
µA
VIH
IIL
IIH
−1
+1
DIGITAL OUTPUTS
Data Format
Pipeline Delay
Serial 18 bits, twos complement
Conversion results available immediately
after completed conversion
VOL
VOH
ISINK = +500 µA
ISOURCE = −500 µA
0.4
V
V
VIO − 0.3
POWER SUPPLIES
VDD
VIO
VIO Range
Standby Current1, 2
Power Dissipation
Specified performance
Specified performance
4.75
2.3
1.8
5.25
V
V
V
nA
µW
mW
mW
VDD + 0.3
VDD + 0.3
50
VDD and VIO = 5 V, 25°C
1
VDD = 5 V, 100 SPS throughput
VDD = 5 V, 100 kSPS throughput
VDD = 5 V, 400 kSPS throughput
4.25
4.25
17
5
20
Energy per Conversion
TEMPERATURE RANGE3
Specified Performance
50
nJ/sample
TMIN to TMAX
−40
+85
°C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact an Analog Devices, Inc., sales representative for the extended temperature range.
Rev. C | Page 4 of 24
Data Sheet
AD7690
TIMING SPECIFICATIONS
VDD = 4.75 V to 5.25 V, VIO = 2.3 V to VDD, VREF = VDD, all specifications TMIN to TMAX, unless otherwise noted.
Table 4.1
Parameter
Symbol
tCONV
tACQ
tCYC
tCNVH
tSCK
Min
0.5
400
2.5
10
Typ
Max
Unit
µs
ns
µs
ns
Conversion Time: CNV Rising Edge to Data Available
Acquisition Time
Time Between Conversions
2.1
CNV Pulse Width (CS Mode)
SCK Period (CS Mode)
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
SCK Low Time
SCK High Time
SCK Falling Edge to Data Remains Valid
SCK Falling Edge to Data Valid Delay
VIO Above 4.5 V
17
18
19
20
7
ns
ns
ns
ns
ns
ns
ns
tSCKL
tSCKH
tHSDO
tDSDO
7
4
14
15
16
17
ns
ns
ns
ns
VIO Above 3 V
VIO Above 2.7 V
VIO Above 2.3 V
CNV or SDI Low to SDO D17 MSB Valid (CS Mode)
VIO Above 4.5 V
VIO Above 2.7 V
tEN
15
18
22
25
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
VIO Above 2.3 V
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
SDI Valid Setup Time from CNV Rising Edge (CS Mode)
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
SDI High to SDO High (Chain Mode with BUSY Indicator)
VIO Above 4.5 V
tDIS
tSSDICNV
tHSDICNV
tSSCKCNV
tHSCKCNV
tSSDISCK
tHSDISCK
tDSDOSDI
15
0
5
10
3
4
15
26
ns
ns
VIO Above 2.3 V
1 See Figure 3 and Figure 4 for load conditions.
70% VIO
500µA
I
OL
30% VIO
tDELAY
tDELAY
1
1
2V OR VIO – 0.5V
2V OR VIO – 0.5V
1.4V
TO SDO
2
2
0.8V OR 0.5V
0.8V OR 0.5V
C
L
50pF
NOTES:
1. 2V IF VIO ABOVE 2.5V, VIO– 0.5V IF VIO BELOW 2.5V.
2. 0.8V IF VIO ABOVE 2.5V, 0.5V IF VIO BELOW 2.5V.
500µA
I
OH
Figure 3. Load Circuit for Digital Interface Timing
Figure 4. Voltage Levels for Timing
Rev. C | Page 5 of 24
AD7690
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Analog Inputs
IN+,1 IN−1
Rating
GND − 0.3 V to VDD + 0.3 V
or 130 mA
GND − 0.3 V to VDD + 0.3 V
REF
Supply Voltages
VDD, VIO to GND
VDD to VIO
Digital Inputs to GND
Digital Outputs to GND
Storage Temperature Range
Junction Temperature
−0.3 V to +7 V
7 V
−0.3 V to VIO + 0.3 V
−0.3 V to VIO + 0.3 V
−65°C to +150°C
150°C
ESD CAUTION
θJA Thermal Impedance
(10-Lead MSOP)
200°C/W
θJC Thermal Impedance
(10-Lead MSOP)
44°C/W
Lead Temperature Range
JEDEC J-STD-20
1 See the Analog Inputs section.
Rev. C | Page 6 of 24
Data Sheet
AD7690
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
REF
VDD
IN+
1
2
3
4
5
10 VIO
9
8
7
6
SDI
AD7690
TOP VIEW
(Not to Scale)
SCK
SDO
CNV
IN–
REF
VDD
IN+
1
2
3
4
5
10 VIO
GND
9
8
7
6
SDI
AD7690
TOP VIEW
(Not to Scale)
SCK
SDO
CNV
NOTES
1. THE EXPOSED PAD IS NOT CONNECTED
IN–
INTERNALLY. FOR INCREASED RELIABILITY OF
THE SOLDER JOINTS, IT IS RECOMMENDED THAT
THE PAD BE SOLDERED TO THE GROUND PLANE.
GND
Figure 5. 10-Lead MSOP Pin Configuration
Figure 6. 10-Lead LFCSP Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Type1
Description
1
REF
AI
Reference Input Voltage. The REF range is from 0.5 V to VDD. It is referred to the GND pin. This
pin should be decoupled closely to the pin with a 10 μF capacitor.
2
3
4
5
6
VDD
IN+
IN−
GND
CNV
P
Power Supply.
AI
AI
P
Differential Positive Analog Input.
Differential Negative Analog Input.
Power Supply Ground.
Convert Input. This input has multiple functions. On its leading edge, it initiates the conversions
and selects the interface mode of the part, chain or CS mode. In CS mode, the SDO pin is
enabled when CNV is low. In chain mode, the data should be read when CNV is high.
DI
7
8
9
SDO
SCK
SDI
DO
DI
DI
Serial Data Output. The conversion result is output on this pin. It is synchronized to SCK.
Serial Data Clock Input. When the part is selected, the conversion result is shifted out by this clock.
Serial Data Input. This input provides multiple features. It selects the interface mode of the ADC
as follows:
Chain mode is selected if SDI is low during the CNV rising edge. In this mode, SDI is used as a
data input to daisy-chain the conversion results of two or more ADCs onto a single SDO line.
The digital data level on SDI is output on SDO with a delay of 18 SCK cycles.
CS mode is selected if SDI is high during the CNV rising edge. In this mode, either SDI or CNV
can enable the serial output signals when low. If SDI or CNV is low when the conversion is
complete, the busy indicator feature is enabled.
10
VIO
P
Input/Output Interface Digital Power. Nominally at the same supply as the host interface (1.8 V,
2.5 V, 3 V, or 5 V).
EPAD
Exposed Pad. The exposed pad is not connected internally. For increased reliability of the solder
joints, it is recommended that the pad be soldered to the ground plane.
1AI = analog input, DI = digital input, DO = digital output, and P = power.
Rev. C | Page 7 of 24
AD7690
Data Sheet
TERMINOLOGY
and is expressed in bits.
Integral Nonlinearity Error (INL)
INL refers to the deviation of each individual code from a line
drawn from negative full scale through positive full scale. The
point used as negative full scale occurs ½ LSB before the first
code transition. Positive full scale is defined as a level 1½ LSB
beyond the last code transition. The deviation is measured from
the middle of each code to the true straight line (see Figure 25).
Effective Resolution
Effective resolution is calculated as
Effective Resolution = log2(2N/RMS Input Noise)
and is expressed in bits.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal and is
expressed in decibels.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. DNL is the
maximum deviation from this ideal value. It is often specified in
terms of resolution for which no missing codes are guaranteed.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the total rms noise measured with the inputs shorted together.
The value for dynamic range is expressed in decibels.
Zero Error
Zero error is the difference between the ideal midscale voltage,
that is, 0 V, from the actual voltage producing the midscale
output code, that is, 0 LSB.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components that is less than the
Nyquist frequency, excluding harmonics and dc. The value of
SNR is expressed in decibels.
Gain Error
The first transition (from 100 ... 00 to 100 ... 01) should occur at
a level ½ LSB above nominal negative full scale (−4.999981 V
for the 5 V range). The last transition (from 011 … 10 to
011 … 11) should occur for an analog voltage 1½ LSB below the
nominal full scale (+4.999943 V for the 5 V range). The gain
error is the deviation of the difference between the actual level
of the last transition and the actual level of the first transition
from the difference between the ideal levels.
Signal-to-(Noise + Distortion) Ratio (SINAD)
SINAD is the ratio of the rms value of the actual input signal to
the rms sum of all other spectral components below the Nyquist
frequency, including harmonics but excluding dc. The value for
SINAD is expressed in decibels.
Spurious-Free Dynamic Range (SFDR)
Aperture Delay
SFDR is the difference, in decibels, between the rms amplitude
of the input signal and the peak spurious signal.
Aperture delay is the measure of the acquisition performance. It
is the time between the rising edge of the CNV input and when
the input signal is held for a conversion.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input. It is related to SINAD by the following formula:
Transient Response
Transient response is the time required for the ADC to accurately
acquire its input after a full-scale step function is applied.
ENOB = (SINADdB − 1.76)/6.02
and is expressed in bits.
Noise-Free Code Resolution
Noise-free code resolution is the number of bits beyond which it is
impossible to distinctly resolve individual codes. It is calculated as:
Noise-Free Code Resolution = log2(2N/Peak-to-Peak Noise)
Rev. C | Page 8 of 24
Data Sheet
AD7690
TYPICAL PERFORMANCE CHARACTERISTICS
1.0
0.5
1.5
POSITIVE INL = +0.42LSB
NEGATIVE INL = –0.6LSB
1.0
0.5
0
0
–0.5
–1.0
–1.5
–0.5
–1.0
0
65536
131072
CODE
196608
262144
0
65536
131072
CODE
196608
262144
Figure 7. Integral Nonlinearity vs. Code
Figure 10. Differential Nonlinearity vs. Code
80k
60k
VDD = REF = 5V
VDD = REF = 5V
53936
52500
67198
70k
60k
50k
40k
30k
20k
10k
0
50k
40k
30k
20k
10k
0
31666
27546
12623
11212
1991
2614
59
533
263
0
0
39
58
18
0
0
0
0
2
3
0
0
55
57
5A 5B 5C 5D 5E
CODE IN HEX
5F
60
31 32 33 34 35 36 37 38 39 3A 3B 3C
CODE IN HEX
Figure 8. Histogram of a DC Input at the Code Center
Figure 11. Histogram of a DC Input at the Code Transition
105
104
103
102
101
100
99
–110
0
–20
fS = 400kSPS
fIN = 1.99kHz
SNR = 101.4dB
THD = –122dB
SFDR = 130dB
SINAD = 101.3dB
–112
–114
–116
–118
–120
–122
–124
–126
–128
–130
–40
–60
SNR
–80
–100
–120
–140
–160
–180
98
97
THD
96
95
–10
–8
–6
–4
–2
0
0
20
40
60
80
100 120 140 160 180 200
INPUT LEVEL (dB)
FREQUENCY (kHz)
Figure 9. Fast Fourier Transform Plot
Figure 12. SNR, THD vs. Input Level
Rev. C | Page 9 of 24
AD7690
Data Sheet
104
102
100
98
20
19
18
17
16
15
14
–100
–105
–110
–115
–120
–125
135
SNR
130
125
120
115
110
SFDR
SINAD
ENOB
96
94
THD
3.5
92
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
2.3
2.7
3.1
3.9
4.3
4.7
5.1
5.5
REFERENCE VOLTAGE (V)
REFERENCE VOLTAGE (V)
Figure 13. SNR, SINAD, and ENOB vs. Reference Voltage
Figure 16. THD, SFDR vs. Reference Voltage
103
102
101
100
99
–90
–100
–110
–120
–130
V
= 5V
V
= 5V
REF
REF
98
97
96
95
–55
–35
–15
5
25
45
65
85
105
125
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. SNR vs. Temperature
Figure 17. THD vs. Temperature
105
100
95
–60
–70
V
= 5V, –10dB
REF
V
= 5V, –1dB
–80
REF
90
–90
85
V
= 5V, –1dB
REF
–100
–110
–120
–130
80
V
= 5V, –10dB
REF
75
70
65
0
50
100
FREQUENCY (kHz)
150
200
0
50
100
FREQUENCY (kHz)
150
200
Figure 15. SINAD vs. Frequency
Figure 18. THD vs. Frequency
Rev. C | Page 10 of 24
Data Sheet
AD7690
1000
6
4
fS = 100kSPS
VDD
GAIN ERROR
750
500
250
0
2
0
–2
–4
–6
ZERO ERROR
85 105
VIO
4.50
4.75
5.00
SUPPLY (V)
5.25
5.50
–55
–35
–15
5
25
45
65
125
TEMPERATURE (°C)
Figure 19. Operating Current vs. Supply
Figure 22. Zero and Gain Error vs. Temperature
25
20
15
10
5
1000
750
500
250
0
VDD = 5V, 85°C
VDD = 5V, 25°C
VDD + VIO
0
–55
–35
–15
5
25
45
65
85
105
125
0
20
40
60
80
100
120
TEMPERATURE (°C)
SDO CAPACITIVE LOAD (pF)
Figure 20. Power-Down Current vs. Temperature
Figure 23. tDSDO Delay vs. Capacitance Load and Supply
1000
750
500
250
–6
fS = 100kSPS
VDD
VIO
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 21. Operating Current vs. Temperature
Rev. C | Page 11 of 24
AD7690
Data Sheet
THEORY OF OPERATION
IN+
SWITCHES CONTROL
CONTROL
MSB
LSB
LSB
SW+
SW–
131,072C 65,536C
4C
4C
2C
2C
C
C
C
C
BUSY
REF
COMP
LOGIC
GND
OUTPUT CODE
131,072C 65,536C
MSB
CNV
IN–
Figure 24. ADC Simplified Schematic
CIRCUIT INFORMATION
CONVERTER OPERATION
The AD7690 is a fast, low power, single-supply, precise, 18-bit
ADC using a successive approximation architecture.
The AD7690 is a successive approximation ADC based on a
charge redistribution DAC. Figure 24 shows the simplified
schematic of the ADC. The capacitive DAC consists of two
identical arrays of 18 binary-weighted capacitors, which are
connected to the two comparator inputs.
The AD7690 is capable of converting 400,000 samples per
second (400 kSPS) and powers down between conversions.
When operating at 1 kSPS, for example, it consumes 50 µW
typically, ideal for battery-powered applications.
During the acquisition phase, terminals of the array tied to the
comparator’s input are connected to GND via SW+ and SW−.
All independent switches are connected to the analog inputs.
Thus, the capacitor arrays are used as sampling capacitors and
acquire the analog signal on the IN+ and IN− inputs. When the
acquisition phase is complete and the CNV input goes high, a
conversion phase is initiated. When the conversion phase
begins, SW+ and SW− are opened first. The two capacitor
arrays are then disconnected from the inputs and connected to
the GND input. Therefore, the differential voltage between the
IN+ and IN− inputs captured at the end of the acquisition phase
is applied to the comparator inputs, causing the comparator to
become unbalanced. By switching each element of the capacitor
array between GND and REF, the comparator input varies by
binary-weighted voltage steps (VREF/2, VREF/4 ... VREF/262,144).
The control logic toggles these switches, starting with the MSB,
to bring the comparator back into a balanced condition. After
the completion of this process, the part returns to the
The AD7690 provides the user with an on-chip track-and-hold
and does not exhibit pipeline delay or latency, making it ideal
for multiple multiplexed channel applications.
The AD7690 is specified from 4.75 V to 5.25 V and can be
interfaced to any 1.8 V to 5 V digital logic family. It is housed in
a 10-lead MSOP or a tiny 10-lead LFCSP that allows space
savings and flexible configurations.
It is pin-for-pin compatible with the 18-bit AD7691 and AD7982
and the 16-bit AD7687, AD7688, and AD7693.
acquisition phase, and the control logic generates the ADC
output code and a busy signal indicator.
Because the AD7690 has an on-board conversion clock, the
serial clock, SCK, is not required for the conversion process.
Rev. C | Page 12 of 24
Data Sheet
AD7690
Transfer Functions
Table 7. Output Codes and Ideal Input Voltages
Analog Input
VREF = 5 V
Digital Output
Code (Hex)
The ideal transfer characteristic for the AD7690 is shown in
Figure 25 and Table 7.
Description
FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
+4.999962 V
+38.15 µV
0 V
−38.15 µV
−4.999962 V
−5 V
0x1FFFF1
0x00001
0x00000
0x3FFFF
0x20001
0x200002
011...111
011...110
011...101
1 This is also the code for an overranged analog input (VIN+ − VIN− above VREF − VGND).
2 This is also the code for an underranged analog input (VIN+ − VIN− below VGND).
TYPICAL CONNECTION DIAGRAM
100...010
100...001
100...000
Figure 26 shows an example of the recommended connection
diagram for the AD7690 when multiple supplies are available.
–FSR
–FSR + 1LSB
+FSR – 1LSB
+FSR – 1.5LSB
–FSR + 0.5LSB
ANALOG INPUT
Figure 25. ADC Ideal Transfer Function
1
V+
V+
REF
5V
2
10µF
100nF
1.8V TO VDD
100nF
15Ω
REF
VDD
VIO
SDI
0 TO V
REF
IN+
IN–
2.7nF
4
3
ADA4841-2
SCK
V–
V+
5
AD7690
3- OR 4-WIRE INTERFACE
SDO
CNV
GND
15Ω
V
TO 0
REF
2.7nF
4
3
ADA4841-2
V–
1
SEE VOLTAGE REFERENCE INPUT SECTION FOR REFERENCE SELECTION.
2
3
4
5
C
IS USUALLY A 10µF CERAMIC CAPACITOR (X5R).
REF
SEE TABLE 8 FOR ADDITIONAL RECOMMENDED AMPLIFIERS.
OPTIONAL FILTER. SEE ANALOG INPUT SECTION.
SEE THE DIGITAL INTERFACE SECTION FOR MOST CONVENIENT INTERFACE MODE.
Figure 26. Typical Application Diagram with Multiple Supplies
Rev. C | Page 13 of 24
AD7690
Data Sheet
When the source impedance of the driving circuit is low, the
AD7690 can be driven directly. Large source impedances
significantly affect the ac performance, especially total
harmonic distortion (THD). The dc performances are less
sensitive to the input impedance. The maximum source
impedance depends on the amount of THD that can be
tolerated. The THD degrades as a function of the source
impedance and the maximum input frequency.
–80
ANALOG INPUTS
Figure 27 shows an equivalent circuit of the input structure of
the AD7690.
The two diodes, D1 and D2, provide ESD protection for the
analog inputs, IN+ and IN−. Care must be taken to ensure that
the analog input signal does not exceed the supply rails by more
than 0.3 V because this causes the diodes to become forward
biased and start conducting current. These diodes can handle a
forward-biased current of 130 mA maximum. For instance, these
conditions could eventually occur when the input buffer’s (U1)
supplies are different from VDD. In such a case (for example, an
input buffer with a short circuit), the current limitation can be
used to protect the part.
V
= VDD 5V
REF
–85
–90
–95
250Ω
100Ω
–100
–105
–110
–115
–120
–125
–130
VDD
33Ω
D1
D2
C
IN
R
IN
IN+
OR IN–
15Ω
50Ω
C
PIN
GND
Figure 27. Equivalent Analog Input Circuit
0
10
20
30
40
50
60
70
80
90
FREQUENCY (kHz)
The analog input structure allows the sampling of the true
differential signal between IN+ and IN−. By using these
differential inputs, signals common to both inputs are rejected.
90
Figure 29. THD vs. Analog Input Frequency and Source Resistance
DRIVER AMPLIFIER CHOICE
V
= VDD = 5V
REF
Although the AD7690 is easy to drive, the driver amplifier must
meet the following requirements:
85
80
75
70
65
60
55
50
45
40
•
The noise generated by the driver amplifier must be kept
as low as possible to preserve the SNR and transition noise
performance of the AD7690. The noise from the driver is
filtered by the AD7690 analog input circuit’s 1-pole, low-
pass filter made by RIN and CIN or by the external filter,
if one is used. Because the typical noise of the AD7690 is
28 µV rms, the SNR degradation due to the amplifier is
28
SNRLOSS = 20 log
1
10
100
1000
10000
π
π
282 + f−3 dB (NeN+
)
+
f−3 dB (NeN− )
2
2
FREQUENCY (kHz)
2
2
Figure 28. Analog Input CMRR vs. Frequency
where:
During the acquisition phase, the impedance of the analog
inputs (IN+ and IN−) can be modeled as a parallel combination
of the capacitor, CPIN, and the network formed by the series
connection of RIN and CIN. CPIN is primarily the pin capacitance.
RIN is typically 600 Ω and is a lumped component composed
of serial resistors and the on resistance of the switches. CIN is
typically 30 pF and is mainly the ADC sampling capacitor.
f−3 dB is the input bandwidth in megahertz of the AD7690
(9 MHz) or the cutoff frequency of the input filter, if one is
used.
N is the noise gain of the amplifier (for example, 1 in
buffer configuration).
e
N+ and eN− are the equivalent input noise voltage densities
of the op amps connected to IN+ and IN−, in nV/√Hz.
During the conversion phase, where the switches are opened,
the input impedance is limited to CPIN. RIN and CIN make a
1-pole, low-pass filter that reduces undesirable aliasing effects
and limits the noise.
This approximation can be used when the resistances
around the amplifiers are small. If larger resistances are
used, their noise contributions should also be root
summed squared.
•
For ac applications, the driver should have a THD
performance commensurate with the AD7690.
Rev. C | Page 14 of 24
Data Sheet
AD7690
R5
R3
R6
R4
For multichannel multiplexed applications, the driver
amplifier and the AD7690 analog input circuit must settle
for a full-scale step onto the capacitor array at an 18-bit
level (0.0004%, 4 ppm). In the amplifier’s data sheet, settling
at 0.1% to 0.01% is more commonly specified. This may
differ significantly from the settling time at an 18-bit level
and should be verified prior to driver selection.
+5V REF
+5.2V
10µF
+5.2V
100nF
100nF
15Ω
15Ω
REF
VDD
IN+
2.7nF
2.7nF
AD7690
IN–
Table 8. Recommended Driver Amplifiers
GND
Amplifier
ADA4941-1
ADA4841-x
AD8655
Typical Application
ADA4941
Very low noise, low power single to differential
Very low noise, small, and low power
5 V single supply, low noise
±10V, ±5V, ...
R1
R2
AD8021
AD8022
OP184
Very low noise and high frequency
Low noise and high frequency
Low power, low noise, and low frequency
C
F
Figure 30. Single-Ended-to-Differential Driver Circuit
AD8605, AD8615 5 V single supply, low power
VOLTAGE REFERENCE INPUT
The AD7690 voltage reference input, REF, has a dynamic input
impedance and should therefore be driven by a low impedance
source with efficient decoupling between the REF and GND
pins, as explained in the Layout section.
SINGLE-TO-DIFFERENTIAL DRIVER
For applications using a single-ended analog signal, either bipolar
or unipolar, the ADA4941-1 single-ended-to-differential driver
allows for a differential input into the part. The schematic is
shown in Figure 30.
When REF is driven by a very low impedance source (for
example, a reference buffer using the AD8031 or the AD8605),
a 10 μF (X5R, 0805 size) ceramic chip capacitor is appropriate
for optimum performance.
R1 and R2 set the attenuation ratio between the input range and
the ADC range (VREF). R1, R2, and CF are chosen depending on
the desired input resistance, signal bandwidth, antialiasing, and
noise contribution. For example, for the 10 V range with a 4 kΩ
impedance, R2 = 1 kΩ and R1 = 4 kΩ.
If an unbuffered reference voltage is used, the decoupling value
depends on the reference used. For instance, a 22 μF (X5R,
1206 size) ceramic chip capacitor is appropriate for optimum
performance using a low temperature drift ADR43x reference.
R3 and R4 set the common mode on the IN− input, and R5 and
R6 set the common mode on the IN+ input of the ADC. The
common mode should be set close to VREF/2; however, if single
supply is desired, it can be set slightly above VREF/2 to provide
some headroom for the ADA4941-1 output stage. For example,
for the 10 V range with a single supply, R3 = 8.45 kΩ, R4 =
11.8 kΩ, R5 = 10.5 kΩ, and R6 = 9.76 kΩ.
If desired, a reference-decoupling capacitor with a value as small
as 2.2 μF can be used with a minimal impact on performance,
especially DNL.
Regardless, there is no need for an additional lower value
ceramic decoupling capacitor (for example, 100 nF) between the
REF and GND pins.
Rev. C | Page 15 of 24
AD7690
Data Sheet
POWER SUPPLY
5V
5V
The AD7690 uses two power supply pins: a core supply, VDD, and
a digital input/output interface supply, VIO. VIO allows a direct
interface with any logic between 1.8 V and VDD. To reduce the
number of supplies needed, the VIO and VDD pins can be tied
together. The AD7690 is independent of power supply sequencing
between VIO and VDD. Additionally, it is very insensitive to power
supply variations over a wide frequency range, as shown in Figure 31.
95
10Ω
5V 10kΩ
1µF
AD8031 10µF
1µF
1
REF
VDD
VIO
AD7690
1
OPTIONAL REFERENCE BUFFER AND FILTER.
Figure 33. Example of Application Circuit
90
85
80
75
70
65
DIGITAL INTERFACE
Though the AD7690 has a reduced number of pins, it offers
flexibility in its serial interface modes.
CS
When in
mode, the AD7690 is compatible with SPI, QSPI™,
digital hosts, and DSPs, for example, Blackfin® ADSP-BF53x or
ADSP-219x. In this mode, the AD7690 can use either a 3-wire
or 4-wire interface. A 3-wire interface using the CNV, SCK, and
SDO signals minimizes wiring connections useful, for instance,
in isolated applications. A 4-wire interface using the SDI, CNV,
SCK, and SDO signals allows CNV, which initiates the conversions,
to be independent of the readback timing (SDI). This is useful
in low jitter sampling or simultaneous sampling applications.
1
10
100
1000
10000
FREQUENCY (kHz)
Figure 31. PSRR vs. Frequency
The AD7690 powers down automatically at the end of each
conversion phase and, therefore, the power scales linearly with
the sampling rate. This makes the part ideal for low sampling
rates (even of a few hertz) and low battery-powered applications.
10000
When in chain mode, the AD7690 provides a daisy-chain
feature using the SDI input for cascading multiple ADCs on a
single data line similar to a shift register.
The mode in which the part operates depends on the SDI level
CS
when the CNV rising edge occurs. The
mode is selected if
1000
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is selected.
VDD = 5V
100
10
In either mode, the AD7690 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must
timeout the maximum conversion time prior to readback.
VIO
1
0.1
0.01
The busy indicator feature is enabled
0.001
CS
In mode if CNV or SDI is low when the ADC conversion
10
100
1k
10k
100k
1M
ends (see Figure 37 and Figure 41).
In chain mode if SCK is high during the CNV rising edge
(see Figure 45).
SAMPLING RATE (SPS)
Figure 32. Operating Current vs. Sample Rate
SUPPLYING THE ADC FROM THE REFERENCE
For simplified applications, the AD7690, with its low operating
current, can be supplied directly using the reference circuit
shown in Figure 33. The reference line can be driven by
The system power supply directly.
A reference voltage with enough current output capability,
such as the ADR43x.
A reference buffer, such as the AD8031, which can also
filter the system power supply, as shown in Figure 33.
Rev. C | Page 16 of 24
Data Sheet
AD7690
before the minimum conversion time elapses and then held
CS MODE, 3-WIRE WITHOUT BUSY INDICATOR
high for the maximum possible conversion time to avoid the
generation of the busy signal indicator. When the conversion is
complete, the AD7690 enters the acquisition phase and powers
down. When CNV goes low, the MSB is output onto SDO. The
remaining data bits are clocked by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the 18th SCK falling edge or when
CNV goes high (whichever occurs first), SDO returns to high
impedance.
This mode is usually used when a single AD7690 is connected
to an SPI-compatible digital host. The connection diagram is
shown in Figure 34, and the corresponding timing is given in
Figure 35.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
conversion, selects the
mode, and forces SDO to high
impedance. Once a conversion is initiated, it continues until
completion irrespective of the state of CNV. This can be useful,
for instance, to bring CNV low to select other SPI devices, such
as analog multiplexers; however, CNV must be returned high
CONVERT
DIGITAL HOST
DATA IN
CNV
VIO
SDI
SDO
AD7690
SCK
CLK
CS
Figure 34. 3-Wire Mode Without Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
16
17
18
tHSDO
tSCKH
tDSDO
tEN
tDIS
SDO
D17
D16
D15
D1
D0
CS
Figure 35. 3-Wire Mode Without Busy Indicator Serial Interface Timing (SDI High)
Rev. C | Page 17 of 24
AD7690
Data Sheet
impedance to low impedance. With a pull-up on the SDO line,
this transition can be used as an interrupt signal to initiate the
data reading controlled by the digital host. The AD7690 then
enters the acquisition phase and powers down. The data bits are
clocked out, MSB first, by subsequent SCK falling edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host using the SCK falling
edge allows a faster reading rate, provided it has an acceptable
hold time. After the optional 19th SCK falling edge or when
CNV goes high (whichever occurs first), SDO returns to high
impedance.
CS MODE, 3-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7690 is connected
to an SPI-compatible digital host having an interrupt input.
The connection diagram is shown in Figure 36, and the
corresponding timing is given in Figure 37.
With SDI tied to VIO, a rising edge on CNV initiates a
CS
conversion, selects the
mode, and forces SDO to high
impedance. SDO is maintained in high impedance until the
completion of the conversion irrespective of the state of CNV.
Prior to the minimum conversion time, CNV can be used to
select other SPI devices, such as analog multiplexers, but CNV
must be returned low before the minimum conversion time
elapses and then held low for the maximum possible conversion
time to guarantee the generation of the busy signal indicator.
When the conversion is complete, SDO goes from high
If multiple AD7690s are selected at the same time, the SDO
output pin handles this contention without damage or induced
latch-up. Meanwhile, it is recommended to keep this contention
as short as possible to limit extra power dissipation.
CONVERT
VIO
47kΩ
DIGITAL HOST
CNV
VIO
DATA IN
IRQ
SDI
SDO
AD7690
SCK
CLK
CS
Figure 36. 3-Wire Mode with Busy Indicator
Connection Diagram (SDI High)
SDI = 1
tCYC
tCNVH
CNV
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
SCK
1
2
3
17
18
19
tHSDO
tSCKH
tDSDO
tDIS
SDO
D17
D16
D1
D0
CS
Figure 37. 3-Wire Mode with Busy Indicator Serial Interface Timing (SDI High)
Rev. C | Page 18 of 24
Data Sheet
AD7690
time elapses and then held high for the maximum possible
CS MODE, 4-WIRE WITHOUT BUSY INDICATOR
conversion time to avoid the generation of the busy signal
indicator. When the conversion is complete, the AD7690 enters
the acquisition phase and powers down. Each ADC result can
be read by bringing its SDI input low, which consequently
outputs the MSB onto SDO. The remaining data bits are clocked
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the 18th SCK
falling edge or when SDI goes high (whichever occurs first), SDO
returns to high impedance and another AD7690 can be read.
This mode is usually used when multiple AD7690s are connected
to an SPI-compatible digital host.
A connection diagram example using two AD7690s is shown in
Figure 38, and the corresponding timing is given in Figure 39.
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned high before the minimum conversion
CS2
CS1
CONVERT
DIGITAL HOST
CNV
CNV
SDI
SDO
SDI
SDO
AD7690
AD7690
SCK
SCK
DATA IN
CLK
CS
Figure 38. 4-Wire Mode Without Busy Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
tSSDICNV
CONVERSION
ACQUISITION
SDI(CS1)
tHSDICNV
SDI(CS2)
SCK
tSCK
tSCKL
1
2
3
16
17
18
19
20
34
35
36
tHSDO
tSCKH
tDSDO
tDIS
tEN
SDO
D17
D16
D15
D1
D0
D17
D16
D1
D0
CS
Figure 39. 4-Wire Mode Without Busy Indicator Serial Interface Timing
Rev. C | Page 19 of 24
AD7690
Data Sheet
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7690
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 19th SCK falling edge or
SDI going high (whichever occurs first), SDO returns to high
impedance.
CS MODE, 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7690 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the analog
input, independent of the signal used to select the data reading.
This independence is particularly important in applications where
low jitter on CNV is desired.
The connection diagram is shown in Figure 40, and the
corresponding timing is given in Figure 41.
With SDI high, a rising edge on CNV initiates a conversion,
CS
selects the
mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
CS1
CONVERT
VIO
47kΩ
DIGITAL HOST
CNV
DATA IN
IRQ
SDI
SDO
AD7690
SCK
CLK
CS
Figure 40. 4-Wire Mode with Busy Indicator Connection Diagram
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSSDICNV
SDI
tSCK
tHSDICNV
tSCKL
SCK
SDO
1
2
3
17
tSCKH
18
19
tHSDO
tDSDO
tDIS
tEN
D17
D16
D1
D0
CS
Figure 41. 4-Wire Mode with Busy Indicator Serial Interface Timing
Rev. C | Page 20 of 24
Data Sheet
AD7690
readback. When the conversion is complete, the MSB is output
onto SDO and the AD7690 enters the acquisition phase and
powers down. The remaining data bits stored in the internal
shift register are clocked by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N clocks are required to
read back the N ADCs. The data is valid on both SCK edges.
Although the rising edge can be used to capture the data, a
digital host using the SCK falling edge allows a faster reading
rate and consequently more AD7690s in the chain, provided the
digital host has an acceptable hold time. The maximum conversion
rate may be reduced due to the total readback time.
CHAIN MODE WITHOUT BUSY INDICATOR
This mode can be used to daisy-chain multiple AD7690s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register.
A connection diagram example using two AD7690s is shown in
Figure 42, and the corresponding timing is given in Figure 43.
When SDI and CNV are low, SDO is driven low. With SCK low,
a rising edge on CNV initiates a conversion, selects the chain
mode, and disables the busy indicator. In this mode, CNV is
held high during the conversion phase and the subsequent data
CONVERT
CNV
CNV
DIGITAL HOST
AD7690
AD7690
SDI
SDO
SDI
SDO
DATA IN
A
B
SCK
SCK
CLK
Figure 42. Chain Mode Without Busy Indicator Connection Diagram
SDI = 0
A
tCYC
CNV
tACQ
tCONV
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSCKL
tSSCKCNV
SCK
1
A
B
2
3
A
B
16
17
18
19
20
34
35
36
tHSCKCNV
tSSDISCK
tSCKH
tHSDISCK
tEN
D
D
17
D
16
D
D
15
15
D
1
1
D
0
SDO = SDI
A
A
A
A
B
tHSDO
tDSDO
17
D
16
D
B
D
0
D
17
D
16
D
1
D 0
A
SDO
B
B
A
A
A
B
Figure 43. Chain Mode Without Busy Indicator Serial Interface Timing
Rev. C | Page 21 of 24
AD7690
Data Sheet
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7690 ADC labeled C in Figure 44) is
driven high. This transition on SDO can be used as a busy
indicator to trigger the data readback controlled by the digital
host. The AD7690 then enters the acquisition phase and powers
down. The data bits stored in the internal shift register are
clocked out, MSB first, by subsequent SCK falling edges. For
each ADC, SDI feeds the input of the internal shift register and
is clocked by the SCK falling edge. Each ADC in the chain
outputs its data MSB first, and 18 × N + 1 clocks are required to
read back the N ADCs. Although the rising edge can be used to
capture the data, a digital host using the SCK falling edge allows
a faster reading rate and consequently more AD7690s in the
chain, provided the digital host has an acceptable hold time.
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7690s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications
or for systems with a limited interfacing capacity. Data readback
is analogous to clocking a shift register.
A connection diagram example using three AD7690s is shown
in Figure 44, and the corresponding timing is given in Figure 45.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
CONVERT
DIGITAL HOST
DATA IN
CNV
CNV
CNV
AD7690
AD7690 SDO
AD7690
SDI
SDO
SDI
SDI
SDO
A
B
C
SCK
SCK
SCK
IRQ
CLK
Figure 44. Chain Mode with Busy Indicator Connection Diagram
tCYC
CNV = SDI
A
tCONV
tACQ
ACQUISITION
CONVERSION
ACQUISITION
tSCK
tSSCKCNV
tSCKH
SCK
1
2
3
A
4
17
18
19
20
21
35
36
37
38
39
53
54
55
tHSCKCNV
tSSDISCK
tSCKL
tDSDOSDI
tHSDISCK
tEN
SDO = SDI
D
17
D
16
D
15
D
1
D 0
A
A
B
A
A
A
tHSDO
tDSDO
tDSDOSDI
tDSDOSDI
tDSDOSDI
SDO = SDI
B
D
17
D
D
16
D
15
B
D
D
1
D
0
D
17
D
16
D 1
A
D 0
A
C
B
B
B
B
A
A
tDSDOSDI
SDO
D
17
16
D
15
1
D
0
D
17
D
16
D
1
D
0
D
17
D
16
D
1
D 0
A
C
C
C
C
C
C
B
B
B
B
A
A
A
Figure 45. Chain Mode with Busy Indicator Serial Interface Timing
Rev. C | Page 22 of 24
Data Sheet
AD7690
APPLICATION HINTS
LAYOUT
The printed circuit board that houses the AD7690 should be
designed so that the analog and digital sections are separated
and confined to certain areas of the board. The pinout of the
AD7690, with its analog signals on the left side and its digital
signals on the right side, eases this task.
Avoid running digital lines under the device because these
couple noise onto the die unless a ground plane under the
AD7690 is used as a shield. Fast switching signals, such as CNV
or clocks, should not run near analog signal paths. Crossover of
digital and analog signals should be avoided.
At least one ground plane should be used. It can be common or
split between the digital and analog sections. In the latter case,
the planes should be joined underneath the AD7690s.
Figure 46. Example Layout of the AD7690 (Top Layer)
The AD7690 voltage reference input REF has a dynamic input
impedance and should be decoupled with minimal parasitic
inductances. This is done by placing the reference decoupling
ceramic capacitor close to, ideally right up against, the REF and
GND pins and connecting them with wide, low impedance traces.
Finally, the AD7690 VDD and VIO power supplies should be
decoupled with ceramic capacitors, typically 100 nF, placed
close to the AD7690 and connected using short, wide traces to
provide low impedance paths and to reduce the effect of glitches
on the power supply lines.
An example of a layout following these rules is shown in
Figure 46 and Figure 47.
EVALUATING THE AD7690 PERFORMANCE
Other recommended layouts for the AD7690 are outlined
in the documentation of the evaluation board (EVAL-
AD7690SDZ). The evaluation board package includes
a fully assembled and tested evaluation board, documentation,
and software for controlling the board from a PC via the
EVAL-SDP-CB1Z.
Figure 47. Example Layout of the AD7690 (Bottom Layer)
Rev. C | Page 23 of 24
AD7690
Data Sheet
OUTLINE DIMENSIONS
3.10
3.00
2.90
10
1
6
5
5.15
4.90
4.65
3.10
3.00
2.90
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.70
0.55
0.40
0.15
0.05
0.23
0.13
6°
0°
0.30
0.15
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 48.10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
2.48
2.38
2.23
3.10
3.00 SQ
0.50 BSC
2.90
10
6
PIN 1 INDEX
EXPOSED
PAD
1.74
1.64
1.49
AREA
0.50
0.40
0.30
0.20 MIN
1
5
BOTTOM VIEW
TOP VIEW
PIN 1
INDICATOR
(R 0.15)
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
SECTION OF THIS DATA SHEET.
SEATING
PLANE
0.30
0.25
0.20
0.20 REF
Figure 49. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm × 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2, 3
Notes Temperature Range Package Description
Package Option Branding Ordering Quantity
AD7690BCPZRL
AD7690BCPZRL7
AD7690BRMZ
AD7690BRMZ-RL7
EVAL-AD7690SDZ
EVAL-SDP-CB1Z
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
Evaluation Board
Controller Board
CP-10-9
CP-10-9
RM-10
C4C
C4C
C4C
C4C
Reel, 5,000
Reel, 1,000
Tube, 50
RM-10
Reel, 1,000
1 Z = RoHS Compliant Part.
2 The EVAL-AD7690SDZ board can be used as a standalone evaluation board or in conjunction with the EVAL-SDP-CB1Z for evaluation/demonstration purposes.
3 The EVAL-SDP-CB1Z allows a PC to control and communicate with all Analog Devices evaluation boards ending in the SD designator.
©2006–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05792-0-7/14(C)
Rev. C | Page 24 of 24
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