AD7280WBCPZ [ADI]
IC 6-CHANNEL POWER SUPPLY SUPPORT CKT, QCC48, LEAD FREE, MO-220WKKD, LFCSP-48, Power Management Circuit;
| 型号： | AD7280WBCPZ |
| 厂家： | 
ADI |
| 描述： | IC 6-CHANNEL POWER SUPPLY SUPPORT CKT, QCC48, LEAD FREE, MO-220WKKD, LFCSP-48, Power Management Circuit |
| 文件： | 总38页 (文件大小：435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Lithium Ion Battery
Monitoring System
AD7280
Preliminary Technical Data
FEATURES
FUNCTIONAL BLOCK DIAGRAM
12-bit ADC, 1us per channel conversion time
6 Analog Input Channels, CM range 0.5V to 27.5V
6 Temperature Measurements Inputs
On Chip Voltage Regulator
Cell Balancing Interface
Daisy Chain Interface
Internal Reference: 3 ppm/oC
V
DD
CB1
CB6
AD7280
DAIS Y CHAIN
INTER FACE
CEL L
BALANCING
INTER FACE
Vin(6)
Vin(5)
Vin(4)
Vin(3)
Vin(2)
Vin(1)
Vin(0)
REGUL ATOR
V
REG
DGND
DVCC
AVCC
MUX
+
-
+
12 BIT ADC
Low Quiescent Current
High Input Impedance
VDRIVE
-
VT(6)
VT(5)
VT(4)
VT(3)
VT(2)
VT(1)
Serial Interface with Alert Function
1 SPI interface for up to 120 channels
On Chip Registers for Channel Sequencing
VDD Operating Range 7.5V to 30V
Temperature Range -40 oC to 105oC
48 lead LQFP and LFCSP Packages
CONTRO L LOGIC
& SELF TEST
CLOCK
SCLK
SDIN
SDOUT
ALERT
CS
VTTERM
LIMIT REG
SQN LOGIC
DATA MEMO RY
SPI INTER FACE
V
REF
REF
REFGND
2.5V
REF
C
PD
CNVST
MASTER
APPLICATIONS
Lithium Ion Battery Monitoring
Figure 1
Nickel Metal Hydride Battery Monitoring
GENERAL DESCRIPTION
The AD72801 contains all the functions required for general
purpose monitoring of stacked Lithium Ion batteries as used in
Hybrid Electric Vehicles. The part has multiplexed analog input
and temperature measurement channels for up to six cells of
battery management. An internal 3-ppm reference is provided
to drive the ADC. The ADC resolution is 12 bits with a 1 Msps
throughput rate offering a 1µs conversion time.
The AD7280 also includes an Alert function which generates an
interrupt output signal if the cell voltages exceed an upper or
lower limit defined by the user. The AD7280 has balancing
interface outputs designed to control external FET transistors to
allow discharging of individual cells.
The AD7280 includes a built in Self Test feature which
internally applies a known voltage to the ADC inputs.
The AD7280 operates from just one VDD supply which has a
range of 7.5V to 30V (with an absolute max rating of 33V). The
part provides 6 pseudo differential analog input channels to
accommodate large common mode signals across the full VDD
range. Each channel allows an input signal range, Vin(+) --
Vin(-), of 1V to 5V. The input pins assume a series stack of 6
cells. In addition the part can accommodate 6 external sensors
for temperature measurement.
There is a daisy chain interface which allows up to 20 parts to
be stacked without the need for individual device isolation.
The AD7280 requires only one supply pin which takes 7mA
under normal operation, while converting at 1 MSPS.
All this functionality is provided in a 48 pin LQFP or 48 pin
LFCSP package operating over a temperature range of −40°C to
+105°C.
The AD7280 includes on chip registers which allow a sequence
of channel measurements to be programmed to suit the
applications requirements.
1 Patents Pending
Rev. PrF
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No
licenseis granted byimplication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
Preliminary Technical Data
AD7280
SPECIFICATIONS
VDD = 7.5 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.25 V, TA = -40oC to 105oC, unless otherwise noted
Table 1.
Parameter1
DC ACCURACY [Vin(0) to Vin(6)]2
Min
Typ
Max
Unit
Test Conditions/Comments
Resolution
12
Bits
LSB
LSB
LSB
ppm/oC
LSB
LSB
ppm/oC
LSB
%
No Missing Codes
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset Error Drift
Offset Error Match
Gain Error
Gain Error Drift
Gain Error Match
ADC Unadjusted Error3,4
1
1
1
3
1
1
2
1
0.05
0.08
0.07
0.1
0.1
0.3
0.2
0.5
-40oC to 85oC
-40oC to 105oC
-40oC to 85oC
-40oC to 105oC
%
%
%
Total Unadjusted Error5,6
ANALOG INPUTS [Vin(0) to
Vin(6)]
Pseudo Differential Input
Voltage
Vin(n) – Vin(n-1)
1V
2VREF
V
Absolute Input Voltage
Common Mode Input Voltage
DC Leakage Current
Input Capacitance
VCM - VREF
0.5
VCM + VREF
27.5
V
V
nA
pF
pF
70
15
3
CNVST pulse every 100ms
When in track
When in hold
DC ACCURACY [VT1 to VT6]2
Resolution
Integral Nonlinearity
Differential Nonlinearity
Offset Error
Offset Error Drift
Offset Error Match
Gain Error
12
Bits
LSB
LSB
LSB
ppm/oC
LSB
LSB
ppm/oC
LSB
%
No Missing Codes
1
1
2
2
2
2
1.2
2
0.1
0.16
0.15
0.2
Gain Error Drift
Gain Error Match
ADC Unadjusted Error7
0.2
0.6
0.4
1
-40oC to 85oC
-40oC to 105oC
-40oC to 85oC
-40oC to 105oC
%
%
%
Total Unadjusted Error8
ANALOG INPUTS (VT1 to VT6)
Input Voltage Range
Leakage Current
0
2VREF
V
70
15
3
nA
pF
pF
CNVST pulse every 100ms
When in track
When in hold
Input Capacitance
DYNAMIC PERFORMANCE
Common Mode Rejection Ratio
[CMRR]
-75
dB
Up to 10kHz ripple frequency
Rev. PrF | Page 2 of 38
Preliminary Technical Data
AD7280
Parameter1
Min
Typ
Max
Unit
Test Conditions/Comments
REFERENCE
Reference Voltage
Reference Temperature
Coefficient
Output Voltage Hysteresis
Long Term Drift
2.495
2.5
3
2.505
15
V
VREF @ 25oC
ppm/°C
-40 oC to +85 oC
50
100
ppm
ppm/1000
Hours
-40 oC to +85 oC
Line Regulation
15
10
ppm/V
ms
AVDD =7.5V
VREF = 10uF , CREF = 100nF
Turn-On Settling Time
REGULATOR OUTPUT
Input Voltage Range
Output Voltage VREG
Output Current9
Line Regulation
7.5
4.75
5
30
5.25
V
V
5
mA
mV/V
mV/mA
uV
0.4
2.5
700
20
Load Regulation
Output Noise Voltage
Internal Short Protection Limit
CELL BALANCING OUTPUTS10
Output High Voltage, VOH
Output Low Voltage, VOL
CB1 Output ramp up time11
CB1 Output ramp down time12
mA
For a 10 Ohm short
4
0
5
5.25
V
V
us
ns
us
For a 80pF load, ISOURCE = 40 nA
5
50
350
For a 80pF load
For a 80pF load
For a 80pF load
CB2-CB6 Output ramp up
time11
CB2-CB6 Output ramp down
time12
10
10
5
us
For a 80pF load
LOGIC INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current, IIN
Input Capacitance, CIN
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
Floating-State Leakage
Current
2.4
V
V
µA
pF
0.4
1
VDRIVE * 0.9
V
V
µA
ISOURCE = 200 µA
ISINK = 200 µA
0.4
1
Floating-State Output
Capacitance
pF
Output Coding
Straight natural binary
POWER REQUIREMENTS
VDD
7.5
30
V
IDD During Conversion
IDD During Data Readback
IDD During Cell Balancing
IDD Software Powerdown
IDD Full Powerdown Mode
POWER DISSIPATION
During Conversion
During Data Readback
During Cell Balancing
Software Powerdown
Full Powerdown Mode
7
5
4.5
1.8
10
8
6
2.5
4
mA
mA
mA
mA
µA
VDD = 30 V
VDD = 30 V
VDD = 30 V
VDD = 30 V
VDD = 30 V
300
240
180
75
mW
mW
mW
mW
µW
VDD = 30 V
VDD = 30 V
VDD = 30 V
VDD = 30 V
VDD = 30 V
120
Rev. PrF| Page 3 of 38
Preliminary Technical Data
AD7280
1 Temperature range is −40°C to +105°C.
2 For dc accuracy specifications, the LSB size for cell voltage measurements is (2VREF-1V)/4096, the LSB size for temperature measurements is 2VREF/4096.
3 ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels.
4 The conversion accuracy during Cell Balancing is decreased due to the activation of the Cell Balance circuitry. The ADC Unadjusted Error will increase from 0.1% to
0.4% within the -40oC to 85oC temperature range.
5 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the Vin0 to Vin6 input channels as well as the temperature coefficient of the 2.5V reference.
6 The conversion accuracy during Cell Balancing is decreased due to the activation of the Cell Balance circuitry. The Total Unadjusted Error will increase from 0.2% to
0.8% within the -40oC to 85oC temperature range.
7 ADC Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels.
8 Total Unadjusted Error includes the INL of the ADC and the Gain and Offset Errors of the VT input channels as well as the temperature coefficient of the 2.5V reference.
9 This spec outlines the regulator output current which is available for external use, that is, it does not include the regulator current already being used by the AD7280.
10 CB output can be set to 0V or 5V with respect to negative terminal of cell being balanced.
11 The CB1 to CB6 output ramp up times are defined from the rising edge of the CS command until the CB output exceeds 4V with respect to negative terminal of cell
being balanced.
12 The CB1 to CB6 output ramp down times are defined from the rising edge of the CS command until the CB output falls below 50mV with respect to negative terminal
of cell being balanced.
TIMING SPECIFICATIONS
VDD = 7.5 V to 30 V, VSS = 0 V, DVCC = AVCC = VREG, VDRIVE = 2.7 V to 5.25 V, TA = -40oC to 105oC, unless otherwise noted.1
Table 2.
Limit at TMIN, TMAX
Parameter
tCONV
tDELAY
Unit
Test Conditions/Comments
ADC Conversion time
Propogation delay between adjacent parts on the Daisy
Chain
2.7 V ≤ VDRIVE < 4.75 V 4.75 V ≤ VDRIVE ≤ 5.25 V
610
200
250
5
610
200
250
5
ns max
ns typ
ns max
μs min
tWAIT
fSCLK
Time required between the end of conversions and
beginning to read back the conversion results
Frequency of serial read clock
10
1
10
1
kHz min
MHz max
ns min
tQUIET
200
200
Minimum quiet time required between the end of serial
read and the start of the next conversion
t1
t2
t3
400
10
400
10
ns min
ns min
ns max
Minimum CONVST low pulse
CS falling edge to SCLK rising edge
10
10
Delay from CS falling edge until SDO is three-state
disabled
t4
t5
t6
t7
t8
t9
5
3
20
7
0.3 × tSCLK
0.3 × tSCLK
10
5
3
14
7
0.3 × tSCLK
0.3 × tSCLK
10
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns max
SDI setup time prior to SCLK falling edge
SDI hold time after SCLK falling edge
Data access time after SCLK falling edge
SCLK to data valid hold time
SCLK high pulse width
SCLK low pulse width
2
3
t10
CS rising edge to SCLK rising edge
t11
10
10
CS rising edge to SDO high impedance
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE) and timed from a voltage level of 1.6 V.
All timing specifications given are with a 25 pF load capacitance.
2 The time required for the output to cross 0.4 V or 2.4 V.
3 t10 applies when using a continuous SCLK.
Rev. PrF | Page 4 of 38
Preliminary Technical Data
AD7280
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VDD to AGND
−0.3 V to +33 V
VSS to AGND
−0.3 V to +0.3 V
VSS − 0.3 V to VDD + 0.3 V
VDD −0.3 V to VDD + 1 V
−0.3 V to DVCC + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to AVCC + 0.3 V
−0.3 V to +7 V
Vin0 to Vin5 Voltage to AGND
Vin6 Voltage to AGND
CB1 Output to AGND
CB2 to CB6 Output to AGND
VT1 to VT6 Voltage to AGND
AVCC to AGND, DGND
DVCC to AVCC
−0.3 V to +0.3 V
−0.3 V to +7 V
DVCC to DGND
VDRIVE to AGND
AGND to DGND
−0.3 V to DVCC+0.3 V
−0.3 V to +0.3 V
−0.3 V to VDRIVE + 0.3V
−0.3 V to VDRIVE + 0.3V
−40°C to +105°C
−65°C to +150°C
150°C
Digital Input Voltage to DGND
Digital Output Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
LQFP Package
θJA Thermal Impedance
θJC Thermal Impedance
LFCSP Package
76.2°C/W
17°C/W
θJA Thermal Impedance
θJC Thermal Impedance
Pb-free Temperature, Soldering
Reflow
54°C/W
15°C/W
260(+0)°C
2kV
ESD
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrF| Page 5 of 38
Preliminary Technical Data
AD7280
PIN CONFIGURATIONS AND FUNCTIONAL DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
1
2
36
35
34
33
32
31
30
29
28
27
26
25
VIN6
CB6
VIN5
CB5
VIN4
CB4
VIN3
CB3
VIN2
CB2
VIN1
CB1
VT3
VIN6
CB6
VIN5
CB5
VIN4
CB4
VIN3
CB3
VIN2
1
2
3
4
5
6
7
8
9
36 VT3
PIN 1
INDICATOR
PIN 1
VT4
35 VT4
34 VT5
3
VT5
33 VT6
4
VT6
32 VTTERM
31 AGND
30 AVCC
29 VDRIVE
28 ALERTlo
27 ALERT
26 SDO
5
VTTERM
AGND
AVCC
VDRIVE
ALERTlo
ALERT
SDO
AD7280
TOP VIEW
AD7280
TOP VIEW
6
7
8
CB2 10
VIN1 11
CB1 12
9
10
11
12
25 SDOlo
SDOlo
13 14 15 16 17 18 19 20 21 22 23 24
Figure 3.
Figure 2.
Table 4.
Pin No.
Mnemonic Description
1, 3, 5, 7,
9, 11, 13
Vin6 to
Vin0
Analog Input 0 to Analog Input 6. Analog input 0 should be connected to the base of the series connected
battery cells. Analog Input 1 should be connected to the top of cell 1, Analog Input 2 should be connected to
the top of cell 2, etc. The Analog Inputs are multiplexed into the on-chip track-and-hold allowing the potential
across each cell to be measured.
2, 4, 6, 8,
10, 12
CB6 to CB1 Cell Balance Outputs. These provide a voltage output which can be used to supply the gate drives of a cell
balancing transistor network. Each CB(n) output provides a 5V voltage output referenced to the absolute
voltage of Cell(n-1).
14
MASTER
Voltage Input. In an application with 2 or more AD7280s Daisy Chained the MASTER pin of the AD7280
connected directly to the DSP or uP should be connected to the VDD supply pin through a 10kOhm resistor. The
MASTER pin on the remaining AD7280s in the application should be tied to their respective VSS supply pins
through 10kOhm resistors.
15
16
PD
Power down Input. This input is used to power down the AD7280. When acting as master the PD input is
supplied from the DSP/uP. When acting as a slave on the Daisy Chain the PD input should be connected to the
PDhi output of the AD7280 immediately below it in potential in the Daisy Chain.
VDD
Positive Power Supply Voltage. This is the positive supply voltage for the high voltage analog input structure
AD7280. The supply must be greater than a minimum voltage of 7.5 V. In an application monitoring the cell
voltages of up to 6 series connected battery cells the supply voltage may be supplied directly from the cell with
the highest potential. The maximum voltage which can be applied between VDD and VSS is 30V. Place 10 µF and
100 nF decoupling capacitors on the VDD pin.
17
18
VSS
Negative Power Supply Voltage. This is the negative supply voltage for the high voltage analog input structure
of the AD7280. This input should be at the same potential as the AGND voltage.
Analog Voltage output, 5V. The internally generated VREG voltage, which provides the supply voltage for the
ADC core, is available on this pin for use external to the AD7280. Place 10 µF and 100 nF decoupling capacitors
on the VREG pin.
VREG
19
20
DVCC
Digital Supply Voltage, 4.75 V to 5.25 V. The DVCC and AVCC voltages should ideally be at the same potential.
For best performance, it is recommended that the DVCC and AVCC pins be shorted together, to ensure that the
voltage difference between them never exceeds 0.3 V even on a transient basis. This supply should be decoupled
to DGND. Place 100 nF decoupling capacitors on the DVCC pin. The DVCC supply pin should be connected to the
V
REG output
DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7280. The DGND and AGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
Rev. PrF | Page 6 of 38
Preliminary Technical Data
AD7280
21
CS
Chip select Input. When acting as a master, that is the Master pin of the AD7280 is connected to VDD, the CS
input is used to frame the input and output data on the SPI. The CS input also frames the input and output data
on the Daisy Chain Interface when the MASTER input of the AD7280 is connected to VSS.
22
23
SCLK
SDI
Serial Clock Input. When acting as master the SCLK input is supplied from the DSP/uP. When acting as a slave on
the Daisy Chain this input should be connected to the SCLKhi output of the AD7280 immediately below it in
potential in the Daisy Chain.
Serial Data Input. Data to be written to the on-chip registers is provided on this input and is clocked into the
AD7280 on the falling edge of SCLK. When acting as master this is the data input of the SPI interface. When
acting as a slave on the Daisy Chain this input acepts data from the SDOhi output of the AD7280 immediately
below it in potential in the Daisy Chain.
24
25
CNVST
SDOlo
Convert Start Input. The conversion is initiated on the falling edge of CONVST. When acting as master the
CNVST pulse is supplied from the DSP/uP. When acting as a slave on the Daisy Chain this input should be
connected to the CNVSThi output of the AD7280 immediately below it in potential in the Daisy Chain. This
input can also be tied to VCC and the conversion initiated through the serial interface.
Serial Data Output in Daisy Chain mode. When configured as a slave device this output should be connected to
the SDIhi input of the AD7280 immediately below it in potential on the Daisy Chain. The data from each
AD7280 in the Daisy Chain will be passed through the SDOlo outputs and SDIhi inputs of each AD7280 in the
chain and supplied to the uP/DSP through the SDO output of the master AD7280. When configured as a master
device it is recommended that this output, which is not required in slave mode, be connected to VSS either
directly or through a pull-down 1kOhm resistor.
26
SDO
Serial Data Output. The conversion output data or the register output data is supplied to this pin as a serial data
stream. The bits are clocked out on the rising edge of the SCLK input, and 32 SCLKs are required to access the
data. The data is provided MSB first. In a Daisy Chain application the SDO output of the master AD7280 should
be connected to the uP/DSP. The SDO outputs of the remaining AD7280s in the chain should be terminated to
V
SS through a 1kΩ resistor. The data from each AD7280 in the Daisy Chain will be passed through the SDOlo
outputs and SDIhi inputs of each AD7280 in the chain and supplied to the uP/DSP through the SDO output of
the master AD7280. 32 SCLKs are required for each AD7280 in the chain to access the data.
27
28
ALERT
Digital Output. Flag to indicate over voltage, under voltage, over temperature or under temperature. The ALERT
output of the master AD7280 should be connected to the uP/DSP. The ALERT outputs of the remaining
AD7280s in the chain should be be terminated to VSS through a 1kΩ resistor.
Alert Output in Daisy Chain mode. The alert signal from each AD7280 in the Daisy Chain will be passed through
the ALERTlo outputs and ALERThi inputs of each AD7280 in the chain and supplied to the uP/DSP through the
ALERT output of the master AD7280. When configured as a slave device this output should be connected to the
ALERThi input of the AD7280 immediately below it in potential on the Daisy Chain. When configured as a
master device it is recommended that this output, which is not required in slave mode, be connected to VSS
either directly or through a pull-down 1kOhm resistor.
ALERTlo
29
30
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage range on this pin is 2.7 V to 5.25 V and may be different to
the voltage at AVCC and DVCC, but should never exceed either by more than 0.3 V.
Analog Supply Voltage, 4.75 V to 5.25 V. This is the supply voltage for the ADC core. The AVCC and DVCC voltages
should ideally be at the same potential. For best performance, it is recommended that the DVCC and AVCC pins
be shorted together, to ensure that the voltage difference between them never exceeds 0.3 V even on a
transient basis. This supply should be decoupled to AGND. Place 100 nF decoupling capacitors on the AVCC pin.
The AVCC supply pin should be externally connected to the VREG output.
AVCC
31
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7280. This input should be at the
same potential as the base of the series connected battery cells. The AGND and DGND voltages ideally should
be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
32
33 to 38
39
VTTERM
VT6 to VT1
CREF
Thermistor termination resistor input.
Voltage temperature input from potential divider with thermistor.
A 100 nF decoupling capacitor to REFGND should be placed on this pin.
40
VREF
Reference Output. The on-chip reference is availble on this pin for use external to the AD7280. The nominal
internal reference voltage is 2.5V, which appears at the pin. A 10 µF decoupling capacitor to REFGND is
recommended on this pin.
41
42
REFGND
ALERThi
Reference Ground. This is the ground reference point for the internal bandgap reference circuitry on the
AD7280. The REFGND voltage should be at the same potential as the AGND voltage.
Alert Input in Daisy Chain mode. Flag to indicate over voltage, under voltage, over temperature or under
temperature in Daisy Chain mode. The alert signal from each AD7280 in the Daisy Chain will be passed through
the ALERTlo outputs and ALERThi inputs of each AD7280 in the chain and supplied to the uP/DSP through the
ALERT output of the master AD7280. This input should be connected to the ALERTlo output of the AD7280
immediately above it in potential on the Daisy Chain. When this pin is unused,it is recommended that it is
connected to VDD through a 1kOhm resistor.
Rev. PrF| Page 7 of 38
Preliminary Technical Data
AD7280
43
SDIhi
Serial Data Input in Daisy Chain mode. The data from each AD7280 in the Daisy Chain will be passed through
the SDOlo outputs and SDIhi inputs of each AD7280 in the chain and supplied to the uP/DSP through the SDO
output of the master AD7280. This input should be connected to the SDOlo output of the AD7280 immediately
above it in potential on the Daisy Chain. When this pin is unused,it is recommended that it is connected to VDD
through a 1kOhm resistor.
44
CNVSThi
Conversion Start Output in Daisy Chain mode. The convert start signal from the uP/DSP supplied to the CNVST
input of the Master AD7280 is passed through each AD7280 by means of the CNVST input and the CNVSThi
output. This output should be connected to the CNVST pin of the AD7280 immediately above it in potential on
the Daisy Chain. When this pin is unused,it is recommended that it is connected to VDD
.
45
46
47
SDOhi
SCLKhi
CShi
Serial Data Output in Daisy Chain mode. The Serial Data input from the uP/DSP supplied to the SDI input of the
Master AD7280 is passed through each AD7280 by means of the SDI input and the SDOhi output. This output
should be connected to the SDI input of the AD7280 immediately above it in potential on the Daisy Chain.
When this pin is unused,it is recommended that it is connected to VDD
.
Serial Clock Output in Daisy Chain mode. The clock signal from the uP/DSP supplied to the SCLK input of the
Master AD7280 is passed through each AD7280 by means of the SCLK input and the SCLKhi output. This output
should be connected to the SCLK input of the AD7280 immediately above it in potential in the Daisy Chain.
When this pin is unused,it is recommended that it is connected to VDD
.
Chip select Output in Daisy Chain mode. The chip select signal from the uP/DSP supplied to the CS input of the
Master AD7280 is passed through each AD7280 by means of the CS input and the CShi output. This output
should be connected to the CS input of the AD7280 immediately above it in potential on the Daisy Chain.
When this pin is unused,it is recommended that it is connected to VDD
.
48
PDhi
Power down Output in Daisy Chain mode. The power down signal from the uP/DSP supplied to the PD input of
the Master AD7280 is passed through each AD7280 by means of the PD input and the PDhi output. This output
should be connected to the PD pin of the AD7280 immediately above it in potential on the Daisy Chain. When
this pin is unused,it is recommended that it is connected to VDD
.
Rev. PrF | Page 8 of 38
Preliminary Technical Data
TERMINOLOGY
AD7280
Vin(n-1) frequency, fS, as
CMRR (dB) = 10 log (Pf/PfS)
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
where Pf is the power at frequency f in the ADC output, and PfS
is the power at frequency fS in the ADC output.
Integral Nonlinearity
Power Supply Rejection Ration (PSRR)
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale (a point 1 LSB
below the first code transition) and full scale (a point 1 LSB above
the last code transition).
Variations in power supply affect the full-scale transition but
not the converter’s linearity. PSRR is the maximum change in
the full-scale transition point due to a change in power supply
voltage from the nominal value.
Reference Voltage Temperature Coefficient
Offset Code Error
Reference voltage temperature coefficient is derived from the
maximum and minimum reference output voltage (VREF
measured at TMIN, T(25°C), and TMAX. It is expressed in ppm/°C
using the following equation:
This applies to straight binary output coding. It is the deviation
of the first code transition (00 ... 000) to (00 ... 001) from the
ideal, that is, AGND +1 LSB for VT1 to VT6 and 1V + AGND
+1 LSB for Vin0 to Vin6.
)
VREF ( Max)–VREF (Min)
REF (25°C) × (TMAX –TMIN )
×106
Gain Error
TCVREF (ppm/°C) =
V
This applies to straight binary output coding. It is the deviation
of the last code transition (111 ... 110) to (111 ... 111) from the
ideal (that is 2 × VREF − 1 LSB) after adjusting for the offset
error.
where:
V
V
V
T
T
REF(Max) = Maximum VREF at TMIN, T(25°C), or TMAX
REF(Min) = Minimum VREF at TMIN, T(25°C), or TMAX
REF(25°C) = VREF at +25°C
ADC Unadjusted Error
ADC Unadjusted Error includes integral nonlinearity errors,
offset and gain errors of the ADC and measurement channel.
MAX = +85°C
MIN = –40°C
Output Voltage Hysteresis
Total Unadjusted Error (TUE)
This is the maximum deviation of the output code from the
ideal. Total Unadjusted Error includes integral nonlinearity
errors, offset and gain errors and reference drift.
Output voltage hysteresis, or thermal hysteresis, is defined as
the absolute maximum change of reference output voltage after
the device is cycled through temperature from either
Offset Error Match
This is the difference in zero code error across all 6 channels.
T_HYS+ = +25°C to TMAX to +25°C
T_HYS– = +25°C to TMIN to +25°C
Gain Error Match
The difference in gain error across all 6 channels.
It is expressed in ppm using the following equation:
V
REF (25°C) −VREF (T _ HYS)
V
HYS (ppm) =
× 106
Track-and-Hold Acquisition Time
V
REF (25°C)
The track-and-hold amplifier returns to track mode at the end
of a conversion. Track-and-hold acquisition time is the time
required for the output of the track-and-hold amplifier to reach
its final value, within ±± LSB.
where:
REF(25°C) = VREF at 25°C
VREF(T_HYS) = Maximum change of VREF at T_HYS+ or
V
T_HYS–.
Common Mode Rejection Ration (CMRR)
CMRR is defined as the ratio of the power in the ADC output
at full-scale frequency, f, to the power of a 100 mV sine wave
applied to the common-mode voltage of the Vin(n) and
Rev. PrF| Page 9 of 38
Preliminary Technical Data
AD7280
results exceed the maximum and minimum voltage thresholds
selected by the user. The threshold levels are selected by writing
to the internal registers.
THEORY OF OPERATION
CIRCUIT INFORMATION
The AD7280 provides 6 analog output voltages which can be
used to control external transistors as part of a cell balancing
circuit. Each Cell Balance output provides a 0V or 5V voltage,
with respect to the potential on base of each individual cell,
which can be applied to the gate of the external cell balancing
transistors.
The AD7280 is a Lithium Ion battery monitoring chip with the
ability to monitor the voltage and temperature of 6 series
connected battery cells. The AD7280 also provides an interface
which can be used to control transistors for cell balancing.
The VDD and VSS supplies required by the AD7280 can be taken
from the upper and lower voltages of the series connected
battery cells. An internal VREG rail is generated from the supply
voltage which provides power for the ADC and the internal
interface circuitry. This VREG voltage is available on an output
pin for use external to the AD7280.
The AD7280 features a daisy chain interface. Individual
AD7280s can monitor the cell voltages and temperatures of 6
cells, a chain of AD7280s can be used to monitor the cell
voltages and temperatures of a larger number of cells. The
conversion data from each AD7280 in the chain passes to the
system controller via a single standard serial interface. Control
data can similarly be passed via the standard serial interface up
the chain to each individual AD7280s
The AD7280 consists of a high voltage input multiplexer, a low
voltage input multiplexer and a 12 bit ADC. The high voltage
multiplexer allows up to 6 series connected Lithium Ion battery
cells to be measured. The low voltage multiplexer allows the
The AD7280 includes an on-chip 2.5V reference. The reference
voltage is available for use external to the AD7280.
temperature of each cell to be measured. A single
CNVST
signal is required to initiate conversions on all 12 channels, that
is 6 voltage and 6 temperature channels. Alternatively the
CONVERTER OPERATION
conversion can be initiated through the rising edge of
on the
CS
SPI interface. Each conversion result is stored in a results
register (See Register section). On power-up, the
The AD7280 consists of a high voltage input multiplexer, a low
voltage input multiplexer and a 12 bit ADC.
signal
CNVST
The high voltage multiplexer selects which pair of analog
inputs, Vin0 to Vin6, are to be converted. The voltage of each
individual cell is measured by converting the difference
between adjacent analog inputs, that is, Vin1 – Vin0, Vin2 –
Vin1, etc. This is illustrated in Figure 4 and Figure 5. The
conversion results for each cell may be accessed after the
programmed conversion sequence is complete.
is the default option, this can be changed by writing to the
CONTROL register. The default sequence of conversions
completed following the
signal, or software convert
CNVST
start, is all 6 voltage channels followed by all 6 temperature
channels. Two further conversion sequences may be selected by
the user, 6 voltage channels followed by 3 temperature channels
or just 6 voltage channels. The conversion sequence may be
selected by writing to the CONTROL register.
The second multiplexer selects which voltage temperature
input, VT1 to VT6, is to be converted. The conversion results
for each cell may be accessed after the programmed conversion
sequence is complete.
Each voltage and temperature measurement requires a
minimum of 1us to acquire and complete a conversion.
Depending on the external components connected to the
analog inputs of the AD7280 additional acquisition time may be
required. A higher acquisition time may be selected through the
CONTROL register. For increased accuracy in a noisy
environment the user may also select the averaging option
through the CONTROL register. This option allows the user to
complete 2, 4 or 8 averages on each cell voltage and cell
temperature measurement. The averaged conversion results are
stored in the results registers. On power-up the default
combined acquisition and conversion time will be 1us, with the
averaging register set to zero, that is, a single conversion per
channel.
Vin6
Vin5
Vin4
Vin3
Vin2
ADC Vin+
ADC Vin-
Vin1
Vin0
Figure 4. MUX Configuration During Vin1-Vin0 Sampling
The results of the voltage and temperature conversions are read
back via the 4 wire Serial Peripheral Interface. The SPI interface
is also used to write to and read data from the internal registers.
The AD7280 features an ALERT function which is triggered if
the voltage conversion results or the temperature conversion
Rev. PrF | Page 10 of 38
Preliminary Technical Data
AD7280
ANALOG INPUT STRUCTURE
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Figure 8 shows the equivalent circuit of the analog input
structure of the AD7280. The two diodes provide ESD
protection. The resistors are lumped components made up of
the on-resistance of the input multiplexer and the track-and-
hold switch. The value of these resistors is typically about
300Ω. Capacitor C1 can primarily be attributed to pin
capacitance while Capacitor C2 is the sampling capacitor of the
ADC. The total lumped capacitance of C1 and C2 is approxi-
mately 13 pF.
ADC Vin+
ADC Vin-
Figure 5. MUX Configuration During Vin2-Vin1 Sampling
V
DD
D
C2
R1
The ADC is a 12-bit successive approximation analog-to-digital
converter. The converter is composed of a comparator, SAR,
some control logic and 2 capacitive DACs. Figure 6 shows a
simplified schematic of the converter. During the acquisition
phase switches SW1, SW2 and SW3 are closed. The sampling
capacitor array acquires the signal on the input during this
phase.
V
+
IN
C1
D
V
SS
V
DD
D
C2
R1
V
–
IN
CAPACITIVE
DAC
C1
D
COMPARATOR
C
V
S
SS
B
V
V
+
–
IN
A
A
SW1
SW2
CONTROL
LOGIC
Figure 8. Equivalent Analog Input Circuit
SW3
IN
B
C
S
TRANSFER FUNCTION
CAPACITIVE
DAC
The output coding of the AD7280 is straight binary. The
designed code transitions occur at successive integer LSB values
(that is, 1 LSB, 2 LSB, and so on). The LSB size is dependent on
whether the voltage or temperature inputs are being measured.
The analog input range of the voltage inputs is 1V to 5V, the
analog input range of the temperature inputs is 0V to 5V. The
ideal transfer characteristic is shown in Figure 9.
Figure 6. ADC Configuration During Acquisition Phase
When the ADC starts a conversion (Figure 7), SW3 opens and
SW1 and SW2 move to position B, causing the comparator to
become unbalanced. The control logic and capacitive DACs are
used to add and subtract fixed amounts of charge to bring the
comparator back into a balanced condition. When the
comparator is rebalanced, the conversion is complete. The
control logic generates the ADC output code. This output code
is then stored in the appropriate register for the input that has
been converted.
Table 5. LSB Sizes for Each Analog Input Range
Selected
inputs
Input
Range
Full-Scale LSB Size
Range
Voltage
1 V to 5 V
4 V/4096
5 V/4096
976 µV
1.22 mV
Temperature 0 V to 5 V
CAPACITIVE
DAC
COMPARATOR
111...111
111...110
C
S
S
B
V
V
+
–
IN
A
A
SW1
SW2
CONTROL
LOGIC
SW3
111...000
011...111
IN
B
C
CAPACITIVE
DAC
000...010
000...001
000...000
Figure 7. ADC Configuration During Conversion Phase
1V + 1LSB
AGND + 1LSB
5V – 1LSB
5V – 1LSB
4V INPUT RANGE
5V INPUT RANGE
ANALOG INPUT
Figure 9. Transfer Characteristic
TYPICAL CONNECTION DIAGRAMS
Rev. PrF| Page 11 of 38
Preliminary Technical Data
AD7280
10kΩ
0.1µF
10µF
MASTER
VDD
Vin6
VREG
DVCC
AVCC
10uF
CB6
Vin5
0.1uF
0.1uF
VDRIVE
CB5
Vin4
VREF
CREF
OPTIONAL
INTERFACE
PINS
10uF
CB4
Vin3
0.1uF
AD7280
CB3
Vin2
ALERT
CNVST
PD
CB2
Vin1
µC/µP
SDO
SCLK
SDI
CB1
Vin0
CS
VSS
4 WIRE SPI
INTERFACE
Figure 10. AD7280 Configuration Diagram for 6 Battery Cells
The AD7280 can be used to monitor 6 battery cells connected
in series. A typical configuration for a 6 cell battery monitoring
application is shown in Figure 10. Lithium Ion Battery
applications require a significant number of individual cells to
provide the required output voltage. Individual AD7280s can
monitor the cell voltages and temperatures of 6 series connected
cells. The Daisy Chain Interface of the AD7280 allows each
individual AD7280 to communicate with another AD7280
immediately above or below it. The daisy chain interface allows
the AD7280s to be electrically connected to the battery
management chip, as shown in Figure 11 without the need for
individual isolation between each AD7280.
When using a chain of AD7280s it is also recommended that a
100kOhm series resistor is placed on the PD input. This is
recommended to limit current into the PD pin in the event that
the uP/DSP or isolators are connected before the supplies of the
master AD7280.
Please refer to the Daisy Chain Interface Section for a more
detailed description of the Daisy Chain Interface.
In an application which includes a safety mechanism, designed
to open circuit the Battery Stack, additional isolation will be
required between the AD7280 above the break point and the
battery management chip.
Daisy Chain Connection Diagram
EMC Considerations
As shown in Figure 11 external diodes have been included on
the VDD supply to each AD7280 and on each Daisy Chain signal
between adjacent AD7280s. These diodes, in combination with
the 10kΩ series resistors on the analog inputs, are
recommended to prevent damage to the AD7280 in the event of
an open circuit in the battery stack.
In addition to the standard decoupling capacitors, C2n and
C3n, as shown in Figure 11, it is also recommended that an
option for additional capacitors, C1n and C4n, be included in
the circuit to increase immunity to Electromagnetic
Interference. These capacitors, placed on either side of the VDD
protection diode, would be used to decouple the VDD supply of
each AD7280 with respect to system ground, that is, the ground
of the master AD7280 in the daisychain.
It is also recommended that a zener diode be placed across the
supplies of each AD7280 as shown in Figure 11. This will
prevent an over voltage across the supplies of each AD7280
during the initial connection of the daisychain of AD7280s to
the battery stack. A voltage rating of 33V is suggested for this
zener diode but lower values may also be used to suit the
application.
It is recommended that ferrite beads be included on the battery
Rev PrE | Page 12 of 38
Preliminary Technical Data
AD7280
ALERT and SDO outputs on each of the slave parts in the
connections to the VDD and VSS supplies. It is also
recommended that pull-down resistors should be used on the
AD7280 daisychain.
VDDn
C4n
C2n
C3n
C1n
0.1uF 0.1uF
DD(n-1)
10k
10uF
0.1uF
V
VDD
VREG
0.1uF
DVCC
Ω
10uF
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
100nF
AVCC
VDRIVE
AD7280
1k
1k
10k
Ω
ALERT
SDO
Ω
Ω
MASTER
10uF
VREF
CREF
0.1uF
VSS
VDD(n-1)
VDD(n-1)
VDD1
C4
1
10uF
C3
C2
1
C1
1
0.1uF
0.1uF
0.1uF
1
V 0
10k
DD
VDD
VREG
Ω
10uF
0.1uF
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
DVCC
AVCC
100nF
VDRIVE
AD7280
1k
1k
10k
Ω
ALERT
SDO
Ω
Ω
MASTER
10uF
VREF
CREF
0.1uF
VSS
VDD0
VDD0
C4
0
0.1uF
V
10uF
C3
10kΩ
C1
0.1uF
0
0
DD
VREG
10kΩ
10uF
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
DVCC
AVCC
100nF
OPTIONAL
INTERFACE
PINS
0.1uF
VDRIVE
AD7280
ALERT
CNVST
PD
100k
Ω
µC/µP
SDO
SCLK
SDI
CS
V
SS
4 WIRE SPI
INTERFACE
VSS0
10uF
0.1uF
Figure 11. AD7280 Daisy Chain Configuration
processors.
VDRIVE
The AD7280 also has a VDRIVE feature to control the voltage at
which the serial interface operates. VDRIVE allows the ADC to
easily interface to both 3 V and 5 V processors. For example, in
the recommended configuration the AD7280 is operated with a
REFERENCE
The internal reference is temperature compensated to 2.5 V ± 5
mV. The reference is trimmed to provide a typical drift of
3 ppm/°C. The internal reference circuitry consists of a 1.2 V
band gap reference and a reference buffer. The AD7280 internal
VCC of 5 V, however the VDRIVE pin could be powered from a 3 V
supply, allowing a large dynamic range with low voltage digital
Rev. PrF| Page 13 of 38
Preliminary Technical Data
AD7280
reference is available at the VREF pin. The VREF pin should be
decoupled to REFGND using a 10 µF, or greater, ceramic
capacitor. The CREF pin should be decoupled to REFGND using
a 0.1 µF, or greater, ceramic capacitor. The internal reference is
capable of driving an external load of up to 10kOhms.
results may be read back from either a single device or from all
devices in a daisychain by use of the SPI and Daisychain
interfaces. More information on this may be found in the Serial
Interface and Daisy Chain Interface sections. As shown in
Figure 13, a wait time, tWAIT, is required between the completion
of conversions and the start of readback. This time is required
to synchronise between the high speed conversion clock and the
lower speed clock used for all other AD7280 operations. The
maximum value of tWAIT is 5μs.
CONVERTING CELL VOLTAGES AND
TEMPERATURES
A conversion may be initiated on the AD7280 using either the
input or the serial interface. A single
signal is
CNVST
CNVST
Track-and-Hold
required to initiate conversions on all 12 channels, that is 6
voltage and 6 temperature channels. Alternatively the
The track-and-hold on the analog input of the AD7280 allows the
ADC to accurately convert an input sine wave of full-scale
amplitude to 12-bit accuracy.
conversion can be initiated through the rising edge of
on the
CS
SPI interface.
Following a completed conversion the AD7280 enters its
tracking mode. The time required to acquire an input signal
depends on how quickly the sampling capacitor is charged. This
in turn will depend on the input impedance and any external
components placed on the analog inputs. The default acquisition
time of the AD7280 on initial power up is 400 ns. This can be
increased in steps of 400ns to 1.6 us to provide flexibility in
selecting external components on the analog inputs. The
acquisition time is selected by writing to bits D6 and D5 in the
CONTROL register.
When using the
input the falling edge of
CNVST
places
CNVST
the track and hold on the voltage inputs Vin6 and Vin5, that is
across Cell 6, into hold mode and initiates the conversion. At
the end of the first conversion the AD7280 generates an internal
End of Conversion signal. This internal EOC will select the next
cell voltage inputs for measurement though the multiplexer, that
is, Vin5 and Vin4. The track-and-hold circuit will acquire the
new input voltage and a second internal convert start signal is
generated which places the track-and-hold into hold mode and
initiates the conversion. This process is repeated until all the
selected voltage and temperature cell inputs have been
converted. Please refer to Figure 12 and Figure 13. Note, once
all selected conversions have been completed voltage inputs
Vin6 and Vin5 are again selected through the multiplexer and
the voltage across Cell 6 is acquired in preparation for the next
conversion request.
It should also be noted once the acquisition time is reconfigured
90μs should be allowed before performing any conversions.
This time should be allowed between writing to the CONTROL
register to change the acquisition time and initiating the first
conversion. In the case of conversions which are being initiated
by the rising edge of the
pin, this will require 2 separate
CS
write commands to the CONTROL register. The first to
configure the AD7280 for the required acquisition time, the
second, following a delay of 90μs, to initiate the conversion on
By setting bits D15 and D14 in the control register the voltage
and temperature cells to be converted are selected. There are
four options available.
the rising edge of
.
CS
Table 6. Voltage and Temperature Cell Selection
Table 7.Analog Input Acquisition Time.
D15 to
D14
Voltage inputs
Temperature
Inputs
D6 to D5
Acquisition Time
400 ns
00
01
10
11
00
01
10
11
1 to 6
1 to 6
1 to 6
ADC Self Test
1 to 6
1, 3 & 5
None
None
800 ns
1.2 µs
1.6 µs
The acquisition time required is calculated using the following
formula:
Each voltage and temperature conversion requires a minimum
of 1us to acquire and convert the cell voltage or temperature
voltage input. For example, when D15 and D14 are set to zero
t
ACQ = 10 × ((RSOURCE + R) C)
the falling edge of
will trigger a series of 12
CNVST
where:
conversions. This will require a minimum of 12µs to convert all
selected measurements. If no temperature conversions are
required then Bits D15 and D14 would be set to 10. In this case
the conversion request will trigger a series of 6 conversions,
requiring a minimum of 6µs.
C is the sampling capacitance, the value of the sampling
capacitor, 13pF
R is the resistance seen by the track-and-hold amplifier looking
at the input, 300Ω.
RSOURCE should include any extra source impedance on the
analog input.
Following the completion of all requested conversions the
Rev. PrF | Page 14 of 38
Preliminary Technical Data
AD7280
t1
CNVST
tACQ
tCONVERT
tCONVERT
INTERNAL ADC
CONVERSIONS
VOLT 4
VOLT 6
VOLT 5
TEMP 6
Figure 12. ADC conversions on the AD7280
t1
CNVST
tQUIET
tWAIT
INTERNAL ADC
CONVERSIONS
V 6
V 5
V 4
T 5
T 6
V 6
V 5
CS
SCLK
SERIAL READ OPERATION
1
32 x NO. OF CONVERSIONS
Figure 13. ADC conversions & Readback on the AD7280
calculated using the following equation:
Total Conversion time = ((tACQ + tCONV) × (#conversions per
Converting Cell Voltages and Temperatures with a chain
of AD7280s
The AD7280 provides a daisy chain interface which allows up to
20 parts to be stacked without the need for individual isolation.
One feature of this daisychain interface is the ability to initiate
conversions on all parts in the daisychain stack with a single
conversion start command. The conversion can be initiated
part) - tACQ + (#parts x tDELAY
)
Where
tACQ is the analog input acquisition time of the AD7280 as
outlined in Table 7
through a single
pulse or through the rising edge of
CNVST
CS
on the SPI interface. The convert start command is transferred
up the daisychain, from the master device, to each AD7280 in
turn. The delay time between each AD7280 is tDELAY, as outlined
in Figure 14. The maximum delay between the start of
conversions on the master AD7280 and the last AD7280 device
in the chain can be determined by multiplying tDELAY by the
number ofAD7280s in the daisychain. The total conversion
time for all cell voltage and temperature conversions can be
t
2
CONV is the conversion time of the AD7280 as outlined in Table
#conversions per part is 6, 9 or 12 as outlined in Table 6.
#parts is the number of AD7280s in the daisychain
Rev. PrF| Page 15 of 38
Preliminary Technical Data
AD7280
TOTAL CONVERSION TIME
= ((tACQ + tCONV) x #conversions per part) - tACQ+ (#parts x tDELAY
)
CNVST
tACQ + tCONV
VOLT 4
tCONV
INTERNAL ADC
CONVERSIONS
PART 1
VOLT 6
VOLT 5
TEMP 6
tDELAY
tDELAY
INTERNAL ADC
CONVERSIONS
PART 2
VOLT 10
VOLT 12
VOLT 11
TEMP 12
tACQ + tCONV
tDELAY
tDELAY
INTERNAL ADC
CONVERSIONS
PART 3
VOLT 16
VOLT 18
VOLT 17
TEMP 18
tACQ + tCONV
Figure 14. ADC conversions & Readback on a chain of 3 AD7280s
Suggested External Component Configurations on
Analog Inputs
acquisition and conversion time of 1µs.
As outlined in the Track-and –Hold section the acquisition time
of the AD7280 is selected by the status of bits D6 and D5 in the
CONTROL register. This provides flexibility in selecting external
components on the analog inputs. Included below are two
suggested configurations for placing external components on the
analog inputs to the AD7280.
Current Limiting Resistors
Please refer to Figure 16.
Combined LP filter and Current Limiting Resistors
AD7280
10kΩ
10kΩ
Vin6
Vin5
Vin4
Vin3
Vin2
Vin1
Vin0
Please refer to Figure 15.
10kΩ
10kΩ
10kΩ
AD7280
10kΩ
10kΩ
10kΩ
Vin6
100nF
10kΩ
Vin5
100nF
10kΩ
Vin4
100nF
10kΩ
Vin3
10kΩ
10kΩ
10kΩ
100nF
100nF
100nF
Vin2
Vin1
Vin0
Figure 16. External Series Resistance
The 10kΩ resistor in series with the inputs provides protection
to the analog inputs in the event of an over-voltage or under-
voltage on those inputs. Using these external components an
acquisition time of 1.6 µs should be used, which will allow a
combined acquisition and conversion time of 2.2µs.
Figure 15. External Series Resistance & Shunt Capacitance
The 10kΩ resistor in series with the inputs provides protection
to the analog inputs in the event of an over-voltage or under-
voltage on those inputs. The 100nF capacitor across the pseudo
differential inputs acts as a low pass filter in conjunction with
the 10kΩ resistor. The cut off frequency of the low pass filter is
318Hz. Using these external components the default acquisition
time of 400 ns may be used, which will allow a combined
SELF TEST CONVERSION
A self-test conversion may be initiated on the AD7280 which
allows the operation of the ADC to be verified. The self-test
conversion is completed on the internal 1.2V bandgap reference
voltage. The self-test conversion may be initiated on either a
single AD7280 or on all AD7280s in the battery stack
Rev. PrF | Page 16 of 38
Preliminary Technical Data
AD7280
connections to the AD7280 in a 4 cell battery monitoring
simultaneously. The conversion results may be read back
though the read protocols defined in the Register map section.
application is shown in Figure 17.
The self-test conversion may also be used to verify the
operation of the ALERT outputs as described in the ALERT
Output section.
Regardless of how many cell measurements are required in the
user application the AD7280 will acquire and convert the
voltages on all 6 voltage input channels. The conversion data on
all 6 channels will be supplied to the DSP/uP using the SPI
/Daisy Chain interfaces. The user should then ignore the
conversion data which is not required in their application. If
using the Alert function the user should program the Alert
register to ensure that the shorted out channels do not
incorrectly trigger an Alert output. Please refer to ALERT
Output section.
CONVERSION AVERAGING
The AD7280 includes an option where the acquisition and
conversion of each cell input may be repeated with an averaged
conversion result being stored in the individual register. The
averaged conversion result may then be read back through the
SPI interface in the same manner as a standard conversion
result. The AD7280 may be programmed, through bits D10 and
D9 of the CONTROL register, to complete 1, 2, 4 or 8
AD7280
conversions. The default on power up is a single conversion.
Vin6
Vin5
Vin4
Selection of the 2, 4, or 8 average options, through the
CONTROL register, will cause the control sequence of both the
high voltage and low voltages input multiplexers to be
reconfigured to allow the additional acquisitions and
conversions to be completed. In each case the requested number
of conversions will be completed on each channel before
beginning to acquire and convert on the next channel in
sequence. For example, if an average of 2 conversions is
requested the new sequence will be voltage channel 6, voltage
channel 6, voltage channel 5, voltage channel 5, voltage channel
4 etc.
100nF
10kΩ
Vin3
10kΩ
10kΩ
10kΩ
100nF
100nF
100nF
Vin2
Vin1
Vin0
Figure 17. Typical connections for a 4 cell application
CELL TEMPERATURE INPUTS
It should also be noted once the high voltage multiplexors are
reconfigured, 90μs should be allowed before performing any
conversions. This time should be allowed between writing to
the CONTROL register to select averaging and initiating the
first conversion. In the case of conversions which are being
The AD7280 provides 6 single ended analog inputs, VT1 to
VT6, to the ADC which may be used to convert the voltage
output of a thermistor temperature measurement circuit. In the
event that no temperature measurements are required, or that
individual cell temperature measurements are not required the
VT inputs may be used to convert any other 0 V to 5 V input
signal.
initiated by the rising edge of the
pin, this will require 2
CS
separate write commands to the CONTROL register. The first
to configure the AD7280 for the required the required
averaging, the second, following a delay of 90μs, to initiate the
The AD7280 may be programmed to complete conversions on
all 6 temperature channels, on 3 temperature channels (VT1,
VT3 & VT5) or on none of the temperature input channels. The
number of conversions is programmed through bits D15 and
D14 of the CONTROL register. The number of conversions
results supplied by the AD7280 for read back by the DSP/uP is
programmed through bits D13 and D12 of the CONTROL
register. In an application where the ALERT function is being
used but only one or two temperature inputs are required the
AD7280 should first be programmed to complete and readback
only 3 temperature conversions, by setting bits D15 and D13 of
the CONTROL register to 0, and bits D14 and D12 to 1. VT
Channels VT5 and VT3 may be removed from the Alert
detection by writing to bits D1 and D0 of the ALERT register.
Please refer to ALERT Output section.
conversion on the rising edge of
.
CS
CONVERSION OF LESS THAN 6 VOLTAGE CELLS
The AD7280 provides 6 input channels for Battery Cell voltage
measurement. The AD7280 may also be used in applications
which require less than 6 voltage measurements. In these
applications care should be taken to ensure that the sum of the
individual cell voltages will still exceed the minimum VDD
supply voltage. For this reason it is recommended that the
minimum number of battery cells connected to each AD7280 is
4. Care should also be taken to ensure that the voltage on the
Vin6 inputs is always greater than or equal to the voltage on the
VDD supply pin. This design requirement is in place to allow the
use of a diode on the VDD supply pin of the AD7280 which
provides protection in the event of an open circuit in the battery
stack. Even if a protection diode is not being used in the
application the Vin6 input voltage must be greater than or equal
to the VDD supply voltage. An example of the battery
Rev. PrF| Page 17 of 38
Preliminary Technical Data
AD7280
Thermistor Termination Input
the voltage and/or temperature conversion results from a chain
of AD7280s the current required for each AD7280 is typically
4mA, as outlined in Table 1. The time required to read back the
voltage conversions results from 96 Lithium Ion cells will
depend on the speed of the interface clock used, that is SCLK,
but it can be as low as 3.2ms.
In the event that thermistors circuits are being used to measure
each individual cell temperature the Thermistors Termination
pin, VTTERM, may be used to the terminate the thermistor
inputs for each cell temperature measurement. This reduces the
termination resistor requirement from 6 resistors to 1. Bit D3 in
the CONTROL register should be set to 1 when using the
VTTERM input.
The typical current consumed by the AD7280 when the cell
balancing outputs are switched on is 4.5mA. The duration of
the Cell Balance outputs on time is defined by the user.
It should be noted that, due to settling time requirements, the
thermistor termination resistor option should only be used
when the acquisition time of the AD7280 is set to its highest
value, that is, 1.6µs. The acquisition time is configured by
setting bits D6 and D5 of the CONTROL register as outlined in
Table 7.
When the AD7280 is not being used in any of the above modes
of operation it is recommended that the AD7280 be powered
down, as outlined below. This will significantly reduce the
current draw by each AD7280 on the chain which will avoid
unnecessary draining of the Lithium Ion cells.
AD7280
POWER DOWN
VREG
Rterm
The AD7280 provides a number of powerdown options. These
may be described as follows:
VTTERM
VT1
VT2
VT3
VT4
VT5
•
•
Full Powerdown (Hardware)
Software Powerdown
The AD7280 may be placed into full powerdown mode, which
requires only 4uA max current, by taking the pin low. The
VT6
VSS
PD
pin will power down all analog and
falling edge of the
PD
digital circuitry. The AD7280 includes a digital filter on the
PD
pin which prevents the power down being initiated by noise or
Figure 18. Typical Circuit using the Thermistor Termination Resistor
glitches on the hardware
pin. A hardware power down will
PD
In the example shown the termination resistor is placed
between the source voltage and the thermistor in the thermistor
circuit. The VTTERM input may be used to terminate the
thermistor inputs to either high or low voltage of the
Thermistor circuit.
not be initiated until the
approximately 150μs. Similarly the AD7280 will not be taken
out of powerdown mode until the
for approximately 5μs.
pin has been held low for
PD
pin has been held high
PD
The AD7280 may be placed into Software Power down mode,
which requires only 1.8mA of current by setting bit D8 in the
CONTROL register through the serial interface. When the
AD7280 is powered down through the serial interface the
regulator, the reference and the daisy chain circuitry stay
powered up but the remaining analog and digital circuitry is
powered down. This is necessary to ensure that the signal to
power on the part, or series of parts, is correctly received.
POWER REQUIREMENTS
The current consumed by the AD7280 in normal operation,
that is when not in powerdown mode, is dependent on the
mode in which the part is being operated. In a typical Lithium
Ion battery monitoring application there are 3 distinct modes of
operation. These can be described as follows:
•
•
•
Voltage and Temperature Conversion
AD7280 Configuration & Data Readback
Cell Balancing
The AD7280 offers a PD TIMER register which allows the user
to program a set time after which the AD7280 will go into
power down. This will act as a time delay between the falling
edge of the
input, or the setting of bit D8 in the CONTROL
PD
register, and the AD7280 powering down. The PD Timer can be
set to a value between 0 and 39 minutes, with a resolution of 75
seconds. The user should first write to the PD TIMER register,
to define the desired delay. Any subsequent falling edge on the
The AD7280 consumes its highest level of current while
converting voltage and/or temperature inputs to digital outputs.
Depending on the configuration of the AD7280 the conversion
time can be as little as 6us. As outlined in Table 1 the typical
current required by the AD7280 during conversion is 7mA.
input or setting of bit D8 the CONTROL register, will start
PD
the PD timer and after the programmed time will place the
AD7280 into powerdown. The default value of the PD TIMER
When configuring the chain of AD7280s or when reading back
Rev. PrF | Page 18 of 38
Preliminary Technical Data
AD7280
register on power up is 0h.
Vin6
POWER UP TIME
10kΩ
10kΩ
10kΩ
CB6
Vin5
As outlined in the Power Down section a full power down of
the AD7280, that is, an active low on the
input, will power
PD
CB5
Vin4
down all analog and digital circuitry. The recommended power
up time for the internal reference, when decoupled with a 10µF
capacitor, is 10ms. It is recommended that no conversions be
completed until the 10ms power up time has elapsed as it may
result in inaccurate data.
AD7280
CB4
Vin3
10kΩ
10kΩ
CB3
Vin2
CELL BALANCING OUTPUTS
The AD7280 provides 6 CB outputs which can be used to drive
the gate of external transistors as part of a cell balancing circuit.
Each CB output may be set to provide either a 0V or 5V output
with respect to the absolute amplitude of the negative terminal
of the battery cell which is being balanced. For example, the
CB6 output will provide a 0V or 5V output with respect to the
voltage on the Vin5 analog input. The CB outputs are set by
writing to the CELL BALANCE register. The default value of
the CELL BALANCE register on power up is 0h.
CB2
Vin1
10kΩ
CB1
Vin0
Figure 19. Cell Balancing Configuration
The AD7280 offers 6 Cell Balance timer registers which allow
the on-time of each CB output to be programmed. These are
referred to as the CB TIMER registers. The CB timers can be
set to a value between 0 and 39 minutes. The resolution of the
CB Timer is 75 seconds. At the end of the programmed CB
Time the 6 CB outputs will return to their default state of 0V.
The default value of the CB TIMER registers on power up is 0h.
In an application which daisychains a number of AD7280s
together it is recommended that series resistors be placed
between the CB outputs of the AD7280 and the gates of the
external Cell Balancing transistors. These are recommended to
protect the AD7280s in the event that the external cell
balancing transistors are damaged during the initial connection
of the monitoring circuitry to the battery stack.
As noted in the Power Down section a power down timer may
be programmed to allow cell balancing to occur for a set time
before powering down the AD7280. If no power down timer
has been set, that is if the PD TIMER register is at its default
value of 0h, then a falling edge on the PD pin, or the setting of
bit D8 in the CONTROL register to 1, will switch off the CB
outputs and power down the AD7280. If a power down time has
been set the CB outputs will be powered down when the
programmed power down timer has elapsed and the AD7280 is
powered down.
An example of how this could occur would be a connection
sequence which first provides the system ground, that is the
ground supply to the master AD7280 on the daisychain,
followed by a connection from any of the battery cells at a
potential high enough to exceed the VGS of the cell balancing
transistor, for example 40V. If these two connections are the
only battery connections made in the system then this will
result in 40V being applied to one of the Vin pins of the
AD7280, which is also connected to the source input of one of
the cell balancing transistors. However, because no power has
been supplied to the VDD pin of the AD7280 all the CB outputs
will be 0V. This will result in a reverse voltage of 40V across the
VGS of the external transistor which may damage the device.
In the event that the external transistor is damaged, the AD7280
may be protected by the use of 10kOhm series resistors on each
of the CB output pins. Consideration should also be given to the
protection of these external transistors during the initial
connection of the monitoring circuitry to the battery stack.
Rev. PrF| Page 19 of 38
Preliminary Technical Data
AD7280
ALERT OUTPUT
The Alert output on the AD7280 may be used to indicate if any
of the following faults have occurred:
Table 8.ALERT Register settings
D7 to D6
D5 to D4
D3 to D0
AD7280 Action
00
XX
XXXX
No Alert signal generated
or passed [Default]
01
10
XX
00
XXXX
XXXX
Generates static [High]
Alert signal to be passed
down the Daisy Chain
Generates 100Hz Square
wave Alert signal to be
passed down the Daisy
Chain
Generates 1kHz Square
wave Alert signal to be
passed down the Daisy
Chain
Reserved
Reserved
•
•
•
•
Over-Voltage
Under-Voltage
Over-Temperature
Under-Temperature
10
01
XXXX
Following each completed conversion the cell voltage and
temperature measurement results are compared to the fault
thresholds. The fault thresholds can be set by writing to the
OVER VOLTAGE. UNDER VOLTAGE, OVER TEMP and
UNDER TEMP registers. An ALERT output is generated if the
cell voltage or temperature results are outside the programmed
fault thresholds.
10
10
11
10
11
XX
XXXX
XXXX
XXXX
Passes Alert signal from
AD7280 at higher
potential in Daisy Chain
D7 to D4
XXXX
D3 to D2
00
D1 to D0
XX
AD7280 Action
Includes all 6 Voltage
channels in Alert
detection [Default]
Removes Vin5 from Alert
detection
Removes Vin5 & Vin4
from Alert detection
Reserved
Includes all 6
Temperature channels in
Alert detection [Default]
The Alert output can be defined as a static or a dynamic output,
this is set by writing to the ALERT register. The static Alert
output is a high signal which is pulled low in the event of an
over or under voltage or temperature. The dynamic Alert is a
square wave which can be programmed to a frequency of 100Hz
or 1kHz. The Alert output may be used as part of a daisy chain
in which case the AD7280 at the top of the chain, that is
furthest away from the DSP/µP should be programmed to
generate the initial Alert output and each AD7280 in the chain
will either pass that output through or pull the Alert signal low
to indicate that there is a fault with that particular device. At
the end of the daisy chain the master AD7280, that is the
AD7280 which is connected to the DSP/µP will take the Alert
signal from the chain and pass it, in standard digital voltage
format to the DSP/µP. The functionality of the fault detection
circuit, which generates the Alert output, may be programmed
through bits D7 to D4 of the ALERT register.
XXXX
XXXX
01
10
XX
XX
XXXX
XXXX
11
XX
XX
00
XXXX
XXXX
XX
XX
01
10
Removes VT5 from Alert
detection
Removes VT5 & VT3 from
Alert detection
The operation of the ALERT output can be verified by initiating
a Self-Test conversion. The self-test conversion will convert a
known voltage, 1.2V, which will trigger an ALERT output if the
under voltage fault threshold is higher than 1.2V. To test the
ALERT output the self-test should be initiated on the AD7280
furthest away from the DSP/µP. This allows the ALERT path
through each AD7280 to be verified. The remaining AD7280s
in the battery stack should be placed into software powerdown
to ensure that only the part which is converting the self-test
voltage may generate an ALERT output.
As outlined previously (See Conversion of less thAn 6 Voltage
cells) some applications may require less than 6 voltage
measurements. As shown in Figure 17 it is recommended that
the channels which are not being used on the AD7280 be
shorted to the channel below them. To prevent the incorrect
triggering of the Alert output in this application the AD7280
allows the user to select up to 2 voltage channels which may be
taken out of the fault detection circuit. This may be
programmed through bits D3 and D2 of the ALERT register.
Rev. PrF | Page 20 of 38
Preliminary Technical Data
AD7280
The SELF-TEST register stores the conversion result of the
REGISTER MAP
ADC self-test. A self-test conversion is initiated by setting bits
D15 and D14 of the CONTROL register to 11. The user should
then pulse the CNVST input or complete a software convert
Table 9.
Register Name
Register
Address
Register
Data
Read/Write
Register
start through the
input. The conversion result is in 12-bit
CS
CELL VOLTAGE 1
CELL VOLTAGE 2
CELL VOLTAGE 3
CELL VOLTAGE 4
CELL VOLTAGE 5
CELL VOLTAGE 6
CELL TEMP 1
0h
1h
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D11 to D0
D15 to D8
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
D7 to D0
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
natural binary format.
2h
CONTROL REGISTER
Table 13. 16-Bit Register
3h
Dh
D15 to D8
Read/Write
Read/Write
4h
Eh
D7 to D0
5h
6h
The CONTROL register is a 16-bit register that sets the AD7280
Control modes.
CELL TEMP 2
7h
CELL TEMP 3
8h
Table 14. 16-Bit Register
D15 to D14
CELL TEMP 4
9h
Select Conversion Inputs
00 = 6 Voltage & 6 Temp [default]
01 = 6 Voltage & Temp 1,3 &5
10 = 6 Voltage only
CELL TEMP 5
Ah
CELL TEMP 6
Bh
SELF TEST
Ch
CONTROL
Dh
Eh
11 = ADC Self Test
D13 to D12
Read Conversion Results
00 = 6 Voltage & 6 Temp [default]
01 = 6 Voltage & Temp 1,3 &5
10 = 6 Voltage only
11 = No Read operation
Conversion Start Format
0 = Falling edge of CNVST input [default]
1 = Rising edge of CS
OVER VOLTAGE
UNDER VOLTAGE
OVER TEMP
UNDER TEMP
ALERT
Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
D11
CELL BALANCE
CB TIMER 1
CB TIMER 2
CB TIMER 3
CB TIMER 4
CB TIMER 5
CB TIMER 6
PD TIMER
D10 to D9
Conversion Averaging
00 = Single Conversion only [default]
01 = Average by 2
10 = Average by 4
11 = Average by 8
D8
Powerdown format
0 = Falling edge of PD input [default]
1 = Software PD
READ
CONTROL 3
D7
Software Reset
0 = Bring out of Reset [default]
1= Reset AD7280
Set Acquisition Tme
CELL VOLTAGE REGISTERS
Table 10. 12-Bit Registers
D6 to D5
0h to 5h
D11 to D0
Read/Write
00 = Acquisition time 400ns [default]
01 = Acquisition time 800ns
10 = Acquisition time 1.2us
11 = Acquisition time 1.6us
Reserved; set to 1
Thermistor Termination Resistor
0 = Function not in use [default]
1 = Termination resistor connected
Lock Device Address
The CELL VOLTAGE registers store the conversion result from
each cell input. The conversion result is in 12-bit natural binary
format.
D4
D3
CELL TEMPERATURE REGISTERS
Table 11. 12-Bit Register
6h to Bh
D11 to D0
Read/Write
D2
The CELL TEMP registers store the conversion result from each
temperature input. The conversion result is in 12-bit natural
binary format.
0 = Does not lock to new Device Address.
Contiues to operate with Device Address
0h. [default]
1 = Part locks to new Devices Address it is
presented with.
SELF-TEST REGISTER
Table 12. 12-Bit Register
Ch
D11 to D0
Read/Write
Rev. PrF| Page 21 of 38
Preliminary Technical Data
AD7280
D1
Increment Device Address
Acquisition time of the ADC. Please refer to the Track-and-
Hold section for further detail. The default value of the
Conversion time setting is 00.
0 = Does not increment the Device
Address when transferring data up the
Daisychain.
1 = Increments the Device Address when
transferring data up the Daisychain
[default]
Daisychain Register Readback
0 = Function not in use
1 = Set Daisychain for Register Readback
[default]
Table 15.Analog Input Acquisition Time.
D6 to D5
Acquisition Time
00
01
10
11
400 ns
800 ns
D0
1.2 µs
1.6 µs
Thermistor Termination Resistor
Select Conversion Inputs
Bit D3 of the CONTROL register should be set if the user
wishes to use a single thermistor termination resistor on the
VTTERM pin. It should be noted that, due to settling time
requirements, the thermistor termination resistor option should
only be used when the acquisition time of the AD7280 is set to
its highest value, that is, 1.6µs.
Bits D15 and D14 of the CONTROL register determine which
cell voltages and temperatures are converted following a
pulse or the setting of the CNVST bit, D11, in the
CNVST
CONTROL register. The default value of D15 and D14 on
power up are 00.
Read Conversion Results
Lock Devices Address
Bits D13 and D12 of the CONTROL register determine which
cell voltages and temperatures conversion results are supplied to
the serial or Daisychain data outputs pins for readback. The
default value of D15 and D14 on power up are 00.
Bit D2 of the CONTROL register is used in conjunction with bit
D1 to allow individual Device Addresses for each AD7280 in
the daisychain to be defined and locked to the part. Bit D1 is
used to generate the individual Device Addresses which are
presented to each AD7280 in the daisychain in the form of a
write command. When bit D2 is set high the AD7280 locks to
the Device Address which is has been presented with. This new
Device Address is used for all subsequent CRC calculations.
When bit D2 is reset low the Device Address of the AD7280 is
not locked. In this case a Device Address of 0h will be used for
CRC calculations.
Conversion Start Format
The AD7280 offers two methods of initiating a conversion, the
hardware
pin or the software
input. Bit D11 of the
CNVST
CONTROL register determines whether a conversion is
initiated on the falling edge of the input or on the rising
CS
CNVST
edge of the CS input. The default format on power up is the
pin. When using the rising edge of CS to initiate
CNVST
Increment Device Address
conversions it should be noted that bit D11 is reset to 0
following the initiation of conversions.
Bit D1 of the CONTROL register determines whether the
AD7280 increments the Device Address it receives as part of a
write command when transferring that command up the
daisychain. When bit D1 is set to 1 the Device Address is
incremented as the command is passed up the chain. This mode
of operation is used on initial power up and following a reset
operation to allow individual Device Addresses for each
AD7280 in the daisychain stack to be defined, When D1 is reset
to 0 no change is made to the Device Address as the command
is passed up the chain.
Conversion Averaging
Bits D10 and D9 of the CONTROL register determines the
number of conversions completed on each input with the
average result being stored in the Result registers. The default
value of the Conversion Averaging bits is 00, that is, no
averaging.
Powerdown Format
Bit D8 of the CONTROL register allows the AD7280 be placed
into a software powerdown. Please refer to the Power Down
section for more details. The default format on power up is
Daisychain Register Readback
Bit D0 of the CONTROL register enables the readback of
individual registers from each AD7280 is a daisychain. When
bit D0 is set high the application of sufficient clocks will allow
the data stored in the register address identified by the READ
register to be shifted out of each AD7280 in turn. This data will
be passed down the daisychain and read back by the DSP/μP.
When bit D0 is reset low daisychain read is disabled. Repeated
read requests when D0 is low will result in the repeated
readback of an individual register from a single device.
powerdown through the
pin.
PD
Software Reset
Bit D7 of the CONTROL register allows the user to initiate a
software Reset of the AD7280. Two write commands are
required to complete the reset operation. Bit D7 must be set
high to put the AD7280 into Reset. Bit D7 must then be set low
to bring the AD7280 out of Reset.
Select Acquisition Time
Bits D6 and D5 of the CONTROL register determine the
Rev. PrF | Page 22 of 38
Preliminary Technical Data
AD7280
the frequency of which can be set to either 100Hz or 1kHz.
OVER VOLTAGE REGISTER
Table 16. 8-Bit Register
When a number of AD7280s are operating in daisy chain mode
the ALERT configuration is set on the AD7280 furthest away
from the uP or DSP only. The ALERT registers on the
remaining AD7280s in the chain should be programmed to pass
the ALERT signal through the chain. Each of these parts will
pass the static or dynamic ALERT signal through the chain or
pull the signal low to indicate that an over/under voltage or
over/under temperature has occurred.
Fh
D7 to D0
Read/Write
The OVERVOLTAGE THRESHOLD register determines the
high voltage threshold of the AD7280. Cell voltage conversions
which exceed the Over Voltage threshold trigger the ALERT
output. The AD7280 allows the user to set the Over Voltage
threshold to a value between 1V and 5V. The resolution of the
Over Voltage threshold is 8-bits, that is, 16mV. The default
value of the Over Voltage threshold on power up is FFh.
Table 21.ALERT Register settings
D7 to D6 D5 to D4 D3 to D0 AD7280 Action
UNDER VOLTAGE REGISTER
Table 17. 8-Bit Register
00
XX
XXXX
No Alert signal generated
or passed [Default]
10h
D7 to D0
Read/Write
01
XX
XXXX
Generates static [High] Alert
signal to be passed down
the Daisy Chain
Generates 100Hz Square
wave Alert signal to be
passed down the Daisy
Chain
Generates 1kHz Square
wave Alert signal to be
passed down the Daisy
Chain
Reserved
Reserved
The UNDER VOLTAGE THRESHOLD register determines the
low voltage threshold of the AD7280. Cell voltage conversions
lower than the Under Voltage threshold trigger the ALERT
output. The AD7280 allows the user to set the Under Voltage
threshold to a value between 1V and 5V. The resolution of the
Under Voltage threshold is 8-bits, that is, 16mV. The default
value of the Under Voltage threshold on power up is 00h.
10
10
00
01
XXXX
XXXX
OVER TEMP REGISTER
Table 18. 8-Bit Register
11h
10
10
11
10
11
XX
XXXX
XXXX
XXXX
D7 to D0
Read/Write
Passes Alert signal from
AD7280 at higher potential
in Daisy Chain
The OVER TEMP THRESHOLD register determines the high
temperature threshold of the AD7280. Cell temperature
conversions which exceed the Over Temp threshold trigger the
ALERT output. The AD7280 allows the user to set the Over
Temperature threshold to a value between 0V and 5V. The
resolution of the Over Temperature threshold is 8-bits, that is,
19mV. The default value of the Over Voltage threshold on
power up is FFh.
D7 to D4 D3 to D2 D1 to D0 AD7280 Action
XXXX
00
XX
Includes all 6 Voltage
channels in Alert detection
[Default]
Removes Vin5 from Alert
detection
Removes Vin5 & Vin4 from
Alert detection
Reserved
Includes all 6 Temperature
channels in Alert detection
[Default]
Removes VT5 from Alert
detection
XXXX
XXXX
01
10
XX
XX
UNDER TEMP REGISTER
Table 19. 8-Bit Register
12h
XXXX
XXXX
11
XX
XX
00
D7 to D0
Read/Write
The UNDER TEMP THRESHOLD register determines the low
temperature threshold of the AD7280. Cell temperature
conversions lower than the Under Voltage threshold trigger the
ALERT output. The AD7280 allows the user to set the Under
Temperature threshold to a value between 0V and 5V. The
resolution of the Under Voltage threshold is 8-bits, that is,
19mV. The default value of the Under Voltage threshold on
power up is 00h.
XXXX
XXXX
XX
XX
01
10
Removes VT5 & VT3 from
Alert detection
CELL BALANCE REGISTER
Table 22. 8-Bit Register
14h
D7 to D0
Read/Write
ALERT REGISTER
Table 20. 8-Bit Register
The CELL BALANCE register determines the status of the 6
Cell Balance outputs. The six CB outputs are set by writing to
bits D7 to D2 of the Cell Balance register. The default value of
the Cell Balance register on power up is 0h.
13h
D7 to D0
Read/Write
The ALERT register determines the configuration of the
ALERT function. The ALERT can be configured to be a static
or dynamic signal. The static signal is a high signal which is
pulled low to indicate that an over/under voltage or over/under
temperature has occurred. The dynamic signal is a square wave,
Table 23. Cell Balance register settings
D7
Set CB6 output
0 = output off
Rev. PrF| Page 23 of 38
Preliminary Technical Data
AD7280
1 = output on
Set CB5 output
0 = output off
1 = output on
Set CB4 output
0 = output off
1 = output on
Set CB3 output
0 = output off
1 = output on
Set CB3 output
0 = output off
1 = output on
Set CB1 output
0 = output off
1 = output on
Reserved, set to 0
READ REGISTER
Table 28. 8-Bit Register
1Ch D7 to D0
D6
Read/Write
The READ register, in conjunction with bits D13 and D12 of
the CONTROL register and bit D12 of the write operation
define the read operations of the AD7280. To read back a single
register from the AD7280 the register address should be first
written to the Read register. To read back a series of conversion
results from the AD7280 an address of 0h should be written to
the Read register. The default value of the READ register on
power up is 0h.
D5
D4
D3
Table 29. Read register settings
D7-D2
6-bit binary address for the
register to be read
D2
D1-D0
Reserved, set to 0
D1-D0
CONTROL 3 REGISTER
Table 30. 8-Bit Register
CB TIMER REGISTERS
Table 24. 8-Bit Register
15h to 1Ah D7 to D0
1Dh
The CONTROL 3 register allows the user to gate the input
signal from the pin. This will hold the internal
D7 to D0
Read/Write
Read/Write
CNVST
signal high regardless of any external noise or glitches on the
pin. This may be used in noisy environments to prevent
CNVST
The CB TIMER registers allows the user to program individual
ON times for each of the Cell Balance outputs. The AD7280
allows the user to set the CB Timer to a value between 0 and 39
minutes. The resolution of the CB Timer is 75 seconds. The
default value of the CB TIMER registers on power up is 0h.
CNVST
incorrect initiation of conversions. The default value of the
CONTROL 3 register on power up is 0h.
Table 31. Read register settings
Table 25. CB Timer register settings
D7-D1
D0
Reserved, set to 0
0 = Function not in use
1 = CNVST input gated
D7-D3
5-bit binary code to set CB timer to
value between 0 and 39 minutes
D2-D0
Reserved, set to 0
PD TIMER REGISTER
Table 26. 8-Bit Register
1Bh
D7 to D0
Read/Write
The PD TIMER register determines the elapsed time before the
AD7280 is automatically powered down. The AD7280 allows
the user to set the PD Timer to a value between 0 and 39
minutes. The resolution of the PD Timer is 75 seconds. When
using the PD timer in conjunction with the CB timers the value
programmed to the PD Timer should exceed that programmed
to the CB Timer by at least 1 minute. The default value of the
PD TIMER registers on power up is 0h.
Table 27. PD Timer register settings
D7-D3
5-bit binary code to set PD timer to
value between 0 and 39 minutes
D2-D0
Reserved, set to 0
Rev. PrF | Page 24 of 38
Preliminary Technical Data
SERIAL INTERFACE
AD7280
commands to individual AD7280s. A write to all devices on the
daisychain is completed by setting the ‘Address All Parts’ bit,
D12, of the write command to 1. When issuing a Write All
command the Device Address should be set to 0h. This is also
the Device Address to be used calculating the 8-bit CRC for
transmission with the Write All command.
The AD7280’s serial interface consists of four signals; , SCLK,
CS
SDIN and SDOUT. The SDIN line is used for transferring data
into the on chip registers while the SDOUT line is used for
reading the conversion results from the ADCs. SCLK is the
serial clock input for the device, and all data transfers, either on
SDIN or on SDOUT, take place with respect to SCLK. Data is
clocked into the AD7280 on the SCLK falling edge. Data is
8-bit CRC
clocked out of the AD7280 on the SCLK rising edge. The
input is used to frame the serial data being transferred to or
from the device. , can also be used to initiate the sequence of
CS
conversions.
,
CS
The AD7280 includes an 8-bit Cyclic Redundancy Check on all
Write commands to either individual parts or to a chain of
devices. An AD7280 which receives an invalid CRC in the Write
command will not execute the command. The CRC on the write
command is calculated based on bits D31 to D11 of the Write
command. This includes the Device Address, the Register
Address, the Data to be written, the Address All Parts bit and bit
D11. Further information on the CRC is outlined in Cyclic
Redundancy Check section.
Figure 20 shows the timing diagram for the serial interface of
the AD7280. Please refer to the Daisy Chain Interface section
for further information on the Daisy Chain Interface.
WRITING TO THE AD7280
In a Li-Ion Battery Monitoring application up to 20 AD7280’s
may be daisy chained together to allow up to 120 individual Li-
Ion cell voltages to be monitored. Each write operation must
therefore include Device Address and Register Address in
addition to the data to be written. An additional identifier bit is
also required when addressing all AD7280s in the Daisy Chain.
The AD7280 SPI Interface, in combination with the Daisy
Chain Interface, allows any register in the 20 x AD7280 stack to
be updated using one 32-bit write cycle. The 32-bit write
sequence is outlined in Table 32.
READING FROM THE AD7280
There are two different types of read operation for the AD7280.
•
•
Conversion Results Read
Register Data Read
The data returned from a conversion result read operation
includes the Device Address, the Channel Address, a Write
Acknowledgement bit and the 8-bit CRC information in
addition to the 12-bits of conversion data. The data returned
from a Register Data read operation includes the Device
Address, the Register Address, a Write Acknowledgement bit
and the 8-bit CRC information in addition to the 8-bits of
register data. The 32-bit Read cycle for a Conversion Result
Read is outlined in Table 33. The 32-bit Read cycle for a
Register Data Read is outlined in Table 34.
Device Address
The Device Address is a 5-bit address which allows each
individual AD7280 in battery monitoring stack to be uniquely
identified. On initial power up each AD7280 is configured with
a default address of 0h. A simple sequence of commands,
outlined in the Addressing the AD7280 section, allows each
AD7280 to recognize it’s unique in the stack. This devices
address can be then locked to the AD7280 and will be used in
subsequent read and write commands. The Device Address is
written to and read from the AD7280 stack in reverse order,
that is, LSB first.
The AD7280 SPI Interface, in combination with the Daisy
Chain Interface, allows the conversion results of any AD7280 in
the 20 x AD7280 stack to be read back using an N x 32-bit read
cycle, where N is defined by the number of conversions
completed on that part, that is 12, 9 or 6 (Please refer to Table
6).
Register Address
The register map for the AD7280 is outlined in Table 9. Each
Register Address is 6-bit address and is used when writing to or
reading from the on chip registers of the AD7280.
Device Address
The Device Address is a 5-bit address which allows each
individual AD7280 in battery monitoring stack to be uniquely
identified. On initial power up each AD7280 is configured with
a default address of 0h. A simple sequence of commands,
outlined in the Addressing the AD7280 section, allows each
AD7280 to recognize it’s unique in the stack. This device
address can be then locked to the AD7280 and will be used in
subsequent read and write commands. The Device Address is
written to and read from the AD7280 stack in reverse order,
that is, LSB first.
Register Data
When issuing a write command to a part in the stack of
AD7280 devices the data to be written is an 8-bit word. As
outlined in Table 9, all Read/Write registers are 8 bits wide.
More details on the correct settings for each register may be
found in the Register map section.
Address All Parts
The AD7280 allows write commands to be issued
simultaneously to all devices on the daisychain, as well as write
Rev. PrF| Page 25 of 38
Preliminary Technical Data
AD7280
Channel Address
and compares it to that which was received by the part in the
transmitted write command. If the two CRC values match the
command is executed and the Write Acknowledgment bit in the
subsequent transmission of data from the device is set. If the
transmitted and calculated CRC do not match the write
command will not be executed and the Write
Acknowledgement bit will not be asserted, that is, it will be zero.
For examples on the use of the Write Acknowledgment bit
please refer to the Write Acknowledgement section.
The Channel Address allows each individual Voltage and
Temperature result to be uniquely identified. Each Channel
Address is 4-bits wide. The address for each channel is detailed
in the register map for the AD7280, Table 9.
Register Address
The register map for the AD7280 is outlined in Table 9. Each
Register Address is 6-bit address and is used when writing to or
reading from the on chip registers of the AD7280.
8-bit CRC
Conversion Data
The AD7280 includes an 8-bit Cyclic Redundancy Check on all
data read back from the device, that is both Conversion result
reads and register data reads. When reading back conversion
data from the AD7280 the 8-bit CRC will include the Device
address, the Channel Address, the Conversion Data and the
Write Acknowledge bit. When reading back register data from
the AD7280 the 8-bit CRC will include the Device address, the
Register Address, the Register Data, two reserved zero-bits and
the Write Acknowledge bit. In both cases the CRC is generated
on bits D31 to D10 of the 32-bit read cycle, and is transmitted
using bits D9 to D2 of the same read cycle. Further information
on the CRC is outlined in Cyclic Redundancy Check section.
The 12-bit conversion result from the Voltage inputs, the
Temperature inputs or the ADC Self-test conversion.
Register Data
The 8-bit register data which was requested in a previous write
command.
Write Acknowledgement bit
As indicated above (Writing to the AD7280), an 8-bit CRC is
included in the Write command transmitted to the AD7280.
This is calculated based on bits D31 to D11. A CRC check is
completed before the write command is executed on the device.
Using the same CRC algorithm the AD7280 calculates the CRC
Table 32. 32-Bit Write Cycle
Device
Address1
D31-D27
Register
Address
D26-D21
Register
Data
Address All Parts Reserved
[Zero-bit]
8-bit CRC
Reserved
[Zero-bits]
D2-D0
D20- D13
D12
D11
D10-D3
Table 33. 32-Bit Read Conversion result Cycle
Device Address2
Channel Address
Conversion Data
Write
Acknowledge
8-bit CRC
Reserved
[Zero-bits]
D1-D0
D31-D27
D26-D23
D22-D11
D10
D9-D2
Table 34. 32-Bit Read Register Data Cycle
Device Address2
Register Address
Register Data
Zero
D12-D11
Write
Acknowledge
8-bit CRC
D9-D2
Reserved
[Zero-bits]
D1-D0
D31-D27
D26-D21
D20-D13
D10
1 Device Address should be written LSB first. For example, to address the second device on the stack, that is, the first slave device, the sequence of bits input to the
AD7280 should be 10000. The Register Address, Data bits and CRC bits are input MSB first.
2 Device Address is read out LSB first. The Register Address, Channel Address, all Data bits and CRC bits are read out MSB first.
Rev. PrF | Page 26 of 38
Preliminary Technical Data
AD7280
CS
t2
t8
t10
2
3
4
32
SCLK
SDO
1
t11
t9
t6
t7
t3
MSB
MSB-1
MSB-1
LSB
THREE-STATE
THREE-
STATE
t5
t4
SDI
MSB
LSB
Figure 20. Serial Interface Timing Diagram
being written to the same register address on all parts. The
Device address, bits D32-D27, should be set to 0 when writing
to all parts in the stack and this device address should be used
in the CRC calculation, see the Cyclic Redundancy Check
section for more information. For example, when initiating a
ADDRESSING THE AD7280
In any application using a chain of AD7280’s the Device
Address corresponds to the position of the individual AD7280
in the chain with respect to the device acting as Daisy Chain
Master, that is the device connected directly to the DSP/µP. For
example, in an application which uses 16 AD7280’s to monitor
96 channels the device acting as Daisy Chain Master should be
addressed with a Device Address of 00000, the 16th AD7280 in
the chain should be addressed with a Device Address of 01111.
This device address must be written to the part LSB first as
outlined in Table 32.
conversion using the rising edge of , on all AD7280s in the
CS
stack the following 32 bit write sequence must be written to the
device:
•
•
Device address bits D31-D27 should be set to 0.
Register address bits D26-D21 should be set to Dh to
address the Control register.
On initial power up, when coming out of powerdown and
following a reset operation all AD7280s in the Daisychain will
default to a Device Address of 0h. The following sequence of
commands should be followed to allow each AD7280 in the
daisychain to recognize its unique position in the chain. It
should be noted that the following sequence will allow Device
Addresses on all parts in the chain to be configured and
confirmed through daisychain readback. A subset of these
commands may also be used to simply configure the Device
Addresses without readback confirmation.
•
Register data bits D20-D13 should be set to the
required settings for conversions/readback with bit
D11 set to 1 in order to initiate conversions on the
rising edge of
.
CS
•
•
Bit D12 should be set to 1 to address all parts in the
stack.
The result of the CRC calculation should be filled into
bits D10-D3,
•
A single Write All command should be sent to all
devices in the chain to write the address of Control
Register 2, Eh, to the Read register on all devices.
This will initiate a conversion on the rising edge of , on all
CS
AD7280s in the stack.
•
A second Write All command should be sent to all
devices in the chain to assert the Lock Device Address
bit, D2, to de-assert the Increment Device Address bit,
D1, and to assert the Daisychain Register Read bit, D0.
WRITE ACKNOWLEDGEMENT
The AD7280 SPI interface allows the user to write and read data
to and from the AD7280 at the same time, that is, as the device
is reading in one command it can provide output data on the
SDOUT pin in the same read/write cycle.
•
To verify that all AD7280s in chain have received and
locked their unique Device Address a Daisychain
Register Read should now be requested from all
devices. This may be done by continuing to apply sets
of 32 SCLKs framed by CS until the Control register 2
of each device in the daisychain has been read back.
The user should confirm that all device addresses are
in sequence.
On all writes to the AD7280, the device will internally perform
a CRC calculation on the received data, bits D31 to D11, and it
will verify this CRC against that transmitted by the DSP/uP. If
there is a difference between the CRC generated internally and
that received from the DSP/uP, the AD7280 will not perform
the write operation. If a subsequent 32 SCLK cycles framed by a
To write to the same register on all AD7280’s in the stack, bit
D12, the address all bit, in the 32-bit write cycle should be set
high. This will result in the 8-bit register data, bits D20-D13,
pulse are applied to the AD7280, bit D10, the Write
Acknowledgement bit on SDOUT will indicate to the processor
if the last write to the device was successful (the Write
CS
Rev. PrF| Page 27 of 38
Preliminary Technical Data
AD7280
Acknowledgement bit will be set if the write was successful).
The Write Acknowledgement bit is included in the 8-bit CRC
on the read cycle.
Write Operation CRC
For writes to the AD7280, the CRC will need to be computed in
the DSP/uP and sent as part of the write command. The CRC
must be computed on bits D31 to D11 of the write command,
that is, the device address, the register address, the data to be
written, the address all parts bit and bit D11 which is a reserved
zero input bit. The data is divided by the polynomial x8 + x5 + x3
+ x2 + x + 1 and the 8 bit remainder, following the division,
becomes the CRC bits, CRC[7] to CRC[0]. Note, if the user is
addressing all parts in the stack of AD7280s (by asserting the
Address All Parts bit D12), the CRC must be computed using a
device address of 0h and the data written to the device must
have a device address of 0h. The AD7280 will perform the same
CRC calculation on bits D31 to D11 received by AD7280 and it
will verify this CRC against that transmitted by the DSP/uP. If
there is a difference between the CRC generated within the
AD7280 and that received from the DSP/uP, the AD7280 will
not perform the write operation. To allow the user to verify that
the command has been received and implemented by the
AD7280s in the stack, a Write Acknowledgement bit is also
included in the 32-bit read cycles. For more information of the
Write Acknowledgment bit, see the Write Acknowledgement
section.
An example of how this could be used when writing to and
configuring a stack of AD7280 devices would be as follows; this
example sets the over-voltage thresholds on all devices in the
stack containing 16 AD7280s:
•
Execute a write all command to set register address Fh
(Over Voltage register) to the desired over voltage
threshold level
•
•
Apply a further 16 sets of 32 SCLKs, each framed by
to the master device
CS
A total of 17 sets of 32 SCLK frames have now been
applied to the device. The data read back from the
master device on the second 32 SCLK frame will
include the Write Acknowledgement bit for the Over
Voltage register write to the master device. The data
read back from the master device on the third 32
SCLK from will include the Write Acknowledgement
bit for the Over Voltage register write to the first slave
device in the stack and so on.
Read Operation CRC
It should be noted that by adding an additional step of writing
to the Read register on all devices in the stack first and pointing
to the register being written to ensures that the data provided
back from the stack of AD7280s includes this register data. In
this way, the CRC generated by the AD7280 and sent with the
data already includes the data you have previously written to
that register.
For reads from the AD7280, the 8-bit CRC is generated by the
AD7280 based on bits D31 to D10 of the 32 bit read cycle and is
transmitted using bits D9 to D2 of the same read cycle. When
reading back conversion data from the AD7280, the 8-bit CRC
will include the device address, the channel address, the
conversion data and the write acknowledgement bit. When
reading back register data from the AD7280 the 8-bit CRC will
include the device address, the register address, the register
data, two reserved zero bits and the write acknowledgement bit.
The data received is divided by the polynomial x8 + x5 + x3 + x2
+ x + 1 and the 8 bit remainder, following the division, becomes
the CRC bits, CRC[7] to CRC[0]. The user can compare the
CRC bits calculated, with the CRC that was received from the
AD7280 to check if there was any alteration in the data that was
transmitted by the AD7280.
CYCLIC REDUNDANCY CHECK
The AD7280 32-bit SPI interface includes an 8-bit Cyclic
Redundancy Check (CRC) on the read and write cycles. This
CRC may be used to detect any alteration in the data during
transmission to and from the AD7280. The principle of a cyclic
redundancy check is that the data to be transmitted is divided
by a fixed polynomial, the remainder of this mathematical
operation is then attached to the data and forms part of the
transmission. At the receiving end the same mathematical
operation should be completed on the data received. This will
confirm that the data received is the same as the data which was
originally transmitted.
The polynomial used by the AD7280 to calculate the CRC bits
is x8 + x5 + x3 + x2 + x + 1. The division is implemented using
the digital circuit outlined in Figure 21.
Rev. PrF | Page 28 of 38
Preliminary Technical Data
AD7280
DATA_IN
Q
Q
Q
Q
Q
Q
Q
D
Q
D
D
D
D
D
D
D
CRC[0]
CRC[1]
CRC[2]
CRC[5]
CRC[7]
CRC[3]
CRC[4]
CRC[6]
SCLK
Figure 21. CRC Implementation
CRC Pseudo Code
The CRC is computed in the DSP/uP on bits D31 to D11, that
The following pseudo code may be used to calculate the CRC.
First, the following variables need to be declared:
is, the device address, the register address, the data to be written
to the register, the address all parts bit and the reserved 0.
Num_Bits – The number of data bits that will be used to
calculate the CRC result, 21 for a data write to the AD7280 and
22 for a data read from the AD7280.
Device Address: 00000 (5’h0)
Register Address: 001101 (6’hD)
Data: 00001100 (8’hC)
i – Integer variable.
Address all bits: 0 (1’h0)
Reserved 0: 0 (1’h0)
xor_1, xor_2, xor_3, xor_4, xor_5 – Integer varibles. These are
the outputs of the XOR gates starting with the leftmost XOR
gate in the circuit implementation in Figure 21.
The data input to the CRC algorithm is therefore
000000011010000110000 (21’h3430). Following the completion
of the calculation, the value of CRC_7 to CRC_0 is 01010001
(8’h51). The data that is sent to the AD7280 for this serial write
is therefore:
data_in – Data bits that the CRC will be calculated on. D31 to
D11 for a write operation and D31 to D10 for a read operation.
This data supplies the input to the first XOR gate.
CRC_0, CRC_1, CRC_2, CRC_3, CRC_4, CRC_5, CRC_6,
CRC_7 – Integer variables. The outputs of the shift registers
starting at the leftmost shift register in the circuit
implementation in Figure 21.
0000 0001 1010 0001 1000 0010 1000 1000 (32’h1A18288)
CRC Calculation Example 2:
Writing data to the high byte of the Control Register of device
address 17 in the stack.
With the exception of data_in, all variables should be initialised
to zero. The following code will then implement the CRC
calculation as outlined in Figure 21 above.
The CRC is computed in the DSP/uP on bits D31 to D11 i.e. the
device address, the register address, the data to be written to the
register, the address all parts bit and the reserved 0.
for (i=Num_Bits; i>=0; i--)
{
Device Address (written LSB first): 10001 (5’h11)
Register Address: 001101 (6’hD)
Data: 00001100 (8’hC)
xor_5 = CRC_4 ^ CRC_7;
xor_4 = CRC_2 ^ CRC_7;
xor_3 = CRC_1 ^ CRC_7;
xor_2 = CRC_0 ^ CRC_7;
xor_1 = data_in[i] ^ CRC_7;
Address all bits: 0 (1’h0)
CRC_7 = CRC_6;
CRC_6 = CRC_5;
CRC_5 = xor_5;
CRC_4 = CRC_3;
CRC_3 = xor_4;
CRC_2 = xor_3;
CRC_1 = xor_2;
CRC_0 = xor_1;
}
Reserved 0: 0 (1’h0)
The data input to the CRC algorithm is therefore
100010011010000110000 (21’h113430). Following the
completion of the calculation, the value of CRC_7 to CRC_0 is
10011101 (8’h9D). The data that is sent to the AD7280 for this
serial write is therefore:
1000 1001 1010 0001 1000 0100 1110 1000 (32’h89A184E8)
CRC Calculation Example 1:
Writing data to the high byte of the Control Register of device 0
in the stack, that is, the lowest device in the stack.
Rev. PrF| Page 29 of 38
Preliminary Technical Data
AD7280
CRC Calculation Example 3:
completion of the calculation, the value of CRC_7 to CRC_0 is
01000110 (8’h46). This result matches the CRC that was sent
from the AD7280 so this transmission of data is valid.
Reading the data from the low byte of the Control Register of
device 0 in the stack, that is, the lowest device in the stack.
The CRC is computed in the AD7280 on bits D31 to D10, that
is, the device address, the register address, the register data, two
reserved zero bits and the write acknowledgement bit. The
calculated CRC is sent along with bits D31 to D10 to the
DSP/uP.
The data received from the AD7280 is as follows:
0000 0001 1100 0010 1000 0110 0110 1000 (32’h1C28668)
Device Address: 00000 (5’h0)
Register Address: 001110 (6’hE)
Register Data: 00010100 (8’h14)
Reserved 0’s: 0 (2’h0)
Write Acknowledgement: 1 (1’h1)
CRC: 10011010 (8’h9A)
The CRC bits are computed again in the DSP/uP on bits D31 to
D10 of the data that is read back from the AD7280. The data
input to the CRC algorithm is therefore
0000000111000010100001 (22’h70A1). Following the
completion of the calculation, the value of CRC_7 to CRC_0 is
10011010 (8’h9A). This result matches the CRC that was sent
from the AD7280 so this transmission of data is valid.
CRC Calculation Example 4:
Reading the conversion result from channel Vin3 on device 1 in
the stack.
The CRC is computed in the AD7280 on bits D31 to D13, that
is, the device address, the channel address, the conversion data,
and the write acknowledgement bit. The calculated CRC is sent
along with bits D31 to D10 to the DSP/uP.
The data received from the AD7280 is as follows:
1000 0001 0100 1100 1101 0101 0001 1000 (32’h814CD518)
Device Address (read LSB first): 10000 (5’h10)
Channel Address: 0010 (4’h2)
Conversion Data: 100110011010 (12’h99A)
Write Acknowledgement: 1 (1’h1)
CRC: 01000110 (8’h46)
The CRC bits are computed again in the DSP/uP on bits D31 to
D10 of the data that is read back from the AD7280. The data
input to the CRC algorithm is therefore
1000000101001100110101 (22’h205335). Following the
Rev. PrF | Page 30 of 38
Preliminary Technical Data
DAISY CHAIN INTERFACE
AD7280
propagation delay between adjacent parts on the daisychain, see
DELAY in Table 2. This delay does not apply if the part is reading
registers or conversion data from the part in daisychain mode,
that is, the max SCLK of 1MHz can always be used in
daisychain mode.
In a Li-Ion Battery Monitoring application up to 20 AD7280’s
may be daisy chained together to allow up to 120 individual Li-
Ion cell voltages to be monitored. Each AD7280 is capable of
monitoring up to 6 Li-Ion cells and is powered from the top and
bottom voltage of the 6 Li-Ion cells. As a result the supply
voltages of each AD7280 are offset by up to 30V from adjacent
AD7280’s in the chain. For this reason a standard Serial
Interface Daisy Chain method cannot be used.
t
When reading back both register and conversion data from the
device using the daisychain readback mode, the SDI line must
not just idle high or low but must be set up to address and write
to either the top device in the chain or address and write to a
part higher than the top device in the chain and set the Address
All Parts bit to 0. A recommendation would be to write to the
top available address, that is, address 31 and set the Address All
Parts bit to 0.
The AD7280 includes a Daisy Chain Interface separate to the
standard SPI interface. This Daisy Chain interface allows each
AD7280 in the chain to relay data to and from adjacent
AD7280’s. In addition to the standard 4 wire SPI the AD7280
serial interface include 3 optional interface pins, ALERT,
and
.
CNVST
PD
Each input and output pin on the 7 wire interface requires at
least one additional I/O for the Daisy Chain Interface, that is, to
allow the information to be passed to an AD7280 operating at a
higher supply voltage. The SDO and ALERT outputs will also
require a further daisy chain pin to allow the information to be
passed to an AD7280 operating at a lower supply voltage. The
remaining 5 interface pins, , SCLK, SDI,
and
do
CS
CNVST
PD
not require additional pins to pass information to a AD7280
operating at a lower voltage as each of these input pins can
operate as both SPI inputs or Daisy Chain inputs. Their
functionality is defined by the state of the Master pin.
The MASTER pin on the AD7280 at the base of the Daisy
Chain should be set high, tied to VDD supply, to ensure that this
device interfaces to the DSP or µProcessor using the standard
Serial Interface. The MASTER pin on the remaining AD7280s
in the Daisy Chain should each be connected to their respective
VSS pins which disable the serial interface pins on those devices.
This allows the , SCLK, SDI, and inputs, in
CS
CNVST
PD
addition to the SDOlo and ALERTlo outputs, to pass signals to
and from an AD7280 operating at a lower potential.
As explained in the Serial Interface section only one 32-bit write
cycle is required to write to any register in the 20 x AD7280
stack. To read back the conversion data from all channels
monitoring the battery stack requires only a (32 x N)-bit read
cycle where N is the number of channels in the battery stack.
Note: this is the default read configuration on power up. If the
settings of the Read or control registers have been changed then
additional write cycles may be required. The recommended
SCLK frequency to ensure correct operation of the Daisy Chain
Interface is 1MHz. With a 1MHz SCLK it will take ~3.2 ms to
read back the voltage conversions on 96 channels.
It should be noted that when reading from a single device in a
stack of AD7280s, in some cases the SCLK frequency will need
to be lower than 1MHz in order to read back the register data
from parts up the chain of AD7280s. This is due to the
Rev. PrF| Page 31 of 38
Preliminary Technical Data
AD7280
daisychain. Note: 0h is the default value of this register
on power up and following a reset operation.
READING DATA FROM THE AD7280
There are a number of read options available on the AD7280.
The user may read back the results from all the conversions
completed on an individual part in the chain, from all the
conversions completed on all parts in the chain or from
individual registers on selected parts in the chain.
•
Write to the Control register on all parts. Set bits D15
and D14 to select the required conversions. Set bits
D13 and D12 to select the required conversion results
for read back.
•
•
Initiate the conversions through either the falling edge
In each case the user is required to first write to the Read
register on the selected parts to configure that part to supply the
correct data on the outputs. When reading back an individual
register result, the address of that register should be written to
the read register of the selected part. When reading back
conversion results from any or all parts in the chain an address
of 0h should be written to the read register of the selected parts.
When the address written to the read register is 0h the
conversion results selected for read back are controlled by
setting bits D13 and D12 of the Control register. Please refer to
Table 14. This allows the user to select 4 different read back
options
of
or the rising edge of
.
CNVST
CS
Allow sufficient time for each conversion to be
completed plus 5μs. Please refer to Converting Cell
Voltages and Temperatures section.
•
Apply a
low pulse that frames 32 SCLKs for each
CS
conversion result to be read back.
The following section outlines eleven examples of Conversion
and/or Readback routines which would be commonly used in
an application using a chain of AD7280s to monitor the voltage
and/or temperature of the a stack of Lithium Ion batteries.
•
Read back 12 conversion results: 6 voltage and 6
temperature
Example 1: Convert and Read all parts, all voltages and
all temperatures
•
Read back 9 conversion results: 6 voltage and 3
temperature
•
Register address 0h should be written to the Read
register on all parts. A Device Address of 0 is used
when computing the CRC for commands to write to
all parts. The 32 bit write command is 32’h38011C8.
For a breakdown see Table 35, Example 1, Write 1.
•
•
Read back 6 conversion results: 6 voltage results only
Switch off read operation on this part
•
Bits D15-D12 of the CONTROL register should be set
to 0 on all parts. The 32 bit write command is
32’h1A01318. For a breakdown see Table 35, Example
1, Write 2.
If the user wishes to read back the conversion results from a
single AD7280 in the daisy chain bits D13 and D12 of the
control register on that part should be set to select the correct
conversion results. Bits D13 and D12 on all other AD7280s in
the daisy chain should be set to switch off the read operation on
those parts. It should be noted that it is more efficient in terms
of 32-bit write cycles to first switch off the read operation on all
AD7280s in the daisy chain. This can be achieved with a single
write cycle, using bit D12 to address all parts in the chain. The
user may then address the individual part and set bits D13 and
D12 to select the required conversion results.
•
•
Initiate conversions through the falling edge of
.
CNVST
Allow sufficient time for each conversion to be
completed plus 5μs. Following the completion of the
conversions, apply a
low pulse that frames 32
CS
SCLKs for each conversion result to be read back.
When reading back conversion data from any, or all, of the
AD7280s in a daisy chain the conversion results returned from
the AD7280 will be the last completed set of conversions on that
part. It is recommended that the user also set bits D15 and D14
of the control register, to select the number of conversions to be
completed on each part, and initiate the conversions through
Example 2: Convert and Read all parts, all voltages and
three temperatures per part
•
Register address 0h should be written to the Read
register on all parts. A Device Address of 0 is used
when computing the CRC for commands to write to
all parts. The 32 bit write command is 32’h38011C8.
For a breakdown see Table 35, Example 2, Write 1.
either the
pin or the rising edge of , as part of the
CNVST
CS
read operation. This allows the user to implement a simple
convert and read back routine with the most efficient number
of 32-bit write and read operations. A general example of this
routine, which would convert and read back from all parts in
the AD7280 daisy chain would be:
•
Bits D15 and D13 of the CONTROL register should be
set to 0, bits D14 and D12 should be set to 1 on all
parts. The 32 bit write command is 32’h1AA1060. For
a breakdown see Table 35, Example 2, Write 2.
•
Write 0h to the Read register on all of the parts in the
Rev. PrF | Page 32 of 38
Preliminary Technical Data
AD7280
SCLKs for each conversion result to be read back.
•
Initiate conversions through the falling edge of
.
CNVST
Example 5: Convert and Read one part, all voltages and
temperatures 1, 3 & 5
•
Allow sufficient time for each conversion to be
completed plus 5μs. Following the completion of the
•
•
•
Register address 0h should be written to the Read
register of the part that is to be read. This example
uses a device address of 5. The 32 bit write command
is 32’hA3800658. For a breakdown see Table 35,
Example 5, Write 1.
conversions, apply a
low pulse that frames 32
CS
SCLKs for each conversion result to be read back.
Example 3: Convert and Read all parts, all voltages and
no temperatures
Bits D13-D12 of the CONTROL register should be set
to 1 on all parts. This switches off the read operation
on all parts. The 32 bit write command is
32’h1A61518. For a breakdown see Table 35, Example
5, Write 2.
•
Register address 0h should be written to the Read
register on all parts. A Device Address of 0 is used
when computing the CRC for commands to write to
all parts. The 32 bit write command is 32’h38011C8.
For a breakdown see Table 35, Example 3, Write 1.
Bit D15 and D13 of the CONTROL register of the part
to be read from should be set to 0 and bits D14 and
D12 should be set to 1. This example uses a device
address of 5. The 32 bit write command is
32’hA1AA07F0. For a breakdown see Table 35,
Example 5, Write 3.
•
Bits D15 and D13 of the CONTROL register should be
set to 1, bits D14 and D12 should be set to 0 on all
parts. The 32 bit write command is 32’h1B415E8. For
a breakdown see Table 35, Example 3, Write 2.
•
•
Initiate conversions through the falling edge of
.
CNVST
•
•
Initiate conversions through the falling edge of
.
CNVST
Allow sufficient time for each conversion to be
completed plus 5μs. Following the completion of the
Allow sufficient time for each conversion to be
conversions, apply a
low pulse that frames 32
CS
completed plus 5μs. Following the completion of the
SCLKs for each conversion result to be read back.
conversions, apply a
low pulse that frames 32
CS
SCLKs for each conversion result to be read back.
Example 4: Convert and Read one part, all voltages and
all temperatures
•
•
•
Register address 0h should be written to the Read
register of the part that is to be read. This example
uses a device address of 2. The 32 bit write command
is 32’h438005F0. For a breakdown see Table 35,
Example 4, Write 1.
Example 6: Convert and Read one part, all voltages, no
temperatures
•
•
•
Register address 0h should be written to the Read
register of the part that is to be read. This example
uses a device address of 7. The 32 bit write command
is 32’hE3800270. For a breakdown see Table 35,
Example 6, Write 1.
Bits D13-D12 of the CONTROL register should be set
to 1 on all parts. This switches off the read operation
on all parts. The 32 bit write command is
32’h1A61518. For a breakdown see Table 35, Example
4, Write 2.
Bits D13-D12 of the CONTROL register should be set
to 1 on all parts. This switches off the read operation
on all parts. The 32 bit write command is
32’h1A61518. For a breakdown see Table 35, Example
6, Write 2.
Bits D15-D12 of the CONTROL register of the part to
be read from should be set to 0. This example uses a
device address of 2. The 32 bit write command is
32’h41A00720. For a breakdown see Table 35,
Example 4, Write 3.
Bits D14 and D12 of the CONTROL register of the
part to be read from should be set to 0 and bits D15
and D13 should be set to 1. This example uses a device
address of 7. The 32 bit write command is
32’hE1B40650. For a breakdown see Table 35,
Example 6, Write 3.
•
•
Initiate conversions through the falling edge of
.
CNVST
Allow sufficient time for each conversion to be
completed plus 5μs. Following the completion of the
•
Initiate conversions through the falling edge of
.
CNVST
conversions, apply a
low pulse that frames 32
CS
Rev. PrF| Page 33 of 38
Preliminary Technical Data
AD7280
register from all parts. The 32 bit write command is
32’h3829348. For a breakdown see Table 35, Example
8, Write 2.
•
Allow sufficient time for each conversion to be
completed plus 5μs. Following the completion of the
conversions, apply a low pulse that frames 32
CS
SCLKs for each conversion result to be read back.
•
Apply a
low pulse that frames 32 SCLKs for each
CS
device in the stack to read back the desired register
contents from all parts.
Example 7: Convert and Read a single voltage or
temperature result
Example 9: Read a single register
•
The register address corresponding to the voltage or
temperature result to be read should be written to the
Read register of the part that is to be read, see Table 9
for register addresses. This example reads the Cell
Voltage 6 result from device 3 in the stack. The 32 bit
write command is 32’hC3828658. For a breakdown
see Table 35, Example 7, Write 1.
•
•
•
Bits D13-D12 of the CONTROL register should be set
to 1 on all parts. This switches off the read operation
on all parts. The 32 bit write command is
32’h1A61518. For a breakdown see Table 35, Example
9, Write 1.
Bits D13 and D12 of the CONTROL register of the
part to be read from should be set to 0. This example
reads from part 1 in the stack. The 32 bit write
command is 32’h81A00220. For a breakdown see
Table 35, Example 9, Write 2.
•
•
Bits D13-D12 of the CONTROL register should be set
to 1 on all parts. This switches off the read operation
on all parts. The 32 bit write command is
32’h1A61518. For a breakdown see Table 35, Example
7, Write 2.
The register address corresponding to the
Bits D13 and D12 of the CONTROL register of the
part to be read from should be set such that a
configuration register to be read should be written to
the Read register of the part that is to be read, see
Table 9 for register addresses. This example reads the
Alert register from part 1 in the stack. The 32 bit write
command is 32’h83898008. For a breakdown see Table
35, Example 9, Write 3.
conversion will be completed on the required channel.
Note: With the exception of a Self-Test conversion it is
not possible to convert on a single channel, 6, 9 or 12
conversions must be completed. This example reads a
voltage conversion from device 3 in the stack so bits
D14 and D12 of the CONTROL register should be set
to 0 and bits D15 and D13 should be set to 1 on device
3. The 32 bit write command is 32’h C1B400F8. For a
breakdown see Table 35, Example 7, Write 3.
•
Apply a
low pulse that frames 32 SCLKs to read
CS
back the desired register contents.
Example 10: Self-Test conversion, all parts
•
•
Initiate conversions through the falling edge of
•
Bits D15-D14 of the CONTROL register should be set
to 1 and bits D13-D12 should be set to 0 on all parts to
select the self-test conversion. The 32 bit write
command is 32’h1B81090. For a breakdown see Table
35, Example 10, Write 1.
.
CNVST
Allow sufficient time for each conversion to be
completed plus 5μs. Following the completion of the
conversions, apply a
low pulse that frames 32
CS
SCLKs to read back the desired voltage or temperature
result.
•
•
Initiate conversions through the falling edge of
.
CNVST
Bit D0 of the CONTROL register should be set to 1 on
all parts. This enables the Daisychain Register Read
operation on all parts. The 32 bit write command is
32’h1C2B6E0. For a breakdown see Table 35, Example
10, Write 2.
Example 8: Read a single configuration register all parts
•
Bit D0 of the CONTROL register should be set to 1 on
all parts. This enables the Daisychain Register Read
operation on all parts. The 32 bit write command is
32’h1C2B6E0. For a breakdown see Table 35, Example
8, Write 1.
•
•
The register address corresponding to the self-test
conversion should be written to the Read register of all
parts, see Table 9 for register addresses. The 32 bit
write command is 32’h38617C8. For a breakdown see
Table 35, Example 10, Write 3.
•
The register address corresponding to the
configuration register to be read should be written to
the Read register on all parts, see Table 9 for register
addresses. This example reads the Cell Balance
Allow sufficient time for each conversion to be
Rev. PrF | Page 34 of 38
Preliminary Technical Data
AD7280
completed plus 5μs. Following the completion of the
on the part under test to select the self-test conversion.
Bits D13-D12 of the CONTROL register should be set
to 0 the part under test to enable reads. This example
reads self-test conversion result from device 4 in the
stack. The 32 bit write command is 32’h21B80628. For
a breakdown see Table 35, Example 11, Write 1.
conversions, apply a
low pulse that frames 32
CS
SCLKs for each device in the stack.
Example 11: Self-Test conversion, single part
•
Bits D13-D12 of the CONTROL register should be set
to 1 on all parts. This switches off the read operation
on all parts. Bit D8 in the CONTROL register of all
parts should be set to 1 to put each part into a
software power down. This prevents the ALERT
function on the parts not undergoing a self-test
conversion from being triggered. The 32 bit write
command is 32’h1A63538. For a breakdown see Table
35, Example 11, Write 1.
•
•
Initiate conversions through the falling edge of
.
CNVST
The register address corresponding to the self-test
conversion should be written to the Read register of
the part under test (device 4 in this case); see Table 9
for register addresses. The 32 bit write command is
32’h23860170. For a breakdown see Table 35, Example
11, Write 3.
•
Bit D8 in the CONTROL register of the part for which
a self-test conversion is requested should be set to 0.
This brings this part out of software power down. Bits
D15-D14 of the CONTROL register should be set to 1
•
Allow sufficient time the self-test conversion to be
completed plus 5μs. Following the completion of the
conversion, apply a
low pulse that frames 32
CS
SCLKs to read back the single self-test result.
Table 35. Reading Data from the AD7280 Examples
Device
Address
Register Address
Data
Write
All
0
8-bit CRC
000
32-bit Write
Command
Example 1 – Write 1
Example 1 – Write 2
Example 2 – Write 1
Example 2 – Write 2
Example 3 – Write 1
Example 3 – Write 2
Example 4 – Write 1
Example 4 – Write 2
Example 4 – Write 3
Example 5 – Write 1
Example 5 – Write 2
Example 5 – Write 3
Example 6 – Write 1
Example 6 – Write 2
Example 6 – Write 3
Example 7 – Write 1
Example 7 – Write 2
00000 = 5’h0
00000 = 5’h0
00000 = 5’h0
00000 = 5’h0
00000 = 5’h0
00000 = 5’h0
01000 = 5’h8
00000 = 5’h0
01000 = 5’h8
10100 = 5’h14
00000 = 5’h0
10100 = 5’h14
11100 = 5’h1C
00000 = 5’h0
11100 = 5’h1C
11000 = 5’h18
00000 = 5’h0
011100 = 6’h1C
001101 = 6’hD
011100 = 6’h1C
001101 = 6’hD
011100 = 6’h1C
001101 = 6’hD
011100 = 6’h1C
001101 = 6’hD
001101 = 6’hD
011100 = 6’h1C
001101 = 6’hD
001101 = 6’hD
011100 = 6’h1C
001101 = 6’hD
001101 = 6’hD
011100 = 6’h1C
001101 = 6’hD
00000000 = 8’h0
00000000 = 8’h0
00000000 = 8’h0
01010000 = 8’h50
00000000 = 8’h0
10100000 = 8’hA0
00000000 = 8’h0
00110000 = 8’h30
00000000 = 8’h0
00000000 = 8’h0
00110000 = 8’h30
01010000 = 8’h50
00000000 = 8’h0
00110000 = 8’h30
10100000 = 8’hA0
00010100 = 8’h14
00110000 = 8’h30
1
1
1
1
1
1
0
1
0
0
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00111001 = 8’h39
01100011 = 8’h63
00111001 = 8’h39
00001100 = 8’hC
00111001 = 8’h39
10111101 = 8’hBD
10111110 = 8’hBE
10100011 = 8’hA3
11100100 = 8’hE4
11001011 = 8’hCB
10100011 = 8’hA3
11111110 = 8’hFE
01001110 = 8’h4E
10100011 = 8’hA3
11001010 = 8’hCA
11001011 = 8’hCB
10100011 = 8’hA3
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
000
32’h38011C8
32’h1A01318
32’h38011C8
32’h1AA1060
32’h38011C8
32’h1B415E8
32’h438005F0
32’h1A61518
32’h41A00720
32’hA3800658
32’h1A61518
32’hA1AA07F0
32’hE3800270
32’h1A61518
32’hE1B40650
32’hC3828658
32’h1A61518
Rev. PrF| Page 35 of 38
Preliminary Technical Data
AD7280
Example 7 – Write 3
Example 8 – Write 1
Example 8 – Write 2
Example 9 – Write 1
Example 9 – Write 2
Example 9 – Write 3
11000 = 5’h18
00000 = 5’h0
00000 = 5’h0
00000 = 5’h0
10000 = 5’h10
10000 = 5’h10
001101 = 6’hD
001110 =6’hE
011100 = 6’h1C
001101 = 6’hD
001101 = 6’hD
011100 = 6’h1C
10100000 = 8’hA0
00010101 = 8’h15
01010000 = 8’h50
00110000 = 8’h30
00000000 = 8’h0
01001100 = 8’h4C
0
1
1
1
0
0
0
0
0
0
0
0
00011111 = 8’h1F
11011100 = 8’hDC
01010110 = 8’h56
10100011 = 8’hA3
01000100 = 8’h44
00000001 = 8’h01
000
000
000
000
000
000
32’hC1B400F8
32’h1C2B6E0
32’h38A12B0
32’h1A61518
32’h81A00220
32’h83898008
32’h1B81090
32’h1C2B6E0
32’h38617C8
Example 10 – Write 1
Example 10 – Write 2
Example 10 – Write 3
00000 = 5’h0
00000 = 5’h0
00000 = 5’h0
001101 = 6’hD
001110 =6’hE
011100 = 6’h1C
11000000 = 8’hC0
00010101 = 8’h15
00110000 = 8’h30
1
1
1
0
0
0
00010010 = 8’h12
11011100 = 8’hDC
11111001 = 8’hF9
000
000
000
Example 11 – Write 1
Example 11 – Write 2
Example 11 – Write 3
00000 = 5’h0
00100 = 5’h4
00100 = 5’h4
001101 = 6’hD
001101 = 6’hD
011100 = 6’h1C
00110001 = 8’h31
11000000 = 8’hC0
00110000 = 8’h30
1
0
0
0
0
0
10100111 = 8’hA7
11000101 = 8’h C5
00101110 = 8’h 2E
000
000
000
32’h1A63538
32’h21B80628
32’h23860170
Rev. PrF | Page 36 of 38
Preliminary Technical Data
OUTLINE DIMENSIONS
AD7280
9.20
9.00 SQ
8.80
0.75
0.60
0.45
1.60
MAX
37
48
36
1
PIN 1
7.20
TOP VIEW
(PINS DOWN)
7.00 SQ
6.80
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
25
12
0.15
0.05
13
24
SEATING
0.08
0.27
0.22
0.17
PLANE
VIEW A
0.50
BSC
LEAD PITCH
COPLANARITY
VIEW A
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
Figure 22. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
7.00
BSC SQ
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
48
1
37
36
0.50
BSC
EXPOSED
PAD
5.20
5.10 SQ
5.00
12
13
25
24
0.45
0.40
0.35
0.25 MIN
TOP VIEW
BOTTOM VIEW
0.80
0.75
0.70
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD.
Figure 23. 48-Lead Frame Chip Scale Package [LFCSP]
(CP-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD7280WBSTZ1
AD7280WDSTZ1
AD7280WBCPZ1
AD7280WDCPZ1
Temperature Range
–40°C to +85°C
Package Description
48-Lead LQFP
Package Option
ST-48
–40°C to +105°C
–40°C to +85°C
48-Lead LQFP
ST-48
48-Lead LFCSP
48-Lead LFCSP
CP-48-4
CP-48-4
–40°C to +105°C
1 Z = Pb-free part.
Rev. PrF| Page 37 of 38
Preliminary Technical Data
AD7280
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PR07731-0-10/09(PrF)
Rev PrE | Page 38 of 38
相关型号：
AD7280WBSTZ
IC 6-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48, LEAD FREE, MS-026BBC, LQFP-48, Power Management Circuit
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AD7280WDCPZ
IC 6-CHANNEL POWER SUPPLY SUPPORT CKT, QCC48, LEAD FREE, MO-220WKKD, LFCSP-48, Power Management Circuit
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AD7280WDSTZ
IC 6-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48, LEAD FREE, MS-026BBC, LQFP-48, Power Management Circuit
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