AD7292BCPZ [ADI]
10-Bit Monitor and Control System with ADC,DACs, Temperature Sensor, and GPIOs;
| 型号： | AD7292BCPZ |
| 厂家： | 
ADI |
| 描述： | 10-Bit Monitor and Control System with ADC,DACs, Temperature Sensor, and GPIOs |
| 文件： | 总41页 (文件大小：734K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
10-Bit Monitor and Control System with ADC,
DACs, Temperature Sensor, and GPIOs
Data Sheet
AD7292
FEATURES
FUNCTIONAL BLOCK DIAGRAM
REF
REF DV
IN
AV
V
DD DRIVE
OUT
DD
10-bit SAR ADC
8 multiplexed analog input channels
Single-ended mode of operation
Differential mode of operation
5 V analog input range
TEMPERATURE
SENSOR
÷4
AD7292
1.25V
REF
BUF
BUF
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
10-BIT
DAC
V
REF, 2 × VREF, or 4 × VREF input ranges
VOUT0
VOUT1
VOUT2
VOUT3
Input measured with respect to AGND or VDD
4 monotonic, 10-bit, 5 V DACs
2 µs settling time
10-BIT
SAR ADC
CONTROL
LOGIC
10-BIT
DAC
MUX
T/H
Power-on reset to 0 V
10-BIT
DAC
10 mA sink and source capability
Internal temperature sensor
1°C accuracy
12 general-purpose digital I/O pins
Internal 1.25 V reference
10-BIT
DAC
ALERT AND LIMIT
REGISTERS
Built-in monitoring features
Minimum and maximum value register for each channel
Programmable alert thresholds
Programmable hysteresis
SPI
INTERFACE
DIGITAL I/Os
SPI interface
Temperature range: −40°C to +125°C
Package type: 36-lead LFCSP
APPLICATIONS
Base station power amplifier (PA) monitoring and control
RF control loops
Optical communication system control
General-purpose system monitoring and control
Figure 1.
GENERAL DESCRIPTION
The AD7292 contains all the functionality required for general-
purpose monitoring of analog signals and control of external
devices, integrated into a single-chip solution. The AD7292
features an 8-channel, 10-bit SAR ADC, four 10-bit DACs, a
1°C accurate internal temperature sensor, and 12 GPIOs to
aid system monitoring and control.
Four 10-bit digital-to-analog converters (DACs) provide outputs
from 0 V to 5 V. A n internal, high accuracy, 1.25 V reference
provides a separately buffered reference source for both the ADC
and the DACs.
A high accuracy band gap temperature sensor is monitored and
digitized by the 10-bit ADC to give a resolution of 0.03125°C.
The AD7292 also features built-in limit and alarm functions.
The 10-bit, high speed, low power successive approximation
register (SAR) ADC is designed to monitor a variety of single-
ended input signals. Differential operation is also available by
configuring VIN0 and VIN1 to operate as a differential pair.
The AD7292 is a highly integrated solution offered in a 36-lead
LFCSP package with an operating temperature range of −40°C
to +125°C.
The AD7292 offers a register programmable ADC sequencer,
which enables the selection of a programmable sequence of
channels for conversion.
Rev. A
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AD7292* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DESIGN RESOURCES
• AD7292 Material Declaration
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• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• AD7292 Evaluation Board
DOCUMENTATION
Application Notes
DISCUSSIONS
View all AD7292 EngineerZone Discussions.
• AN-1178: AD7292 DAC Disable Function Timing
Data Sheet
SAMPLE AND BUY
• AD7292: 10-Bit Monitor and Control System with ADC,
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DACs, Temperature Sensor, and GPIOs Data Sheet
User Guides
TECHNICAL SUPPORT
• UG-449: Evaluating the AD7292 10-Bit Monitor and
Control System
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number.
SOFTWARE AND SYSTEMS REQUIREMENTS
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AD7292
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
ADC Sequence Register (Address 0x03)................................. 21
Configuration Register Bank (Address 0x05) .......................... 21
Alert Limits Register Bank (Address 0x06) ............................ 30
Alert Flags Register Bank (Address 0x07) .............................. 31
Minimum and Maximum Register Bank (Address 0x08) .... 32
Offset Register Bank (Address 0x09)....................................... 32
DAC Buffer Enable Register (Address 0x0A)......................... 33
GPIO Register (Address 0x0B)................................................. 33
Conversion Command Register (Address 0x0E)................... 34
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
ADC Specifications ...................................................................... 3
DAC Specifications....................................................................... 4
General Specifications ................................................................. 5
Temperature Sensor Specifications ............................................ 5
Timing Specifications .................................................................. 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 15
Analog Inputs.............................................................................. 15
ADC Transfer Functions ........................................................... 16
Temperature Sensor ................................................................... 17
DAC Operation........................................................................... 17
Digital I/O Pins........................................................................... 17
Serial Port Interface (SPI).............................................................. 18
Interface Protocol ....................................................................... 18
Register Structure ........................................................................... 20
Register Descriptions ..................................................................... 21
Vendor ID Register (Address 0x00)......................................... 21
ADC Data Register (Address 0x01)......................................... 21
ADC Conversion Result Registers, VIN0 to VIN7
(Address 0x10 to Address 0x17)............................................... 34
TSENSE Conversion Result Register (Address 0x20) ................ 34
DAC Channel Registers (Address 0x30 to Address 0x33).... 34
ADC Conversion Control ............................................................. 35
ADC Conversion Command.................................................... 35
ADC Sequencer .......................................................................... 36
DAC Output Control ..................................................................... 37
LDAC Operation ........................................................................ 37
Simultaneous Update of All DAC Outputs............................. 37
Alerts and Limits ............................................................................ 38
Alert Limit Monitoring Features.............................................. 38
Hardware Alert Pins................................................................... 38
Alert Flag Bits in the Conversion Result Registers................ 38
Alert Flags Register Bank.......................................................... 39
Minimum and Maximum Conversion Results ...................... 39
Outline Dimensions ....................................................................... 40
Ordering Guide .......................................................................... 40
REVISION HISTORY
9/14—Rev. 0 to Rev. A
Changes to VIN ALERT0 Routing and VIN ALERT1 Routing
Subregisters (Address 0x15 and Address 0x16) Section,
Table 25, and Table 26.................................................................... 27
Changes to Figure 40 and Figure 41 ............................................ 35
Changes to Figure 42...................................................................... 36
Changes to Figure 2.......................................................................... 6
Changed t11 from 4 ns max to 4 ns min and Removed
Endnote 4; Table 5 .......................................................................... 21
Changes to Figure 35...................................................................... 18
Changes to Table 15........................................................................ 21
Changes to VIN Filter Subregister (Address 0x13) Section,
Conversion Delay Control Subregister (Address 0x14) Section,
Table 23, and Table 24.................................................................... 26
10/12—Revision 0: Initial Version
Rev. A | Page 2 of 40
Data Sheet
AD7292
SPECIFICATIONS
ADC SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = −40°C to +125°C,
unless otherwise noted. Specifications apply to single-ended mode only, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC ACCURACY
Resolution
Integral Nonlinearity (INL)1
10
Bits
LSB
LSB
0.11
0.5
0.6
(AVDD − 4 × VREF) to AVDD input range
(AVDD − 4 × VREF) to AVDD input range
Differential Nonlinearity (DNL)1
Offset Error
0.1
3
0.99
8
12
1
LSB
mV
mV
mV
ppm/°C
% FS
% FS
% FS
ppm/°C
Offset Error Matching
Offset Error Drift
Gain Error
0.5
0.22
0.09
0.25
0.36
(AVDD − 4 × VREF) to AVDD input range
fIN = 10 kHz sine wave
Gain Error Matching
Gain Error Drift
DYNAMIC PERFORMANCE1
0.5
4.17
Signal-to-Noise Ratio (SNR)
Signal-to-Noise-and-Distortion (SINAD)
Ratio
61.5
61.5
dB
dB
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range (SFDR)
Channel-to-Channel Isolation
Full Power Bandwidth
−84
84.5
−80
60
dB
dB
dB
MHz
MHz
fIN = 3 kHz to 1000 kHz
At −3 dB (0 V to VREF input range)
At −0.1 dB (0 V to VREF input range)
3
CONVERSION RATE
Conversion Time
900
ns
See Table 5
Track-and-Hold Acquisition Time
Throughput Rate
45
625
ns
kSPS
ADC only; temperature sensor
disabled
150
kSPS
ADC and temperature sensor
ANALOG INPUT
Single-Ended Input Range
With Respect to AGND
0
0
0
4 × VREF
2 × VREF
VREF
V
V
V
With Respect to AVDD
Fully Differential Input Range
AVDD − 4 × VREF
−4 × VREF
−2 × VREF
−VREF
AVDD
V
V
V
V
+4 × VREF
+2 × VREF
+VREF
VIN0 and VIN1 inputs only
Input Capacitance
23
18
15
pF
pF
pF
µA
0 V to VREF input range
0 V to 2 × VREF input range
0 V to 4 × VREF input range
DC Input Leakage Current
INTERNAL REFERENCE
1
Reference Output Voltage
Reference Temperature Coefficient
1.245
1.25
13
1.255
V
At 25°C
ppm/°C
Rev. A | Page 3 of 40
AD7292
Data Sheet
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
EXTERNAL REFERENCE
Reference Input Voltage
4.75
AVDD
V
Internal reference used to calibrate
temperature sensor
Input Resistance
100
kΩ
1 Specifications also apply to differential mode.
DAC SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = −40°C to +125°C,
unless otherwise noted.
Table 2.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
DC ACCURACY
Resolution
10
Bits
LSB
LSB
mV
% FS
mV
Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
Full-Scale Error
0.2
0.1
4.8
0.1
1.62
1
0.3
10
0.5
10
Guaranteed monotonic
All 0s loaded to DAC register
All 1s loaded to DAC register
Measured in the linear region,
TA = −40°C to +125°C
Offset Error
Offset Error Drift
Gain Error
Gain Error Drift
DC Power Supply Rejection Ratio (PSRR)
DC Crosstalk
4.4
0.35
2.6
ppm/°C
% FS
ppm/°C
dB
Measured in the linear region, TA = 25°C
fRIPPLE up to 100 kHz
0.5
−50
5
μV
DAC OUTPUT CHARACTERISTICS
Output Voltage Range
Short-Circuit Current
Load Current
0
4 × VREF
V
mA
mA
30
10
Sink/source current; within 200 mV
of supply
Resistive Load to AGND
Capacitive Load Stability
DC Output Impedance
AC CHARACTERISTICS1
Output Voltage Settling Time
500
1
Ω
nF
Ω
1
2
1
µs
¼ to ¾ scale step change within 1 LSB,
measured from last SCLK edge
Overshoot
200
mV
¼ to ¾ scale step change within 1 LSB,
measured from last SCLK edge;
CL = 200 pF, RL = 25 kΩ
Slew Rate
9
12
4
0.4
2
730
28
5
V/µs
Digital-to-Analog Glitch Impulse
Digital Feedthrough
DAC-to-DAC Crosstalk
Output Noise Spectral Density
Output Noise
nV-sec
nV-sec
nV-sec
nV/√Hz
μV rms
mV
DAC code = midscale, 1 kHz
0.1 Hz to 10 Hz
AVDD ramp of 1 ms with 100 kΩ load
Output Transient Response During
Power-Up
1 The DAC buffer output level is undefined until 30 µs after all supplies reach their minimum specified operating voltages.
Rev. A | Page 4 of 40
Data Sheet
AD7292
GENERAL SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = −40°C to +125°C,
unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
LOGIC INPUTS
Input High Voltage, VIH
0.7 × VDRIVE
0.8 × VDRIVE
V
V
V
V
µA
pF
V
VDRIVE = 2.3 V to 5.25 V
VDRIVE = 1.8 V to 1.95 V
VDRIVE = 2.3 V to 5.25 V
VDRIVE = 1.8 V to 1.95 V
Input Low Voltage, VIL
0.3 × VDRIVE
0.2 × VDRIVE
1
Input Leakage Current, IIN
Input Capacitance, CIN
Input Hysteresis, VHYST
GPIO OUTPUTS
ISINK/ISOURCE
Output High Voltage, VOH
Output Low Voltage, VOL
POWER REQUIREMENTS
AVDD
3
0.05 × VDRIVE
1.6
mA
V
V
DVDD − 0.2
ISINK/ISOURCE = 1.6 mA
ISINK/ISOURCE = 1.6 mA
0.4
4.75
1.8
1.8
5.25
5.25
5.25
V
V
V
DVDD
VDRIVE
Static Current
IAVDD
IDVDD
4.2
5.4
1.3
0.35
mA
mA
mA
mA
0.65
0.12
4.97
IDRIVE
Total Static Current
Dynamic Current
IAVDD
IDVDD
IDRIVE
AVDD + DVDD + VDRIVE
6.45
0.65
0.12
7.22
8.5
1.3
0.35
mA
mA
mA
mA
Total Dynamic Current
AVDD + DVDD + VDRIVE, DAC outputs loaded
and converting at full scale, continuous
conversion on ADC inputs
Power Dissipation
Static
Dynamic
26
37.9
34.125
50.925
mW
mW
TEMPERATURE SENSOR SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, TA = −40°C to +125°C,
unless otherwise noted.
Table 4.
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
INTERNAL TEMPERATURE SENSOR
Operating Range
Accuracy
−40
+125
3
2
°C
°C
°C
°C
°C
ms
1
1
TA = −40°C to +125°C
TA = 0°C to +125°C
TA = 25°C
0.5
0.03125
1.25
1.5
Resolution
Update Rate
Digital filter enabled
Rev. A | Page 5 of 40
AD7292
Data Sheet
TIMING SPECIFICATIONS
AVDD = 4.75 V to 5.25 V, DVDD = 1.8 V to 5.25 V, VREF = 1.25 V internal, VDRIVE = 1.8 V to 5.25 V, AGND = 0 V, CL = 27 pF, TA = −40°C
to +125°C, unless otherwise noted.1
Table 5.
Limit at TMIN/TMAX
Parameter
Description
VDRIVE = 1.8 V
VDRIVE = 2.7 V to 5.25 V
Unit
tCONVERT
ADC conversion time/BUSY high time
Temperature sensor disabled
Temperature sensor enabled
ADC acquisition time
950
5.85
50
15
66
33
33
4
950
5.85
50
25
40
20
20
4
ns max
μs max
ns max
MHz max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns min
ns min
ns max
tACQ
fSCLK
t1
Frequency of serial read clock2
SCLK period
t2
t3
t4
SCLK low
SCLK high
CS falling edge to SCLK rising edge
DIN setup time to SCLK falling edge
DIN hold time after SCLK falling edge
SCLK falling edge to CS rising edge
CS high
t5
t6
4
2
5
4
2
5
3
t7
t8
5
5
t9
t10
t11
SCLK to output data valid delay time
SCLK to output data valid hold time
CS rising edge to SCLK rising edge
CS rising edge to DOUT high impedance
30
7
4
19
5
4
4
t12
15
15
1 Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDRIVE).
2 For VDRIVE = 2.5 V, fSCLK = 22 MHz maximum.
3 Time required for the output to cross 0.2 × VDRIVE and 0.8 × VDRIVE when VDRIVE = 1.8 V; time required for the output to cross 0.3 × VDRIVE and 0.7 × VDRIVE when VDRIVE = 2.7 V to 5.25 V.
4 Guaranteed by design.
Timing Diagram
2
BUSY
t7
t8
t3
CS
t11
t2
t1
t4
SCLK
DIN
t5
t6
X
R
W
D5
D4
D3
D2
D1
D0
LSB
X
t10
HIGH-Z
HIGH-Z
t12
1
LSB
DOUT
t9
1
2
PROVIDED THE READ BIT IS SET.
IF AN ADC CONVERSION IS REQUESTED.
t7 = 5ns IF NO ADC CONVERSION
955ns WITH ADC CONVERSION
Figure 2. Serial Interface Timing Diagram
Rev. A | Page 6 of 40
Data Sheet
AD7292
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 6.
Parameter
Rating
AVDD to AGND
DVDD to DGND
VDRIVE to DGND
VINx to AGND
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to +6 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to VDRIVE + 0.3 V
−0.3 V to +2.2 V
−0.3 V to AVDD + 0.3 V
0.3 V
THERMAL RESISTANCE
VOUTx to AGND
Digital Inputs/Outputs to DGND
CS, SCLK, DIN, DOUT to DGND
REFOUT to AGND
REFIN to AGND
DGND to AGND
Table 7. Thermal Resistance
Package Type
θJA
Unit
36-Lead LFCSP
54.1
°C/W
ESD CAUTION
Operating Temperature Range
Storage Temperature Range
Junction Temperature (TJ max)
ESD, Human Body Model
Reflow Soldering Peak Temperature
−40°C to +125°C
−65°C to +150°C
150°C
2.5 kV
260°C
Rev. A | Page 7 of 40
AD7292
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
27 GPIO0/ALERT0
26 GPIO1/ALERT1
25 GPIO2/DAC DISABLE0
24 GPIO3/LDAC
23 GPIO4/DAC DISABLE1
22 GPIO5
21 GPIO6/BUSY
20 GPIO7
19 REF
OUT
AV
A
D
1
2
3
4
5
6
7
8
9
DD
GND
GND
DV
AD7292
TOP VIEW
(Not to Scale)
DD
V
DRIVE
CS
SCLK
DIN
DOUT
NOTES
1. THE EXPOSED PAD IS INTERNALLY CONNECTED TO A
AND
GND
CAN BE SOLDERED TO THE GROUND PLANE OF THE SYSTEM.
Figure 3. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
AVDD
Supply Pin. This pin should be decoupled to AGND with a 0.1 μF decoupling capacitor.
2, 14
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7292. All analog signals should
be referred to AGND. Both the AGND and DGND pins should be connected to the ground plane of the system.
3
DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7292. All digital signals should be
referred to DGND. Both the DGND and AGND pins should be connected to the ground plane of the system.
4
5
DVDD
VDRIVE
Sets the GPIO voltage level. This pin should be decoupled to DGND with a 0.1 μF decoupling capacitor.
This pin sets the reference level of the SPI bus from 1.8 V to 5.25 V. This pin should be decoupled to DGND
with a 0.1 μF decoupling capacitor.
6
7
8
CS
Chip Select Signal. This active low logic input signal is used to frame the serial data input.
SPI Clock Input.
SPI Serial Data Input. Serial data to be loaded into the registers of the AD7292 is provided on this pin.
Data is clocked into the serial interface on the falling edge of SCLK.
SCLK
DIN
9
DOUT
SPI Serial Data Output. Serial data to be read from the registers of the AD7292 is provided on this pin.
Data is clocked out on the rising edge of SCLK. DOUT is high impedance when it is not outputting data.
10 to 13
VOUT3 to VOUT0 Buffered DAC Analog Outputs. Each DAC analog output is driven from an output amplifier and has a
maximum output voltage span of 5 V. Each DAC is capable of sourcing and sinking 10 mA and driving a
1 nF load.
15 to 18
19
GPIO11 to GPIO8 General-Purpose Input/Output Pins.
REFOUT
ADC Internal Reference Output. Decouple the internal ADC reference buffer to AGND with a 0.1 μF
decoupling capacitor.
20
21
GPIO7
GPIO6/BUSY
General-Purpose Input/Output Pin.
General-Purpose Input/Output Pin (GPIO6).
Busy Output Pin (BUSY). When a conversion starts, this output pin transitions high and remains high until
the conversion is completed.
22
23
GPIO5
GPIO4/
General-Purpose Input/Output Pin.
General-Purpose Input/Output Pin (GPIO4).
DAC DISABLE1
DAC Disable Pin 1 (DAC DISABLE1). When this pin is activated, the selected DAC outputs are disabled.
Select the DAC channels to be disabled by this pin using the GPIO4/DAC DISABLE1 subregister within the
configuration register bank (see Table 30).
24
25
GPIO3/LDAC
General-Purpose Input/Output Pin (GPIO3).
LDAC Input Pin (LDAC). When this input is taken high, the DAC registers are updated.
General-Purpose Input/Output Pin (GPIO2).
GPIO2/
DAC DISABLE0
DAC Disable Pin 0 (DAC DISABLE0). When this pin is activated, the selected DAC outputs are disabled.
Select the DAC channels to be disabled by this pin using the GPIO2/DAC DISABLE0 subregister within the
configuration register bank (see Table 29).
Rev. A | Page 8 of 40
Data Sheet
AD7292
Pin No.
Mnemonic
Description
26
GPIO1/ALERT1
GPIO0/ALERT0
VIN0 to VIN7
General-Purpose Input/Output Pin (GPIO1).
Alert Pin 1 (ALERT1). When configured as an alert, this pin acts as an out-of-range indicator and becomes
active when the conversion result violates the high or low limit stored in the alert limits register bank. The
polarity of the alert signal is controlled using the general subregister within the configuration register bank.
27
General-Purpose Input/Output Pin (GPIO0).
Alert Pin 0 (ALERT0). When configured as an alert, this pin acts as an out-of-range indicator and becomes
active when the conversion result violates the high or low limit stored in the alert limits register bank. The
polarity of the alert signal is controlled using the general subregister within the configuration register bank.
Analog Inputs. The eight single-ended analog inputs of the AD7292 are multiplexed into the on-chip
track-and-hold amplifier. Each input channel can accept analog inputs from 0 V to 5 V. Any unused input
channels should be connected to AGND to avoid noise pickup.
28 to 35
36
REFIN
EPAD
Voltage Reference Input. An external reference for the AD7292 can be applied to this pin. If this pin is
unused, connect it to AGND
.
EPAD
The exposed pad is internally connected to AGND and can be soldered to the ground plane of the system.
Rev. A | Page 9 of 40
AD7292
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
–20
AV
DV
= 5V
= 5V
= 3V
AV
DV
= 5V
= 5.25V
DD
DD
DD
DD
–20
–40
V
V
= 1.8V
DRIVE
DRIVE
= 25°C
T
T = 25°C
A
fSAMPLE = 200kSPS
A
fSAMPLE = 200kSPS
RANGE = 0V TO V
–40
RANGE = 0V TO 2 × V
REF
REF
SINGLE-ENDED MODE
SNR = 61.6dB
THD = –84.0dB
SINAD = 61.49dB
SFDR = 79.05dB
DIFFERENTIAL MODE
SNR = 61.798dB
THD = –86.602dB
SINAD = 61.784dB
SFDR = 86.142dB
–60
–60
–80
–80
–100
–120
–100
–120
0
10
20
30
40
50
60
70
80
90
100
0
10
20
30
40
50
60
70
80
90
100
INPUT FREQUENCY (kHz)
INPUT FREQUENCY (kHz)
Figure 4. ADC FFT, 200 kSPS, fIN = 10 kHz, Single-Ended Mode
Figure 7. ADC FFT, 200 kSPS, fIN = 10 kHz, Differential Mode
0.3
0.3
0.2
AV = DV = 5.25V
DD
DD
AV = 4.75V
DD
T = 25°C
A
V
= 1.8V
DRIVE
DV = 5.25V
WCP INL = 0.091LSB
WCN INL = –0.093LSB
DD
CHANNEL 3
V
= 3.3V
DRIVE
0.2
0.1
INTERNAL REFERENCE
CHANNEL 0 AND CHANNEL 1
INTERNAL REFERENCE
DIFFERENTIAL MODE, 0V TO V
T
= 25°C
A
WCP INL = 0.068LSB
RANGE
WCN INL = –0.255LSB
REF
0.1
SINGLE-ENDED MODE, 0V TO 4 × V
RANGE
REF
0
0
–0.1
–0.2
–0.3
–0.1
–0.2
–0.3
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
ADC CODE
ADC CODE
Figure 5. Typical ADC INL, Single-Ended Mode
Figure 8. Typical ADC INL, Differential Mode
0.3
0.2
0.25
0.20
0.15
0.10
0.05
0
AV = DV = 5.25V
T
= 25°C
AV = 4.75V
DD
T = 25°C
A
WCP INL = 0.067LSB
WCN INL = –0.08LSB
DD
DD
A
V
= 1.8V
WCP DNL = 0.11LSB
WCN DNL = –0.119LSB
DV = 5.25V
DRIVE
DD
CHANNEL 3
INTERNAL REFERENCE
SINGLE-ENDED MODE, 0V TO 4 × V
V
= 3.3V
DRIVE
CHANNEL 0 AND CHANNEL 1
INTERNAL REFERENCE
DIFFERENTIAL MODE, 0V TO V
RANGE
REF
RANGE
REF
0.1
0
–0.05
–0.10
–0.15
–0.20
–0.25
–0.1
–0.2
–0.3
0
128
256
384
512
640
768
896
1024
0
128
256
384
512
640
768
896
1024
ADC CODE
ADC CODE
Figure 6. Typical ADC DNL, Single-Ended Mode
Figure 9. Typical ADC DNL, Differential Mode
Rev. A | Page 10 of 40
Data Sheet
AD7292
0.4
0.3
1.0
AV
DV
= 5V
= 3V
AV
DV
= 5V
= 3V
DD
DD
DD
DD
0.8
0.6
V
f
= 3V
V
f
= 3V
DRIVE
SAMPLE
DRIVE
SAMPLE
= 225kSPS
= 225kSPS
INTERNAL REFERENCE
SINGLE-ENDED MODE
INTERNAL REFERENCE
SINGLE-ENDED MODE
0.2
0.4
0.1
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.1
–0.2
–0.3
–0.4
0V TO V
0V TO V
0V TO 2 × V
0V TO 2 × V
0V TO 4 × V
0V TO 4 × V
, –INL
, +INL
0V TO V
0V TO V
0V TO 2 × V
0V TO 2 × V
0V TO 4 × V
0V TO 4 × V
, –DNL
, +DNL
REF
REF
REF
REF
, –INL
, –DNL
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
REF
, +INL
, –INL
, +INL
, +DNL
, –DNL
, +DNL
(AV
(AV
– 4 × V
– 4 × V
) TO AV , –INL
(AV
(AV
– 4 × V
– 4 × V
) TO AV , –DNL
DD
DD
DD
DD
DD
DD
DD
) TO AV , +INL
) TO AV , +DNL
DD
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. ADC INL vs. Temperature
Figure 13. ADC DNL vs. Temperature
3
2
5
4
AV
DV
V
= 5.25V
= 5V
AV
DV
V
= 5.25V
= 5V
DD
DD
DD
DD
= 3.3V
= 3.3V
DRIVE
DRIVE
f
= 200kSPS
f
= 200kSPS
SAMPLE
3
SAMPLE
INTERNAL REFERENCE
INTERNAL REFERENCE
2
1
1
0
0
–1
–2
–3
–4
–5
–1
–2
–3
0V TO V
0V TO 2 × V
0V TO 4 × V
REF
0V TO V
0V TO 2 × V
0V TO 4 × V
REF
REF
REF
REF DD
REF
REF
(AV
– 4 × V
) TO AV
DD
(AV – 4 × V
) TO AV
DD
DD
REF
–40
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 11. Offset Error vs. Temperature, Single-Ended
and Differential Modes
Figure 14. ADC Gain Error vs. Temperature, Single-Ended
and Differential Modes
120
–20
–30
115
110
105
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
25
20
AV – 4 × V
0Ω
220Ω
510Ω
0V TO V
0V TO V
0V TO V
0V TO 2 × V
0V TO 2 × V
0V TO 2 × V
0Ω
220Ω
510Ω
DD
REF,
REF,
REF,
REF,
REF,
REF,
AV – 4 × V
DD
AV – 4 × V
DD
–40
0V TO 4 × V
0Ω
0Ω
220Ω
510Ω
REF,
REF,
REF,
REF,
0V TO 4 × V
0V TO 4 × V
0V TO 4 × V
220Ω
430Ω
510Ω
–50
REF,
REF,
REF,
–60
AV
DV
= 5V
= 3V
–70
DD
DD
V
f
= 3V
DRIVE
–80
= 250kSPS
SAMPLE
0V TO V
0V TO 2 × V
0V TO 4 × V
REF
T
= 25°C
AV
DV
V
= 5V
= 3V
= 3V
= 225kSPS
A
–90
DD
DD
DRIVE
REF
REF
REF DD
INTERNAL REFERENCE
fIN = 10kHz
(AV
– 4 × V
) TO AV
–100
–110
–120
DD
f
SAMPLE
T
FULL-SCALE SIGNAL ON CHANNEL,
VIN0 TO VIN3 AND VIN5 TO VIN7
INPUT FREQUENCY RAMPED MEASUREMENTS ON VIN4
= 25°C
A
INTERNAL REFERENCE
100
1k
10k
100k
1M
10M
100M
INPUT FREQUENCY (Hz)
INPUT FREQUENCY (kHz)
Figure 12. THD vs. Input Frequency for Various Source Impedances,
Single-Ended Mode
Figure 15. ADC Channel-to-Channel Isolation
Rev. A | Page 11 of 40
AD7292
Data Sheet
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
900
800
700
600
500
400
300
200
100
0
AV
DV
= 5V
= 5V
= 2.5V
DD
DD
V
T
DRIVE
= 25°C
A
AV
DV
= 5V
DD
DD
= V
= 3V
DRIVE
fSAMPLE = 225kSPS
ANALOG INPUT RANGE = AV – 4 × V
DD REF
T
= 25°C
A
1k
10k
100k
1M
510
511
512
LOAD RESISTANCE (Ω)
OUTPUT CODE
Figure 19. Reference Voltage vs. Load Resistance
Figure 16. Histogram of Codes
0.5
0.3
0.25
0.15
0.1
0.05
–0.1
–0.3
–0.05
–0.15
–0.25
AV = 5.25V
DD
DV = 5V
DD
AV = 5.25V
DD
DV = 5V
DD
V
T
= 3.3V
= 25°C
V
T
= 3.3V
= 25°C
DRIVE
DRIVE
A
A
INTERNAL REFERENCE
INTERNAL REFERENCE
–0.5
0
128
256
384
512
640 768 896
1024
0
128
256
384
512
640 768 896 1024
DAC CODE
DAC CODE
Figure 17. Typical DAC INL vs. Output Code
Figure 20. Typical DAC DNL vs. Output Code
1.0
0.9
1.0
0.9
0.8
0.8
0.7
0.7
0.6
0.6
0.5
0.5
0.4
0.4
0.3
0.3
0.2
0.1
0
0.2
0.1
0
DNL MAX
DNL MIN
INL MAX
INL MIN
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
–40
–0.1
–0.2
–0.3
–0.4
–0.5
–0.6
–0.7
–0.8
–0.9
–1.0
AV
DV
= 5.25V
= 5V
AV
DV
V
= 5.25V
= 5V
DD
DD
DD
DD
V
= 3.3V
= 3.3V
DRIVE
DRIVE
INTERNAL REFERENCE
INTERNAL REFERENCE
–20
0
20
40
60
80
100
120
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 18. DAC INL vs. Temperature
Figure 21. DAC DNL vs. Temperature
Rev. A | Page 12 of 40
Data Sheet
AD7292
0.4
0.3
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
DV
= 5V
= 3.3V
DD
V
DRIVE
INTERNAL REFERENCE
0.2
0.1
0
AV = 5.25V
DD
–0.1
–0.2
–0.3
–0.4
AV
= 5.25V
AV = 4.75V
DD
DD
DV
V
= 5V
DD
= 3.3V
DRIVE
AV
= 4.75V
0
INTERNAL REFERENCE
60 80 100 120
TEMPERATURE (°C)
DD
–40
–20
0
20
40
–40
–20
20
40
60
80
100
120
TEMPERATURE (°C)
Figure 22. DAC Offset Error vs. Temperature
Figure 25. DAC Gain Error vs. Temperature
0.10
0.09
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
4.996
AV = 5.25V
DD
DV = 5V
4.995
4.994
4.993
4.992
4.991
4.990
4.989
4.988
DD
V
= 3.3V
DRIVE
INTERNAL REFERENCE
CODE = 0x3FF
T
= 25°C
A
AV = 5.25V
DD
DV = 5V
DD
V
= 3.3V
DRIVE
INTERNAL REFERENCE
CODE = 0x000
T
= 25°C
A
0
0
1
2
3
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
SINK CURRENT (mA)
SOURCE CURRENT (mA)
Figure 23. DAC Source Current (Full Scale)
Figure 26. DAC Sink Current (Zero Scale)
1.255
1.254
1.253
1.252
1.251
1.250
1.249
1.248
1.247
1.246
1.245
2.510
2.508
2.506
2.504
2.502
2.500
2.498
2.496
2.494
AV = DV = V
DD DD DRIVE
10 DEVICES
= 5V
AV
DV = 5V
= 5.25V
DD
DD
V
= 3.3V
DRIVE
INTERNAL REFERENCE
CODE = 0x200
–40
–20
0
20
40
60
80
100
120
–10
–8
–6
–4
–2
0
2
4
6
8
10
TEMPERATURE (°C)
LOAD CURRENT (mA)
Figure 27. Reference Voltage vs. Temperature
Figure 24. DAC Output Voltage vs. Load Current (Midscale)
Rev. A | Page 13 of 40
AD7292
Data Sheet
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
6.0
5.8
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
AV = DV = V = 5V
DRIVE
10 DEVICES
DD
DD
AVDD = 5V, DVDD = 3V, VDRIVE = 3V, SCLK VARIED
AVDD = 5.25V, DVDD = 5.25V, VDRIVE = 5.25V, SCLK FIXED, 25MHz
AVDD = 4.75V, DVDD = 1.8V, VDRIVE = 1.8V, SCLK FIXED, 15 MHz
–0.2
–0.4
–40
0
100
200
300
400
500
600
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
SAMPLING FREQUENCY (kHz)
Figure 28. Temperature Sensor Error vs. Temperature
Figure 30. Total Supply Current vs. Throughput Rate
80
70
60
50
40
30
20
10
0
AV
DV
= 5V
= 3V
= 3V
DD
DD
V
T
DRIVE
= 25°C
0V TO V
0V TO 2 × V
0V TO 4 × V
A
REF
fSAMPLE = 225kSPS
INTERNAL REFERENCE
REF
REF
1k
10k
100k
1M
10M
POWER SUPPLY RIPPLE FREQUENCY (Hz)
Figure 29. PSRR vs. Power Supply Ripple Frequency
Rev. A | Page 14 of 40
Data Sheet
AD7292
THEORY OF OPERATION
ANALOG INPUTS
V
V
IN+
IN–
VIN0
V
V
p-p
p-p
REF
REF
The AD7292 has eight analog input channels. By default, these
channels are configured as single-ended inputs. Differential
operation is also available by configuring VIN0 and VIN1 to
operate as a differential pair.
AD7292
COMMON-MODE
VOLTAGE
VIN1
Single-Ended Mode
Figure 32. Differential Analog Input
In applications where the signal source has high impedance, it
is recommended that the analog input be buffered before it is
applied to the ADC.
The amplitude of the differential signal is the difference
between the signals applied to the input pins of the differential
pair, VIN0 and VIN1. The resulting converted data is stored in
straight binary format in the ADC data register. VIN0 and VIN1
should be simultaneously driven by two signals that are 180° out
of phase; each signal should be of maximum amplitude VREF
2 × VREF, or 4 × VREF, depending on the selected range.
The analog input range is programmed to one of these values:
0 V to VREF, 0 V to 2 × VREF, or 0 V to 4 × VREF. For information
about programming the input range, see the VIN RANGE0 and
VIN RANGE1 Subregisters (Address 0x10 and Address 0x11)
section.
,
Therefore, if the 0 V to VREF range is selected, the amplitude of
the differential signal is −VREF to +VREF peak-to-peak (2 × VREF),
regardless of the common-mode voltage (VCM).
In 0 V to 2 × VREF mode, the input is scaled by a factor of 2 before
the conversion takes place. In 0 V to 4 × VREF mode, the input
is scaled by a factor of 4 before the conversion takes place. Note
that the voltage with respect to AGND on the ADC analog input
The common-mode voltage is the average of the two signals.
pins cannot exceed AVDD
.
VCM = (VIN+ + VIN−)/2
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias this signal
up so that it is correctly formatted for the ADC. Figure 31 shows
a typical connection diagram when operating the ADC in single-
ended mode with a bipolar 0.625 V input signal.
+1.25V
The common-mode voltage is, therefore, the voltage on which
the two inputs are centered; the resulting span for each input is
VCM VREF/2. This voltage must be set up externally. When the
inputs are driven with an amplifier, the actual common-mode
range is determined by the output voltage swing of the amplifier
and the input common-mode range of the AD7292. The common-
mode voltage must be in this range to guarantee the functionality
of the AD7292 (see Figure 33). When a conversion takes place,
the common-mode voltage is rejected, resulting in a virtually
R
0V
+0.625V
R
V
0V
IN
VIN0
VIN7
3R
noise-free signal of amplitude −VREF to +VREF
.
–0.625V
AD7292
R
69
REF
OUT
DIFFERENTIAL MODE
AV
DV
= 5V
= 3V
= 3V
DD
67
65
63
61
59
57
DD
V
T
DRIVE
= 25°C
0.47µF
fSAAMPLE = 225kSPS
INTERNAL REFERENCE
Figure 31. Interfacing to a Bipolar Input Signal
Differential Mode
The AD7292 can be configured to have one differential analog
input pair (VIN0 and VIN1). Differential signals have some
benefits over single-ended signals, including noise immunity
based on the common-mode rejection of the device and improve-
ments in distortion performance. Figure 32 shows the fully
differential analog input of the AD7292.
1 × V
REF
2 × V
4 × V
REF
REF
55
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
COMMON-MODE VOLTAGE (V)
Figure 33. Common-Mode Voltage (Dependent on Input Range)
Rev. A | Page 15 of 40
AD7292
Data Sheet
The LSB size depends on the input range selected (see Table 9).
ADC TRANSFER FUNCTIONS
The output coding of the AD7292 is 10-bit straight binary for the
analog input channels. The designated code transitions occur at
successive LSB values.
Table 9. Input Range and LSB Size
Input Range
LSB Size
VREF/210
0 V to VREF
0 V to 2 × VREF
0 V to 4 × VREF
2VREF/210
4VREF/210
To select the input range, set the appropriate bits in the VIN
RANGE1 and VIN RANGE0 subregisters of the configuration
register bank (see Table 10).
The ideal transfer function for the AD7292 when operating
with an input range of 0 V to VREF is shown in Figure 34.
Table 10. Analog Input Range Selection
2
Sample with Respect to AGND
Sample with Respect to AVDD
Single-Ended Input Range
(VIN0 to VIN7)
Subregister Bit Settings1
Single-Ended Input Range Differential Input Range
VIN RANGE1
VIN RANGE0
(VIN0 to VIN7)
0 V to 4 × VREF
0 V to 2 × VREF
0 V to 2 × VREF
0 V to VREF
(VIN0 and VIN1 Only)
−4 × VREF to +4 × VREF
−2 × VREF to +2 × VREF
−2 × VREF to +2 × VREF
−VREF to +VREF
0
0
1
1
0
1
0
1
(AVDD − 4 × VREF) to AVDD
Not applicable
Not applicable
Not applicable
1 For more information, see the ADC Sampling Mode Subregister (Address 0x12) section.
2 The contents of the VIN RANGE0 and VIN RANGE1 subregisters are ignored when the AD7292 is configured to sample with respect to AVDD; the only input range
allowed when sampling with respect to AVDD is from (AVDD − 4 × VREF) to AVDD
.
111...111
111...110
111...000
011...111
1LSB = V
/1024
REF
000...010
000...001
000...000
0V
1LSB
+V
– 1LSB
REF
ANALOG INPUT
NOTES
1. V
IS 1.25V.
REF
2. INPUT RANGE IS 0V TO V
.
REF
Figure 34. Straight Binary Transfer Characteristic Corresponding to Single-Ended Input Range of 0 V to VREF
Table 11. Output Codes and Ideal Input Voltages (AVDD = 5 V)
Analog Input Range
Single-Ended Mode of Operation
Differential Mode of Operation
0 V to
4 × VREF
0 V to
2 × VREF
(AVDD − 4 × VREF
to AVDD
)
−4 × VREF to
−2 × VREF to
+2 × VREF
Digital Output
−VREF to +VREF Code (Hex)
Description
+FSR − 1 LSB
Midscale + 1 LSB
Midscale
Midscale − 1 LSB
−FSR + 1 LSB
−FSR
0 V to VREF
+4 × VREF
4.990234 V
0.009766 V
0 V
−0.009766 V
4.995117 V
−5 V
4.995117 V
2.504883 V
2.5 V
2.495117 V
0.004883 V
0 V
2.497559 V 1.248779 V 4.995117 V
1.252441 V 0.626221 V 2.504883 V
1.25 V
1.247559 V 0.623779 V 2.495117 V
0.002441 V 0.001221 V 0.004883 V
0 V
2.495117 V
0.004883 V
0 V
−0.004883 V
−2.495117 V
−2.5 V
1.247559 V
0.002441 V
0 V
−0.002441 V
−1.247559 V
−1.25 V
0x3FF
0x201
0x200
0x1FF
0x001
0x000
0.625 V
2.5 V
0 V
0 V
Rev. A | Page 16 of 40
Data Sheet
AD7292
TEMPERATURE SENSOR
DAC OPERATION
The AD7292 contains one local temperature sensor. The on-chip,
band gap temperature sensor measures the temperature of the
AD7292 die. The temperature sensor input gathers data and
computes a value over a period of several hundred microseconds.
The temperature measurement takes place continuously in the
background, leaving the user free to perform conversions on the
other channels.
The four DACs of the AD7292 provide digital control with 10 bits
of resolution. DAC outputs VOUT0 to VOUT3 feature an output
voltage range up to 5 V (LSB of 4.88 mV).
The DAC output buffer can be controlled via software using the
GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 subregisters
within the configuration register bank, or via hardware using
the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins.
After a temperature value is computed, a signal passes to the
control logic to initiate a conversion automatically. If an ADC
conversion is in progress, the temperature sensor conversion is
performed as soon as the ADC conversion is completed. If the
ADC is idle, the temperature sensor conversion takes place
immediately.
DIGITAL I/O PINS
To aid in system monitoring, the AD7292 features 12 digital I/O
pins. All 12 pins can be configured as GPIO pins. Six of the digital
I/O pins can be configured for other functionality; on power-up,
the non-GPIO functionality of these six pins is enabled by default.
For more information, see the Digital Output Driver Subregister
(Address 0x01) section and the Digital I/O Function Subregister
(Address 0x02) section.
The TSENSE conversion result register stores the result of the last
conversion on the temperature channel; this result can be read at
any time provided that the temperature sensor is enabled via the
temperature sensor subregister within the configuration register
bank (see the Temperature Sensor Subregister (Address 0x20)
section).
GPIO0/ALERT0 and GPIO1/ALERT1 Pins
When Pin 27 and Pin 26 (GPIO0/ALERT0 and GPIO1/ALERT1,
respectively) are configured as alert pins, they act as out-of-range
indicators that become active when the selected conversion result
exceeds the high or low limit stored in the alert limits register bank.
The polarity of the alert output pins can be set to active high or
active low via the general subregister within the configuration
register bank (see the General Subregister (Address 0x08) section).
Temperature readings from the ADC are stored in the TSENSE
conversion result register. Results are in 14-bit straight binary
format and accommodate both positive and negative tempera-
ture measurements. Bit D0 and Bit D1 hold alert flags; Bit D2
stores the LSB, which corresponds to 0.03125°C if the digital
filter is enabled.
GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 Pins
When Pin 25 and Pin 23 (GPIO2/DAC DISABLE0 and GPIO4/
DAC DISABLE1, respectively) are configured as DAC disable pins,
they can be used to power down the selected DAC outputs, as
determined by the contents of the GPIO2/DAC DISABLE0 and
GPIO4/DAC DISABLE1 subregisters within the configuration
register bank. For more information, see the GPIO2/DAC
DISABLE0 and GPIO4/DAC DISABLE1 Subregisters (Address
0x30 and Address 0x31) section.
Table 12 provides examples of temperature sensor data. An output
of all 0s is equal to −256°C; this value is output by the AD7292
until the first measurement is completed. Note that when digital
filtering is disabled, Bit D3 and Bit D2 of the TSENSE conversion
result register are set to 0, producing a 12-bit straight binary result
with an LSB of 0.125°C. When the TSENSE conversion result is
read via the ADC data register (Address 0x01), the temperature
sensor result is a 10-bit result with an LSB that equates to 0.5°C.
GPIO3/LDAC Pin
Table 12. Temperature Sensor Data Format
When Pin 24 (GPIO3/LDAC) is configured as an LDAC pin,
the DAC registers are updated when this input pin is taken high.
T
SENSE Conversion Result Register,
Temperature (°C)
Bits[D15:D2]
−40
−25
−10
−0.03125
0
+0.03125
+10
+25
+50
+75
01 1011 0000 0000
01 1100 1110 0000
01 1110 1100 0000
01 1111 1111 1111
10 0000 0000 0000
10 0000 0000 0001
10 0001 0100 0000
10 0011 0010 0000
10 0110 0100 0000
10 1001 0110 0000
10 1100 1000 0000
10 1111 1010 0000
GPIO6/BUSY Pin
Pin 21 (GPIO6/BUSY) can be configured as a general-purpose
input/output or as a busy output pin. When configured as a busy
output pin, this pin transitions high when a conversion starts
and remains high until the conversion is completed.
+100
+125
Rev. A | Page 17 of 40
AD7292
Data Sheet
SERIAL PORT INTERFACE (SPI)
The AD7292 serial port interface (SPI) allows the user to
configure the device for specific functions and operations
through an internal structured register space. The interface
Table 13. Address Pointer
D7
D6
D5
D4
D3
D2
D1
D0
R
W
Register select
CS
consists of four signals: , SCLK, DIN, and DOUT. The SPI
After the address pointer, subsequent data for writing to the part
is supplied in bytes (see Figure 36). Some registers are located
within register banks and, therefore, require both a pointer address
and a subpointer address. The subpointer address is specified
in the first byte following the pointer address (see Figure 37).
Figure 36 through Figure 38 show the read and write data formats.
These figures show read operations; for a write to a register or
subregister, the write bit is set and the DOUT line remains high
impedance.
reference level is set by Pin 5 (VDRIVE) to a level in the range of
1.8 V to 5.25 V.
SCLK is the serial clock input for the device; all data transfers
on DIN or DOUT take place with respect to SCLK. The chip
CS
select input pin ( ) is an active low control that initiates the
data transfer and conversion process.
Data is clocked into the AD7292 on the SCLK falling edge.
Data is loaded into the device MSB first. The length of each
frame can vary and depends on the command being sent. Data
is clocked out of the AD7292 on DOUT in the same frame as
If neither the read nor write bit is set (Bit D7 and Bit D6 of the
address pointer are set to 0), the address pointer is updated but
no data is read or written. Note that writing this command also
reinitializes the ADC sequencer (see the ADC Conversion
Control section).
CS
the read command, on the rising edge of SCLK while
is low.
CS
When
is high, the SCLK and DIN signals are ignored and
the DOUT line becomes high impedance.
On completion of a read or write, the AD7292 is ready to accept
INTERFACE PROTOCOL
CS
a new pointer address; alternatively, the
to terminate the operation.
pin can be taken high
When reading from or writing to the AD7292, the first byte con-
tains the address pointer (see Table 13). Bit D7 and Bit D6 of the
address pointer are the read and write bits, respectively. Bit D5 to
Bit D0 of the address pointer specify the register address for the
read or write operation. A register can be simultaneously read
from and written to by setting both Bit D7 and Bit D6 to 1.
2
BUSY
t7
t8
t3
CS
t11
t2
t1
t4
SCLK
t5
t6
DIN
X
R
W
D5
D4
D3
D2
D1
D0
LSB
X
t10
HIGH-Z
HIGH-Z
t12
1
LSB
DOUT
t9
1
2
PROVIDED THE READ BIT IS SET.
IF AN ADC CONVERSION IS REQUESTED.
t7 = 5ns IF NO ADC CONVERSION
955ns WITH ADC CONVERSION
Figure 35. Serial Interface Timing Diagram
CS
DIN
R
W
POINTER [D5:D0]
DIN [D15:D8]
DIN [D7:D0]
1
DOUT [D15:D0]
DOUT
1
PROVIDED THE READ BIT IS SET.
Figure 36. Accessing a 16-Bit Register
Rev. A | Page 18 of 40
Data Sheet
AD7292
CS
DIN
R
W
POINTER [D5:D0]
SUBPOINTER [D7:D0]
DIN [D7:D0]
1
DOUT [D7:D0]
DOUT
1
PROVIDED THE READ BIT IS SET.
Figure 37. Accessing an 8-Bit Subregister Within a Register Bank
CS
DIN
R
W
POINTER [D5:D0]
SUBPOINTER [D7:D0]
DIN [D15:D8]
DIN [D7:D0]
1
DOUT [D15:D0]
DOUT
1
PROVIDED THE READ BIT IS SET.
Figure 38. Accessing a 16-Bit Subregister Within a Register Bank
Rev. A | Page 19 of 40
AD7292
Data Sheet
REGISTER STRUCTURE
The AD7292 contains internal registers that store conversion
results, high and low conversion limits, and information to
configure and control the device (see Figure 39). Each register
has an address; the address pointer register points to the address
when communicating with the register. Some registers and sub-
registers contain reserved bits. The AD7292 allows either a 0 or
a 1 to be written to these reserved bits.
Table 14 lists each register and specifies whether the register has
read access or read and write access.
Table 14. AD7292 Registers
Data
Address Register Name
Access1 Format
0x00
0x01
0x03
0x05
0x06
0x07
0x08
Vendor ID register
ADC data register
R
R
Figure 36
Figure 36
Figure 36
Figure 38
Figure 38
Figure 38
Figure 38
ADC sequence register
Configuration register bank
Alert limits register bank
Alert flags register bank
Minimum and maximum
register bank
R/W
R/W
R/W
R/W
R/W
VENDOR ID
REGISTER
ADC DATA
ADC SEQUENCE
REGISTER
CONFIGURATION
REGISTER BANK
0x09
0x0A
0x0B
0x0E
0x10
Offset register bank
DAC buffer enable register
GPIO register
R/W
R/W
R/W
N/A
R
Figure 37
Figure 36
Figure 36
N/A
ALERT LIMITS
REGISTER BANK
Conversion command2
ALERT FLAGS
REGISTER BANK
ADC conversion result register,
Channel 0
Figure 36
ADDRESS
POINTER
REGISTER
MINIMUM AND MAXIMUM
REGISTER BANK
0x11
0x12
0x13
0x14
0x15
0x16
0x17
ADC conversion result register,
Channel 1
ADC conversion result register,
Channel 2
ADC conversion result register,
Channel 3
ADC conversion result register,
Channel 4
ADC conversion result register,
Channel 5
ADC conversion result register,
Channel 6
ADC conversion result register,
Channel 7
R
R
R
R
R
R
R
Figure 36
Figure 36
Figure 36
Figure 36
Figure 36
Figure 36
Figure 36
OFFSET
REGISTER BANK
DAC BUFFER
ENABLE REGISTER
GPIO
REGISTER
CONVERSION
COMMAND
ADC CONVERSION
RESULT REGISTERS × 8
T
CONVERSION
SENSE
RESULT REGISTER
DAC CHANNEL
REGISTERS × 4
DIN
0x20
0x30
0x31
0x32
0x33
TSENSE conversion result register
DAC Channel 0 register
DAC Channel 1 register
DAC Channel 2 register
DAC Channel 3 register
R
Figure 36
Figure 36
Figure 36
Figure 36
Figure 36
SCLK
DOUT
CS
SERIAL BUS INTERFACE
R/W
R/W
R/W
R/W
Figure 39. AD7292 Register Structure
1 R is read only; R/W is read/write.
2 See the ADC Conversion Command section for more information.
Rev. A | Page 20 of 40
Data Sheet
AD7292
REGISTER DESCRIPTIONS
VENDOR ID REGISTER (ADDRESS 0x00)
CONFIGURATION REGISTER BANK (ADDRESS 0x05)
The 16-bit, read-only vendor ID register stores the Analog
Devices vendor ID, 0x0018. The vendor ID register is provided
to identify the AD7292 to an SPI master such as a microcontroller.
The configuration register bank subregisters are listed in Table 15.
On power-up, the subregisters within the configuration register
bank contain all 0s by default.
ADC DATA REGISTER (ADDRESS 0x01)
Table 15. Configuration Register Bank Subregisters
Subaddress (Hex) Subregister Name1
The 16-bit, read-only ADC data register provides read access to
the most recent ADC conversion result. This register provides
10 bits of conversion data, four channel identifier bits, and two
alert bits (see the ADC Conversion Control section).
0x01
0x02
0x08
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x20
0x21
0x30
0x31
Digital output driver
Digital I/O function
General
VIN RANGE0
VIN RANGE1
ADC SEQUENCE REGISTER (ADDRESS 0x03)
The 16-bit, read/write ADC sequence register allows the user to
specify a preprogrammed sequence of ADC channels for conver-
sion. The ADC converts on each of the specified ADC channels
in turn. For more information, see the ADC Conversion Control
section. Table 16 describes the register bit functions. Bit D15 is
the first bit in the data stream. On power-up, the ADC sequence
register contains all 0s by default.
ADC sampling mode
VIN filter
Conversion delay control
VIN ALERT0 routing
VIN ALERT1 routing
Temperature sensor
Temperature sensor alert routing
GPIO2/DAC DISABLE0
GPIO4/DAC DISABLE1
Temperature sensor results can be inserted into the sequence by
writing a 1 to Bit D8 of the ADC sequence register, provided that
the temperature sensor has been enabled in the temperature
sensor subregister within the configuration register bank (see
the Temperature Sensor Subregister (Address 0x20) section).
1 All subregisters in the configuration register bank are read/write.
Table 16. ADC Sequence Register, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D9]
D8
Reserved
TSENSE readback enable
Reserved
0 = disable TSENSE readback
1 = enable TSENSE readback
D7
D6
D5
D4
D3
D2
D1
D0
ADC Channel 7 convert
ADC Channel 6 convert
ADC Channel 5 convert
ADC Channel 4 convert
ADC Channel 3 convert
ADC Channel 2 convert
ADC Channel 1 convert
ADC Channel 0 convert
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 = disable conversion of Channel 7
1 = enable conversion of Channel 7
0 = disable conversion of Channel 6
1 = enable conversion of Channel 6
0 = disable conversion of Channel 5
1 = enable conversion of Channel 5
0 = disable conversion of Channel 4
1 = enable conversion of Channel 4
0 = disable conversion of Channel 3
1 = enable conversion of Channel 3
0 = disable conversion of Channel 2
1 = enable conversion of Channel 2
0 = disable conversion of Channel 1
1 = enable conversion of Channel 1
0 = disable conversion of Channel 0
1 = enable conversion of Channel 0
Rev. A | Page 21 of 40
AD7292
Data Sheet
Digital Output Driver Subregister (Address 0x01)
Digital I/O Function Subregister (Address 0x02)
The 16-bit digital output driver subregister enables the output
drivers of the digital I/O pins. Setting Bits[D11:D0] to 1 enables
the corresponding digital I/O output driver. Six of the 12 digital
I/O pins offer mixed functionality (see Table 18). When a digital
I/O pin is configured as a GPIO pin and its output is enabled, its
value is controlled by the GPIO register (see the GPIO Register
(Address 0x0B) section).
Six of the 12 GPIO pins offer dual functionality. To enable
standard GPIO functionality, write a 1 to the corresponding
bit in the 16-bit digital I/O subregister. To enable the alternative
functionality, write a 0 to the appropriate bit (see Table 18). For
example, to configure the GPIO6/BUSY pin as an ADC busy pin,
write a 0 to Bit D6 of Address 0x02.
Table 17. Digital Output Driver Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
[D15:D12] Reserved
Reserved
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GPIO11 output
0 = disable GPIO11 output driver; 1 = enable GPIO11 output driver
0 = disable GPIO10 output driver; 1 = enable GPIO10 output driver
0 = disable GPIO9 output driver; 1 = enable GPIO9 output driver
0 = disable GPIO8 output driver; 1 = enable GPIO8 output driver
0 = disable GPIO7 output driver; 1 = enable GPIO7 output driver
0 = disable GPIO6 output driver; 1 = enable GPIO6/BUSY output driver
0 = disable GPIO5 output driver; 1 = enable GPIO5 output driver
0 = disable GPIO4 output driver; 1 = enable GPIO4/DAC DISABLE1 output driver
0 = disable GPIO3 output driver; 1 = enable GPIO3/LDAC output driver
0 = disable GPIO2 output driver; 1 = enable GPIO4/DAC DISABLE0 output driver
0 = disable GPIO1 output driver; 1 = enable GPIO1/ALERT1 output driver
0 = disable GPIO0 output driver; 1 = enable GPIO1/ALERT0 output driver
GPIO10 output
GPIO9 output
GPIO8 output
GPIO7 output
GPIO6 output
GPIO5 output
GPIO4 output
GPIO3 output
GPIO2 output
GPIO1 output
GPIO0 output
Table 18. Digital I/O Function Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D12] Reserved
Reserved
0 = reserved
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GPIO11
1 = enable the GPIO11 function
0 = reserved
1 = enable the GPIO10 function
0 = reserved
1 = enable the GPIO9 function
0 = reserved
1 = enable the GPIO8 function
0 = reserved
1 = enable the GPIO7 function
0 = enable the ADC busy output function
1 = enable the GPIO6 function
0 = reserved
1 = enable the GPIO5 function
0 = enable the DAC DISABLE1 input function
1 = enable the GPIO4 function
0 = enable the LDAC input function
1 = enable the GPIO3 function
0 = enable the DAC DISABLE0 input function
1 = enable the GPIO2 function
0 = enable the ALERT1 output function
1 = enable the GPIO1 function
GPIO10
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
GPIO9
GPIO8
GPIO7
GPIO6/BUSY
GPIO5
GPIO4/DAC DISABLE1
GPIO3/LDAC
GPIO2/DAC DISABLE0
GPIO1/ALERT1
GPIO0/ALERT0
0 = enable the ALERT0 output function
1 = enable the GPIO0 function
Rev. A | Page 22 of 40
Data Sheet
AD7292
General Subregister (Address 0x08)
Bit D5 and Bit D4 of the general subregister are used to configure
the polarity of the ALERT output pins when the GPIO1/ALERT1
and GPIO0/ALERT0 pins are configured as alert outputs (see the
Digital Output Driver Subregister (Address 0x01) section and
the Digital I/O Function Subregister (Address 0x02) section).
When the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1
pins are configured as DAC disable pins (via the digital I/O func-
tion subregister), Bits[D2:D1] of the 16-bit general subregister
control the power disable mode of these two pins. Table 19 shows
the four power disable modes. The GPIO2/DAC DISABLE0 and
GPIO4/DAC DISABLE1 subregisters determine which DAC out-
puts are controlled by the GPIO2/DAC DISABLE0 and GPIO4/
DAC DISABLE1 pins (see Table 29 and Table 30).
Bit D8 is used to select the source of the voltage reference used
for the AD7292. When this bit is set to 1, the external reference
is used. When this bit is set to 0, the internal reference is used.
Table 19. General Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D9]
D8
Reserved
Reference mode
Reserved.
This bit specifies whether the internal reference or an external reference is used.
0 = internal reference used (default).
1 = external reference used.
[D7:D6]
D5
Reserved
ALERT1 polarity
R/W
R/W
Reserved.
When the GPIO1/ALERT1 pin is configured to function as an alert, this bit sets the polarity
of the ALERT1 pin.
0 = active low (default).
1 = active high.
D4
ALERT0 polarity
R/W
When the GPIO0/ALERT0 pin is configured to function as an alert, this bit sets the polarity
of the ALERT0 pin.
0 = active low (default).
1 = active high.
D3
[D2:D1]
Reserved
DAC disable mode
R/W
R/W
Reserved.
These bits control the disable mode of the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1
pins when these pins are configured to function as DAC disable pins.
00 = 1 kΩ and 100 kΩ resistors in parallel to ground (default).
01 = 100 kΩ resistor to ground.
10 = 1 kΩ resistor to ground.
11 = high impedance.
D0
Reserved
R/W
Reserved.
Rev. A | Page 23 of 40
AD7292
Data Sheet
VIN RANGE0 and VIN RANGE1 Subregisters
(Address 0x10 and Address 0x11)
each channel; that is, setting Bit D0 of VIN RANGE1 and Bit D0
of VIN RANGE0 enables a divide-by-4 factor for the VIN0 input
range. The settings of the VIN RANGE0 and VIN RANGE1 bits
are ignored if samples are with respect to AVDD (see the ADC
Sampling Mode Subregister (Address 0x12) section).
The 16-bit VIN RANGE0 and VIN RANGE1 subregisters
specify a divide-by-2 factor for each analog input channel,
VIN0 to VIN7. A divide-by-2 factor from both the VIN
RANGE0 and VIN RANGE1 subregisters can be applied to
Table 20. VIN RANGE0 and VIN RANGE1 Subregisters, Bit Function Descriptions (Default = 0)
Bits
[D15:D8]
D7
D6
D5
D4
D3
D2
D1
Bit Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
Reserved
Reserved
VIN7 range
VIN6 range
VIN5 range
VIN4 range
VIN3 range
VIN2 range
VIN1 range
VIN0 range
Analog input range for VIN7 (see Table 21)
Analog input range for VIN6 (see Table 21)
Analog input range for VIN5 (see Table 21)
Analog input range for VIN4 (see Table 21)
Analog input range for VIN3 (see Table 21)
Analog input range for VIN2 (see Table 21)
Analog input range for VIN1 (see Table 21)
Analog input range for VIN0 (see Table 21)
D0
Table 21. Analog Input Range Selection
Subregister Bit Settings
Sample with Respect to AGND
Sample with Respect to AVDD
Single-Ended Input Range
(VIN0 to VIN7)
Single-Ended Input Range Differential Input Range
VIN RANGE1
VIN RANGE0
(VIN0 to VIN7)
0 V to 4 × VREF
0 V to 2 × VREF
0 V to 2 × VREF
0 V to VREF
(VIN0 and VIN1 Only)
−4 × VREF to +4 × VREF
−2 × VREF to +2 × VREF
−2 × VREF to +2 × VREF
−VREF to +VREF
0
0
1
1
0
1
0
1
(AVDD − 4 × VREF) to AVDD
Not applicable
Not applicable
Not applicable
Rev. A | Page 24 of 40
Data Sheet
AD7292
ADC Sampling Mode Subregister (Address 0x12)
input to the ADC is (VIN0, VIN1). When enabled and convert-
ing on VIN1, the differential input to the ADC is (VIN1, VIN0).
To use differential mode, Bit D0 must be set to 1.
Table 22 lists the bit function descriptions for the 16-bit ADC
sampling mode subregister. Bit D0 allows the user to enable
differential input mode for analog input channels VIN0 and
VIN1. When enabled and converting on VIN0, the differential
Bits[D15:D8] specify whether the corresponding analog input,
VIN7 to VIN0, is measured with respect to AVDD or AGND
.
Table 22. ADC Sampling Mode Subregister, Bit Function Descriptions (Default = 0)
Bits
Bit Name
R/W
Description
D15
VIN7 sampling mode
R/W
This bit specifies whether VIN7 is measured with respect to AVDD or AGND
.
.
.
.
.
.
.
.
0 = sample with respect to AVDD.
1 = sample with respect to AGND
.
D14
D13
D12
D11
D10
D9
VIN6 sampling mode
VIN5 sampling mode
VIN4 sampling mode
VIN3 sampling mode
VIN2 sampling mode
VIN1 sampling mode
VIN0 sampling mode
Reserved
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This bit specifies whether VIN6 is measured with respect to AVDD or AGND
0 = sample with respect to AVDD.
1 = sample with respect to AGND
.
This bit specifies whether VIN5 is measured with respect to AVDD or AGND
0 = sample with respect to AVDD.
1 = sample with respect to AGND
.
This bit specifies whether VIN4 is measured with respect to AVDD or AGND
0 = sample with respect to AVDD.
1 = sample with respect to AGND
.
This bit specifies whether VIN3 is measured with respect to AVDD or AGND
0 = sample with respect to AVDD.
1 = sample with respect to AGND
.
This bit specifies whether VIN2 is measured with respect to AVDD or AGND
0 = sample with respect to AVDD.
1 = sample with respect to AGND
.
This bit specifies whether VIN1 is measured with respect to AVDD or AGND
0 = sample with respect to AVDD.
1 = sample with respect to AGND
.
D8
This bit specifies whether VIN0 is measured with respect to AVDD or AGND
0 = sample with respect to AVDD.
1 = sample with respect to AGND
.
[D7:D1]
D0
R/W
R/W
Reserved.
VIN0/VIN1 differential
mode
This bit specifies whether VIN0 and VIN1 function as two single-ended inputs or as a
differential pair.
0 = single-ended mode.
1 = differential mode.
Rev. A | Page 25 of 40
AD7292
Data Sheet
VIN Filter Subregister (Address 0x13)
Conversion Delay Control Subregister (Address 0x14)
The 16-bit VIN filter subregister enables digital filtering of the
analog inputs channels. The digital filter consists of a simple
low-pass filter function to help reduce unwanted noise on dc
signals. Writing a 1 to Bits[D7:D0] in this subregister enables
digital filtering of the corresponding analog input channel (see
Table 23). On power-up, the VIN filter subregister contains all
0s by default.
The 16-bit conversion delay control subregister is used to delay
the start (including the sample point) of a conversion. The delay
is a count of internal ADC clocks following the falling SCLK
signal that triggers the start of a conversion.
For example, if the conversion delay control subregister holds
the value 0x0003, three ADC clocks are counted before the
ADC enters hold mode and the conversion begins. The ADC
clock has a period of 40 ns typically.
If the conversion delay control subregister is set to a nonzero
value N, the ADC waits for the programmed number of ADC
clock periods (N) after a conversion is triggered before
sampling the input. If the register holds the default value of 0,
there is no delay, and the conversion is started from the falling
SCLK that triggers the start of the conversion. When using the
conversion delay, the conversion is extended by N + 1 clocks.
Table 23. VIN Filter Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D8] Reserved
Reserved
0 = disable digital filtering of VIN7
1 = enable digital filtering of VIN7
0 = disable digital filtering of VIN6
1 = enable digital filtering of VIN6
0 = disable digital filtering of VIN5
1 = enable digital filtering of VIN5
0 = disable digital filtering of VIN4
1 = enable digital filtering of VIN4
0 = disable digital filtering of VIN3
1 = enable digital filtering of VIN3
0 = disable digital filtering of VIN2
1 = enable digital filtering of VIN2
0 = disable digital filtering of VIN1
1 = enable digital filtering of VIN1
D7
D6
D5
D4
D3
D2
D1
D0
Enable digital filtering of VIN7
Enable digital filtering of VIN6
Enable digital filtering of VIN5
Enable digital filtering of VIN4
Enable digital filtering of VIN3
Enable digital filtering of VIN2
Enable digital filtering of VIN1
Enable digital filtering of VIN0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 = disable digital filtering of VIN0
1 = enable digital filtering of VIN0
Table 24. Conversion Delay Control Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
Description
[D15:D0]
Delay value
R/W
These bits specify the 16-bit delay value (0 to 0xFFFF) before the start of a conver-
sion. The delay is a count of internal ADC clocks following the falling SCLK signal.
Rev. A | Page 26 of 40
Data Sheet
AD7292
VIN ALERT0 Routing and VIN ALERT1 Routing
Subregisters (Address 0x15 and Address 0x16)
For information about how to configure the GPIO0/ALERT0
and GPIO1/ALERT1 pins as alert pins, see the Digital I/O
Function Subregister (Address 0x02) section and the Digital
Output Driver Subregister (Address 0x01) section.
The 16-bit VIN ALERT0 and VIN ALERT1 subregisters enable
the routing of alerts from the analog input channels, VIN0 to
VIN7, to the GPIO0/ALERT0 and GPIO1/ALERT1 pins (see
Table 25 and Table 26.
For information about how to enable routing of the temperature
sensor alerts, see the Temperature Sensor Alert Routing
Subregister (Address 0x21) section.
Table 25. VIN ALERT0 Routing Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D8]
D7
Reserved
Route VIN7 alerts to ALERT0 pin
Reserved
0 = disable routing ofVIN7 alerts to the ALERT0 pin
1 = enable routing ofVIN7 alerts to the ALERT0 pin
D6
D5
D4
D3
D2
D1
D0
Route VIN6 alerts to ALERT0 pin
Route VIN5 alerts to ALERT0 pin
Route VIN4 alerts to ALERT0 pin
Route VIN3 alerts to ALERT0 pin
Route VIN2 alerts to ALERT0 pin
Route VIN1 alerts to ALERT0 pin
Route VIN0 alerts to ALERT0 pin
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 = disable routing of VIN6 alerts to the ALERT0 pin
1 = enable routing of VIN6 alerts to the ALERT0 pin
0 = disable routing of VIN5 alerts to the ALERT0 pin
1 = enable routing of VIN5 alerts to the ALERT0 pin
0 = disable routing of VIN4 alerts to the ALERT0 pin
1 = enable routing of VIN4 alerts to the ALERT0 pin
0 = disable routing of VIN3 alerts to the ALERT0 pin
1 = enable routing of VIN3 alerts to the ALERT0 pin
0 = disable routing of VIN2 alerts to the ALERT0 pin
1 = enable routing of VIN2 alerts to the ALERT0 pin
0 = disable routing of VIN1 alerts to the ALERT0 pin
1 = enable routing of VIN1 alerts to the ALERT0 pin
0 = disable routing of VIN0 alerts to the ALERT0 pin
1 = enable routing of VIN0 alerts to the ALERT0 pin
Table 26. VIN ALERT1 Routing Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D0]
D7
Reserved
Route VIN7 alerts to ALERT1 pin
Reserved
0 = disable routing ofVIN7 alerts to the ALERT1 pin
1 = enable routing ofVIN7 alerts to the ALERT1 pin
D6
D5
D4
D3
D2
D1
D0
Route VIN6 alerts to ALERT1 pin
Route VIN5 alerts to ALERT1 pin
Route VIN4 alerts to ALERT1 pin
Route VIN3 alerts to ALERT1 pin
Route VIN2 alerts to ALERT1 pin
Route VIN1 alerts to ALERT1 pin
Route VIN0 alerts to ALERT1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 = disable routing ofVIN6 alerts to the ALERT1 pin
1 = enable routing ofVIN6 alerts to the ALERT1 pin
0 = disable routing ofVIN5 alerts to the ALERT1 pin
1 = enable routing ofVIN5 alerts to the ALERT1 pin
0 = disable routing ofVIN4 alerts to the ALERT1 pin
1 = enable routing ofVIN4 alerts to the ALERT1 pin
0 = disable routing ofVIN3 alerts to the ALERT1 pin
1 = enable routing ofVIN3 alerts to the ALERT1 pin
0 = disable routing ofVIN2 alerts to the ALERT1 pin
1 = enable routing ofVIN2 alerts to the ALERT1 pin
0 = disable routing ofVIN1 alerts to the ALERT1 pin
1 = enable routing ofVIN1 alerts to the ALERT1 pin
0 = disable routing ofVIN0 alerts to the ALERT1 pin
1 = enable routing ofVIN0 alerts to the ALERT1 pin
Rev. A | Page 27 of 40
AD7292
Data Sheet
Temperature Sensor Subregister (Address 0x20)
For information about how to configure the GPIO0/ALERT0 and
GPIO1/ALERT1 pins as alert pins, see the Digital I/O Function
Subregister (Address 0x02) section and the Digital Output Driver
Subregister (Address 0x01) section.
The 16-bit temperature sensor subregister enables temperature
sensor conversions and digital filtering of the temperature sensor
channel. To enable temperature sensor conversions or digital
filtering, the corresponding bit in the temperature sensor sub-
register must be set to 1 (see Table 27). On power-up, the
temperature sensor subregister contains all 0s by default.
For information about how to enable routing of the analog input
channel alerts, see the VIN Filter Subregister (Address 0x13)
and Conversion Delay Control Subregister (Address 0x14)
section.
Temperature Sensor Alert Routing Subregister
(Address 0x21)
The 16-bit temperature sensor alert routing subregister enables
the routing of alerts from the internal temperature sensor to the
GPIO0/ALERT0 and GPIO1/ALERT1 pins (see Table 28).
Table 27. Temperature Sensor Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D9]
D8
Reserved
Enable/disable digital
filtering of TSENSE
Reserved.
This bit specifies whether digital filtering is enabled on the temperature sensor channel.
0 = disable digital filtering of the temperature sensor channel (default).
1 = enable digital filtering of the temperature sensor channel.
[D7:D1]
D0
Reserved
Enable/disable TSENSE
conversions
R/W
R/W
Reserved.
This bit enables or disables conversion of the temperature sensor channel.
0 = disable TSENSE conversions (default).
1 = enable TSENSE conversions.
Table 28. Temperature Sensor Alert Routing Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D9]
D8
Reserved
Route TSENSE alerts to
ALERT1 pin
Reserved.
This bit specifies whether alerts from the internal temperature sensor are routed to the
ALERT1 pin.
0 = disable routing of alerts from the temperature sensor to the ALERT1 pin (default).
1 = enable routing of alerts from the temperature sensor to the ALERT1 pin.
[D7:D1]
D0
Reserved
Route TSENSE alerts to
ALERT0 pin
R/W
R/W
Reserved.
This bit specifies whether alerts from the internal temperature sensor are routed to the
ALERT0 pin.
0 = disable routing of alerts from the temperature sensor to the ALERT0 pin (default).
1 = enable routing of alerts from the temperature sensor to the ALERT0 pin.
Rev. A | Page 28 of 40
Data Sheet
AD7292
GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1
Subregisters (Address 0x30 and Address 0x31)
For information about how to enable the DAC disable function
on the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1
pins, see the Digital Output Driver Subregister (Address 0x01)
section and the Digital I/O Function Subregister (Address 0x02)
section.
The 16-bit, read/write GPIO2/DAC DISABLE0 and GPIO4/DAC
DISABLE1 subregisters specify which DAC channels are disabled
by the GPIO2/DAC DISABLE0 and GPIO4/DAC DISABLE1 pins.
For example, when Bit D0 in the GPIO2/DAC DISABLE0 sub-
register is set to 1, the GPIO2/DAC DISABLE0 pin disables DAC
output VOUT0 when the pin is taken high. On power-up, these
subregisters contain all 0s by default.
Table 29. GPIO2/DAC DISABLE0 Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D4]
D3
Reserved
Disable VOUT3 pin
Reserved.
This bit specifies whether the VOUT3 output is disabled when the GPIO2/DAC DISABLE0
pin is high.
0 = disable control of VOUT3 by the GPIO2/DAC DISABLE0 pin (default).
1 = enable control of VOUT3 by the GPIO2/DAC DISABLE0 pin.
D2
D1
D0
Disable VOUT2 pin
Disable VOUT1 pin
Disable VOUT0 pin
R/W
R/W
R/W
This bit specifies whether the VOUT2 output is disabled when the GPIO2/DAC DISABLE0
pin is high.
0 = disable control of VOUT2 by the GPIO2/DAC DISABLE0 pin (default).
1 = enable control of VOUT2 by the GPIO2/DAC DISABLE0 pin.
This bit specifies whether the VOUT1 output is disabled when the GPIO2/DAC DISABLE0
pin is high.
0 = disable control of VOUT1 by the GPIO2/DAC DISABLE0 pin (default).
1 = enable control of VOUT1 by the GPIO2/DAC DISABLE0 pin.
This bit specifies whether the VOUT0 output is disabled when the GPIO2/DAC DISABLE0
pin is high.
0 = disable control of VOUT0 by the GPIO2/DAC DISABLE0 pin (default).
1 = enable control of VOUT0 by the GPIO2/DAC DISABLE0 pin.
Table 30. GPIO4/DAC DISABLE1 Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D4]
D3
Reserved
Disable VOUT3 pin
Reserved.
This bit specifies whether the VOUT3 output is disabled when the GPIO4/DAC DISABLE1
pin is high.
0 = disable control of VOUT3 by the GPIO4/DAC DISABLE1 pin (default).
1 = enable control of VOUT3 by the GPIO4/DAC DISABLE1 pin.
D2
D1
D0
Disable VOUT2 pin
Disable VOUT1 pin
Disable VOUT0 pin
R/W
R/W
R/W
This bit specifies whether the VOUT2 output is disabled when the GPIO4/DAC DISABLE1
pin is high.
0 = disable control of VOUT2 by the GPIO4/DAC DISABLE1 pin (default).
1 = enable control of VOUT2 by the GPIO4/DAC DISABLE1 pin.
This bit specifies whether the VOUT1 output is disabled when the GPIO4/DAC DISABLE1
pin is high.
0 = disable control of VOUT1 by the GPIO4/DAC DISABLE1 pin (default).
1 = enable control of VOUT1 by the GPIO4/DAC DISABLE1 pin.
This bit specifies whether the VOUT0 output is disabled when the GPIO4/DAC DISABLE1
pin is high.
0 = disable control of VOUT0 by the GPIO4/DAC DISABLE1 pin (default).
1 = enable control of VOUT0 by the GPIO4/DAC DISABLE1 pin.
Rev. A | Page 29 of 40
AD7292
Data Sheet
Table 31. Alert Limits Register Bank Subregisters
Subaddress (Hex) Subregister Name1
ALERT LIMITS REGISTER BANK (ADDRESS 0x06)
The alert limits register bank comprises subregisters that set the
high and low alert limits for the eight analog input channels and
the temperature sensor channel (see Table 31). Each subregister
is 16 bits in length; values are 10-bit, left-justified (padded with
0s as the 6 LSBs). On power-up, the low limit and hysteresis
subregisters contain all 0s, whereas the high limit subregisters
are set to 0xFFC0.
0x00
0x01
0x02
VIN0 alert high limit
VIN0 alert low limit
VIN0 hysteresis
0x03
0x04
0x05
VIN1 alert high limit
VIN1 alert low limit
VIN1 hysteresis
0x06
0x07
0x08
VIN2 alert high limit
VIN2 alert low limit
VIN2 hysteresis
If a conversion result exceeds the high or low limit set in the
alert limits subregister, the AD7292 signals an alert in one or
more of the following ways:
0x09
0x0A
0x0B
VIN3 alert high limit
VIN3 alert low limit
VIN3 hysteresis
•
Via hardware using the GPIO0/ALERT0 and GPIO1/ALERT1
pins (see the Hardware Alert Pins section)
•
Via software using the alert flag bits in the conversion result
registers (see the ADC Conversion Result Registers, VIN0
to VIN7 (Address 0x10 to Address 0x17) section and the
0x0C
0x0D
0x0E
VIN4 alert high limit
VIN4 alert low limit
VIN4 hysteresis
T
SENSE Conversion Result Register (Address 0x20) section)
0x0F
0x10
0x11
0x12
0x13
0x14
VIN5 alert high limit
VIN5 alert low limit
VIN5 hysteresis
VIN6 alert high limit
VIN6 alert low limit
VIN6 hysteresis
•
Via software using the alert bits in the alert flags register
bank (see the Alert Flags Register Bank (Address 0x07)
section)
Alert High Limit and Alert Low Limit Subregisters
The alert high limit subregisters store the upper limit that
activates an alert. If the conversion result is greater than the value
in the alert high limit subregister, an alert is triggered. The alert
low limit subregister stores the lower limit that activates an alert.
If the conversion result is less than the value in the alert low limit
subregister, an alert is triggered.
0x15
0x16
0x17
0x18 to 0x2F
0x30
0x31
0x32
0x33 to 0xFF
VIN7 alert high limit
VIN7 alert low limit
VIN7 hysteresis
Reserved
TSENSE alert high limit
TSENSE alert low limit
TSENSE hysteresis
An alert associated with either the alert high limit or alert low
limit subregister is cleared automatically after the monitored
signal is back in range, that is, when the conversion result returns
between the configured high and low limits. The contents of the
alert flags subregisters are updated after each conversion (see the
Alert Flags Register Bank (Address 0x07) section).
Reserved
1 All subregisters in the alert limits register bank are read/write.
Hysteresis Subregisters
Each channel has an associated hysteresis subregister that stores
the hysteresis value, N (see Table 31). The hysteresis subregisters
can be used to avoid flicker on the GPIO0/ALERT0 and GPIO1/
ALERT1 pins. If the hysteresis function is enabled, the conversion
result must return to a value of at least N LSB below the alert high
limit subregister value, or N LSB above the alert low limit sub-
register value for the alert output pins and alert flag bits to be reset
(see Figure 46). The value of N is taken from the 10 MSBs of the
16-bit, read/write hysteresis subregister. For more information,
see the Hysteresis section.
Rev. A | Page 30 of 40
Data Sheet
AD7292
These subregisters contain two status bits per channel: one
ALERT FLAGS REGISTER BANK (ADDRESS 0x07)
corresponding to the high limit, and the other corresponding to
the low limit. A bit with a status of 1 shows the channel on which
the violation occurred and whether the violation occurred on the
high or low limit.
If a conversion result activates an alert (as specified in the alert
limits register bank), the alert flags register bank can be read
to obtain more information about the alert. This register bank
contains the ADC alert flags and TSENSE alert flags subregisters.
Both subregisters store flags that are triggered when the mini-
mum or maximum conversion limits, as defined in the alert
limits register bank, are exceeded.
If additional alert events occur on any other channels after the
first alert is triggered but before the alert flags subregister is read,
the corresponding bits for the new alert events are also set. For
example, if Bit D14 in the ADC alert flags subregister is set to 1,
the low limit on Channel 7 has been exceeded, whereas if Bit D3
is set to 1, the high limit on Channel 1 has been exceeded.
Table 32. Alert Flags Register Bank Subregisters
Subaddress (Hex) Subregister Name1
0x00
0x01
ADC alert flags subregister
Reserved
To find out which channel or channels caused the alert flag, the
user must read the ADC alert flags subregister or the TSENSE alert
flags subregister. If the ADC alert flags subregister or the TSENSE
alert flags subregister is accessed with both the read and write bits
of the address pointer set to 1, the stored alert flags can be read
and reset in one operation. A blanket reset can be performed by
writing 0xFFFF to the ADC alert flags subregister, or 0x0003 to
the TSENSE alert flags subregister, thus clearing all alert flags.
0x02
0x03 to 0xFF
TSENSE alert flags subregister
Reserved
1 Bits in the alert flags subregisters can be reset by writing 1 to the selected bits.
ADC Alert Flags and TSENSE Alert Flags Subregisters
(Address 0x00 and Address 0x02)
The ADC alert flags subregister stores alerts for the analog volt-
age conversion channels, VIN0 to VIN7. The TSENSE alert flags
subregister stores alerts for the temperature sensor channel.
Table 33. ADC Alert Flags Subregister, Bit Function Descriptions
Bits
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
Bit Name
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Description
VIN7 high limit flag
VIN7 low limit flag
VIN6 high limit flag
VIN6 low limit flag
VIN5 high limit flag
VIN5 low limit flag
VIN4 high limit flag
VIN4 low limit flag
VIN3 high limit flag
VIN3 low limit flag
VIN2 high limit flag
VIN2 low limit flag
VIN1 high limit flag
VIN1 low limit flag
VIN0 high limit flag
VIN0 low limit flag
1 = VIN7 high limit exceeded
1 = VIN7 low limit exceeded
1 = VIN6 high limit exceeded
1 = VIN6 low limit exceeded
1 = VIN5 high limit exceeded
1 = VIN5 low limit exceeded
1 = VIN4 high limit exceeded
1 = VIN4 low limit exceeded
1 = VIN3 high limit exceeded
1 = VIN3 low limit exceeded
1 = VIN2 high limit exceeded
1 = VIN2 low limit exceeded
1 = VIN1 high limit exceeded
1 = VIN1 low limit exceeded
1 = VIN0 high limit exceeded
1 = VIN0 low limit exceeded
D4
D3
D2
D1
D0
Table 34. TSENSE Alert Flags Subregister, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
R/W
Description
[D15:D2]
D1
D0
Reserved
TSENSE high limit flag
TSENSE low limit flag
Reserved
1 = TSENSE high limit exceeded
1 = TSENSE low limit exceeded
Rev. A | Page 31 of 40
AD7292
Data Sheet
MINIMUM AND MAXIMUM REGISTER BANK
(ADDRESS 0x08)
OFFSET REGISTER BANK (ADDRESS 0x09)
The offset register bank contains nine subregisters. Each of the
eight analog input channels, as well as the temperature sensor
channel, has a corresponding offset register (see Table 36).
The minimum and maximum register bank contains the mini-
mum and maximum conversion values for each of the eight
analog input channels and the temperature sensor channel.
Values are 10-bit, left justified.
Table 36. Offset Register Bank Subregisters
Subaddress (Hex)
Subregister Name1
VIN0 offset
VIN1 offset
VIN2 offset
VIN3 offset
VIN4 offset
VIN5 offset
VIN6 offset
The minimum and maximum subregisters are cleared when a
value is written to them—that is, they return to their power-up
values. This means that if a subregister is accessed with both the
read and write bits set, the stored minimum or maximum value
can be read and reset in one operation. On power-up, the mini-
mum value subregisters contain 0xFFC0, and the maximum value
subregisters contain 0x0000.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x10
VIN7 offset
Temperature sensor offset
Table 35. Minimum and Maximum Register Bank Subregisters
Subaddress (Hex)
Subregister Name1
VIN0 maximum value
VIN0 minimum value
VIN1 maximum value
VIN1 minimum value
VIN2 maximum value
VIN2 minimum value
VIN3 maximum value
VIN3 minimum value
VIN4 maximum value
VIN4 minimum value
VIN5 maximum value
VIN5 minimum value
VIN6 maximum value
VIN6 minimum value
VIN7 maximum value
VIN7 minimum value
Reserved
1 All subregisters in the offset register bank are read/write.
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Each 8-bit, read/write offset subregister stores data in twos
complement format. Values are added to the ADC conversion
results. The offset encoding scheme used for the analog input
channels and the temperature sensor are shown in Table 39 and
Table 40, respectively. The default value for all subregisters in
the offset register bank is 0x00.
When bits in these subregisters are set, the offset value is cumula-
tive. Table 37 provides examples of analog input channel values,
and Table 38 provides examples of temperature sensor channel
values.
Table 37. Examples of Analog Input Channel Offset Values
Offset Subregister Value
Offset Value (LSB)
10000000
11000000
00001000
−32
−16
+2
0x10 to 0x1F
0x20
0x21
TSENSE maximum value
TSENSE minimum value
Reserved
Table 38. Examples of Temperature Sensor Channel Offset
Values
0x22 to 0xFF
1 Bits in the minimum and maximum subregisters can be reset by writing 1 to
the selected bits.
Offset Subregister Value
Offset Value (°C)
10000000
11000000
−16
−8
00001000
+1
Table 39. VIN0 to VIN7 Offset Encoding Scheme
D7
D6
D5
D4
D3
D2
D1
D0
−32 LSB
+16 LSB
+8 LSB
+4 LSB
+2 LSB
+1 LSB
+0.5 LSB
+0.25 LSB
Table 40. Temperature Sensor Offset Encoding Scheme
D7
D6
D5
D4
D3
D2
D1
D0
−16°C
+8°C
+4°C
+2°C
+1°C
+0.5°C
+0.25°C
+0.125°C
Rev. A | Page 32 of 40
Data Sheet
AD7292
DAC BUFFER ENABLE REGISTER (ADDRESS 0x0A)
GPIO REGISTER (ADDRESS 0x0B)
The 16-bit, read/write DAC buffer enable register enables the
DAC output buffers. Setting the appropriate bit to 1 enables the
corresponding DAC output buffer (see Table 41). On power-up,
the DAC buffer enable register contains all 0s by default.
The 16-bit, read/write GPIO register is used to read or write data
to the GPIO pins, provided that the GPIO functionality is enabled
(see the Digital Output Driver Subregister (Address 0x01) section
and the Digital I/O Function Subregister (Address 0x02) section).
On power-up, the GPIO register contains all 0s by default.
Table 41. DAC Buffer Enable Register, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D4]
D3
Reserved
Enable DAC 3
Reserved
0 = disable DAC 3 output buffer (default)
1 = enable DAC 3 output buffer
D2
D1
D0
Enable DAC 2
Enable DAC 1
Enable DAC 0
R/W
R/W
R/W
0 = disable DAC 2 output buffer (default)
1 = enable DAC 2 output buffer
0 = disable DAC 1 output buffer (default)
1 = enable DAC 1 output buffer
0 = disable DAC 0 output buffer (default)
1 = enable DAC 0 output buffer
Table 42. GPIO Register, Bit Function Descriptions
Bits
Bit Name
R/W
R/W
R/W
Description
[D15:D12] Reserved
Reserved
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
GPIO11
GPIO10
GPIO9
GPIO8
GPIO7
GPIO6
GPIO5
GPIO4
GPIO3
GPIO2
GPIO1
GPIO0
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
0 = low output for write; low input for read
1 = high output for write; high input for read
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. A | Page 33 of 40
AD7292
Data Sheet
CONVERSION COMMAND REGISTER
(ADDRESS 0x0E)
TSENSE CONVERSION RESULT REGISTER
(ADDRESS 0x20)
The conversion command signals the ADC to begin conversions.
See the ADC Conversion Control section for more information.
The 16-bit, read-only TSENSE conversion result register stores the
ADC data generated from the internal temperature sensor. The
temperature data is stored in a 14-bit straight binary format. Bit D2
has a weight of 0.03125°C. An output of all 0s is equal to −256°C;
this value is output by the AD7292 until the first measurement is
completed. An output of 10 0000 0000 0000 corresponds to 0°C.
ADC CONVERSION RESULT REGISTERS, VIN0 TO
VIN7 (ADDRESS 0x10 TO ADDRESS 0x17)
The 16-bit, read-only ADC conversion result registers store the
conversion results of the eight ADC input channels. Bits[D15:D6]
store the 10-bit, straight binary result; Bits[D5:D0] contain the
channel ID and alert information. Table 43 lists the contents
of the two bytes that are read from the ADC conversion result
registers. Channel ID numbers 0 to 7 correspond to the analog
input channels, VIN0 to VIN7.
When digital filtering is disabled, Bit D3 and Bit D2 are set to 0,
producing a 12-bit straight binary result with an LSB of 0.125°C.
See the Temperature Sensor section for more information.
DAC CHANNEL REGISTERS (ADDRESS 0x30 TO
ADDRESS 0x33)
Writing to the DAC channel registers sets the DAC output voltage
codes. For more information, see the DAC Output Control section.
Table 43. ADC Conversion Result Register Format
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
[D5:D2]
D1
D0
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
4-bit channel ID TSENSE
ADC
(0000 to 0111)
alert flag alert flag
Table 44. TSENSE Conversion Result Register Format
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
B6
D7
B5
D6
D5
D4
D31
D21
D1
D0
B13
B12
B11
B10
B9
B8
B7
B4
B3
B2
B1
B0
TSENSE
alert
flag
ADC
alert
flag
1 When digital filter is enabled (see the Temperature Sensor Subregister (Address 0x20) section).
Table 45. DAC Channel Register Format
MSB
LSB
D0
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
0
0
0
0
Copy
LDAC
Rev. A | Page 34 of 40
Data Sheet
AD7292
ADC CONVERSION CONTROL
In this example, the ADC sequence register is programmed to
convert on analog input channels VIN0 and VIN1. The AD7292
stays in conversion mode and performs a new ADC conversion
ADC CONVERSION COMMAND
To initiate an ADC conversion on a channel, the conversion
command must be written to the AD7292. The special address
pointer byte, 0x8E, consists of the conversion command register
(Address 0x0E) with the MSB read bit set to 1 to signify an
ADC conversion. When the conversion command is received,
the AD7292 uses the current value of the address pointer to
determine which channel to convert on.
CS
at the end of each read until the
input signal is taken high.
In the examples shown in Figure 40 and Figure 41, an SCLK
delay is inserted following the conversion command to allow
the ADC to perform the conversion before the data is read. If
temperature sensor conversions are requested, a longer delay
is necessary (see the Temperature Sensor section).
In Figure 40, the first byte sets the address pointer with both the
read and write bits cleared and sets Bits[D5:D0] to point to the
selected channel conversion result register. The second byte con-
tains the conversion command with the read bit set. After receiving
the conversion command, the AD7292 stays in conversion mode,
performing a new ADC conversion at the end of each read, until
In some applications, the SPI bus master may not allow the
serial clock to be held low during a read sequence, and it may
CS
be necessary to take
high, as shown in Figure 42. In this
line must remain low while the ADC conversion is
CS
case, the
in progress to prevent possible corruption of the ADC result.
CS
the
(chip select) input signal is taken high.
In the example shown in Figure 42, the address pointer is set
to point to the ADC data register (Address 0x01) with both the
read and write bits cleared. The conversion command is issued
In Figure 41, the address pointer is set to point to the ADC data
register (Address 0x01) with both the read and write bits cleared.
The conversion command is issued, and the contents of the ADC
sequence register specify the sequence of ADC channels for
conversion (see the ADC Sequencer section).
CS
with the read bit set. The
line is taken high after the conver-
CS
sion on VIN0 is completed. The
line is then brought low,
and the ADC data register is pointed to with the read bit set.
The conversion result is clocked out. The conversion command
CS
is reissued before the
line is taken high again, and so on.
CS
1
16
1
16
1
16
8
SCLK
DIN
POINT TO CHANNEL ISSUE CONVERSION
FOR CONVERSION COMMAND
CONVERSION RESULT FOR
SELECTED CHANNEL [D15:D0]
CONVERSION RESULT FOR
SELECTED CHANNEL [D15:D0]
DOUT
CONVERT
SELECTED
CHANNEL
BUSY
CONVERT
SELECTED
CHANNEL
CONVERT
SELECTED
CHANNEL
NOTES
1. CS CANNOT BE TAKEN HIGH UNTIL AFTER A CHANNEL CONVERSION HAS TAKEN PLACE OR WHEN BUSY IS HIGH.
Figure 40. ADC Conversion Command (ADC Sequencer Not Used)
CS
1
16
1
16
1
8
16
8
8
SCLK
DIN
POINT TO ADC
DATA REGISTER
ISSUE CONVERSION
COMMAND
VIN0 RESULT
[D15:D0]
VIN1 RESULT
[D15:D0]
DOUT
NOTE 2
CONVERT
VIN0
CONVERT
VIN1
CONVERT
VIN0
BUSY
NOTES
1. CS CANNOT BE TAKEN HIGH UNTIL AFTER A CHANNEL CONVERSION HAS TAKEN PLACE OR WHEN BUSY IS HIGH.
2. TEMP SENSOR CONVERSIONS TAKE PLACE EACH 1.25ms AFTER THE NEXT CHANNEL CONVERSION.
Figure 41. ADC Conversion Command (ADC Sequencer Used)
Rev. A | Page 35 of 40
AD7292
Data Sheet
CS
1
8
16
1
8
16
24
32
1
8
16
24
SCLK
DIN
POINT TO
ADC DATA
REGISTER
ISSUE
CONVERSION
COMMAND
POINT TO
ADC DATA
REGISTER
POINT TO
ADC DATA
REGISTER
ISSUE
CONVERSION
COMMAND
VIN0 RESULT
[D15:D0]
VIN1 RESULT
[D15:D0]
DOUT
BUSY
CONVERT
VIN0
CONVERT
VIN1
CS
Figure 42. ADC Conversion Command ( Line Taken High After Conversions)
CS
1
16
24
40
1
8
16
8
32
SCLK
DIN
POINT TO ADC
SEQUENCE
REGISTER
POINT TO ADC
DATA
REGISTER
WRITE TO ADC
SEQUENCE REGISTER [D15:D0]
ISSUE CONVERSION
COMMAND
CONVERSION RESULT FOR VIN0
[D15:D0]
DOUT
BUSY
CONVERT
VIN0
CS
1
16
1
16
8
8
SCLK
DIN
CONVERSION RESULT FOR VIN1
[D15:D0]
CONVERSION RESULT FOR VIN2
[D15:D0]
DOUT
BUSY
CONVERT
VIN1
CONVERT
VIN2
Figure 43. Example of Using the ADC Sequencer
After the first ADC conversion is complete, the first result is read
back, which requires 16 serial clocks. The first 10 bits contain
the ADC result, the next four bits are the channel identifier, and
the last two bits are alert bits (see Table 43). On the last falling
edge of the clock, the next ADC conversion begins.
ADC SEQUENCER
The AD7292 provides an ADC sequencer, which enables the
selection of a preprogrammable sequence of channels for con-
version. Figure 43 shows the operation of the ADC sequencer.
To initiate a write to the ADC sequence register (Address 0x03),
point to it in the address pointer register with the write bit set
and the read bit cleared. The next two bytes specify the sequence
of channels that the ADC converts on (see Table 16). The ADC
data register (Address 0x01) is then pointed to and the conver-
sion command is issued. Note that the read bit is set when issuing
the conversion command.
The AD7292 continues converting on the channels specified by
the ADC sequence register. On completing the first sequence of
conversions, the sequencer loops back and begins the sequence
CS
again until
is taken high. The AD7292 is ready to accept a new
CS
address pointer after
is taken low. It is recommended that the
serial clock be kept low during the ADC conversions to ensure
that there is no disturbance of the results.
When the ADC sequencer is used, ADC conversions are trig-
gered based on the contents of the ADC sequence register; the
address pointer reverts to its previous value—in this example,
the ADC data register—allowing the conversion results to be
read back.
Rev. A | Page 36 of 40
Data Sheet
AD7292
DAC OUTPUT CONTROL
To set the DAC output voltage codes, the user must write to the
DAC channel registers (Address 0x30 to Address 0x33). Figure 44
shows an example of how to set the DAC output voltage codes.
LDAC
bit in the DAC channel register is set to 1, the
10-bit DAC value is stored, but the DAC channel output is not
updated. When a write to any DAC channel register occurs with
When the
LDAC
the
the stored values from previous writes.
LDAC
bit cleared, all DAC channel outputs are updated with
1. The DAC buffer enable register (Address 0x0A) is pointed
to with the write bit set.
2. The following two bytes specify which of the four DAC
output buffers are enabled.
3. The DAC channel register (DAC Channel 0 register in
Figure 44) is pointed to with the write bit set.
4. The following two bytes contain the value to be written to
the DAC channel.
When the
bit in the DAC channel register is used to control
the updating of the DAC output, the LDAC pin function should
be disabled, that is, the GPIO3/LDAC pin should be configured
as GPIO3.
The GPIO3/LDAC pin can be used to update the DAC outputs
with the stored values when the pin is configured as an LDAC
pin (see the Digital Output Driver Subregister (Address 0x01)
section and the Digital I/O Function Subregister (Address 0x02)
section). If the GPIO3/LDAC pin is configured as an LDAC
input and is taken high, the DAC output registers are updated;
conversely, if this input pin is held low, the DAC value is stored
but the channel output is not updated.
On completion of this write, the DAC channel output is imme-
LDAC
diately updated to the new value, provided that the
the DAC channel register is not set.
bit in
Note that the process can be reversed—that is, the user can first
write a value to the DAC channel register and then enable the
DAC output buffer.
SIMULTANEOUS UPDATE OF ALL DAC OUTPUTS
LDAC OPERATION
It may be useful to update all four DAC channel registers
simultaneously with the same value but not update the DAC
A write to a DAC channel register (Address 0x30 to Address 0x33)
is addressed to the DAC input register; a read from a DAC channel
register is addressed to the DAC output register (see Figure 45).
LDAC
outputs (
bit is set to 1; LDAC pin is set to 0). Setting
the copy bit (Bit 1) when writing to any DAC channel register
instructs the AD7292 to copy the new DAC value to all the DAC
input registers.
LDAC
The DAC output registers are updated based on the
bit in
the DAC channel register or on the polarity of the GPIO3/LDAC
pin (if the pin is configured as an LDAC pin).
CS
1
24
48
8
32
SCLK
DIN
POINT TO DAC
BUFFER ENABLE
REGISTER
POINT TO DAC
CHANNEL 0
REGISTER
WRITE TO DAC
BUFFER ENABLE REGISTER [D15:D0]
WRITE TO DAC
CHANNEL 0 REGISTER [D15:D0]
Figure 44. Setting the DAC Output Voltage Code
READ
DAC CHANNEL REGISTER (0x30 TO 0x33)
DAC INPUT REGISTER DAC OUTPUT REGISTER
WRITE
SCLK
DAC
VOUTx
LDAC BIT
1
GPIO3/LDAC PIN
1
PROVIDED THE GPIO3/LDAC PIN IS CONFIGUREDAS AN LDAC PIN.
Figure 45. DAC Input and Output Registers
Rev. A | Page 37 of 40
AD7292
Data Sheet
ALERTS AND LIMITS
The advantage of using the hysteresis subregister associated with
each limit subregister is that hysteresis prevents chatter on the
alert bits associated with each ADC channel and also prevents
flicker on the alert output pins. Figure 46 shows the limit check-
ing operation.
ALERT LIMIT MONITORING FEATURES
The alert limits register bank comprises subregisters that set the
high and low alert limits for the eight analog input channels and
the temperature sensor channel (see Table 31). Each subregister
is 16 bits in length; values are 10-bit, left-justified (padded with
0s as the 6 LSBs). On power-up, the low limit and hysteresis sub-
registers contain all 0s, whereas the high limit subregisters are
set to 0xFFC0.
HARDWARE ALERT PINS
Pin 27 and Pin 26 (GPIO0/ALERT0 and GPIO1/ALERT1,
respectively) can be configured as alert pins (see the Digital I/O
Function Subregister (Address 0x02) section). When these pins
are configured as alert pins, they become active when the selected
conversion result exceeds the high or low limit stored in the alert
limits register bank. The polarity of the alert output pins can be
set to active high or active low via the general subregister within
the configuration register bank (see the General Subregister
(Address 0x08) section).
The alert high limit subregisters store the upper limit that
activates an alert. If the conversion result is greater than the value
in the alert high limit subregister, an alert is triggered. The alert
low limit subregister stores the lower limit that activates an alert.
If the conversion result is less than the value in the alert low limit
subregister, an alert is triggered.
If a conversion result exceeds the high or low limit set in the
alert limits subregister, the AD7292 signals an alert in one or
more of the following ways:
If an alert pin signals an alert event and the contents of the alert
flags subregisters are not read before the next conversion is com-
pleted, the contents of the subregister may change if the out-of-
range signal returns to the specified range. In this case, the ALERTx
pin no longer signals the occurrence of an alert event.
Via hardware using the GPIO0/ALERT0 and GPIO1/
ALERT1 pins
Via software using the alert flag bits in the conversion
result registers
Via software using the alert bits in the alert flags register
bank
ALERT FLAG BITS IN THE CONVERSION RESULT
REGISTERS
The TSENSE alert and ADC alert flag bits in the ADC conversion
result and TSENSE conversion result registers indicate whether the
conversion result being read or any other channel result has
violated the limit registers associated with it. If an alert occurs
and the alert bit is set in a conversion result register, the master
can read the alert flags register bank to obtain more information
about where the alert occurred.
Hysteresis
The hysteresis value determines the reset point for the alert pins
and alert flags if a violation of the limits occurs. Each channel has
an associated hysteresis subregister that stores the hysteresis
value, N (see Table 31). If the hysteresis function is enabled, the
conversion result must return to a value of at least N LSB below
the alert high limit subregister value, or N LSB above the alert
low limit subregister value to reset the alert output pins and the
alert flag bits (see Figure 46).
HIGH LIMIT
HIGH LIMIT – HYSTERESIS
INPUT SIGNAL
LOW LIMIT + HYSTERESIS
LOW LIMIT
ALERT SIGNAL
TIME
Figure 46. Limit Checking: Alert High Limit, Alert Low Limit, and Hysteresis
Rev. A | Page 38 of 40
Data Sheet
AD7292
To find out which channel or channels caused the alert flag, the
user must read the ADC alert flags subregister or the TSENSE alert
flags subregister. If the ADC alert flags subregister or the TSENSE
alert flags subregister is accessed with both the read and write bits
of the address pointer set to 1, the stored alert flags can be read
and reset in one operation. A blanket reset can be performed by
writing 0xFFFF to the ADC alert flags subregister, or 0x0003 to
the TSENSE alert flags subregister, thus clearing all alert flags.
ALERT FLAGS REGISTER BANK
The alert flags register bank contains two subregisters: the ADC
alert flags subregister and the TSENSE alert flags subregister. The
ADC alert flags subregister stores alerts for the analog voltage
conversion channels, VIN0 to VIN7. The TSENSE alert flags sub-
register stores alerts for the temperature sensor channel. These
subregisters contain two status bits per channel: one correspond-
ing to the high limit, and the other corresponding to the low
limit (see Table 33 and Table 34). A bit with a status of 1 shows
the channel on which the violation occurred and whether the
violation occurred on the high or low limit.
MINIMUM AND MAXIMUM CONVERSION RESULTS
The read-only minimum/maximum register bank contains the
minimum and maximum conversion values for each of the eight
analog input channels and the temperature sensor channel.
Values are 10-bit, left justified.
If additional alert events occur on any other channels after the
first alert is triggered but before the alert flags subregister is read,
the corresponding bits for the new alert events are also set. For
example, if Bit D14 in the ADC alert flags subregister is set to 1,
the low limit on Channel 7 has been exceeded, whereas if Bit D3
is set to 1, the high limit on Channel 1 has been exceeded.
The minimum and maximum subregisters are cleared when a
value is written to them—that is, they return to their power-up
values. This means that if a subregister is accessed with both the
read and write bits set, the stored minimum or maximum value
can be read and reset in one operation. On power-up, the mini-
mum value subregisters contain 0xFFC0, and the maximum value
subregisters contain 0x0000.
An alert associated with either the alert high limit or alert low
limit subregister is cleared automatically after the monitored
signal is back in range, that is, when the conversion result returns
between the configured high and low limits. The contents of the
alert flags subregister are updated after each conversion.
Rev. A | Page 39 of 40
AD7292
Data Sheet
OUTLINE DIMENSIONS
6.10
6.00 SQ
5.90
0.30
0.23
0.18
PIN 1
INDICATOR
PIN 1
INDICATOR
28
36
1
27
0.50
BSC
4.05
3.90 SQ
3.85
EXPOSED
PAD
19
18
9
10
0.70
0.60
0.40
0.25 MIN
TOP VIEW
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
0.80
0.75
0.70
0.05 MAX
0.02 NOM
SECTION OF THIS DATA SHEET.
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-WJJD.
Figure 47. 36-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
6 mm × 6 mm Body, Very Very Thin Quad
(CP-36-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
Package Description
Package Option
AD7292BCPZ
AD7292BCPZ-RL
EVAL-AD7292SDZ
EVAL-SDP-CB1Z
−40°C to +125°C
−40°C to +125°C
36-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
36-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board
CP-36-3
CP-36-3
System Development Platform
1 Z = RoHS Compliant Part.
©2012–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10660-0-9/14(A)
Rev. A | Page 40 of 40
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