AD7294BSUZ_技术文档

12-Bit Monitor and Control System with Multichannel

ADC, DACs, Temperature Sensor, and Current Sense

Data Sheet

AD7294

FEATURES

APPLICATIONS

12-bit SAR ADC with 3 μs conversion time

4 uncommitted analog inputs

Differential/single-ended

Cellular base stations

GSM, EDGE, UMTS, CDMA, TD-SCDMA, W-CDMA, WiMAX

Point-to-multipoint and other RF transmission systems

12 V, 24 V, 48 V automotive applications

Industrial controls

V_REF, 2 × V_REFinput ranges

2 high-side current sense inputs

5 V to 59.4 V operating range

0.5% max gain error

GENERAL DESCRIPTION

The AD7294 contains all the functions required for general-

purpose monitoring and control of current, voltage, and

temperature integrated into a single-chip solution. The device

includes low voltage ( 200 mV) analog input sense amplifiers

for current monitoring across shunt resistors, temperature sense

inputs, and four uncommitted analog input channels multiplexed

into a SAR analog-to-digital converter (ADC) with a 3 μs conver-

sion time. A high accuracy internal reference is provided to drive

both the digital-to-analog converter (DAC) and ADC. Four 12-bit

DACs provide the outputs for voltage control. The AD7294 also

includes limit registers for alarm functions. The device is designed

on Analog Devices, Inc., high voltage DMOS process for high

voltage compliance, 59.4 V on the current sense inputs, and up

to a 15 V DAC output voltage.

200 mV input range

2 external diode temperature sensor inputs

−55°C to +150°C measurement range

2°C accuracy

Series resistance cancellation

1 internal temperature sensor

2°C accuracy

Built-in monitoring features

Minimum/maximum recorder for each channel

Programmable alert thresholds

Programmable hysteresis

Four 12-bit monotonic 15 V DACs

5 V span, 0 V to 10 V offset

8 μs settling time

10 mA sink and source capability

Power-on resets (POR) to 0 V

Internal 2.5 V reference

2-wire fast mode I²C interface

Temperature range: −40°C to +105°C

Package type: 64-lead TQFP or 56-lead LFCSP

The AD7294 is a highly integrated solution that offers all the

functionality necessary for precise control of the power amplifier

in cellular base station applications. In these types of applications,

the DACs provide 12-bit resolution to control the bias currents

of the power transistors. Thermal diode-based temperature sensors

are incorporated to compensate for temperature effects. The ADC

monitors the high-side current and temperature. All this function-

ality is provided in a 64-lead TQFP or a 56-lead LFCSP operating

over a temperature range of −40°C to +105°C.

Rev. I

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Last Content Update: 11/29/2017

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Multichannel ADC, DACs, Temperature Sensor, and

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Control System with Multichannel ADC, DACs,

Temperature Sensor, and Current Sense

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AD7294

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

TSENSE1, TSENSE2 Result Registers (0x02 and 0x03)........ 29

TSENSEINT Result Register (0x04) ........................................ 29

DAC_A,DAC_B, DAC_C, DAC_D, Registers (0x01 to 0x04)............... 30

Applications....................................................................................... 1

General Description......................................................................... 1

Revision History ............................................................................... 3

Functional Block Diagram .............................................................. 4

Specifications..................................................................................... 5

DAC Specifications....................................................................... 5

ADC Specifications ...................................................................... 6

General Specifications ................................................................. 8

Timing Characteristics ................................................................ 9

Absolute Maximum Ratings.......................................................... 10

Thermal Resistance .................................................................... 10

ESD Caution................................................................................ 10

Pin Configurations and Function Descriptions ......................... 11

Typical Performance Characteristics ........................................... 14

Terminology .................................................................................... 19

DAC Terminology...................................................................... 19

ADC Terminology...................................................................... 19

Theory of Operation ...................................................................... 20

ADC Overview ........................................................................... 20

ADC Transfer Functions ........................................................... 20

Analog Inputs.............................................................................. 20

Current Sensor............................................................................ 22

Analog Comparator Loop ......................................................... 23

Temperature Sensor ................................................................... 24

DAC Operation........................................................................... 25

ADC and DAC Reference.......................................................... 25

V_DRIVEFeature .............................................................................. 26

Register Setting ............................................................................... 27

Address Pointer Register ........................................................... 27

Command Register (0x00)........................................................ 28

Result Register (0x01)................................................................ 28

Alert Status Register A (0x05), Register B (0x06), and

Register C (0x07)........................................................................ 30

Channel Sequence Register (0x08) .......................................... 30

Configuration Register (0x09).................................................. 31

Power-Down Register (0x0A)................................................... 32

DATA_HIGH/DATA_LOWRegisters: 0x0B, 0x0C (V_IN0); 0x0E, 0x0F

(V_IN1); 0x11, 0x12 (V_IN2); 0x14, 0x15 (V_IN3) .............................. 32

Hysteresis Registers: 0x0D (VIN0), 0x10 (VIN1), 0x13

(VIN2), 0x16 (VIN3)................................................................. 32

T_SENSEOffset Registers (0x26 and 0x27)................................... 33

I²C Interface .................................................................................... 34

General I²C Timing.................................................................... 34

Serial Bus Address Byte ............................................................. 35

Interface Protocol....................................................................... 35

Modes of Operation ....................................................................... 39

Command Mode ........................................................................ 39

Autocycle Mode.......................................................................... 40

Alerts and Limits Theory .............................................................. 41

Alert_Flag Bit.............................................................................. 41

Alert Status Registers ................................................................. 41

Data_HIGHand Data_LOWMonitoring Features............................ 41

Hysteresis..................................................................................... 42

Applications Information.............................................................. 43

Base Station Power Amplifier Monitor and Control............. 43

Gain Control of Power Amplifier............................................. 44

Layout and Configuration............................................................. 45

Power Supply Bypassing and Grounding................................ 45

Outline Dimensions....................................................................... 46

Ordering Guide .......................................................................... 46

Rev. I | Page 2 of 47

Data Sheet

AD7294

REVISION HISTORY

2/16—Rev. H to Rev. I

Changes to Table 2 ............................................................................6

Changes to Table 6 ..........................................................................10

Added Figure 4 ................................................................................11

Changes to Table 7 ..........................................................................12

Changes to Command Register Section ......................................28

Changes to Autocycle Mode Section............................................40

Updated Outline Dimensions........................................................47

Changes to Ordering Guide...........................................................48

Changed CP-56-1 to CP-56-11.................................... Throughout

Changes to Figure 4.........................................................................11

Updated Outline Dimensions........................................................46

Changes to Ordering Guide...........................................................46

1/12—Rev. G to Rev. H

Changes to Table 2 ............................................................................6

11/11—Rev. F to Rev. G

7/09—Rev. B to Rev. C

Change to DAC Output Characteristics Parameter of

Table 1 .................................................................................................5

Deleted DAC HIGH-Z Pin Leakage from Table 3........................8

Change to Figure 4 ..........................................................................11

Changes to Table 7 ..........................................................................12

Deleted Figure 47; Renumbered Sequentially .............................25

Deleted High Impedance Input Pin Section................................26

Changes to Table 4 Endnotes...........................................................8

4/09—Rev. A to Rev. B

Changes to Table 2 ............................................................................6

Changes to Table 3 ............................................................................7

Changes to Table 23 ........................................................................29

3/09—Rev. 0 to Rev. A

11/10—Rev. E to Rev. F

Change to Table 2, Dynamic Performance, Spurious-Free

Dynamic Range (SFDR)...................................................................6

Changes to Configuration Register (0x09) Section....................29

Changes to Table 23 and Table 24.................................................29

Changes to Table 27 ........................................................................30

Changes to Autocycle Mode Section............................................38

Change to Alert Status Registers Section.....................................39

Changes to DATA_HIGHand DATA_LOWMonitoring Features

Section ..............................................................................................39

10/10—Rev. D to Rev. E

Change to Reflow Temperature, Table 5 ......................................10

5/10—Rev. C to Rev. D

Added 56-Lead LFCSP ......................................................Universal

Change to Features Section and General Description Section ...1

1/08—Revision 0: Initial Version

Rev. I | Page 3 of 47

AD7294

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

R

SENSE

TO LOAD

REF

/

AV

DD

AGND DAC OUT

OUT

RS2(–) REF ADC

OUT

V

(1 TO 2)

RS1(+) RS1(–) RS2(+)

REF DAC (1 TO 6) (1 TO 7) V+ AB/CD

PP

IN

2.5V

REF

HIGH SIDE

CURRENT

SENSE

HIGH SIDE

CURRENT

SENSE

100kΩ 200kΩ

12-BIT

DAC

I

2

SENSE

OVERRANGE

V

A

OUT

V

REF

10.41

I

1

SENSE

OVERRANGE

100kΩ 200kΩ

OFFSET IN A

V

0

1

2

3

IN

100kΩ 200kΩ

12-BIT

DAC

12-BIT

ADC

MUX

V

B

OUT

D1+

D2+

LIMIT

REGISTERS

100kΩ 200kΩ

OFFSET IN B

100kΩ 200kΩ

12-BIT

DAC

T1

T2

TEMP

SENSOR

D2–

D1–

V

C

OUT

100kΩ 200kΩ

OFFSET IN C

100kΩ 200kΩ

12-BIT

DAC

CONTROL LOGIC

AD7294

V

D

OUT

2

I C INTERFACE

PROTOCOL

100kΩ 200kΩ

OFFSET IN D

DGND

(1 TO 2)

SDA

SCL AS2 AS1

DV

DD

DCAP ALERT/

BUSY

AS0

Figure 1.

Rev. I | Page 4 of 47

Data Sheet

AD7294

SPECIFICATIONS

DAC SPECIFICATIONS

AV_DD= DV_DD= 4.5 V to 5.5 V, AGND = DGND = 0 V, internal 2.5 V reference; V_DRIVE= 2.7 V to 5.5 V; T_A=−40°C to +105°C, unless

otherwise noted. DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V, OFFSET IN x is floating, therefore, the DAC output

span = 0 V to 5 V.

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

ACCURACY

Resolution

12

Bits

LSB

mV

Relative Accuracy (INL)

Differential Nonlinearity (DNL)

Zero-Scale Error

Full-Scale Error of DAC and

Output Amplifier

1

0.3

2.5

3

1

Guaranteed monotonic

DAC OUTV+ = 5.0 V

8

15.5¹

Full-Scale Error of DAC

Offset Error

2

5

mV

ppm/°C

DAC OUTV+ = 15.0 V

Measured in the linear region, T_A= −40°C to +105°C

Measured in the linear region, T_A= 25°C

8.575

2

Offset Error Temperature

Coefficient

Gain Error

0.025

0.155

% FSR

Gain Temperature Coefficient

5

ppm/°C

DAC OUTPUT CHARACTERISTICS

Output Voltage Span

Output Voltage Offset

0

2 × V_REF

10

V

0 V to 5 V for a 2.5 V reference

The output voltage span can be positioned in the 0 V to

15 V range; if the OFFSET IN x is left floating, the offset

pin = 2/3 × V_REF, giving an output of 0 V to 2 × V_REF

Offset Input Pin Range

DC Input Impedance²

0

5

V_OUT= 3 V_OFFSET− 2 × V_REF+ V_DAC

100 kΩ to V_REF, and 200 kΩ to AGND, see Figure 48

1/4 to 3/4 change within 1/2 LSB, measured from last

SCL edge

75

8

kΩ

µs

Output Voltage Settling Time²

Slew Rate²

Short-Circuit Current²

Load Current²

Capacitive Load Stability²

DC Output Impedance²

REFERENCE

1.1

40

10

V/µs

mA

nF

Full-scale current shorted to ground

Source and/or sink within 200 mV of supply

R_L= ∞

10

1

Ω

Reference Output Voltage

Reference Input Voltage Range

Input Current

Input Capacitance²

V_REFOutput Impedance²

2.49

0

2.5

2.51

AV_DD− 2

125

V

µA

pF

0.4% maximum at 25°C, AV_DD= DV_DD= 4.5 V to 5.5 V

V_REF= 2.5 V

100

20

25

Ω

Reference Temperature

Coefficient

10

25

ppm/°C

¹This value indicates that the DAC output amplifiers can output voltages 15.5 mV below the DAC OUTV+ supply. If higher DAC OUTV+ supply voltages are used, the

full-scale error of the DAC is typically 2 mV with no load.

²Samples are tested during initial release to ensure compliance; they are not subject to production testing.

Rev. I | Page 5 of 47

AD7294

Data Sheet

ADC SPECIFICATIONS

AV_DD= DV_DD= 4.5 V to 5.5 V, AGND = DGND = 0 V, V _REF= 2.5 V internal or external; V_DRIVE= 2.7 V to 5.5 V; V_PP= AV_DDto 59.4 V;

T_A= −40°C to +105°C, unless otherwise noted.

Table 2.

Parameter

Min

Typ Max

Unit

Test Conditions/Comments

DC ACCURACY

Resolution

12

Bits

LSB

Integral Nonlinearity (INL)¹

0.5

1

1.5

0.99

Differential mode

Single-ended or pseudo differential mode

Differential, single-ended, and pseudo differential

modes

Differential Nonlinearity (DNL)¹

Single-Ended Mode

Offset Error

Offset Error Match

Gain Error

1

7

LSB

0.4

0.5

0.4

2.5

Gain Error Match

Differential Mode

Positive Gain Error

Positive Gain Error Match

Zero Code Error

Zero Code Error Match

Negative Gain Error

Negative Gain Error Match

CONVERSION RATE

Conversion Time²

Autocycle Update Rate²

Throughput Rate

1

0.5

3

0.5

1

0.5

LSB

3

μs

kSPS

50

22.22

f_SCL= 400 kHz

ANALOG INPUT³

Single-Ended Input Range

0

V_REF

2 × V_REF

V_REF

2 × V_REF

+V_REF

+2 × V_REF

V

0 V to V_REFmode

0 V to 2 × V_REFmode

0 V to V_REFmode

0 V to 2 × V_REFmode

0 V to V_REFmode

0 V to 2 × V_REFmode

4

Pseudo Differential Input Range: V_IN+−V_IN−

Fully Differential Input Range: V_IN+− V_IN−

−V_REF

−2 × V_REF

Input Capacitance²

30

pF

DC Input Leakage Current

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)¹

1

µA

73

72

dB

f_IN= 10 kHz sine wave; differential mode

f_IN= 10 kHz sine wave; single-ended and pseudo

differential modes

Signal-to-Noise + Distortion (SINAD) Ratio¹

Total Harmonic Distortion (THD)¹

71.5

72.5

dB

f_IN= 10 kHz sine wave; differential mode

f_IN= 10 kHz sine wave; single-ended and pseudo

differential modes

f_IN= 10 kHz sine wave; differential mode

f_IN= 10 kHz sine wave; single-ended and pseudo

differential modes

−81

−79

dB

Spurious-Free Dynamic Range (SFDR)¹

Channel-to-Channel Isolation²

−81

−79

dB

f_IN= 10 kHz sine wave; differential mode

f_IN= 10 kHz sine wave; single-ended and pseudo

differential modes

−90

f_IN= 10 kHz to 40 kHz

Rev. I | Page 6 of 47

Data Sheet

AD7294

Parameter

Min

Typ Max

Unit

Test Conditions/Comments

TEMPERATURE SENSOR—INTERNAL

Operating Range

Accuracy

−40

+105

2

2.5

°C

ms

Internal temperature sensor, T_A= −30°C to +90°C

Internal temperature sensor, T_A= −40°C to +105°C

LSB size

Resolution

Update Rate

0.25

5

TEMPERATURE SENSOR—EXTERNAL

Operating Range

Accuracy

External transistor is 2N3906

Limited by external diode

T_A= T_DIODE= −40°C to +105°C

LSB size

−55

+150

2

°C

µA

Ω

Resolution

0.25

8

32

Low Level Output Current Source²

Medium Level Output Current Source²

High Level Output Current Source²

128

100

Maximum Series Resistance (R_S) for

External Diode²

Maximum Parallel Capacitance (C_P) for

External Diode²

For < 0.5°C additional error, C_P= 0, see Figure 31

R_S= 0, see Figure 30

1

nF

CURRENT SENSE

V_PPSupply Range

Gain

V_PP= AV_DDto 59.4 V

AV_DD

59.4

V

12.4375 12.5 12.5625

Gain of 12.5 gives a gain error = 0.5% maximum;

delivers 200 mV range with +2.5 V reference

RS(+)/RS(−) Input Bias Current

CMRR/PSRR²

Offset Error

25

80

50

32

340

µA

dB

µV

Inputs shorted to V_PP

Offset Drift

Amplifier Peak-To-Peak Noise²

1

400

µV/°C

µV

Referred to input

V_PP= 59.4 V

V_PPSupply Current

0.18 0.25

mA

REFERENCE

Reference Output Voltage

Reference Input Voltage Range

2.49

0.1

1

2.51

4.1

AV_DD− 2

V

0.2% maximum at 25°C only

For four uncommitted ADCs

For current sense

DC Leakage Current

2

μA

V_REFOutput Impedance²

Input Capacitance²

Reference Temperature Coefficient

25

20

10

Ω

pF

ppm/°C

25

¹See the Terminology section for more details.

²Sampled during initial release to ensure compliance, not subject to production testing.

³V_IN+or V_IN−must remain within GND/V_DD

⁴V_IN−= 0 V for specified performance. For full input range on V_IN−, see Figure 40.

.

Rev. I | Page 7 of 47

AD7294

Data Sheet

GENERAL SPECIFICATIONS

AV_DD= DV_DD= 4.5 V to 5.5 V, AGND = DGND = 0 V, V _REF= 2.5 V internal or external; V_DRIVE= 2.7 V to 5.5 V; V_PP= AV_DDto 59.4 V;

DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V;

T_A= −40°C to +105°C, unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUTS

Input High Voltage, V_IH

Input Low Voltage, V_IL

Input Leakage Current, I_IN

Input Hysteresis, V_HYST

Input Capacitance, C_IN

Glitch Rejection

0.7 V_DRIVE

V

µA

V

pF

ns

SDA, SCL only

0.3 V_DRIVE

1

0.05 V_DRIVE

8

50

Input filtering suppresses noise spikes of less

than 50 ns

I²C Address Pins Maximum External

Capacitance if Floating

30

pF

Tristate input

LOGIC OUTPUTS

SDA, ALERT

SDA and ALERT/BUSY are open-drain outputs

Output Low Voltage, V_OL

0.4

0.6

1

V

µA

pF

I_SINK= 3 mA

I_SINK= 6 mA

Floating-State Leakage Current

Floating-State Output Capacitance

8

I_SENSEOVERRANGE

Output High Voltage, V_OH

Output Low Voltage, V_OL

Overrange Setpoint

POWER REQUIREMENTS

V_PP

I_SENSEOVERRANGE is a push-pull output

I_SOURCE= 200 µA for push-pull outputs

I_SINK= 200 µA for push-pull outputs

V_DRIVE− 0.2

0.2

V

mV

V_FS

V_FS× 1.2

V_FS= V_REFADC/12.5

AV_DD

4.5

59.4

5.5

V

AV_DD

V(+)

DV_DD

4.5

16.5

5.5

V

Tie DV_DDto AV_DD

V_DRIVE

2.7

5.5

V

I_DDDynamic

DAC OUTV+ x, I_DD

5.3

0.6

6.5

1.2

mA

AV_DD+ DV_DD+ V_DRIVE, DAC outputs unloaded

At midscale output voltage, DAC outputs

unloaded

Power Dissipation

Power-Down

I_DD

70

105

mW

0.5

1

35

1

16.5

60

µA

mW

For each AV_DDand V_DRIVE

DI_DD

DAC OUTV+ x, I_DD

Power Dissipation

2.5

Rev. I | Page 8 of 47

Data Sheet

AD7294

TIMING CHARACTERISTICS

I²C Serial Interface

AV_DD= DV_DD= 4.5 V to 5.5 V, AGND = DGND = 0 V, V_REF= 2.5 V internal or external; V_DRIVE= 2.7 V to 5.5 V; V_PP= AV_DDto 59.4 V;

DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; T_A=

−40°C to +105°C, unless otherwise noted.

Table 4.

Parameter¹

Limit at T_MIN, T_MAX

Unit

Description

f_SCL

t₁

t₂

t₃

t₄

400

2.5

0.6

1.3

0.6

100

0.9

0

0.6

1.3

300

0

kHz max

μs min

ns min

μs max

μs min

ns max

ns min

ns max

ns min

ns max

ns min

pF max

SCL clock frequency

SCL cycle time

t_HIGH, SCL high time

t_LOW, SCL low time

t_HD,STA, start/repeated start condition hold time

t_SU,DAT, data setup time

t_HD,DAT, data hold time

t₅

t₆

t_HD,DAT, data hold time

t₇

t₈

t₉

t₁₀

t_SU,STA, setup time for repeated start

t_SU,STO, stop condition setup time

t_BUF, bus free time between a stop and a start condition

t_R, rise time of SCL and SDA when receiving

t_R, rise time of SCL and SDA when receiving (CMOS compatible)

t_F, fall time of SDA when transmitting

t_F, fall time of SDA when receiving (CMOS compatible)

t_F, fall time of SCL and SDA when receiving

t_F, fall time of SCL and SDA when transmitting

Capacitive load for each bus line

t₁₁

300

0

300

20 + 0.1C_b

400

2

C_b

¹See Figure 2.

²C_bis the total capacitance in pF of one bus line. t_Rand t_Fare measured between 0.3 DV_DDand 0.7 DV_DD

.

Timing and Circuit Diagrams

SDA

t₉

t₃

t₁₀

t₁₁

t₄

SCL

t₄

t₆

t₂

t₁

t₈

t₅

t₇

START

CONDITION

REPEATED

START

CONDITION

STOP

CONDITION

Figure 2. I²C-Compatible Serial Interface Timing Diagram

200µA

I

OL

V

(MIN) OR

(MAX)

OH

OL

TO OUTPUT PIN

C

L

50pF

I

200µA

OH

Figure 3. Load Circuit for Digital Output

Rev. I | Page 9 of 47

AD7294

Data Sheet

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C, unless otherwise noted.¹

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Table 5.

Parameter

Rating

V_PPx to AGND

AV_DDx to AGND

DAC OUTV+ AB to AGND

DAC OUTV+ CD to AGND

DV_DDto DGND

−0.3 V to +70 V

−0.3 V to +7 V

−0.3 V to +17 V

−0.3 V to +7 V

To conform with IPC 2221 industrial standards, it is advisable

to use conformal coating on the high voltage pins.

V_DRIVEto OPGND

Digital Inputs to OPGND

SDA/SCL to OPGND

Digital Outputs to OPGND

RS(+)/RS(−) to V_PPx

REF_OUT/REF_INADC to AGND

REF_OUT/REF_INDAC to AGND

OPGND to AGND

−0.3 V to V_DRIVE+ 0.3 V

−0.3 V to +7 V

THERMAL RESISTANCE

−0.3 V to V_DRIVE+ 0.3 V

V_PP− 0.3 V to V_PP+ 0.3 V

−0.3 V to AV_DD+ 0.3 V

−0.3 V to +0.3 V

Table 6. Thermal Resistance

Package Type

64-Lead TQFP

56-Lead LFCSP

θ_JA

54

21

θ_JC

16

2

Unit

°C/W

ESD CAUTION

OPGND to DGND

−0.3 V to +0.3 V

AGND to DGND

−0.3 V to +0.3 V

V_OUTx to AGND

−0.3 V to DAC OUTV(+) + 0.3 V

−0.3 V to AV_DD+ 0.3 V

Analog Inputs to AGND

Operating Temperature Range

B Version

Storage Temperature Range

Junction Temperature (T_JMax)

ESD Human Body Model

−40°C to +105°C

−65°C to +150°C

150°C

1 kV

Reflow Soldering Peak

Temperature

260°C

¹Transient currents of up to 100 mA do not cause SCR latch-up.

Rev. I | Page 10 of 47

Data Sheet

AD7294

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

NC

RS2(–)

RS2(+)

NC

DGND

PIN 1

INDICATOR

I

1 OVERRANGE

2 OVERRANGE

3

SENSE

I

4

SENSE

5

AV

1

DV

DD

6

AGND1

AGND2

DGND

7

V

DRIVE

AD7294

8

OPGND

SCL

AV

2

TQFP

DD

TOP VIEW

(Not to Scale)

9

D2–

10

11

12

13

14

15

16

SDA

D2+

D1+

AS0

AS1

D1–

AS2

AGND3

ALERT/BUSY

AGND5

NC

AV

3

DD

REF

/REF DAC

IN

OUT

NC

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

NC = NO CONNECT

Figure 4. TQFP Pin Configuration

RS2(–)

RS2(+)

NC

1

2

3

4

5

6

7

8

9

42 DGND

I

1 OVERRANGE

2 OVERRANGE

41

40

39

SENSE

DV

AV

1

DD

38 DGND

AGND1

AGND2

V

37

DRIVE

AD7294

AV

2

36 OPGND

35 SCL

DD

TOP VIEW

(Not to Scale)

D2(–)

D2(+)

34

33

SDA

AS0

10

D1(+)

32 AS1

11

12

13

D1(–)

31 AS2

AGND3

30 ALERT/BUSY

29 AGND5

AV

3

DD

REF

/REF DAC 14

IN

OUT

NOTES

1. NC = NO CONNECT.

2. CONNECT THE EXPOSED PAD TO THE GROUND PLANE OF THE PCB USING MULTIPLE VIAS.

Figure 5. LFCSP Pin Configuration

Rev. I | Page 11 of 47

AD7294

Data Sheet

Table 7. Pin Function Descriptions

TQFP Pin No.

LFCSP Pin No.

Mnemonic

RS2(−), RS1(−)

RS2(+), RS1(+)

NC

Description

2, 61

3, 60

1, 4, 16, 17, 32,

33, 59, 64

1, 54

2, 53

3, 52

Connection for External Shunt Resistor.

No Connection. Do not connect these pins.

5, 8, 14, 25, 56, 57 4, 7, 13, 22, 50

AV_DD1 to AV_DD

for TQFP; AV_DD

to AV_DD4 for

LFCSP

6

1

Analog Supply Pins. The operating range is 4.5 V to 5.5 V. These pins provide

the supply voltage for all the analog circuitry on the AD7294. Connect the

AV_DDand DV_DDpins together to ensure that all supply pins are at the same

potential. This supply should be decoupled to AGND with one 10 µF tantalum

capacitor and a 0.1 µF ceramic capacitor for each AV_DDpin.

6, 7, 13, 24, 34,

55, 58

5, 6 12, 21, 29, 49, AGND1 to

Analog Ground. Ground reference point for all analog circuitry on the AD7294.

Refer all analog input signals and any external reference signal to this AGND

voltage. Connect all seven of these AGND pins to the AGND plane of the

system. Note that AGND5 is a DAC ground reference point and should be used

as a star ground for circuitry being driven by the DAC outputs. Ideally, the

AGND and DGND voltages should be at the same potential and must not be

more than 0.3 V apart, even on a transient basis.

51

AGND7

9, 12

10, 11

15

8, 11

9, 10

14

D2(−), D1(−)

D2(+), D1(+)

Temperature Sensor Analog Input. These pins are connected to the external

temperature sensing transistor. See Figure 46 and Figure 47.

Temperature Sensor Analog Input. These pins are connected to the external

temperature sensing transistor. See Figure 46 and Figure 47.

REF_OUT/REF_INDAC DAC Reference Output/Input Pin. The REF_OUT/REF_INDAC pin is common to all

four DAC channels. On power-up, the default configuration of this pin is

external reference (REF_IN). Enable the internal reference by writing to the

power-down register; see Table 27. Decoupling capacitors (220 nF

recommended) are connected to this pin to decouple the reference buffer.

Provided the output is buffered, the on-chip reference can be taken from this

pin and applied externally to the rest of a system. A maximum external

reference voltage of AV_DD− 2 V can be supplied to the REF_OUTportion of the

REF_OUT/REF_INDAC pin.

18, 23, 26, 31

19, 22, 27, 30

20, 29

15, 20 23,28

16, 19, 24, 27

17, 26

OFFSET IN A to

OFFSET IN D

DAC Analog Offset Input Pins. These pins set the desired output range for each

DAC channel. The DACs have an output voltage span of 5 V, which can be

shifted from 0 V to 5 V to a maximum output voltage of 10 V to 15 V by

supplying an offset voltage to these pins. These pins can be left floating, in

which case decouple them to AGND with a 100 nF capacitor.

Buffered Analog DAC Outputs for Channel A to Channel D. Each DAC analog

output is driven from an output amplifier that can be offset using the OFFSET

IN x pin. The DAC has a maximum output voltage span of 5 V that can be level

shifted to a maximum output voltage level of 15 V. Each output is capable of

sourcing and sinking 10 mA and driving a 10 nF load.

V_OUTA to V_OUT

D

DAC OUT GND

AB, DAC OUT

GND CD

Analog Ground. Analog ground pins for the DAC output amplifiers on V_OUT

and V_OUTB, and V_OUTC and V_OUTD, respectively.

A

21, 28

35

18, 25

30

DAC OUTV+ AB,

DAC OUTV+ CD

ALERT/BUSY

Analog Supply. Analog supply pins for the DAC output amplifiers on V_OUTA and

V_OUTB, and V_OUTC and V_OUTD, respectively. The operating range is 4.5 V to 16.5 V.

Digital Output. Selectable as an alert or busy output function in the

configuration register. This is an open-drain output. An external pull-up

resistor is required.

When configured as an alert, this pin acts as an out-of-range indicator and

becomes active when the conversion result violates the DATA_HIGHor DATA_LOW

register values. See the Alert Status Registers section.

When configured as a busy output, this pin becomes active when a conversion

is in progress.

38, 37, 36

39

33, 32, 31

34

AS0, AS1, AS2

SDA

Digital Logic Input. Together, the logic state of these inputs selects a unique

I²C address for the AD7294. See Table 34 for details.

Digital Input/Output. Serial bus bidirectional data; external pull-up resistor

required.

Rev. I | Page 12 of 47

Data Sheet

AD7294

TQFP Pin No.

LFCSP Pin No.

Mnemonic

Description

40

35

SCL

Serial I²C Bus Clock. The data transfer rate in I²C mode is compatible with both

100 kHz and 400 kHz operating modes. Open-drain input; external pull-up

resistor required.

41

42

36

37

OPGND

V_DRIVE

Dedicated Ground Pin for I²C Interface.

Logic Power Supply. The voltage supplied at this pin determines at what

voltage the interface operates. Decouple this pin to DGND. The voltage range

on this pin is 2.7 V to 5.5 V and may be different to the voltage level at AV_DD

and DV_DD, but should never exceed either by more than 0.3 V. To set the input

and output thresholds, connect this pin to the supply to which the I²C bus is

pulled.

43, 47, 48

44

38, 42

39

DGND

DV_DD

Digital Ground. This pin is the ground for all digital circuitry.

Logic Power Supply. The operating range is 4.5 V to 5.5 V. These pins provide

the supply voltage for all the digital circuitry on the AD7294. Connect the AV_DD

and DV_DDpins together to ensure that all supply pins are at the same potential.

Decouple this supply to DGND with a10 µF tantalum capacitor and a 0.1 µF

ceramic capacitor.

46, 45

41, 40

I_SENSE

OVERRANGE,

I_SENSE

1

Fault Comparator Outputs. These pins connect to the high-side current sense

amplifiers.

2

OVERRANGE

49, 50, 51, 52

53

43, 44, 45, 46

47

V_IN3 to V_IN0

Uncommitted ADC Analog Inputs. These pins are programmable as four

single-ended channels or two true differential analog input channel pairs. See

Table 1 and Table 13 for more details.

REF_OUT/REF_INADC ADC Reference Input/Output Pin. The REF_OUT/REF_INADC pin provides the

reference source for the ADC. Upon power-up, the default configuration of this

pin is external reference (REF_IN). Enable the internal reference by writing to the

power-down register; see Table 27. Connect decoupling capacitors (220 nF

recommended) to this pin to decouple the reference buffer. Provided the

output is buffered, the on-chip reference can be taken from this pin and

applied externally to the rest of a system. A maximum external reference

voltage of 2.5 V can be supplied to the REF_OUTportion of the REF_OUT/REF_IN

ADC pin.

54

48

DCAP

External Decoupling Capacitor Input for Internal Temperature Sensor.

Decouple this pin to AGND using a 0.1 μF capacitor. In normal operation, the

voltage is typically 3.7 V.

62, 63

N/A¹

55, 56

0

V_PP1, V_PP2

EPAD

Current Sensor Supply Pins. Power supply pins for the high-side current sense

amplifiers. Operating range is from AV_DDto 59.4 V. Decouple this supply to

AGND. See the Current Sense Filtering section.

The exposed pad is located on the underside of the package. Connect the

exposed pad to the ground plane of the PCB using multiple vias.

¹N/A means not applicable.

Rev. I | Page 13 of 47

AD7294

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

20

0

8192 POINT FFT

AV

= DV = 5V

AV

= DV = 5V

DD

0

–20

V

= 5V, V

RANGE

V

= 5V, 2V

RANGE

DRIVE

SAMPLE

REF

= 22.22kSPS

= 400kHz

DRIVE

REF

= 22.22kSPS

= 10kHz, F = 400kHz

SCLK

F

SAMPLE

= 10kHz, F

IN

SCLK

IN

–20

–40

–60

–80

–100

–120

SINGLE ENDED

DIFFERENTIAL

SNR = 73dB, THD = –82dB

SNR = 71dB, THD = –82dB

–40

–60

–80

–100

–120

0

2000

4000

6000

8000

10000

0

2000

4000

6000

8000

10000

FREQUENCY (kHz)

Figure 6. Signal-to-Noise Ratio Single-Ended, V_REFRange

Figure 9. Signal-to-Noise Ratio Differential, 2 × V_REFRange

20

1.0

0.8

T

= 25°C

8192 POINT FFT

A

V

= 5V, V RANGE

AV

V

= DV = 5V

DRIVE

= 2.5V

REF

DD

0

–20

= 5V, 2V

RANGE

REF

= 5V

DRIVE

REF

F

= 22.22kSPS

0.6

DD

SAMPLE

SINGLE-ENDED

= 10kHz, F

= 400kHz

IN

SCLK

SINGLE ENDED

SNR = 72dB, THD = –80dB

0.4

0.2

–40

0

–60

–0.2

–0.4

–0.6

–0.8

–1.0

–80

–100

–120

256

768

1280

1792

2048

CODE

2304

2816

3328

3840

4096

0

2000

4000

6000

8000

10000

0

512 1024

1536

2560

3072

3584

FREQUENCY (kHz)

Figure 10. ADC INL Single-Ended, V_REFRange

Figure 7. Signal-to-Noise Ratio Single-Ended, 2 × V_REFRange

20

1.0

0.8

T

= 25°C

8192 POINT FFT

A

V

= 5V, V RANGE

REF

AV

= DV = 5V

DRIVE

= 2.5V

DD

0

–20

V

F

= 5V, V

RANGE

= 22.22kSPS

REF

= 5V

DRIVE

REF

DD

0.6

SAMPLE

SINGLE-ENDED

F

= 10kHz, F

= 400kHz

IN

SCLK

DIFFERENTIAL

SNR = 72dB, THD = –86dB

0.4

0.2

–40

0

–60

–0.2

–0.4

–0.6

–0.8

–1.0

–80

–100

–120

256

768

1280

1792

2304

2816

3328

3840

4096

0

2000

4000

6000

8000

10000

0

512 1024

1536

2048

2560

3072

3584

FREQUENCY (kHz)

CODE

Figure 8. Signal-to-Noise Ratio Differential, V_REFRange

Figure 11. ADC DNL Single-Ended, V_REFRange

Rev. I | Page 14 of 47

Data Sheet

AD7294

1.0

0.8

T = 25°C

A

T

= 25°C

A

V

= 5V, V RANGE

V

= 5V, 2V

RANGE

DRIVE

= 5V

REF

0.8

DRIVE

= 2.5V

REF

= 5V

REF

= 5V

DD

0.6

DD

DIFFERENTIAL

SINGLE-ENDED

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

256

768

1280

1792

2304

2816

3328

3840

256

768

1280

1792

2048

CODE

2304

2816

3328

3840

4096

0

512

1024

1536

2048

2560

3072

3584

4096

0

512 1024

1536

2560

3072

3584

CODE

Figure 15. ADC INL Differential, V_REFRange

Figure 12. ADC INL Single-Ended, 2 × V_REFRange

1.0

0.8

1.0

0.8

T

= 25°C

T

= 25°C

A

T

A

= 25°C

A

V

= 5V, 2V RANGE

2.5V

REF

V

= 5V, 2V RANGE

V

DRIVE

=

DRIVE

= 5V

REF

V

= 2.5V

REF= 5V

DD

V

REF

= 5V

V = 5V

DD

FFERENTIAL

DI

DD

0.6

DIFFERENTIAL

SINGLE-ENDED

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

256

768

1280

1792

2304

2816

3328

3840

4096

256

768

1280

1792

2304

2816

3328

3840

4096

0

512 1024

1536

2048

2560

3072

3584

0

512 1024

1536

2048

2560

3072

3584

CODE

Figure 16. ADC DNL Differential, 2 × V_REFRange

Figure 13. ADC DNL Single-Ended, 2 × V_REFRange

1.0

0.8

1.0

0.8

T

= 25°C

T

V

= 25°C

A

V

= 5V, 2V RANGE

= 5V, V RANGE

DRIVE

= 5V

REF

DRIVE

= 2.5V

REF

= 5V

REF

= 5V

DD

0.6

DIFFERENTIAL

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–0.2

–0.4

–0.6

–0.8

–1.0

256

768

1280

1792

2304

2816

3328

3840

4096

256

768

1280

1792

2304

2816

3328

3840

4096

0

512 1024

1536

2048

2560

3072

3584

0

512 1024

1536

2048

2560

3072

3584

CODE

Figure 14. ADC INL Differential, V_REFRange

Figure 17. ADC DNL Differential, 2 × V_REFRange

Rev. I | Page 15 of 47

AD7294

Data Sheet

1.5

0.6

0.4

AV

= DV = 5V

DD

= 5V, INTERNAL REF,

DD

V

DRIVE

1.0

OFFSET IN A/B/C/D = FLOATING

MAX INL

0.5

0.2

0

T

= 25°C

A

V

= 5V, V

= 5V

RANGE

DRIVE

REF

–0.5

–1.0

–1.5

–2.0

0

DD

SINGLE-ENDED

2

I C MODE 400kHz

–0.2

–0.4

–0.6

MIN INL

–2.5

0

1

2

3

4

5

6

256

768

1280

1792

2048

CODE

2304

2816

3328

3840

4096

0

512 1024

1536

2560

3072

3584

REFERENCE VOLTAGE (V)

Figure 18. ADC INL vs. Reference Voltage

Figure 21. DAC DNL

0.8

0.6

0.4

0.2

0

20

15

MAX DNL

10

5

T

V

= 25°C

A

= 5V, V

RANGE

DRIVE

REF

0

= 5V

DD

SINGLE-ENDED

I C MODE 400kHz

2

–5

–0.2

–0.4

MIN DNL

–10

–15

–20

–0.6

0

1

2

3

4

5

6

0

1

2

3

4

5

6

7

8

9

10

REFERENCE VOLTAGE (V)

TIME (s)

Figure 19. ADC DNL vs. Reference Voltage

Figure 22. 0.1 Hz to 10 Hz DAC Output Noise (Code 800)

2.0

1.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

AV

V

= DV = 5V

DD

64pF

1nF

10nF

DD

= 5V, INTERNAL REF,

DRIVE

OFFSET IN A/B/C/D = FLOATING

1.0

0.5

0

–0.5

–1.0

–1.5

–2.0

256

768

1280

1792

2048

CODE

2304

2816

3328

3840

4096

–5 –4 –3 –2 –1

0

1

2

3

4

5

6

7

8

9

10

0

512 1024

1536

2560

3072

3584

TIME (µs)

Figure 20. DAC INL

Figure 23. Settling Time for a ¼ to ¾ Output Voltage Step

Rev. I | Page 16 of 47

Data Sheet

AD7294

0.8

100

80

64pF

1nF

10nF

DAC A

DAC B

DAC C

DAC D

0.6

60

0.4

40

0.2

20

0

–20

–40

–60

–80

–100

–0.2

–0.4

–0.6

–0.8

AV = DV = 5V

DD DD

OFFSET IN = FLOATING

DAC OUT V = 15V

V

= 5V, INTERNAL REF

DRIVE

10

0

2

4

6

8

10

12

14

16

18

20

–50 –40 –30 –20 –10

0

20

30

40

50

TIME (µs)

LOAD CURRENT (mA)

Figure 27. DAC Output Voltage vs. Load Current, Input Code = x800

Figure 24. Zoomed in Settling for a ¼ to ¾ Output Voltage Step

1.0

55

50

45

40

35

30

25

20

DAC A

DAC B

DAC C

DAC D

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

AV = DV = 5V

DD DD

OFFSET IN = FLOATING

DAC OUT V = 15V

V

= 5V, INTERNAL REF

DRIVE

25

–5

0

5

10

15

20

0

5

10

15

20

30

35

40

TIME (Seconds)

SINK CURRENT (mA)

Figure 25. DAC Sinking Current at Input Code = x000, (V_OUT= 0 V)

Figure 28. Response of the AD7294 to Thermal Shock Using 2N3906

(2N3906 Placed in a Stirred Oil Bath)

0

55

DAC A

DAC B

DAC C

DAC D

–0.1

–0.2

–0.3

–0.4

–0.5

–0.6

–0.7

–0.8

–0.9

–1.0

EXTERNAL

50

45

INTERNAL

40

35

30

AV = DV = 5V

DD DD

OFFSET IN = FLOATING

DAC OUT V = 15V

AD7294 IN SOCKET ON

V

= 5V, INTERNAL REF

DRIVE

200mm × 100mm 2-LAYER FR-4 PCB

25

–5

0

5

10 15 20 25 30 35 40 45 50 55 60

TIME (Seconds)

0

5

10

15

20

25

30

35

40

SOURCE CURRENT (mA)

Figure 26. DAC Sourcing Current at Input Code = x000, (V_OUT= 0 V)

Figure 29. Response to Thermal Shock from Room Temperature into 50°C

Stirred Oil (Both the AD7294 and the 2N3906 are Placed in a Stirred Oil Bath)

Rev. I | Page 17 of 47

AD7294

Data Sheet

–50

–55

–60

–65

–70

–75

–80

–85

–90

–95

0

–0.2

–0.4

–0.6

–0.8

–1.0

–1.2

–1.4

–1.6

–1.8

–2.0

0

0.5

1.0

1.5

2.0

2.5

1k

10k

100k

1M

10M

CAPACITANCE FROM D+ TO D– (nF)

FREQUENCY (Hz)

Figure 30. Temperature Error vs. Capacitor Between D+ and D−

Figure 33. I_SENSEPower Supply Rejection Ratio vs. Supply Ripple Frequency

Without V_PPSupply Decoupling Capacitors for a 500 mV Ripple

15

10

–50

–60

5

–70

0

–80

–5

–90

–10

–15

–20

–100

–110

0

2000

4000

6000

8000

10000

12000

1

10

100

1k

10k

100k

1M

10M

100M

SERIES RESISTANCE (Ω)

RIPPLE FREQUENCY (Hz)

Figure 31. Temperature Error vs. Series Resistance for 15 Typical Devices

Figure 34. I_SENSECommon-Mode Rejection Ratio vs. Ripple Frequency for a

400 mV Peak-To-Peak Ripple

5

0

–5

–10

–15

–20

–25

–30

–35

–40

–45

–50

1k

10k

100k

1M

10M

100M

FREQUENCY (Hz)

Figure 32. Frequency Response of the High-Side Current Sensor

on the AD7294

Rev. I | Page 18 of 47

Data Sheet

AD7294

TERMINOLOGY

ratio is dependent on the number of quantization levels in the

DAC TERMINOLOGY

digitization process; the more levels, the smaller the quantization

noise. The theoretical signal-to-noise and distortion ratio for

an ideal N-bit converter with a sine wave input is given by

Relative Accuracy

For the DAC, relative accuracy or integral nonlinearity (INL) is

a measure of the maximum deviation, in LSBs, from a straight

line passing through the endpoints of the DAC transfer function.

Signal-to-(Noise + Distortion) = (6.02 N + 1.76) dB

Thus, the SINAD is 74 dB for an ideal 12-bit converter.

Differential Nonlinearity

Differential nonlinearity (DNL) is the difference between the

measured change and the ideal 1 LSB change between any two

adjacent codes. A specified differential nonlinearity of 1 LSB

maximum ensures monotonicity. This DAC is guaranteed mono-

tonic by design.

Total Harmonic Distortion (THD)

The ratio of the rms sum of harmonics to the fundamental. For

the AD7294, it is defined as

V₂²+V₃²+V₄²+V₅²+V₆

2

THD(dB) = 20log

V₁

Zero Code Error

Zero code error is a measure of the output error when zero code

(0x0000) is loaded to the DAC register. Ideally, the output

should be 0 V. The zero code error is always positive in the

AD7294 because the output of the DAC cannot go below 0 V.

Zero code error is expressed in mV.

where V₁is the rms amplitude of the fundamental and V₂, V₃,

V₄, V₅, and V₆are the rms amplitudes of the second through

sixth harmonics.

Peak Harmonic or Spurious Noise

The ratio of the rms value of the next largest component in the

ADC output spectrum (up to f_S/2 and excluding dc) to the rms

value of the fundamental. Typically, the value of this specification

is determined by the largest harmonic in the spectrum, but for

ADCs where the harmonics are buried in the noise floor, it is a

noise peak.

Full-Scale Error

Full-scale error is a measure of the output error when full-scale

code (0xFFFF) is loaded to the DAC register. Ideally, the output

should be V_DD− 1 LSB. Full-scale error is expressed in mV.

Gain Error

Gain error is a measure of the span error of the DAC. It is the

deviation in slope of the DAC transfer characteristic from ideal,

expressed as a percent of the full-scale range.

Integral Nonlinearity

The maximum deviation from a straight line passing through

the endpoints of the ADC transfer function. The endpoints are

zero scale, a point 1 LSB below the first code transition, and full

scale, a point 1 LSB above the last code transition.

Total Unadjusted Error

Total unadjusted error (TUE) is a measure of the output error,

taking all of the various errors into account.

Differential Nonlinearity

The difference between the measured and the ideal 1 LSB

change between any two adjacent codes in the ADC.

Zero Code Error Drift

Zero code error drift is a measure of the change in zero code

error with a change in temperature. It is expressed in µV/°C.

Offset Error

The deviation of the first code transition (00…000) to

(00…001) from the ideal—that is, AGND + 1 LSB.

Gain Error Drift

Gain error drift is a measure of the change in gain error with

changes in temperature. It is expressed in (ppm of full-scale

range)/°C.

Offset Error Match

The difference in offset error between any two channels.

Gain Error

ADC TERMINOLOGY

The deviation of the last code transition (111…110) to

(111…111) from the ideal (that is, REF_IN− 1 LSB) after the

offset error has been adjusted out.

Signal-to-Noise and Distortion Ratio (SINAD)

The measured ratio of signal-to-noise and distortion at the

output of the ADC. The signal is the rms amplitude of the

fundamental. Noise is the sum of all nonfundamental signals

up to half the sampling frequency (f_S/2), excluding dc. The

Gain Error Match

The difference in gain error between any two channels.

Rev. I | Page 19 of 47

AD7294

Data Sheet

THEORY OF OPERATION

1LSB = 2 × V

/4096

REF

ADC OVERVIEW

011...111

011...110

The AD7294 provides the user with a 9-channel multiplexer, an

on-chip track-and-hold, and a successive approximation ADC

based around a capacitive DAC. The analog input range for the

device can be selected as a 0 V to V_REFinput or a 2 × V_REFinput,

configured with either single-ended or differential analog inputs.

The AD7294 has an on-chip 2.5 V reference that can be disabled

when an external reference is preferred. If the internal ADC

reference is to be used elsewhere in a system, the output must

first be buffered.

000...001

000...000

111...111

100...010

100...001

100...000

–V

+ 1LSB V

REF

– 1LSB

+V – 1LSB

REF

The various monitored and uncommitted input signals are multi-

plexed into the ADC. The AD7294 has four uncommitted

analog input channels, V_IN0 to V_IN3. These four channels allow

single-ended, differential, and pseudo differential mode

measurements of various system signals.

ANALOG INPUT

Figure 36. Differential Transfer Characteristic with V_REFV_REFInput Range

For V_IN0 to V_IN3 in single-ended mode, the output code is

straight binary, where

V_IN= 0 V, D_OUT= x000, V_IN= V_REF− 1 LSB, and D_OUT= xFFF

In differential mode, the code is twos complement, where

ADC TRANSFER FUNCTIONS

The designed code transitions occur at successive integer LSB

values (1 LSB, 2 LSB, and so on). In single-ended mode, the

LSB size is V_REF/4096 when the 0 V to V_REFrange is used and

2 × V_REF/4096 when the 0 V to 2 × V_REFrange is used. The ideal

transfer characteristic for the ADC when outputting straight

binary coding is shown in Figure 35.

V

_IN+− V_IN−= 0 V, and D_OUT= x00

_IN+− V_IN−= V_REF− 1 LSB, and D_OUT= x7FF

_IN+− V_IN−= −V_REF, and D_OUT= x800

Channel 5 and Channel 6 (current sensor inputs) are twos

complement, where

V

_IN+− V_IN−= 0 mV, and D_OUT= x000

111...111

111...110

V_IN+− V_IN−= V_REF/12.5 − 1 LSB, D_OUT= x7FF

_IN+− V_IN−= −V_REF/12.5, D_OUT= x800

V

111...000

Channel 7 to Channel 9 (temperature sensor inputs) are twos

complement with the LSB equal to 0.25°C, where

1LSB = V

/4096

REF

011...111

T_IN= 0°C, and D_OUT= x000

T_IN= +255.75°C, and D_OUT= x7FF

T_IN= −256°C, and D_OUT= x800

000...010

000...001

000...000

ANALOG INPUTS

V

– 1LSB

REF

1LSB

0V

ANALOG INPUT

The AD7294 has a total of four analog inputs. Depending on

the configuration register setup, they can be configured as two

single-ended inputs, two pseudo differential channels, or two

fully differential channels. See the Register Setting section for

further details.

NOTE

1. V

IS EITHER V

OR 2 × V

.

REF

Figure 35. Single-Ended Transfer Characteristic

In differential mode, the LSB size is 2 × V_REF/4096 when the 0 V to

_REFrange is used, and 4 × V_REF/4096 when the 0 V to 2 × V_REF

Single-Ended Mode

V

range is used. The ideal transfer characteristic for the ADC when

outputting twos complement coding is shown in Figure 36 (with

the 2 × V_REFrange).

The AD7294 can have four single-ended analog input channels.

In applications where the signal source has high impedance, it is

recommended to buffer the analog input before applying it to the

ADC. The analog input range can be programmed to be either

0 V to V_REFor 0 V to 2 × V_REF. In 2 × V_REFmode, the input is

effectively divided by 2 before the conversion takes place. Note

that the voltage with respect to GND on the ADC analog input

pins cannot exceed AV_DD.

Rev. I | Page 20 of 47

Data Sheet

AD7294

If the analog input signal to be sampled is bipolar, the internal

reference of the ADC can be used to externally bias up this

The common mode must be in this range to guarantee the

functionality of the AD7294.

signal so that it is correctly formatted for the ADC. Figure 37

shows a typical connection diagram when operating the ADC

in single-ended mode.

When a conversion takes place, the common mode is rejected,

resulting in a virtually noise-free signal of amplitude −V_REFto

+V_REF, corresponding to the digital output codes of −2048 to

+2047 in twos complement format.

+2.5V

R

+1.25V

If the 2 × V_REFrange is used, the input signal amplitude extends

from −2 ×V_REF(V_IN+= 0 V, V _IN−= V_REF) to +2 × V_REF(V_IN−= 0 V,

0V

R

0V

V

IN

AD7294¹

V

0

IN

3R

–1.25V

V_IN+= V_REF).

R

REF

ADC

Driving Differential Inputs

3

OUT

The differential modes available on V_IN0 to V_IN3 in Table 13

require that V_IN+and V_IN−be driven simultaneously with two

equal signals that are 180° out of phase. The common mode on

which the analog input is centered must be set up externally. The

common-mode range is determined by V_REF, the power supply,

and the particular amplifier used to drive the analog inputs.

Differential modes of operation with either an ac or dc input

provide the best THD performance over a wide frequency

range. Because not all applications have a signal preconditioned

for differential operation, there is often a need to perform a single-

ended-to-differential conversion.

0.47µF

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 37. Single-Ended Mode Connection Diagram

Differential Mode

The AD7294 can have two differential analog input pairs.

Differential signals have some benefits over single-ended

signals, including noise immunity based on the common-

mode rejection of the device and improvements in distortion

performance. Figure 38 defines the fully differential analog

input of the AD7294.

Using an Op Amp Pair

An op amp pair can be used to directly couple a differential signal

to one of the analog input pairs of the AD7294. The circuit con-

figurations illustrated in Figure 39 show how a dual op amp can be

used to convert a single-ended bipolar signal into a differential

unipolar input signal.

V

p-p

V

IN+

REF

AD7294¹

COMMON-MODE

VOLTAGE

V

p-p

V

REF

IN–

The voltage applied to Point A sets up the common-mode voltage.

As shown in Figure 39, Point A connects to the reference, but any

value in the common-mode range can be the input at Point A to set

up the common mode. The AD8022 is a suitable dual op amp that

can be used in this configuration to provide differential drive to

the AD7294.

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 38. Differential Input Definition

The amplitude of the differential signal is the difference

between the signals applied to V_IN+and V_IN−in each differential

pair (V_IN+− V_IN−). The resulting converted data is stored in twos

complement format in the result register. Simultaneously drive

V_IN0 and V_IN1 by two signals, each of amplitude V_REF(or 2 ×

Care is required when choosing the op amp because the selection

depends on the required power supply and system performance

objectives. The driver circuits in Figure 39 are optimized for dc

coupling applications requiring best distortion performance.

The differential op amp driver circuit shown in Figure 39 is

configured to convert and level shift a single-ended, ground

referenced (bipolar) signal to a differential signal centered at

the V_REFlevel of the ADC.

V

_REF, depending on the range chosen), that are 180° out of

phase. Assuming the 0 V to V_REFrange is selected, the amplitude

of the differential signal is, therefore, −V_REFto +V_REFpeak-to-

peak (2 × V_REF), regardless of the common mode (V_CM).

The common mode is the average of the two signals

(V_IN++ V_IN−)/2

The common mode is, therefore, the voltage on which the two

inputs are centered.

This results in the span of each input being V_CMV_REF/2. This

voltage has to be set up externally, and its range varies with the

reference value, V_REF. As the value of V_REFincreases, the common-

mode range decreases. When driving the inputs with an amplifier,

the actual common-mode range is determined by the output

voltage swing of the amplifier.

Rev. I | Page 21 of 47

AD7294

Data Sheet

3.75V

2.5V

2 × V

p-p

220Ω

V+

REF

V

REF

p-p

AD7294¹

440Ω

1.25V

V

GND

IN+

27Ω

AD7294¹

V

IN+

V–

220Ω

V+

220kΩ

IN–

3.75V

2.5V

DC INPUT

VOLTAGE

REF

/REF ADC

IN

OUT

1.25V

REF

ADC

V

OUT

IN–

0.47µF

A

V–

10kΩ

0.47µF

20kΩ

1

ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 41. Pseudo Differential Mode Connection Diagram

1

ADDITIONAL PINS OMITTED FOR CLARITY.

CURRENT SENSOR

Figure 39. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal

into a Differential Unipolar Signal

Two bidirectional high-side current sense amplifiers are

provided that can accurately amplify differential current shunt

voltages in the presence of high common-mode voltages from

AV_DDup to 59.4 V. Each amplifier can accept a 200 mV

differential input. Both current sense amplifiers have a fixed

gain of 12.5 and utilize an internal 2.5 V reference.

Pseudo Differential Mode

The four uncommitted analog input channels can be configured

as two pseudo differential pairs. Uncommitted input, V_IN0 and

V_IN1, are a pseudo differential pair, as are V_IN2 and V_IN3. In this

mode, V_IN+is connected to the signal source, which can have a

maximum amplitude of V_REF(or 2 × V_REF, depending on the

range chosen) to make use of the full dynamic range of the

device. A dc input is applied to V_IN−. The voltage applied to this

input provides an offset from ground or a pseudo ground for the

An analog comparator is also provided with each amplifier for

fault detection. The threshold is defined as

1.2 × Full-Scale Voltage Range

When this limit is reached, the output is latched onto a

dedicated pin. This output remains high until the latch is

cleared by writing to the appropriate register.

V

_IN+input. Which channel is V_IN+is determined by the ADC

channel allocation. The differential mode must be selected to

operate in the pseudo differential mode. The resulting converted

pseudo differential data is stored in twos complement format in the

result register.

I

LOAD

R

SENSE

AV

TO 54.5V

DD

V

RS(+)

RS(–)

PP

AD7294

The governing equation for the pseudo differential mode, for

V_IN0 is

R1

R2

40kΩ

V

_OUT= 2(V_IN+− V_IN−) − V_{REF_ADC}

A1

where V_IN+is the single-ended signal and V_IN−is a dc voltage.

Q1

R3

Q2

R4

The benefit of pseudo differential inputs is that they separate

the analog input signal ground from the ADC ground, allowing

dc common-mode voltages to be cancelled. The typical voltage

range for V_IN−while in pseudo differential mode is shown in

Figure 40; Figure 41 shows a connection diagram for pseudo

differential mode.

V

OUT

A2

TO MUX

100kΩ

Figure 42. High-Side Current Sense

The AD7294 current sense comprises two main blocks: a

differential and an instrumentation amplifier. A load current

flowing through the external shunt resistor produces a voltage

at the input terminals of the AD7294. Resistors R1 and R2

connect the input terminals to the differential amplifier (A1).

A1 nulls the voltage appearing across its own input terminals

by adjusting the current through R1 and R2 with Transistor Q1

and Transistor Q2. Common-mode feedback maintains the sum

of these currents at approximately 50 μA. When the input signal

to the AD7294 is zero, the currents in R1 and R2 are equal. When

the differential signal is nonzero, the current increases through

one of the resistors and decreases in the other. The current differ-

ence is proportional to the size and polarity of the input signal.

2.0

AV

= DV = 5V

DD

V

= 5V

DRIVE

1.5

1.0

0.5

0

–0.5

The differential currents through Q1 and Q2 are converted into

a differential voltage by R3 and R4. A2 is configured as an instru-

mentation amplifier, buffering this voltage and providing additional

0

1

2

3

4

5

6

V

(V)

REF

Figure 40. V_IN−Input Range vs. V_REFin Pseudo Differential Mode

Rev. I | Page 22 of 47

Data Sheet

AD7294

gain. Therefore, for an input voltage of 200 mV at the pins, an

output span of 2.5 V is generated.

Note that the maximum series resistance on the RS(+) and

RS(−) inputs (as shown in Figure 42) is limited to a maximum

of 1 kΩ due to back-to-back ESD protection diodes from RS(+)

and RS(−) to V_PP. Also, note that if RF1 and RF2 are in series

with R1 and R2 (shown in Figure 42), it affects the gain of the

amplifier. Any mismatch between RF1 and RF2 can introduce

offset error.

The current sensors on the AD7294 are designed to remove

any flicker noise and offset present in the sensed signal. This is

achieved by implementing a chopping technique that is transpa-

rent to the user. The V_SENSEsignal is first converted by the AD7294,

the analog inputs to the amplifiers are then swapped, and the

differential voltage is once again converted by the AD7294. The

two conversion results enable the digital removal of any offset

or noise. Switches on the amplifier inputs enable this chopping

technique to be implemented. This process requires 6 μs in total

to return a final result.

V

I

PP

LOAD

R

SENSE

RF1

RF2

10nF

CF

V

RSx(+)

RSx(–)

PP

Choosing R_SENSE

AD7294

The resistor values used in conjunction with the current sense

amplifiers on the AD7294 are determined by the specific appli-

cation requirements in terms of voltage, current, and power.

Small resistors minimize power dissipation, have low inductance

to prevent any induced voltage spikes, and have good tolerance,

which reduce current variations. The final values chosen are a

compromise between low power dissipation and good accuracy.

Low value resistors have less power dissipated in them, but higher

value resistors may be required to utilize the full input range of

the ADC, thus achieving maximum SNR performance.

Figure 43. Current Sense Filtering (RS_XCan Be Either RS1 or RS2)

For certain RF applications, the optimum value for RF1 and

RF2 is 1 kΩ whereas CF1 can range from 1 μF to 10 μF. CF2 is a

decoupling capacitor for the V_PPsupply. Its value is application

dependent, but for initial evaluation, values in the range of 1 nF

to 100 nF are recommended.

When the sense current is known, the voltage range of the

AD7294 current sensor (200 mV) is divided by the maximum

sense current to yield a suitable shunt value. If the power dissi-

pation in the shunt resistor is too large, the shunt resistor can

be reduced, in which case, less of the ADC input range is used.

Using less of the ADC input range results in conversion results,

which are more susceptible to noise and offset errors because

offset errors are fixed and are thus more significant when

smaller input ranges are used.

Kelvin Sense Resistor Connection

When using a low value sense resistor for high current

measurement, the problem of parasitic series resistance can

arise. The lead resistance can be a substantial fraction of the

rated resistance, making the total resistance a function of lead

length. Avoid this problem by using a Kelvin sense connection.

This type of connection separates the current path through the

resistor and the voltage drop across the resistor. Figure 44 shows

the correct way to connect the sense resistor between the RS(+)

and RS(−) pins of the AD7294.

R

_SENSEmust be able to dissipate the I²R losses. If the power dissi-

pation rating of the resistor is exceeded, its value may drift or

the resistor may be damaged resulting in an open circuit. This

can result in a differential voltage across the terminals of the

AD7294 in excess of the absolute maximum ratings. Additional

protection is afforded to the current sensors on the AD7294 by

the recommended current limiting resistors, RF1 and RF2, as

illustrated in Figure 43. The AD7294 can handle a maximum

continuous current of 30 mA; thus, an RF2 of 1 kΩ provides

adequate protection for the AD7294.

SENSE RESISTOR

CURRENT

FLOW FROM

SUPPLY

CURRENT

FLOW TO

LOAD

KELVIN

SENSE

TRACES

RSX(+)

RSX(–)

If I_SENSEhas a large high frequency component, take care to

choose a resistor with low inductance. Low inductance metal

film resistors are best suited for these applications.

AD7294

Current Sense Filtering

Figure 44. Kelvin Sense Connections (RSX Can Be Either RS1 or RS2)

In some applications, it may be desirable to use external

filtering to reduce the input bandwidth of the amplifier (see

Figure 43). The −3 dB differential bandwidth of this filter is

equal to

ANALOG COMPARATOR LOOP

The AD7294 contains two setpoint comparators that are used

for independent analog control. This circuitry enables users

to quickly detect if the sensed voltage across the shunt has

BW_DM= 1/(4πRC)

Rev. I | Page 23 of 47

AD7294

Data Sheet

increased about the preset (V_REF× 1.2)/12.5. If this occurs, the

Remote Sensing Diode

I

_SENSEOVERRANGE pin is set to a high logic level enabling

The AD7294 is designed to work with discrete transistors,

2N3904 and 2N3906. If an alternative transistor is used, the

AD7294 operates as specified provided the following conditions

are adhered to.

appropriate action to be taken to prevent any damage to the

external circuitry.

The setpoint threshold level is fixed internally in the AD7294,

and the current sense amplifier saturates above this level. The

comparator also triggers if a voltage of less than AV_DDis applied

to the R_SENSEor V_PPpin.

Ideality Factor

The ideality factor, n_f, of the transistor is a measure of the

deviation of the thermal diode from ideal behavior. The

AD7294 is trimmed for an n_fvalue of 1.008. Use the following

equation to calculate the error introduced at a Temperature T

(°C) when using a transistor whose n_fdoes not equal 1.008:

TEMPERATURE SENSOR

The AD7294 contains one local and two remote temperature

sensors. The temperature sensors continuously monitor the

three temperature inputs and new readings are automatically

available every 5 ms.

ΔT = (n_f− 1.008) × (273.15 K + T)

To factor this in, the user can write the ꢀT value to the offset

register. The AD7294 automatically adds it to, or subtracts it

from, the temperature measurement.

The on-chip, band gap temperature sensor measures the temper-

ature of the system. Diodes are used in conjunction with the two

remote temperature sensors to monitor the temperature of other

critical board components.

Base Emitter Voltage

The AD7294 operates as specified provided that the base-

emitter voltage is greater than 0.25 V at 8 μA at the highest

operating temperature, and less than 0.95 V at 128 μA for the

lowest operating temperature.

V

DD

16 × I

4 × I

I

I-BIAS

TO ADC

MUX

Base Resistance

f_C= 65kHz

LPF

D2+

D1+

The base resistance should be less than 100 Ω.

h_FEVariation

LIMIT

REGISTERS

T1

T2

TEMP

SENSOR

D1–

D2–

Use a transistor with small variation in h_FE(approximately 50 to

150). Small variation in h_FEindicates tight control of the V_BE

characteristics.

MUX

BIAS DIODE

REMOTE

SENSING

TRANSISTORS

AD7294

For RF applications, the use of high Q capacitors functioning as a

filter protects the integrity of the measurement. These capacitors,

such as Johanson Technology 10 pF high Q capacitors: Reference

Code 500R07S100JV4T, should be connected between the base and

the emitter, as close to the external device as possible. However,

large capacitances affect the accuracy of the temperature measure-

ment; thus, the recommended maximum capacitor value is 100 pF.

In most cases, a capacitor is not required; the selection of any

capacitor is dependent on the noise frequency level.

CAP ALERT

Figure 45. Internal and Remote Temperature Sensors

The temperature sensor module on the AD7294 is based on the

three current principle (see Figure 45), where three currents are

passed through a diode and the forward voltage drop is measured

at each diode, allowing the temperature to be calculated free of

errors caused by series resistance.

Each input integrates, in turn, over a period of several hundred

microseconds. This takes place continuously in the background,

leaving the user free to perform conversions on the other channels.

When integration is complete, a signal passes to the control logic

to initiate a conversion automatically. If the ADC is in command

mode, the temperature conversion is performed as soon as the

next conversion is completed. In autocycle mode, the conversion

is inserted into an appropriate place in the current sequence; see

the Register Setting section for further details. If the ADC is

idle, the conversion takes place immediately.

AD7294

2N3904

D+

NPN

10pF

D–

Figure 46. Measuring Temperature Using an NPN Transistor

AD7294

D+

10pF

2N3906

PNP

Three registers store the result of the last conversion on each

temperature channel; these can be read at any time. In addition,

in command mode, one or both of the two external channel

registers can be read out as part of the output sequence.

D–

Figure 47. Measuring Temperature Using a PNP Transistor

Rev. I | Page 24 of 47

Data Sheet

AD7294

The DAC word is digitally inverted on-chip such that

Series Resistance Cancellation

The AD7294 has been designed to automatically cancel out the

effect of parasitic, base, and collector resistance on the tempera-

ture reading. This gives a more accurate result, without the need

for any user characterization of the parasitic resistance. The

AD7294 can compensate for up to 100 Ω in a process that is

transparent to the user.

V

_OUT= 3V_OFFSET+ 2(V_DAC− V_REF)





D

2ⁿ









V_REF

×

and V_DAC

=













where:

V

_DACis the output of the DAC before digital inversion.

D is the decimal equivalent of the binary code that is loaded to the

DAC OPERATION

The AD7294 contains four 12-bit DACs that provide digital

control with 12 bits of resolution with a 2.5 V internal reference.

The DAC core is a thin film 12-bit string DAC with a 5 V output

span and an output buffer that can drive the high voltage output

stage. The DAC has a span of 0 V to 5 V with a 2.5 V reference

input. The output range of the DAC, which is controlled by the

offset input, can be positioned from 0 V to 15 V.

DAC register.

n is the bit resolution of the DAC.

An example of the offset function is given in Table 8.

Table 8. Offset Voltage Function Example

Offset

Voltage

1.67 V

3.33 V

5.00 V

V_OUTwith 0x000

V_OUTwith 0xFFF

5 V − 1 LSB

10 V − 1 LSB

15 V − 1 LSB

0 V

5 V

10 V

Resistor String

The resistor string structure is shown in Figure 48. It consists of

a string of 2ⁿresistors, each of Value R. The code loaded to the

DAC register determines at which node on the string the voltage

is tapped off to be fed into the output amplifier. The voltage is

tapped off by closing one of the switches connecting the string

to the amplifier. This architecture is inherently monotonic,

voltage out, and low glitch. It is also linear because all of the

resistors are of equal value.

The user has the option of leaving the offset pin open, in which

case the voltage on the noninverting input of Op Amp A2 is set

by the resistor divider, giving

V

_OUT= 2V_DAC

This generates the 5 V output span from a 2.5 V reference.

Digitally inverting the DAC allows the circuit to operate as a

generic DAC when no offset is applied. If the offset pin is not

being driven, it is best practice to place a 100 nF capacitor

between the pin and ground to improve both the settling time

and the noise performance of the DAC.

R

Note that a significant amount of power can be dissipated in the

DAC outputs. A thermal shutdown circuit sets the DAC outputs

to high impedance if a die temperature of >150°C is measured

by the internal temperature sensor. This also sets the overtem-

perature alert bit in Alert Register C, see the Alerts and Limits

Theory section. Note that this feature is disabled when the

temperature sensor powers down.

TO OUTPUT

AMPLIFIER

R

ADC AND DAC REFERENCE

R

The AD7294 has two independent internal high performance

2.5 V references, one for the ADCs and the other for the four

on-chip DACs. If the application requires an external reference,

it can be applied to the REF_OUT/REF_INDAC pin and/or to the

REF_OUT/REF_INADC pin. The internal reference should be buffered

Figure 48. Resistor String Structure

before being used by external circuitry. Decouple both the REF_OUT

/

REF_INDAC pin and the REF_OUT/REF_INADC pin to AGND using a

220 nF capacitor. On power-up, the AD7294 is configured for

use with an external reference. To enable the internal references,

write a zero to both the D4 and D5 bits in the power-down

register (see the Register Setting section for more details). Both

the ADC and DAC references require a minimum of 60 μs to

power up and settle to a 12-bit performance when a 220 nF

decoupling capacitor is used.

Output Amplifier

Referring to Figure 48, the purpose of A1 is to buffer the DAC

output range from 0 V to V_REF. The second amplifier, A2, is

configured such that when an offset is applied to OFFSET IN x,

its output voltage is three times the offset voltage minus twice

the DAC voltage.

V

_OUT= 3V_OFFSET− 2V_DAC

Rev. I | Page 25 of 47

AD7294

Data Sheet

The AD7294 can also operate with an external reference.

Suitable reference sources for the AD7294 include the AD780,

AD1582, ADR431, REF193, and ADR391. In addition, choosing

a reference with an output trim adjustment, such as the ADR441,

allows a system designer to trim system errors by setting a

reference voltage to a voltage other than the nominal.

V_DRIVEFEATURE

The AD7294 also has a V_DRIVEfeature to control the voltage at

which the I²C interface operates. The V_DRIVEpin is connected to

the supply to which the I²C bus is pulled. This pin sets the input

and output threshold levels for the digital logic pins and the

I_SENSEOVERRANGE pins. The V_DRIVEfeature allows the AD7294

Long-term drift is a measure of how much the reference drifts

over time. A reference with a low long-term drift specification

ensures that the overall solution remains stable during its entire

lifetime. If an external reference is used, select a low temperature

coefficient specification to reduce the temperature dependence

of the system output voltage on ambient conditions.

to easily interface to both 3 V and 5 V processors. For example,

if the AD7294 is operated with a V_DDof 5 V, the V_DRIVEpin can

be powered from a 3 V supply, allowing a large dynamic range

with low voltage digital processors. Thus, the AD7294 can be

used with the 2 × V_REFinput range with a V_DDof 5 V, yet remains

capable of interfacing to 3 V digital devices. Decouple this pin to

DGND with a 100 nF and a 1 μF capacitor.

Rev. I | Page 26 of 47

Data Sheet

AD7294

REGISTER SETTING

The AD7294 contains internal registers (see Figure 49) that

store conversion results, high and low conversion limits, and

information to configure and control the device.

Table 9. AD7294 Register Address

Address in Hex

Registers (R is Read/W is Write)

00

01

02

03

04

05

06

07

08

09

0A

0B

0C

0D

0E

0F

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

1E

1F

20

21

22

23

24

25

26

27

40

41

Command Register (W)

COMMAND

REGISTER

Result Register (R)/DAC_AValue (W)

T_SENSE1 Result (R)/DAC_BValue (W)

T_SENSE2 Result (R)/DAC_CValue (W)

T_SENSEINT Result (R)/DAC_DValue (W)

Alert Register A (R/W)

RESULT

REGISTER

DAC

REGISTERS

T

RESULT

SENSE

Alert Register B (R/W)

Alert Register C (R/W)

REGISTERS × 3

ALERT

REGISTERS × 3

Channel Sequence Register (R/W)

Configuration Register (R/W)

Power-Down Register (R/W)

DATA_LOWRegister V_IN0 (R/W)

DATA_HIGHRegister V_IN0 (R/W)

Hysteresis Register V_IN0 (R/W)

DATA_LOWRegister V_IN1 (R/W)

DATA_HIGHRegister V_IN1 (R/W)

Hysteresis Register V_IN1 (R/W)

DATA_LOWRegister, V_IN2 (R/W)

DATA_HIGHRegister V_IN2 (R/W)

Hysteresis Register V_IN2 (R/W)

DATA_LOWRegister V_IN3 (R/W)

DATA_HIGHRegister V_IN3 (R/W)

Hysteresis Register V_IN3 (R/W)

DATA_LOWRegister I_SENSE1 (R/W)

DATA_HIGHRegister I_SENSE1 (R/W)

Hysteresis Register I_SENSE1 (R/W)

DATA_LOWRegister I_SENSE2 (R/W)

DATA_HIGHRegister I_SENSE2 (R/W)

Hysteresis Register I_SENSE2 (R/W)

DATA_LOWRegister T_SENSE1 (R/W)

DATA_HIGHRegister T_SENSE1 (R/W)

Hysteresis Register T_SENSE1 (R/W)

DATA_LOWRegister T_SENSE2 (R/W)

DATA_HIGHRegister T_SENSE2 (R/W)

Hysteresis Register T_SENSE2 (R/W)

DATA_LOWRegister T_SENSEINT (R/W)

DATA_HIGHRegister T_SENSEINT (R/W)

Hysteresis Register T_SENSEINT (R/W)

T_SENSE1 Offset Register (R/W)

T_SENSE2 Offset Register (R/W)

Factory Test Mode

CHANNEL

SEQUENCE

REGISTER

ADDRESS

POINTER

REGISTER

CONFIGURATION

REGISTER

POWER-DOWN

REGISTER

DATA

/

HIGH

DATA

LOW

REGISTERS × 18

HYSTERESIS

REGISTER

T

OFFSET

SENSE

REGISTERS × 2

SDA

SCL

SERIAL BUS INTERFACE

Figure 49. AD7294 Register Structure

Each data register has an address to which the address pointer

register points when communicating with it. The command

register is the only register that is a write-only register; the rest

are read/write registers.

ADDRESS POINTER REGISTER

The address pointer register is an 8-bit register, in which the

6 LSBs are used as pointer bits to store an address that points

to one of the AD7294 data registers, see Table 9.

Factory Test Mode

Rev. I | Page 27 of 47

AD7294

Data Sheet

COMMAND REGISTER (0x00)

RESULT REGISTER (0x01)

Writing in the command register puts the device into command

mode. When in command mode, the device cycles through the

selected channels from LSB (D0) to MSB (D7) on each subsequent

read (see Table 10). A channel is selected for conversion if a one is

written to the desired bit in the command register. On power-up,

all bits in the command register are set to zero. If the external T_SENSE

channels are selected in the command register byte, it is not

actually requesting a conversion. The result of the last automatic

conversion is output as part of the sequence (see the Modes of

Operation section).

The result register is a 16-bit read-only register. The conversion

results for the four uncommitted ADC inputs and the two I_SENSE

channels are stored in the result register for reading.

Bit D14 to Bit D12 are the channel allocation bits, each of which

identifies the ADC channel that corresponds to the subsequent

result (see the ADC Channel Allocation section for more details).

Bit D11 to Bit D0 contain the most recent ADC result. D15 is

reserved as an alert_flag bit. Table 11 lists the contents of the

first byte that is read from the AD7294 results register; Table 12

lists the contents of the second byte read.

If a command mode conversion is required while the autocycle

mode is active, it is necessary to disable the autocycle mode

before proceeding to the command mode (see the Autocycle

Mode section for more details).

Table 10. Command Register¹

MSB

LSB

Bits

D7

D6

D5

_SENSE2

D4

D3

D2

D1

D0

Read out last

result from

I

I_SENSE

1

V_IN3 (S.E.)

or

V_IN2 (S.E.)

or

V_IN1 (S.E.)

or

V_IN0 (S.E.)

or

Channel Read out last

result from

T_SENSE

2

T_SENSE

1

V_IN3 − V_IN2

(DIFF)

V_IN2 − V_IN3

(DIFF)

V_IN1 − V_IN0

(DIFF)

V_IN0 − V_IN1

(DIFF)

¹S.E. indicates single-ended and DIFF indicates differential.

Table 11. Result Register (First Read)

MSB

LSB

D8

B8

D15

D14

D13

D12

D11

D10

D9

Alert_Flag

CH_ID2

CH_ID1

CH_ID0

B11

B10

B9

Table 12. Result Register (Second Read)

MSB

LSB

D0

B0

D7

D6

D5

D4

D3

D2

D1

B7

B6

B5

B4

B3

B2

B1

Rev. I | Page 28 of 47

Data Sheet

AD7294

ADC Channel Allocation

Table 14. T_SENSERegister (First Read)

MSB

LSB

The three channel address bits indicate which channel the result

in the result register represents. Table 13 details the channel ID bits

(S.E. indicates single-ended and DIFF indicates differential).

D15

D14

D13

D12

D11

D10 D9 D8

Alert_Flag CH_ID2CH_ID1CH_ID0B11

B10

B9

B8

Table 15. Register (Second Read)

Table 13. ADC Channel Allocation

MSB

LSB

Channel ID

D7

D6

D5

D4

D3

D2

D1

B1

D0

Function

CH_ID2

CH_ID1

CH_ID0

B7

B6

B5

B4

B3

B2

B0

V_IN0 (S.E.) or

0

V_IN0 − V_IN1 (DIFF)

V_IN1 (S.E.) or

V_IN1 − V_IN0 (DIFF)

V_IN2 (S.E.) or

V_IN2 − V_IN3 (DIFF)

V_IN3 (S.E.) or

V_IN3 − V_IN2 (DIFF)

TSENSEINT RESULT REGISTER (0X04)

0

1

0

1

The T_SENSEINT register is a 16-bit read-only register used to

store the ADC data generated from the internal temperature

sensor. Similar to the T_SENSE1 and T_SENSE2 result registers, this

register stores the temperature readings from the ADC in an 11-

bit twos complement format, D10 to D0, and uses the MSB as a

general alert flag. Bits[D14:D11] are not used and are set to

zero. Conversions take place approximately every 5 ms. The

temperature data format in Table 16 also applies to the internal

temperature sensor data.

I_SENSE

1

2

1

0

1

0

1

0

1

T_SENSE

1

2

TSENSE1, TSENSE2 RESULT REGISTERS (0X02 AND

0X03)

Temperature Value Format

The temperature reading from the ADC is stored in an 11-bit

twos complement format, D10 to D0, to accommodate both

positive and negative temperature measurements. The temper-

ature data format is provided in Table 16.

Register T_SENSE1 and Register T_SENSE2 are 16-bit read only registers.

The MSB, D15 is the alert_flag bit whereas Bit D14 to Bit D12

contain the three ADC channel allocation bits. D11 is reserved

for flagging diode open circuits. The temperature reading from

the ADC is stored in an 11-bit twos complement format, D10 to

D0 (see Table 14 and Table 15). Conversions take place approx-

imately every 5 ms.

Table 16. T_SENSEData Format

Input

D10 (MSB)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0 (LSB)

−256

+128

+64

+32

+16

+8

+4

+2

+1

+0.5

+0.25

Value (°C)

Rev. I | Page 29 of 47

AD7294

Data Sheet

ALERT STATUS REGISTER A (0x05), REGISTER B

(0x06), AND REGISTER C (0x07)

DAC_A,DAC_B, DAC_C, DAC_D, REGISTERS (0x01 TO 0x04)

Writing to these register addresses sets the DAC_A, DAC_B, DAC_C,

and DAC_Doutput voltage codes, respectively. Bits[D11:D0] in

the write result register are the data bits sent to DAC_A. Bit D15

to Bit D12 are ignored.

The alert status registers (A, B, and C) are 8-bit read/write

registers that provide information on an alert event. If a

conversion results in activating the ALERT/BUSY pin or the

alert_flag bit in the result register or T_SENSEregisters, the alert

status register can be read to gain further information. To clear

the full content of any one of the alert registers, write a code of

FF (all ones) to the relevant registers. Alternatively, the user can

write to the respective alert bit in the selected alert register to

clear the alert associated with that bit. The entire contents of all

the alert status registers can be cleared by writing a 1 to Bit D1

and Bit D2 in the configuration register, as shown in Table 24.

However, this operation then enables the ALERT/BUSY pin for

subsequent conversions. See the Alerts and Limits Theory

section for more details.

Table 17. DAC Register (First Write)¹

MSB

LSB

D15

D14

D13

D12

D11

D10 D9 D8

X

B11

B10

B9

B8

¹X is don’t care.

Table 18. DAC Register (Second Write)

MSB

LSB

D7

D6

D5

D4

D3

D2

D1

B1

D0

B7

B6

B5

B4

B3

B2

B0

CHANNEL SEQUENCE REGISTER (0x08)

The channel sequence register is an 8-bit read/write register that

allows the user to sequence the ADC conversions to be per-

formed in autocycle mode. Table 22 shows the content of the

channel sequence register. See the Modes of Operation section

for more information.

Table 19. Alert Status Register A

Alert Bit

D7

D6

D5

D4

D3

D2

D1

D0

Function

V_IN3

high alert

V_IN3

low alert

V_IN2

high alert

V_IN2

low alert

V_IN1

high alert

V_IN1

low alert

V_IN0

high alert

V_IN0

low alert

Table 20. Alert Status Register B

Alert Bit

D7

D6

D5

D4

D3

D2

D1

D0

Reserved

I_SENSE2

I_SENSE1

I_SENSE2

I_SENSE1

Function

overrange

high alert

low alert

high alert

low alert

Table 21. Alert Status Register C

Alert Bit

D7

D6

D5

D4

D3

D2

D1

D0

Function

Open-diode

flag

Overtemp

alert

T_SENSEINT

high alert

T_SENSEINT

low alert

T_SENSE

high alert

2

T_SENSE

low alert

2

T_SENSE

high alert

1

T_SENSE1

low alert

Table 22. Channel Sequence Register

Channel Bit D7

D6

D5

D4

D3

D2

D1

D0

Reserved

I_SENSE2

I_SENSE1

V_IN3

V_IN2

V_IN1

V_IN0

Function

Rev. I | Page 30 of 47

Data Sheet

AD7294

good dc linearity performance. For high frequency input signals,

it may be desirable to have a known sampling point, thus the

noise-delayed sampling can be disabled by writing a 1 to Bit D14 in

the configuration register. This ensures that the sampling instance

is fixed relative to SDA, resulting in improved SNR performance. If

noise-delay samplings extend longer than 1 µs, the current

conversion terminates. This termination can occur if there are

edges on SDA that are outside the I²C specification. When noise-

delayed sampling is enabled, the rise and fall times must meet

the I²C-specified standard. When D13 is enabled, the conversion

time may vary.

CONFIGURATION REGISTER (0x09)

The configuration register is a 16-bit read/write register that

sets the operating modes of the AD7294. The bit functions of

the configuration register are outlined in Table 23 and Table 24.

On power-up, the configuration register is reset to 0x0000.

Sample Delay and Bit Trial Delay

It is recommended that no I²C bus activity occur when a con-

version is taking place; however, this may not be possible, for

example, when operating in autocycle mode. Bit D14 and Bit D13

in the configuration register are used to delay critical sample

intervals and bit trials from occurring while there is activity

on the I²C bus. On power-up, Bit D14 (noise-delayed sampling),

Bit D13 (noise-delayed bit trials), and Bit D3 (I²C filters) are

enabled (set to 0). This configuration is appropriate for low

frequency applications because the bit trials are prevented from

occurring when there is activity on the I²C bus, thus ensuring

Table 23. Configuration Register Bit Function Description D15 to D8

Channel

The default configuration for Bit D3 (enabled) is recommended

for normal operation because it ensures that the I²C requirements

for t_Of(minimum) and t_SPare met. The I²C filters reject glitches

shorter than 50 ns. If this function is disabled, the conversion

results are more susceptible to noise from the I²C bus.

Bit

D15

D14

D13

D12

D11

D10

D9

D8

Function

Reserved

Noise-delayed

sampling. Use to

delay critical

sample intervals

from occurring

when there is

activity on the

I²C bus.

Noise-delayed

bit trials. Use to

delay critical bit

trials from

occurring when

there is activity

on the I²C bus.

Autocycle

mode

Pseudo

Differential

mode for

V_IN3/V_IN4

Differential

mode for

V_IN1/V_IN2

differential

mode for

V_IN3/V_IN4

differential

mode for

V_IN1/V_IN2

Setting

Enabled = 0

Disabled = 1

Enabled = 0

Disabled = 1

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Table 24. Configuration Register Bit Function Description D7 to D0

Channel

Bit

D7

D6

D5

D4

D3

I²C filters

D2

D1

D0

Function

2V_REFrange

for V_IN4

2V_REFrange

for V_IN3

2V_REFrange

for V_IN2

2V_REFrange

for V_IN1

ALERT pin

BUSY pin (D2 = 0),

clear alerts (D2 = 1)

Select ALERT

pin polarity

(active high/

active low)

Setting

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 1

Disabled = 0

Enabled = 0

Disabled = 1

Enabled

D2 = 1

D1 = 0

Enabled

D1 = 1 + D0 = 0

Disabled D1 = 0

Active high = 1

Active low = 0

Disabled

D2 = 0

Table 25. Alert/Busy Function Description

D2 D1

ALERT/BUSY Pin Functions

0

1

0

1

0

1

Pin does not provide any interrupt signal.

Configures pin as a busy output.

Configures pin as an alert output.

Resets the ALERT/BUSY output pin, the alert_flag bit in the conversion result register, and the entire alert status register (if any is

active). 1,1 is written to Bits[D2:D1] in the configuration register to reset the ALERT/BUSY pin, the alert_flag bit, and the alert status

register. Following this write, the contents of the configuration register read 1, 0 for Bit D2 and Bit D1, respectively, if read back.

Table 26. ADC Input Mode Example

D11

D10

D9

0

D8

0

1

Description

0

1

All channels single-ended

Differential mode on V_IN1/V_IN2

Pseudo differential mode on V_IN1/V_IN2

0

1

Rev. I | Page 31 of 47

AD7294

Data Sheet

POWER-DOWN REGISTER (0x0A)

Table 28. Default Values for DATA_HIGHand DATA_LOW

Registers

The power-down register is an 8-bit read/write register that

powers down various sections on the AD7294 device. On

power-up, the default value for the power-down register is 0x30.

The content of the power-down register is provided in Table 27.

Single-Ended

Differential

DATA_LOWDATA_HIGH

ADC

Channel

DATA_LOWDATA_HIGH

V_IN0

V_IN1

V_IN2

V_IN3

000

N/A

FFF

N/A

800

400

7FF

3FF

Table 27. Power-Down Register Description

Bit

D7

D6

D5

Function

Power down the full chip

Reserved

Power down the ADC reference buffer (to allow

external reference, 1 at power-up)

I_SENSE

1

2

T_SENSE

1

2

D4

Power down the DAC reference buffer (to allow

external reference, 1 at power-up)

T_SENSEINT

D3

D2

D1

D0

Power down the temperature sensor

Table 29. AD7294 DATA_HIGH

MSB

/

_LOWRegister (First Read/Write)

Power down I_SENSE

1

2

LSB

D15

D14 D13 D12 D11

B11

D10 D9

B10 B9

D8

DAC outputs set to high impedance (set

automatically if die temperature >150°C)

Alert_Flag

0

B8

Table 30. AD7294 DATA_{HIGH LOW}

MSB

/

Register (Second Read/Write)

In normal operation, the two MSBs of the I²C slave address are

set to 11 by an internal ROM. However, in full power-down

mode (power down by setting Bit D7 = 1), this ROM is switched

off and the slave address MSBs become 00. Therefore, to exit the

full-power-down state, it is necessary to write to the AD7294

using this modified slave address.

LSB

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

HYSTERESIS REGISTERS: 0X0D (VIN0), 0X10

(VIN1), 0X13 (VIN2), 0X16 (VIN3)

Each hysteresis register is a 16-bit read/write register wherein

only the 12 LSBs of the register are used; the MSB signals the

alert event. If FFF is written to the hysteresis register, the hyste-

resis register enters the minimum/maximum mode, see the

Alerts and Limits Theory section for further details.

After writing 0 to power down Bit D7, the slave address MSBs

return to their original 11 value.

DATA_HIGH/DATA_LOWREGISTERS: 0x0B, 0x0C (V_IN0);

0x0E, 0x0F (V_IN1); 0x11, 0x12 (V_IN2); 0x14, 0x15 (V_IN3)

The DATA_HIGHand DATA_LOWregisters for a channel are 16-bit,

read/write registers (see Table 29 and Table 30). General alert is

flagged by the MSB, D15. D14 to D12 are not used in the register

and are set to 0s. The remaining 12 bits set the high and low limits

for the relevant channel. For single-ended mode, the default values

for V_IN0 to V_IN3, are 000 and FFF in binary format. For differen-

tial mode on V_IN0 to V_IN3, the default values for DATA_HIGHand

DATA_LOWare 7FF and 800, twos complement format. Note that if

the device is configured in either single-ended or differential

mode and the mode is changed, the user must reprogram the

limits in the DATA_HIGHand DATA_LOWregisters.

Table 31. Hysteresis Register (First Read/Write)

MSB

LSB

D8

B8

D15

D14

D13

D12

D11

D10

D9

Alert_Flag

0

B11

B10

B9

Table 32. Hysteresis Register (Second Read/Write)

MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

Channel 7 to Channel 9 (T_SENSE1, T_SENSE2, and T_SENSEINT) default

to 3FF and 400 for the DATA_HIGHand DATA_LOWlimits because

they are in twos complement 11-bit format.

Rev. I | Page 32 of 47

Data Sheet

AD7294

The offset registers can be used to compensate for transistors

T_SENSEOFFSET REGISTERS (0x26 AND 0x27)

with different ideality factors because the T_SENSEresults are

based on the 2N3906 transistor ideality factor. Different

transistors with different ideality factors result in different

offsets within the region of interest, which can be compensated

for by using this register.

The AD7294 has temperature offset, 8-bit twos complement regis-

ters for both Remote Channel T_SENSE1 and Remote Channel T_SENSE2.

It allows the user to add or subtract an offset to the temperature.

The offset registers for T_SENSE1 and T_SENSE2 are 8-bit read/write

registers that store data in a twos complement format. This data

is subtracted from the temperature readings taken by T_SENSE1

and T_SENSE2 temperature sensors. The offset is implemented

before the values are stored in the T_SENSEresult register.

Table 33. T_SENSEOffset Data Format

MSB

D7

LSB

D0

Input

D6

D5 D4 D3 D2 D1

−32

+16 +8 +4 +2 +1 +0.5 +0.25

Value (°C)

Rev. I | Page 33 of 47

AD7294

Data Sheet

I²C INTERFACE

GENERAL I²C TIMING

communication with a single slave device for the duration of the

transaction.

Figure 50 shows the timing diagram for general read and write

operations using an I²C-compliant interface.

The transaction can be used either to write to a slave device

(data direction bit = 0) or to read data from it (data direction

bit = 1). In the case of a read transaction, it is often necessary

first to write to the slave device (in a separate write transaction)

to tell it from which register to read. Reading and writing

cannot be combined in one transaction.

The I²C bus uses open-drain drivers; therefore, when no device

is driving the bus, both SCL and SDA are high. This is known as

idle state. When the bus is idle, the master initiates a data transfer

by establishing a start condition, defined as a high-to-low

transition on the serial data line (SDA) while the serial clock line

(SCL) remains high. This indicates that a data stream follows. The

master device is responsible for generating the clock.

When the transaction is complete, the master can keep control

of the bus, initiating a new transaction by generating another

start bit (high-to-low transition on SDA while SCL is high). This

is known as a repeated start (Sr). Alternatively, the bus can be

relinquished by releasing the SCL line followed by the SDA line.

This low-to-high transition on SDA while SCL is high is known

as a stop bit (P), and it leaves the I²C bus in its idle state (no

current is consumed by the bus).

Data is sent over the serial bus in groups of nine bits—eight bits

of data from the transmitter followed by an acknowledge bit (ACK)

from the receiver. Data transitions on the SDA line must occur

during the low period of the clock signal and remain stable

during the high period. The receiver should pull the SDA line

low during the acknowledge bit to signal that the preceding byte

has been received correctly. If this is not the case, cancel the

transaction.

The example in Figure 50 shows a simple write transaction

with an AD7294 as the slave device. In this example, the

AD7294 register pointer is being set up ready for a future read

transaction.

The first byte that the master sends must consist of a 7-bit slave

address, followed by a data direction bit. Each device on the bus

has a unique slave address; therefore, the first byte sets up

SCL

SDA

R/W

A6

A5

SLAVE ADDRESS BYTE

USER PROGRAMMABLE 5 LSBs

A4

A3

A2

A1

A0

P7

P6

P5

P4

P3

P2

P1

P0

ACK. BY

AD7294

START COND

BY MASTER

ACK. BY STOP BY

AD7294 MASTER

REGISTER ADDRESS

Figure 50. General I²C Timing

Rev. I | Page 34 of 47

Data Sheet

AD7294

SERIAL BUS ADDRESS BYTE

INTERFACE PROTOCOL

The AD7294 uses the following I²C protocols.

The first byte the user writes to the device is the slave address

byte. Similar to all I²C-compatible devices, the AD7294 has a

7-bit serial address. The 5 LSBs are user-programmable by the

3 three-state input pins, as shown in Table 34.

Writing a Single Byte of Data to an 8-Bit Register

The alert registers (0x05, 0x06, 0x07), power-down register

(0x0A), channel sequence register (0x08), temperature offset

registers (0x26, 0x27), and the command register (0x00) are

8-bit registers; therefore, only one byte of data can be written to

each. In this operation, the master device sends a byte of data to

the slave device (see Figure 51). To write data to the register, the

command sequence is as follows:

In Table 34, H means tie the pin to V_DRIVE, L means tie the pin

to DGND, and NC refers to a pin left floating. Note that in this

final case, the stray capacitance on the pin must be less than

30 pF to allow correct detection of the floating state; therefore,

any PCB trace must be kept as short as possible.

Table 34. Slave Address Control Using Three-State Input Pins

1. The master device asserts a start condition.

2. The master sends the 7-bit slave address followed by a zero

for the direction bit, indicating a write operation.

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends a register address.

5. The slave asserts an acknowledge on SDA.

6. The master sends a data byte.

7. The slave asserts an acknowledge on SDA.

AS2

AS1

AS0

Slave Address (A6 to A0)

L

H

L

H

NC

L

H

NC

L

H

NC

L

H

NC

L

H

NC

L

H

NC

L

H

NC

L

H

NC

L

H

0x61

0x62

0x63

0x64

0x65

0x66

0x67

0x68

0x69

0x6A

0x6B

0x6C

0x6D

0x6E

0x6F

0x70

0x71

0x72

0x73

0x74

0x75

0x76

0x77

0x78

0x79

0x7A

0x7B

8. The master asserts a stop condition to end the transaction.

L

H

NC

L

H

NC

L

H

NC

Rev. I | Page 35 of 47

AD7294

Data Sheet

1

9

1

9

SCL

SDA

A6

A5 A4

A3 A2

FRAME 1

A1 A0

P7

P6

P5

P4

P3

P2

P1

P0

R/W

START BY

MASTER

ACK. BY

AD7294

ACK. BY

AD7294

FRAME 2

SLAVE ADDRESS BYTE

ADDRESS POINTER REGISTER BYTE

1

9

SCL (CONTINUED)

SDA (CONTINUED)

D7

D6

D5

D4

D3 D2

D1

D0

ACK. BY STOP BY

AD7294 MASTER

FRAME 3

DATA BYTE

S

SLAVE ADDRESS

0

A

REG POINTER

A

DATA

A

P

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REPEATED START

P = STOP CONDITION

A = ACKNOWLEDGE

A = NOT ACKNOWLEDGE

Figure 51. Single Byte Write Sequence

Rev. I | Page 36 of 47

Data Sheet

AD7294

Writing Two Bytes of Data to a 16-Bit Register

Writing to Multiple Registers

The limit and hysteresis registers (0x0B to 0x25), the result

registers (0x01 to 0x04), and the configuration register (0x09)

are 16-bit registers; therefore, two bytes of data are required to

write a value to any one of these registers. Writing two bytes of

data to one of these registers consists of the following sequence:

Writing to multiple address registers consists of the following:

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device (AD7294) asserts an

acknowledge on SDA.

4. The master sends a register address, for example the Alert

Status Register A register address. The slave asserts an

acknowledge on SDA.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

3. The addressed slave device asserts an acknowledge on SDA.

4. The master sends a register address. The slave asserts an

acknowledge on SDA.

5. The master sends the first data byte (most significant).

6. The slave asserts an acknowledge on SDA.

7. The master sends the second data byte (least significant).

8. The slave asserts an acknowledge on SDA.

9. The master asserts a stop condition on SDA to end the

transaction.

5. The master sends the data byte.

6. The slave asserts an acknowledge on SDA.

7. The master sends a second register address, for example

the configuration register. The slave asserts an

acknowledge on SDA.

8. The master sends the first data byte.

9. The slave asserts an acknowledge on SDA.

10. The master sends the second data byte.

11. The slave asserts an acknowledge on SDA.

12. The master asserts a stop condition on SDA to end the

transaction.

The previous examples detail writing to two registers only

(the Alert Status Register A and the configuration register).

However, the AD7294 can read from multiple registers in one

write operation as shown in Figure 53.

S

SLAVE ADDRESS

0

A

REG POINTER

A

DATA<15:8>

A

DATA<7:0>

A

P

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REPEATED START

P = STOP CONDITION

A = ACKNOWLEDGE

A = NOT ACKNOWLEDGE

Figure 52. Writing Two Bytes of Data to a 16-Bit Register

...

S

SLAVE ADDRESS

0

A

POINT TO PD REG (0x0A)

A

DATA<7:0>

A

POINT TO CONFIG REG (0x09)

A

...

DATA<15:8>

A

DATA<7:0>

A

P

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REPEATED START

P = STOP CONDITION

A = ACKNOWLEDGE

A = NOT ACKNOWLEDGE

Figure 53. Writing to Multiple Registers

Rev. I | Page 37 of 47

AD7294

Data Sheet

Reading Data from an 8-Bit Register

Reading Two Bytes of Data from a 16-Bit Register

Reading the contents from any of the 8-bit registers is a single

byte read operation, as shown in Figure 55. In this protocol, the

first part of the transaction writes to the register pointer. When

the register address has been set up, any number of reads can be

performed from that particular register without having to write

to the address pointer register again. When the required number

of reads is completed, the master should not acknowledge the final

byte. This tells the slave to stop transmitting, allowing a stop

condition to be asserted by the master. Further reads from this

register can be performed in a future transaction without

having to rewrite to the register pointer.

In this example, the master device reads three lots of two-byte

data from a slave device, but as many lots consisting of two-

bytes can be read as required. This protocol assumes that the

particular register address has been set up by a single byte write

operation to the address pointer register (see the previous read

example).

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge

on SDA.

If a read from a different address is required, the relevant

register address has to be written to the address pointer register,

and again, any number of reads from this register can then be

performed. In the next example, the master device receives two

bytes from a slave device as follows:

4. The master receives a data byte.

5. The master asserts an acknowledge on SDA.

6. The master receives a second data byte.

7. The master asserts an acknowledge on SDA.

8. The master receives a data byte.

9. The master asserts an acknowledge on SDA.

10. The master receives a second data byte.

11. The master asserts an acknowledge on SDA.

12. The master receives a data byte.

13. The master asserts an acknowledge on SDA.

14. The master receives a second data byte.

15. The master asserts a no acknowledge on SDA to notify the

slave that the data transfer is complete.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

read bit (high).

3. The addressed slave device asserts an acknowledge

on SDA.

4. The master receives a data byte.

5. The master asserts an acknowledge on SDA.

6. The master receives another 8-bit data byte.

7. The master asserts a no acknowledge (NACK) on SDA to

inform the slave that the data transfer is complete.

8. The master asserts a stop condition on SDA, and the

transaction ends.

16. The master asserts a stop condition on SDA to end the

transaction.

...

S

SLAVE ADDRESS

1

A

DATA<15:8>

A

DATA<7:0>

A

DATA<15:8>

A

DATA<7:0>

A

...

DATA<15:8>

DATA<7:0>

S = START CONDITION

A

P

FROM MASTER TO SLAVE

SR = REPEATED START

P = STOP CONDITION

A = ACKNOWLEDGE

FROM SLAVE TO MASTER

A = NOT ACKNOWLEDGE

Figure 54. Reading Three Lots of Two Bytes of Data from the Conversion Result Register

...

S

SLAVE ADDRESS

0

A

REG POINTER

A

SR

SLAVE ADDRESS

1

A

DATA<7:0>

A

...

DATA<7:0>

A

P

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

SR = REPEATED START

P = STOP CONDITION

A = ACKNOWLEDGE

A = NOT ACKNOWLEDGE

Figure 55. Reading Two Single Bytes of Data from a Selected Register

Rev. I | Page 38 of 47

Data Sheet

AD7294

MODES OF OPERATION

There are two different methods of initiating a conversion on

the AD7294: command mode and autocycle mode.

3. The addressed slave device (AD7294) asserts an

acknowledge on SDA.

4. The master sends the Command Register Address 0x00.

The slave asserts an acknowledge on SDA.

5. The master sends the Data Byte 0x13, which selects the

V_IN0, V_IN1, and I_SENSE1 channels.

6. The slave asserts an acknowledge on SDA.

7. The master sends the result register address (0x01). The

slave asserts an acknowledge on SDA.

8. The master sends the 7-bit slave address followed by the

write bit (high).

COMMAND MODE

In command mode, the AD7294 ADC converts on-demand on

either a single channel or a sequence of channels. To enter this

mode, the required combination of channels is written into the

command register (0x00). The first conversion takes place at the

end of this write operation, in time for the result to be read out

in the next read operation. While this result is being read out,

the next conversion in the sequence takes place, and so on.

9. The slave (AD7294) asserts an acknowledge on SDA.

10. The master receives a data byte, which contains the

alert_flag bit, the channel ID bits, and the four MSBs of the

converted result for Channel V_IN0. The master then asserts

an acknowledge on SDA.

11. The master receives the second data byte, which contains

the eight LSBs of the converted result for Channel V_IN0.

The master then asserts on acknowledge on SDA.

12. Point 10 and Point 11 repeat for Channel V_IN1 and

Channel I_SENSE1.

13. Once the master has received the results from all the

selected channels, the slave again converts and outputs

the result for the first channel in the selected sequence.

Point 10 to Point 12 are repeated.

14. The master asserts a no acknowledge on SDA and a stop

condition on SDA to end the conversion and exit

command mode.

To exit the command mode, the master should not acknowledge

the final byte of data. This stops the AD7294 transmitting,

allowing the master to assert a stop condition on the bus. It is

therefore important that, after writing to the command register,

a repeated start (Sr) signal be used rather than a stop (P) followed

by a start (S) when switching to read mode; otherwise, the

command mode exits after the first conversion.

After writing to the command register, the register pointer is

returned to its previous value. If a new pointer value is required

(typically the ADC Result Register 0x01), it can be written

immediately following the command byte. This extra write

operation does not affect the conversion sequence because the

second conversion triggers only at the start of the first read

operation.

The maximum throughput that can be achieved using this

mode with a 400 kHz I²C clock is (400 kHz/18) = 22.2 kSPS.

Figure 56 shows the command mode converting on a sequence

of channels including V_IN0, V_IN1, and I_SENSE1.

The AD7294 automatically exits command mode if no read

occurs in a 5 ms period. To change the conversion sequence,

rewrite a new sequence to the command mode.

1. The master device asserts a start condition on SDA.

2. The master sends the 7-bit slave address followed by the

write bit (low).

*

S

SLAVE ADDRESS

0

A

POINT TO COMMAND REG (0x00)

A

COMMAND = 0x13

A

*

...

V

0<11:8>

...

POINT TO RESULT REG (0x01)

A

SR

SLAVE ADDRESS

1

A

ALERT?

CH ID (000)

IN

A

*

...

V

0<7:0>

V

1<11:8>

V

1<7:0>

IN

A

ALERT?

CH ID (001)

IN

A

IN

A

... ^*

*

...

I

1<11:8>

I

1<7:0>

V

0<11:8>

IN

ALERT?

CH ID (100)

SENSE

A

SENSE

A

ALERT?

CH ID (000)

A

FROM MASTER TO SLAVE

FROM SLAVE TO MASTER

S = START CONDITION

...

........

I

1<7:0>

V

0<7:0>

A

P

SENSE

IN

SR = REPEATED START

P = STOP CONDITION

A = ACKNOWLEDGE

*

= POSITION OF A CONVERSION START

A = NOT ACKNOWLEDGE

Figure 56. Command Mode Operation

Rev. I | Page 39 of 47

AD7294

Data Sheet

proceeding to the command mode. This is achieved either by clear-

ing Bit D12 of the configuration register or by writing 0x00 to the

channel sequence register. When the command mode conversion is

complete, the user must exit command mode by issuing a stop

condition before reenabling autocycle mode.

AUTOCYCLE MODE

The AD7294 can be configured to convert continuously on a

programmable sequence of channels making it the ideal mode

of operation for system monitoring. These conversions take

place in the background approximately every 50 µs, and are

transparent to the master. Typically, this mode is used to

automatically monitor a selection of channels with either the

limit registers programmed to signal an out-of-range condition

via the alert function or the minimum/maximum recorders

tracking the variation over time of a particular channel. Reads

and writes can be performed at any time (the ADC Result

Register 0x01 contains the most recent conversion result).

When switching out of autocycle mode to command mode,

the temperature sensor must be given sufficient time to settle

and complete a new temperature integration cycle. Therefore,

temperature sensor conversions performed within the first

500 ms after switching from autocycle mode to command mode

may result in false temperature high and low alarms being

triggered. It is recommended to disable temperature sensor

alarms for the first 500 ms after mode switching by writing

0x400 to the DATA_LOWT_SENSEx register and 0x3FF to the

DATA_HIGHregister T_SENSEx. The temperature sensor alerts should

be reconfigured to the desired alarm level once the 500 ms has

elapsed. Alternatively, temperature alerts triggered during the

first 500 ms after mode switching should be ignored.

On power up, this mode is disabled. To enable this mode, write

to Bit D12 in the configuration register (0x09) and select the

desired channels for conversion in the channel sequence

register (0x08).

If a command mode conversion is required while the autocycle

mode is active, it is necessary to disable the autocycle mode before

Rev. I | Page 40 of 47

Data Sheet

AD7294

ALERTS AND LIMITS THEORY

the I_SENSE1 OVERRANGE and I_SENSE2 OVERRANGE of V_REF/10.41.

During power-up, it is possible for the fault outputs to be trig-

gered, depending on which supply comes up first. Clearing these

bits as part of the initialization routine is recommended on

power-up by writing a 1 to both D4 and D5.

ALERT_FLAG BIT

The alert_flag bit indicates whether the conversion result being

read or any other channel result has violated the limit registers

associated with it. If an alert occurs and the alert_flag bit is set,

the master can read the alert status register to obtain more

information on where the alert occurred.

Internal circuitry in the AD7294 can alert if either the D1 or

the D2 input pins for the external temperature sensor are open

circuit. The most significant bit of Register C (see Table 21)

alerts the user when an open diode flag occurs on the external

temperature sensors. If the internal temperature sensor detects

an AD7294 die temperature greater than 150°C, the overtem-

perature alert bit, Bit D6 in Register C, is set and the DAC

outputs are set to a high impedance sate. The remaining six

bits in Register 6 store alert event data for T_SENSE1, T_SENSE2, and

ALERT STATUS REGISTERS

The alert status registers are 8-bit read/write registers that provide

information on an alert event. If a conversion results in activa-

tion of the ALERT/BUSY pin or the alert_flag bit in the result

register or T_SENSEregisters, the alert status register can be read to

get more information (see Figure 57 for the alert register

structure).

T

_SENSEINT with two status bits per channel, one corresponding to

V

3 HIGH ALERT

3 LOW ALERT

D7

D6

D5

D4

D3

D2

D1

D0

IN

V

each of the DATA_HIGHand DATA_LOWlimits.

IN

2 HIGH ALERT

IN

V

2 LOW ALERT

IN

To clear the full content of any one of the alert registers, write a

code of FF (all ones) to the relevant registers. Alternatively, the

user can write to the respective alert bit in the selected alert

register to clear the alert associated with that bit. The entire

contents of all the alert status registers can be cleared by writing

a 1 to Bit D1 and Bit D2 in the configuration register, as shown

in Table 24. However, this operation then enables the ALERT/

BUSY pin for subsequent conversions.

ALERT

REGISTER

A

1 HIGH ALERT

1 LOW ALERT

IN

V

IN

0 HIGH ALERT

IN

V

0 LOW ALERT

IN

RESERVED

2 OVERRANGE*

1 OVERRANGE*

2 HIGH ALERT

2 LOW ALERT

D7

D6

D5

D4

D3

D2

D1

D0

I

SENSE

ALERT

FLAG

ALERT/BUSY

ALERT

REGISTER

B

SENSE

I

OR

SENSE

I

SENSE

I

1 HIGH ALERT

1 LOW ALERT

DATA_HIGHAND DATA_LOWMONITORING FEATURES

SENSE

CONFIGURATION

REGISTER

D2 = 1, D1 = 0

I

SENSE

The AD7294 signals an alert (in either hardware via the

ALERT/BUSY pin, software via the alert_flag bit, or both,

depending on the configuration) if the result moves outside the

upper or lower limit set by the user.

OPEN DIODE FLAG*

OVER TEMP ALERT*

D7

D6

D5

D4

D3

D2

D1

D0

T

INT HIGH ALERT

INT LOW ALERT

2 HIGH ALERT

SENSE

ALERT

REGISTER

C

T

SENSE

T

SENSE

The DATA_HIGHregister stores the upper limit that activates the

ALERT/BUSY output pin and/or the alert_flag bit in the conver-

sion result register. If the conversion result is greater than the value

in the DATA_HIGHregister, an alert occurs. The DATA_LOWregister

stores the lower limit that activates the ALERT/BUSY output pin

and/or the alert_flag bit in the conversion result register. If the

conversion result is less than the value in the DATA_LOWregister,

an alert occurs.

T

2 LOW ALERT

1 HIGH ALERT

1 LOW ALERT

SENSE

T

SENSE

T

SENSE

*THESE BITS ARE ALWAYS ACTIVE, ALL OTHER BITS CAN BE

PROGRAMMED TO BE ACTIVE OR NOT AS REQUIRED.

Figure 57. Alert Register Structure

Register A (see Table 19) consists of four channels with two status

bits per channel, one corresponding to each of the DATA_HIGHand

DATA_LOWlimits. It stores the alert event data for V_IN3 to V_IN0,

which are the standard voltage inputs. When the content of this

register is read, any bit with a status of 1 indicates a violation of

its associated limit; that is, it identifies the channel and whether

the violation occurred on the upper or lower limit. If a second

alert event occurs on another channel before the content of the

alert register has been read, the bit corresponding to the second

alert event is also set.

An alert associated with either the DATA_HIGHor DATA_LOW

register is cleared automatically once the monitored signal is

back in range; that is, the conversion result is between the limits.

The content of the alert register is updated after each conversion.

A conversion is performed every 50 µs in autocycle mode, so

the content of the alert register may change every 50 µs. If the

ALERT pin signals an alert event and the content of the alert

register is not read before the next conversion is complete, the

content of the register may be changed if the signal being

monitored returns between the prespecified limits. In these

circumstances, the ALERT pin no longer signals the

occurrence of an alert event.

Register B (see Table 20) consists of three channels also with

two status bits per channel, representing the specified DATA_HIGH

and DATA_LOWlimits. Bits[D3:D0] correspond to the high and low

limit alerts for the current sense inputs. Bit D4 and Bit D5 represent

Rev. I | Page 41 of 47

AD7294

Data Sheet

The hysteresis register can be used to avoid flicker on the ALERT/

BUSY pin. If the hysteresis function is enabled, the conversion

result must return to a value of at least N LSB below the DATA_HIGH

register value, or N LSB above the DATA_LOWregister value for the

ALERT/BUSY output pin and alert_flag bit to be reset. The value of

N is taken from the 12-bit hysteresis register associated with that

channel. By setting the hysteresis register to a code close to the

maximum output code for the ADC, that is, 0x77D, DATA_HIGH

or DATA_LOWalerts do not clear automatically by the AD7294.

of 8 LSBs is required on the upper and lower limits of V_IN0,

the 16-bit word 0000 0000 0000 1000 should be written to the

hysteresis register of V_IN0 (see Table 9). On power-up, the

hysteresis registers contain a value of 8 LSBs for nontempera-

ture result registers and 8°C, or 32 LSBs, for the T_SENSEregisters.

If a different hysteresis value is required, that value must be

written to the hysteresis register for the channel in question.

The advantage of having hysteresis registers associated with

each of the limit registers is that it prevents chatter on the alert

bits associated with each ADC channel. Figure 58 shows the

limit checking operation.

Bit D11 of the T_SENSEDATA_HIGHor DATA_LOWlimit registers is

the diode open-circuit flag. If this bit is set to 0, it indicates the

presence of an open circuit between the Dx+ and Dx− pins. An

alert triggered on either I_SENSEOVERRANGE pin remains until it

is cleared by the user writing to the alert register. The contents

of the DATA_HIGHand DATA_LOWregisters are reset to their default

values on power-up (see Table 28).

Using the Limit Registers to Store Minimum/Maximum

Conversion Results

If FFF is written to the hysteresis register for a particular channel,

the DATA_HIGHand DATA_LOWregisters for that channel no longer

act as limit registers as previously described, but act as storage

registers for the maximum and minimum conversion results.

This function is useful when an alert signal is not required in an

application, but it is still required to monitor the minimum and

maximum conversion values over time. Note that on power-up,

the contents of the DATA_HIGHregister for each channel are set to

maximum code, whereas the contents of the DATA_LOWregisters

are set to minimum code by default.

HYSTERESIS

The hysteresis value determines the reset point for the ALERT/

BUSY pin and/or alert_flag bit if a violation of the limits occurs.

The hysteresis register stores the hysteresis value, N, when using

the limit registers. Each pair of limit registers has a dedicated

hysteresis register. For example, if a hysteresis value

HIGH LIMIT

HIGH LIMIT – HYSTERESIS

INPUT SIGNAL

LOW LIMIT + HYSTERESIS

LOW LIMIT

ALERT SIGNAL

TIME

Figure 58. Limit Checking

Rev. I | Page 42 of 47

Data Sheet

AD7294

APPLICATIONS INFORMATION

The AD7294 contains all the functions required for general-

purpose monitoring and control of current, voltage, and

temperature. With its 59.4 V maximum common-mode range,

the device is useful in industrial and automotive applications where

current sensing in the presence of a high common-mode voltage

is required. For example, the device is ideally suited for monitoring

and controlling a power amplifier in a cellular base station.

bringing considerable board area savings over alternative

solutions.

The circuit in Figure 59 is a typical system connection diagram

for the AD7294. The device monitors and controls the overall

performance of two final stage amplifiers. The gain control and

phase adjustment of the driver stage are incorporated in the

application and are carried out by the two available uncommitted

outputs of the AD7294. Both high-side current senses measure

the amount of current on the respective final stage amplifiers.

BASE STATION POWER AMPLIFIER MONITOR AND

CONTROL

The comparator outputs, I_SENSE1 OVERRANGE and I_SENSE

2

The AD7294 is used in a power amplifier signal chain to

achieve the optimal bias condition for the LDMOS transistor.

The main factors influencing the bias conditions are tempera-

ture, supply voltage, gate voltage drift, and general processing

parameters. The overall performance of a power amplifier

configuration is determined by the inherent tradeoffs required

in efficiency, gain, and linearity. The high level of integration

offered by the AD7294 allows the use of a single chip to

dynamically control the drain bias current to maintain a constant

value over temperature and time, thus significantly improving

the overall performance of the power amplifier. The AD7294

incorporates the functionality of eight discrete components

OVERRANGE pins, are the controlling signals for switches

on the RF inputs of the LDMOS power FETs. If the high-side

current sense reads a value above a specified limit compared

with the setpoint, the RF IN signal is switched off by the

comparator.

By measuring the transmitted power (Tx) and the received

power (Rx), the device can dynamically change the drivers and

PA signal to optimize performance. This application requires a

logarithmic detector/controller, such as Analog Devices AD8317 or

AD8362.

R

SENSE

V

R

RF CHOKE

DD

SENSE

RS2(–)

RS1(–)

RS1(+)

RS2(+)

RS2(–)

HIGH SIDE

CURRENT

SENSE

HIGH SIDE

CURRENT

SENSE

RF IN

AD7294*

I

2

SENSE

RF OUT

OVERRANGE

V

A

OUT

RF CUTOFF

12-BIT

DAC

LDMOS

FILTER

I

1

SENSE

OVERRANGE

SET-POINT

240mV

RF IN

RF OUT

LDMOS

V

0

Tx

POWER

Tx POWER

MONITOR

IN

V

B

OUT

12-BIT

DAC

12-BIT

ADC

MUX

V

1

2

3

IN

REF

Rx

POWER

Rx POWER

MONITOR

REF

V

C

D

OUT

GAIN

CONTROL

12-BIT

DAC

D1+

D2+

OUT

GAIN

CONTROL

12-BIT

DAC

T1

T2

TEMP

SENSOR

D2–

D1–

*ADDITIONAL PINS OMITTED FOR CLARITY.

Figure 59. Typical HPA Monitor and Control Application

Rev. I | Page 43 of 47

AD7294

Data Sheet

feedback loop that tracks the output of the AD8362 and adjusts

the VSET input of the AD8362 accordingly.

GAIN CONTROL OF POWER AMPLIFIER

In gain control mode, a setpoint voltage, proportional in dB to

the desired output power, is applied to a power detector such as

the AD8362. A sample of the output power from the power

amplifier (PA), through a directional coupler and attenuator (or

by other means), is fed to the input of the AD8362. The VOUT

is connected to the gain control terminal of the PA, see Figure 60.

Based on the defined relationship between VOUT and the RF

input signal, the AD8362 adjusts the voltage on VOUT (VOUT

is now an error amplifier output) until the level at the RF input

corresponds to the applied VSET. The AD7294 completes a

VOUT of the AD8362 is applied to the gain control terminal of

the power amplifier. For this output power control loop to be

stable, a ground referenced capacitor must be connected to the

CLPF pin. This capacitor integrates the error signal (which is

actually a current) that is present when the loop is not balanced.

In a system where a variable gain amplifier (VGA) or variable

voltage attenuator (VVA) feeds the power amp, only one AD8362

is required. In such a case, the gain on one of the devices (VVA,

PA) is fixed and V_OUTfeeds the control input of the other.

ENVELOPE OF

TRANSMITTED

SIGNAL

POWER

AMPLIFIER

RF IN

DIRECTIONAL

COUPLER

ATTENUATOR

AD7294

C7

0.1nF

C5

1nF

V

IN

AD8362

T2

INHI

VOUT

1:4

INLO

V

VSET

OUT

C6

0.1nF

C

LPF

Figure 60. Setpoint Controller Operation

Rev. I | Page 44 of 47

Data Sheet

AD7294

LAYOUT AND CONFIGURATION

Take the following precautions:

POWER SUPPLY BYPASSING AND GROUNDING

For optimum performance, carefully consider the power supply

and ground return layout on any PCB where the AD7294 is

used. The PCB containing the AD7294 should have separate

analog and digital sections, each having its own area of the

board. The AD7294 should be located in the analog section

on any PCB.

•

Place the remote sensing diode as close as possible to

the AD7294. If the worst noise sources are avoided, this

distance can be 4 inches to 8 inches.

Route the D+ and D− tracks close together, in parallel,

with grounded guard tracks on each side. Provide a ground

plane under the tracks, if possible.

Use wide tracks to minimize inductance and reduce noise

pickup. A 10 mil track minimum width and spacing is

recommended, as shown in Figure 61.

Decouple the power supply to the AD7294 to ground with

10 µF and 0.1 µF capacitors. Place the capacitors as physically

close as possible to the device, with the 0.1 µF capacitor ideally

right up against the device. It is important that the 0.1 µF

capacitor have low effective series resistance (ESR) and low

effective series inductance (ESL); common ceramic types of

capacitors are suitable. The 0.1 µF capacitor provides a low

impedance path to ground for high frequencies caused by

transient currents due to internal logic switching. The 10 µF

capacitors are the tantalum bead type.

AGND

0.25mm

D1+

D1–

0.25mm

AGND

The power supply line should have as large a trace as possible to

provide a low impedance path and reduce glitch effects on the

supply line. Shield clocks and other components with fast

switching digital signals from other parts of the board by a

digital ground. Avoid crossover of digital and analog signals,

if possible. When traces cross on opposite sides of the board,

ensure that they run at right angles to each other to reduce

feedthrough effects on the board. The best board layout

technique is the microstrip technique where the component

side of the board is dedicated to the ground plane only and the

signal traces are placed on the solder side; however, this is not

always possible with a 2-layer board.

0.25mm

Figure 61. Arrangement of Signal Tracks

•

Try to minimize the number of copper/solder joints

because they can cause thermocouple effects. Where

copper/solder joints are used, make sure that they are

in both the Dx+ and Dx− path and are at the same

temperature.

Place a 10 pF capacitor between the base and emitter of the

discrete diode, as close as possible to the diode.

If the distance to the remote sensor is more than 20 cm, the

use of twisted-pair cable is recommended.

•

Layout Considerations for External Temperature Sensors

Because the measurement technique uses switched current

sources, excessive cable and/or filter capacitance can affect the

measurement. When using long cables, the filter capacitor can

be reduced or removed.

Power amplifier boards can be electrically noisy environments.

Take care to protect the analog inputs from noise, particularly

when measuring the very small voltages from a remote diode

sensor.

Rev. I | Page 45 of 47

AD7294

Data Sheet

OUTLINE DIMENSIONS

9.20

9.00 SQ

8.80

1.20

MAX

0.75

0.60

0.45

64

49

48

1

PIN 1

7.20

7.00 SQ

6.80

TOP VIEW

(PINS DOWN)

0° MIN

1.05

1.00

0.95

0.20

0.09

7°

3.5°

0°

0.08 MAX

COPLANARITY

33

32

16

0.15

0.05

17

SEATING

PLANE

VIEW A

0.40

BSC

0.23

0.18

0.13

LEAD PITCH

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-ABD

Figure 62. 64-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-64-1)

Dimensions shown in millimeters

8.10

8.00 SQ

7.90

0.30

0.23

0.18

PIN 1

INDICATOR

PIN 1

INDICATOR

43

42

56

1

0.50

BSC

EXPOSED

PAD

*

6.25

6.10 SQ

5.95

29

28

14

15

0.50

0.40

0.30

BOTTOM VIEW

6.50 REF

0.25 MIN

TOP VIEW

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.20 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-WLLD-2

WITH EXCEPTION TO EXPOSED PAD DIMENSION.

Figure 63. 56-Lead Lead Frame Chip Scale Package [LFCSP]

8 mm × 8 mm body and 0.75mm Package Height

(CP-56-11)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

AD7294BSUZ

AD7294BSUZRL

AD7294BCPZ

AD7294BCPZRL

EVAL-AD7294EBZ

Temperature Range

−40°C to +105°C

Package Description

Package Option

SU-64-1

CP-56-11

64-Lead Thin Plastic Quad Flat Package [TQFP]

56-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Board

¹Z = RoHS Compliant Part.

Rev. I | Page 46 of 47

Data Sheet

NOTES

AD7294

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

D05747-0-2/16(I)

Rev. I | Page 47 of 47


型号：	AD7294BSUZ
厂家：	ADI
描述：	12-Bit Monitor and Control System with Multichannel
文件：	总48页 (文件大小：1341K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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