AD7294 [ADI]
12-Bit, Multichannel, DAC/ADC Temperature Sensor and Current Sense for Monitor and Control Applications; 12位，多通道， DAC / ADC温度传感器和电流检测的监控和控制应用
| 型号： | AD7294 |
| 厂家： | 
ADI |
| 描述： | 12-Bit, Multichannel, DAC/ADC Temperature Sensor and Current Sense for Monitor and Control Applications |
| 文件： | 总45页 (文件大小：683K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit, Multichannel, DAC/ADC Temperature Sensor and
Current Sense for Monitor and Control Applications
Preliminary Technical Data
AD7294
FEATURES
GENERAL DESCRIPTION
4-channel 12-bit DAC
Guaranteed monotonic
10 μs settling time
10 mA sink and source capability
Offset in for range adjustment
Output span: 5 V in 0 to 15 V range
9-channel, 12-bit ADC
The AD7294 contains all the functions required for general-
purpose monitoring and control of current, voltage, and
temperature integrated into a single-chip solution. The part
includes low voltage ( 2ꢀꢀ mꢁV analog-input sense amplifiers
for current monitoring across shunt resistors, temperature-sense
inputs, and four uncommitted analog input channels multiplexed
into a 2ꢀꢀ kSPS SAR ADC. An internal low ppm reference is
provided to drive both the DAC and ADC. Four 12-bit DACs
provide the outputs for voltage control. The AD7294 also includes
limit registers for alarm functions. The part is designed on a high
voltage DMOS process for a high voltage compliance, 48 ꢁ on
the current-sense inputs, and up to 15 ꢁ DAC output voltage.
200 kSPS throughput
Input range: 0 to VREF, 0 to 2 VREF
Differential/single-ended
Limit registers per channel
2 high-side current sense
48 V max operation
1ꢀ FS accuracy
200 mV input range
3-channel temperature sensor
Diode temperature measurement
2ꢁC accuracy
The part is ideal for bias current control of the power transistors
used in power amplifiers employed in CDMA, GSM, EDGE, and
UMTS cellular base stations.
Measurement range: −10ꢁC to +90ꢁC
Internal 2.5 V reference
The DACs provide digital control with 1.2 mꢁ resolution to
control the bias currents of the power transistors. They can also
be used to provide control voltages for variable gain amplifiers
or impedance match networks in the main signal chain. Thermal
diode based temperature sensors are incorporated to compensate
for temperature effects. The ADC monitors the high-side current
I2C®-compatible serial interface
Temperature range: −40ꢁC to +105ꢁC
Alert function
Package type: LFCSP-56, TQFP-64
APPLICATIONS
Cellular base station (GSM, EDGE, UMTS, CDMA)
Point-to-multipoint and other RF transmission systems
12 V, 24 V, 48 V automotive applications
Industrial control
and temperature. All this functionality is provided in a 56-lead
LFCSP package and a 64-lead TQFP package operating over a
temperature range of −4ꢀ°C to +1ꢀ5°C.
FUNCTIONAL BLOCK DIAGRAM
R Sense
REFOUT/
REFIN ADC
REFOUT/
REFIN DAC
RS1(+)
AV D D (1 - 5) AGND(1-9)
V+(1-2)
VPP(1-2)
RS1(-)
RS2(+) RS2(-)
RF CHOKE
HIGH SIDE
CURRENT
SENSE
HIGH SIDE
CURRENT
SENSE
2.5V
REF
RF OUT
100K
200K
12-BIT
DAC
ISENSE
2
VOUT A
OVER-RANGE
LDMOS
FILTER
SET-POINT
240mV
100K
200K
ISENSE1
OVER-RANGE
OFFSET IN A
VIN 0
100K
200K
200K
12-BIT
ADC
12-BIT
DAC
VIN 1
VIN 2
VIN 3
D1 (+)
MUX
VOUT B
LDMOS
FILTER
100K
200K
D0 (+)
OFFSET IN B
LIMIT
REGISTERS
100K
12-BIT
DAC
VOUT C
GAIN
CONTROL
T0
T1
TEMP
SENSOR
100K
200K
D0 (-)
D1 (-)
OFFSET IN C
VOUT D
100K
200K
12-BIT
DAC
CONTROL
LOGIC
IMPEDANCE
MATCH
100K
AD7294
200K
I2C INTERFACE
PROTOCOL
OFFSET IN D
DVDD
DGND(1-2)
SDA
SCL A2 A1
CAP ALERT
A0
Figure 1. Typical Configuration for AD7294 in Cellular Base Station RF LDMOS Power Amplifier Control
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2006 Analog Devices, Inc. All rights reserved.
AD7294
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Gain Control Of PA ................................................................... 24
Analog Comparator Loop......................................................... 24
Register Setting ............................................................................... 25
Address Point Register............................................................... 25
ADC Channel Allocation.......................................................... 25
Command Register .................................................................... 26
Result Register ............................................................................ 26
TSENSE1, TSENSE2 Result Registers................................................ 28
TSENSEINT Result Register.......................................................... 28
TSENSE Offset Registers................................................................ 28
Alert Status Registers ................................................................. 28
Channel Sequence Register....................................................... 28
Configuration Register .............................................................. 28
Sample Delay and Bit Trial Delay............................................. 3ꢀ
Power-Down Register................................................................ 3ꢀ
DATAHIGH/DATALOW Register................................................... 3ꢀ
Hysteresis Registers.................................................................... 31
Serial Bus Interface......................................................................... 32
General I2C Timing.................................................................... 32
Serial Bus Address Byte ............................................................. 33
Writing/Reading to the AD7294.............................................. 34
Modes Of Operation...................................................................... 4ꢀ
Mode 1 – Command Mode....................................................... 4ꢀ
Mode 2 – Autocycle Mode ........................................................ 41
Layout and Configuration............................................................. 42
Power Supply Bypassing and Grounding................................ 42
Evaluation Board For the AD7294............................................... 43
Outline Dimensions....................................................................... 47
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
DAC Specifications....................................................................... 3
ADC Specifications ...................................................................... 4
General Specifications ................................................................. 7
Timing Characteristics, ................................................................ 8
Absolute Maximum Ratings............................................................ 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 1ꢀ
Terminology .................................................................................... 12
System Description......................................................................... 13
ADC Information....................................................................... 14
ADC Operation .......................................................................... 14
ADC Transfer Functions ........................................................... 14
Analog Inputs.............................................................................. 15
Digital Inputs .............................................................................. 17
ꢁDRIꢁE ............................................................................................ 17
DAC Operation........................................................................... 18
Current Sensor............................................................................ 19
Temperature Sensor ................................................................... 2ꢀ
Reference for ADC/DAC........................................................... 21
Analog Comparator Loop ......................................................... 22
Applications..................................................................................... 23
Typical RF Front-End Application........................................... 23
REVISION HISTORY
10/05—Revision PrA: Preliminary Version
Rev. PrB | Page 2 of 45
Preliminary Technical Data
AD7294
SPECIFICATIONS
DAC SPECIFICATIONS1
AꢁDD = DꢁDD 4.5 ꢁ to 5.5 ꢁ, AGND = DGND= ꢀ ꢁ, external 2.5 ꢁ reference. Temperature range for B version: −4ꢀ°C to +1ꢀ5°C. All
specifications TMIN to TMAX, unless otherwise noted. Offset pin is open, so range is from ꢀ to 5ꢁ.
Table 1.
Parameter
Min
Typ
Max
Unit
Test Conditions / Comments
ACCURACY
Resolution
12
Bits
LSB
LSB
mV
Relative Accuracy (INL)
Differential Nonlinearity (DNL)
Zero-Scale Error
±4
±1
4
Guaranteed monotonic
Full-Scale Error
Offset Error
TBD
±4
mV
Measured in the linear region
Offset Error TC
Gain Error
Gain Temperature Coefficient
DC Crosstalk
±5
2
µV/°C
% FSR
ppm FSR/°C
LSB
±±.±24
±.5
DAC OUTPUT CHARACTERISTICS
Output Voltage Range
Output Voltage Span
±
±
5
15
V
V
With a 2.5 V internal reference
The 5 V o/p voltage range can be
positioned on the span by the offset
Output Voltage Settling Time
Slew Rate
Output Noise Spectral Density
Short-Circuit Current
Load Current
TBD
TBD
TBD
4±
±1±
mA
mA
FS current shorted to ground
Source/Sink within 2±± mV of supply
Capacitive Load Stability
RL = ∞
DC Output Impedance
Power Supply Sensitivity
∆Vout/∆ΑVDD
1±±±
±.5
pF
Ω
–85
75
dB
OFFSET INPUT
Input Range
±
V
V
kΩ
VOUT = 3 VOFFSET − 2VREF + VDAC
5
DC Input Impedance
REFERENCE
Reference Output Voltage
Reference Input Voltage Range
DC Leakage Current
2.49
±.1
2.51
2.5
±3±
V
V
µA
Input Capacitance
VREF Output Impedance
Reference Temperature Coefficient
2±
25
pF
Ω
ppm/°C
25
1± ppm/°C typ
1 Guaranteed by design and characterization; not subject to production testing.
Rev. PrB | Page 3 of 45
AD7294
Preliminary Technical Data
ADC SPECIFICATIONS1
AꢁDD = DꢁDD 4.5 ꢁ to 5.5 ꢁ, AGND = DGND= ꢀ ꢁ, external 2.5 ꢁ reference. Temperature range for B version: −4ꢀ°C to +1ꢀ5°C. All
specifications TMIN to TMAX, unless otherwise noted.
Parameter
Min
Typ
Max
Unit
Test Conditions / Comments
ACCURACY
Resolution
Integral Nonlinearity (INL)
12
±±.5
Bits
LSB
±1
±1
Differential Mode
Single Ended or Pseudo-Differential
Mode
Differential Mode
Single Ended or Pseudo-Differential
Mode
Differential Nonlinearity (DNL)
LSB
Offset Error
Gain Error
Total Unadjusted Error (TUE)
Conversion Rate
±3
±2
TBD
3
LSB
LSB
LSB
μS
Analog Input Range
Input Capacitance
DC Input Leakage Current
TEMPERATURE SENSOR
Accuracy
±
VREF or 2 VREF
V
pF
µA
3±
±1
±2
±2
°C
°C
External temperature sensors × 2
TA = −1±°C to +9±°C
Internal temperature sensor
TA = −1±°C to +9±°C
Accuracy
Resolution
Low Level Output Current Source
Medium Level Output Current
Source
11
8
32
Bits
µA
µA
±.25 °C LSB size
High Level Output Current Source
CURRENT SENSE
128
µA
Common-Mode Input Range
Full-Scale Sense Voltage
RS(+) and RS(−) Input Bias Current
CMRR / PSRR
Maximum Series Resistance for
external diode
AVDD
48
V
±2±± mV Full Scale Voltage
2±±
25
8±
mV
µA
dB
k Ω
Pin connected to power supply
TA = TMIN to TMAX
1±
±1
Gain
% FS
Accuracy
Offset
Bandwidth
Amplifier Equivalent RMS Noise
REFERENCE
3±±
kHz
LSB
±.8
6± µV RMS referred to input
Reference Output Voltage
Reference Input Voltage Range
DC Leakage Current
Input Capacitance
VREF Output Impedance
Reference Temperature Coefficient
2.49
±.1
2.51
2.5
±3±
V
V
µA
pF
2±
25
Ω
25
ppm/°C
1± ppm/°C typ
Rev. PrB | Page 4 of 45
Preliminary Technical Data
AD7294
GENERAL SPECIFICATIONS1
AꢁDD = DꢁDD 4.5 ꢁ to 5.5 ꢁ, AGND = DGND= ꢀ ꢁ, external 2.5 ꢁ reference. Temperature range for B version: −4ꢀ°C to +1ꢀ5°C. All
specifications TMIN to TMAX, unless otherwise noted.
Parameter
Min
Typ
Max
Unit
Test Conditions / Comments
LOGIC INPUTS (SDA, SCL ONLY)
VIH, Input High Voltage
VIL, Input Low Voltage
IIN, Input Leakage Current
VHYST, Input Hysteresis
CIN, Input Capacitance
Glitch Rejection
±.7 VDRIVE
V
V
µA
V
pF
ns
±.3 VDRIVE
±1
±.±5 DVDD
8
5±
Input filtering suppresses noise
spikes of less than 5± ns
LOGIC OUTPUTS
(SDA, ALERT, FAULT)
VOL, Output Low Voltage
±.4
±.6
±1
V
V
µA
pF
ISINK = 3 mA
ISINK = 6 mA
Three-State Leakage Current
Three-State Output Capacitance
8
POWER REQUIREMENTS
VPP
AVDD
V(+)
DVDD
AVDD
4.5
4.5
4.5
3
48
V
V
V
V
V
5.5
16.5
5.5
5.5
VDRIVE
IPP
AIDD
TBD
TBD
mA
mA
µA
µA
mW
Outputs unloaded
VIH = DVDD, VIL = DGND
DIDD
1
5
5
TBD
AIDD (Power-Down)
DIDD (Power-Down)
Power Dissipation
1 Guaranteed by design and characterization; not subject to production testing.
Rev. PrB | Page 5 of 45
AD7294
Preliminary Technical Data
TIMING CHARACTERISTICS1,2
I2C Serial Interface
DꢁDD = 4.5 ꢁ to 5.5 ꢁ, AGND = DGND = ꢀ ꢁ. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
FSCL
t1
t2
t3
t4
4±±
2.5
±.6
1.3
±.6
1±±
±.9
±
±.6
±.6
1.3
3±±
±
kHz max
µs min
µs min
µs min
µs min
ns min
µs max
µs min
µs min
µs min
µs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data set-up time
tHD,DAT, data hold time
t5
t6
3
tHD,DAT, data hold time
t7
t8
t9
t1±
tSU,STA, set-up time for repeated start
tSU,STO, stop condition set-up time
tBUF, bus free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
t11
3±±
±
3±±
2± + ±.1Cb
4±±
4
Cb
1 Guaranteed by design and characterization; not subject to production test.
2 See Figure 2.
3 A master device must provide a hold time of at least 3±± ns for the SDA signal (referred to the VIH min of the SCL signal) to bridge the undefined region of SCL’s falling edge.
4 Cb is the total capacitance in pF of one bus line. tR and tF are measured between ±.3 DVDD and ±.7 DVDD
.
SDA
t9
t3
t10
t11
t4
SCL
t4
t6
t2
t1
t8
t5
t7
START
CONDITION
REPEATED
START
STOP
CONDITION
CONDITION
Figure 2. I2C-Compatible Serial Interface Timing Diagram
200µA
I
OL
V
V
(MIN) OR
(MAX)
OH
OL
TO OUTPUT PIN
C
L
50pF
I
200µA
OH
Figure 3. Load Circuit for Digital Output
Rev. PrB | Page 6 of 45
Preliminary Technical Data
AD7294
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.1
Table 3.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Parameter
Rating
VPP to AGND
−±.3 V to +7± V
AVDD to AGND
−±.3 V to +7 V
V(+) to AGND
−±.3 V to +17 V
DVDD to DGND
−±.3 V to +7 V
Digital Inputs to DGND
SDA/SCL to DGND
−±.3 V to DVDD + ±.3 V
−±.3 V to + 7 V
Digital Outputs to DGND
RS(+)/RS(−) to AGND
REFIN to AGND
AGND to DGND
VOUTx to AGND
Analog Inputs to AGND
Operating Temperature Range
Commercial (B Version)
Storage Temperature Range
Junction Temperature (TJ Max)
LFCSP-56 Package
−±.3 V to DVDD + ±.3 V
−±.3 V to VPP + ±.3 V
−±.3 V to AVDD + ±.3 V
−±.3 V to +±.3 V
−±.3 V to AVDD + ±.3 V
−±.3 V to AVDD + ±.3 V
−4±°C to +1±5°C
−65°C to +15±°C
15±°C
θJA Thermal Impedance
θJC Thermal Impedance
Reflow Soldering Peak Temperature
3±°C/W
2.9°C/W
23±°C
1 Transient currents of up to 1±± mA do not cause SCR latch-up.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4±±± V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. PrB | Page 7 of 45
AD7294
Preliminary Technical Data
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RS2 (-)
1
2
42 NC
RS2(+)
41 ISENSE 1 OVERRANGE
40 ISENSE 2 OVERRANGE
39 DVDD
PIN 1
INDICATOR
NC
3
AVDD1
4
AGND1
5
38 DGND
AGND2
37 VDRIVE
6
AVDD2
7
36 OPGND
AD7294
D2(-)
SCL
35
8
D2(+)
34 SDA (I2C) / SDI (SPI)
33 AS0 (I2C) / SDO (SPI)
32 AS1 (I2C) / CSB (SPI)
31 AS2 (I2C) / ALERT (SPI)
9
D1(+)
D1(-)
10
11
12
13
14
TOP VIEW
(Not to scale)
AGND3
AVDD3
REFOUT / REFIN DAC
ALERT (I2C) / AGND6 (SPI)
30
29 AGND5
NC = NO CONNECT
Figure 4.
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
RS2(−), RS1(−)
RS2(+), RS1(+)
NC
Description
1, 54
2, 53
3, 42, 52
4, 7, 13, 22, 5±
Low-Side Connection for External Sense Resistor.
High-Side Connection for External Sense Resistor.
No Connection
Analog Supply Pins. These pins should be decoupled with a ±.1 µF ceramic capacitor and a 1± µF
tantalum capacitor. Operating range is 4.5 V to 5.5 V.
AVDD1 to AVDD5
5, 6, 12, 21,
29, 49, 51
AGND 1 to AGND7
Analog Ground Reference Point. All AGND pins should be connected externally to the AGND
plane.
8, 11
9, 1±
14
D2(−), D1(−)
D2(+), D1(+)
Analog Input. Connected to cathodes of the external temperature-sensing diodes.
Analog Input. Connected to anodes of the external temperature-sensing diodes.
REFOUT/REFIN DAC The AD7294 contains a REFOUT/REFIN DAC pin common to all four DAC channels. When the
internal reference is selected, this pin is the reference output. If the application requires an
external reference, it can be applied to this pin, and the internal reference can be disabled via
the control register. The default for this pin is a reference input.
15, 2±, 23, 28
16, 19, 24, 27
OFFSET IN A to
OFFSET IN D
VOUT A to VOUT D
Used to set the desired output range for each DAC channel. Input range is ± V to 5 V.
Buffered Analog Outputs for DAC Channels A to D. Each analog output is driven by an output
amplifier that can be offset using the offset in pin. DACs provide 12-bit resolution in a 5 V range,
providing an output voltage from ± V to 15 V. Each output is capable of sourcing and sinking
1± mA and driving a 1,±±± pF load.
17, 18
25, 26
3±
DAC OUT GND AB,
DAC OUT V+ AB
DAC OUT V+ CD,
DAC OUT GND CD
Analog Supply Pins for Output Amplifiers on VOUTA and VOUTB.
Analog Supply Pins for Output Amplifiers on VOUTC and VOUTD.
ALERT
Digital Output. This pin acts as an out-of-range indicator and becomes active when a conversion
result violates the DATAHIGH or DATALOW register values associated with each channel input.
31 to 33
AS2, AS1, AS±
Logic Inputs. These inputs are used to select unique addresses for the AD7294. Device address
depends on the voltage applied to these pins.
34
35
SDA
SCL
Digital I/O. Serial bus bidirectional data. Open-drain output.
Digital Input. Serial bus clock. The data transfer rate in I2C mode is compatible with both 1±± kHz
Rev. PrB | Page 8 of 45
Preliminary Technical Data
AD7294
Pin No.
Mnemonic
Description
and 4±± kHz operating modes.
Dedicated Ground Pin for I2C Interface.
36
37
OPGND
VDRIVE
This pin should be connected to the supply that the I2C bus is pulled up to. This is not a supply
pin in I2C mode—it just sets up the input threshold levels.
38
39
DGND
DVDD
Ground for All Digital Circuitry.
Logic Power Supply. Guaranteed operating range is 2.7 V to 5.5 V. It is recommended that these
pins be decoupled with ±.1 µF ceramic and 1± µF tantalum capacitors to DGND.
4±, 41
43 to 46
47
ISENSE1 Overrange,
Outputs from Fault Comparators Connected to High-Side Current Sense Amplifiers.
I
SENSE2 Overrange
VIN3 to VIN±
Single-Ended Analog Inputs with Input Range from ± V to REFIN/REFOUT ADC.
REFOUT/REFIN ADC The AD7294 contains REFOUT/REFIN ADC pin for the ADC. When the internal reference is
selected, this pin is the reference output. If the application requires an external reference, it can
be applied to this pin, and the internal reference can be disabled via the control register. The
default for this pin is a reference input.
48
DCAP
External Decoupling Capacitor Input for Internal Temperature Sensor. A ±.1 μF capacitor to
AGND should be connected to this pin.
55, 56
VPP1, VPP2
Analog Supply Pins. Power supply pins for the high-side current sense amplifiers. Operating
range is from AVDD to +6± V.
Rev. PrB | Page 9 of 45
AD7294
Preliminary Technical Data
TERMINOLOGY
Integral Nonlinearity
Digital-to-Analog Glitch Impulse
The maximum deviation from a straight line passing through
the endpoints of the ADC/DAC transfer function. The
endpoints are zero scale, a point 1 LSB. below the first code
transition, and full scale, a point 1 LSB above the last code
transition.
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nꢁ-s
and is measured when the digital input code is changed by
1 LSB at the major carry transition (ꢀx2ꢀꢀꢀ to ꢀx1FFFV.
Differential Nonlinearity
Digital Feedthrough
Differential nonlinearity (DNLV is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of 1 LSB
maximum ensures monotonicity.
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated.
It is specified in nꢁ-s and is measured with a full-scale code
change on the data bus—from all ꢀs to all 1s or vice versa.
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal,
expressed as a percentage of the full-scale range.
Channel-to-Channel Isolation
A measure of the level of crosstalk between channels, taken
by applying a full-scale sine wave signal to the unselected input
channels and determining how much of the 1ꢀ8 Hz signal is
attenuated in the selected channel. The sine wave signal applied
to the unselected channels is then varied from 1 kHz up to 2 MHz,
and each time it is determined how much of the 1ꢀ8 Hz signal
in the selected channel is attenuated. This figure represents the
worst-case level across all channels.
Gain Error Match
The difference in gain error between any two channels.
Zero-Code Error
Zero-code error is a measure of the output error when zero
code (ꢀxꢀꢀꢀV is loaded into the DAC register. Ideally, the output
should be ꢀ ꢁ. Zero-code error is due to a combination of the
offset errors in the DAC and output amplifier. Zero-code error
is expressed in mꢁ.
Aperture Delay
The measured interval between the sampling clock’s leading
edge and the point at which the ADC takes the sample.
Full-Scale Error
Aperture Jitter
Full-scale error is a measure of the output error when full-scale
code (ꢀxFFFFV is loaded into the DAC register. Ideally, the output
should be ꢁDD − 1 LSB. Full-scale error is expressed in mꢁ.
The sample-to-sample variation in the effective point in time at
which the sample is taken.
Offset Error
Zero-Code Error Drift
Zero-code error drift is a measure of the change in zero-code
error with a change in temperature. It is expressed in µꢁ/°C.
The deviation of the first code transition (ꢀꢀ … ꢀꢀꢀV to
(ꢀꢀ … ꢀꢀ1V from the ideal—that is, AGND + 1 LSB.
Offset Error Match
The difference in offset error between any two channels.
Gain Error Drift
Gain error drift is a measure of the change in gain error with
changes in temperature. It is expressed in (ppm of full-scale
rangeV/°C.
Rev. PrB | Page 1± of 45
Preliminary Technical Data
SYSTEM DESCRIPTION
AD7294
R Sense
REFOUT/
REFIN ADC
REFOUT/
REFIN DAC
RS1(+)
AV D D (1- 5 ) AGND(1-9)
V+(1-2)
VPP(1-2)
RS1(-)
RS2(+) RS2(-)
RF CHOKE
HIGH SIDE
CURRENT
SENSE
HIGH SIDE
CURRENT
SENSE
2.5V
REF
RF OUT
100K
200K
12-BIT
FAULT2
DAC
VOUT A
LDMOS
FILTER
SET-POINT
240mV
100K
200K
FAULT1
VIN 0
VIN 1
VIN 2
VIN 3
D1 (+)
OFFSET IN A
100K
200K
200K
12-BIT
ADC
12-BIT
DAC
MUX
VOUT B
LDMOS
FILTER
100K
200K
D0 (+)
OFFSET IN B
LIMIT
REGISTERS
100K
12-BIT
DAC
VOUT C
GAIN
CONTROL
T0
T1
TEMP
SENSOR
100K
200K
D0 (-)
D1 (-)
OFFSET IN C
VOUT D
100K
200K
12-BIT
DAC
CONTROL
LOGIC
IMPEDANCE
MATCH
AD7294
100K
200K
I2C INTERFACE
PROTOCOL
OFFSET IN D
DVDD
DGND(1-2)
SDA
SCL A2 A1
CAP ALERT
A0
Figure 5. System Diagram
The AD7294 contains all the functions required for general-
purpose monitoring and control of current, voltage, and
temperature integrated into a single-chip solution. The part
includes low voltage ( 2ꢀꢀ mꢁV analog-input sense amplifiers
for current monitoring across shunt resistors, temperature-
sense inputs, and four uncommitted analog input channels
multiplexed into a 2ꢀꢀ kSPS SAR ADC. Four 12-bit DACs
provide the outputs for voltage control and complete the
analog-to-digital digital-to-analog control loop. The DACs
provide digital control with 1.2 mꢁ resolution to control the
bias currents of the power transistors; they can also be used to
provide control voltages for variable gain amplifiers or
impedance-match networks in the main signal chain.
The ADC monitors the high-side current and temperature
sensors as shown in Figure 6. If the temperature of, for
example, an LDMOS High Power Amplifier (HPAV transistor
rises above predetermined limits, out of limit comparisons
generate flags. The on-chip DAC will use the digital correction
loop to decrease the ꢁGS of the device to maintain the desired
output voltage. An external resistor is used to sense the
transistors drain current and so automatically control the gate
bias voltage of the device.
V
DD
CURRENT
SENSE
R
SENSE
ADC
An internal, 2.5 ꢁ, low ppm reference is provided to drive both
the DAC and ADC. This internal reference can be overdriven
when an external reference is required. The AD7294 also
includes limit registers for alarm functions. Using alert registers,
the AD7294 flags an alert signal when the ADC readings go
above or below predetermined values. The analog input range
for the ADC can be selected to be a ꢀ ꢁ to ꢁREF or ꢀ ꢁ to a
2×ꢁREF input, configured with either single-ended or
differential analog inputs.
TEMP
SENSE
RF CHOKE
V
OUTPUT
DAC
HPA
V
DRIVE
Figure 6. Simplified Diagram of System
The part is ideal for bias current control of the power transistors
in power amplifiers employed in CDMA, GSM, EDGE, and UMTS
cellular base stations. The I2C digital interface allows the
flexibility of programming the bias points using an external
controller. The I2C bus also allows a number of devices to be
connected in parallel to control multiple FETS, the standard in
single-carrier and multi-carrier base station systems.
To compensate for temperature effects, one local on-chip, band
gap, temperature sensor and two remote, diode based,
temperature sensors can alternatively be selected. The high side
current sense is specified to manage LDMOS FETs up to 48 ꢁ
with bias currents ranging from 3ꢀꢀ mA to 8ꢀꢀ mA and gate
voltages of 4 ꢁ to 9 ꢁ. The part is designed on a high voltage
DMOS process for high voltage compliance, 6ꢀ ꢁ on the
current-sense inputs, and up to 15 ꢁ DAC output voltage.
Rev. PrB | Page 11 of 45
AD7294
Preliminary Technical Data
When the ADC starts a conversion, as shown in Figure 9, SW3
opens, and SW1 and SW2 move to Position B, causing the com-
parator to become unbalanced. Both inputs are disconnected
once the conversion begins. When the comparator is rebalanced,
the conversion is complete. The control logic generates the ADC
output code. The output impedances of the sources driving the
ꢁIN+ and ꢁIN− pins must be matched; otherwise, the two inputs
will have different settling times, resulting in errors.
ADC INFORMATION
The AD7294 consists of a successive 2ꢀꢀ kSPS approximation
analog-to-digital converter based around a capacitive DAC. The
analog input range for the part can be selected to be a ꢀ ꢁ to ꢁREF
input or a 2 × ꢁREF input, configured with either single-ended or
differential analog inputs. The AD7294 has an on-chip 2.5 ꢁ refer-
ence that can be n when an external reference is preferred. If the
internal reference is to be used elsewhere in a system, the output
must be buffered first.
The various monitored and uncommitted input signals are multi-
plexed into the ADC. The nine channel-allocation address bits
select which analog input channel to convert using the multiplexer.
Four uncommitted analog input channels are multiplexed to the
ADC, ꢁIN (ꢀ to 3V. These four channels allow differential and
pseudodifferential mode measurements of various system signals.
CAPACITIVE
DAC
COMPARATOR
C
C
B
A
S
V
V
IN+
SW1
SW2
CONTROL
LOGIC
SW3
S
A
B
IN–
ADC OPERATION
V
REF
CAPACITIVE
DAC
Figure 7 shows a very simplified schematic of the ADC. The
control logic, SAR and capacitive DACs are used to add and
subtract fixed amounts of charge from the sampling capacitor
arrays to bring the comparator back to a balanced condition.
Figure 9. ADC Conversion Phase
ADC TRANSFER FUNCTIONS
COMPARATOR
The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so onV. In single-ended mode, the
LSB size is ꢁREF/4,ꢀ96 when the ꢀ ꢁ to ꢁREF range is used and
2 × ꢁREF/4,ꢀ96 when the ꢀ ꢁ to 2 × ꢁREF range is used.
CAPACITIVE
DAC
V
IN
SWITCHES
SAR
V
REF
111...111
111...110
CONTROL
LOGIC
CONTROL
INPUTS
OUTPUT DATA
14-BIT PARALLEL
111...000
1LSB = V
/4096
REF
011...111
Figure 7. Simplified ADC Block Diagram
Figure 8 and Figure 9 show simplified schematics of the ADC
during its acquisition and conversion phases in differential mode,
respectively. Figure 8 shows the ADC during its acquisition
phase. SW3 is closed, SW1 and SW2 are in Position A, the
comparator is held in a balanced condition, and the sampling
capacitor arrays acquire the differential signal on the input.
000...010
000...001
000...000
V
– 1LSB
1LSB
REF
0V
ANALOG INPUT
NOTE
1. V
IS EITHER V
REF
OR 2 × V .
REF
REF
Figure 10. Straight Binary Transfer Characteristic
CAPACITIVE
DAC
In differential mode, the LSB size is 2 × ꢁREF /4,ꢀ96 when the ꢀ ꢁ
to ꢁREF range is used and 4 × ꢁREF/4,ꢀ96 when the ꢀ ꢁ to 2 × ꢁREF
range is used. The ideal transfer characteristic for the ADC when
outputting straight binary coding is shown in Figure 1ꢀ, and the
ideal transfer characteristic for the ADC when outputting twos
complement coding is shown in Figure 11 (this is shown with
the 2 × ꢁREF rangeV.
COMPARATOR
C
C
B
A
S
V
V
IN+
SW1
SW2
CONTROL
LOGIC
SW3
S
A
B
IN–
V
REF
CAPACITIVE
DAC
Figure 8. ADC Acquisition Phase
Rev. PrB | Page 12 of 45
Preliminary Technical Data
AD7294
+2.5V
0V
1LSB = 2
×
V
/4096
REF
R
011...111
011...110
+1.25V
0V
R
V
IN
AD72941
V
A1
B6
3R
–1.25V
R
000...001
000...000
V
D
A/D B
CAP
CAP
111...111
0.47µF
100...010
100...001
100...000
1
ADDITIONAL PINS OMITTED FOR CLARITY.
–V
REF
+ 1LSB V
– 1LSB
+V
– 1 LSB
REF
REF
ANALOG INPUT
Figure 12. Single-Ended Mode Connection Diagram
Figure 11. Twos Complement Transfer Characteristic with VREF VREF Input Range
Differential Mode
For Channels 1 to 4 in single-ended mode, the output code is
The AD7294 can have two differential analog input pairs.
Differential signals have some benefits over single-ended
signals, including noise immunity based on the device’s
common-mode rejection and improvements in distortion
performance. Figure 13 defines the fully differential analog
input of the AD7294.
straight binary, where ꢀꢀꢀ = ꢀ ꢁ, FFF = ꢁREF
.
In differential mode, the code is twos complement, where
ꢀꢀꢀ =ꢀ ꢁ, 7FF = +ꢁREF, 8ꢀꢀ = −ꢁREF, and FFF = ꢀ ꢁ − 1 LSB.
Channels 5 and 6 are twos complement, where ꢀꢀꢀ = ꢀ mꢁ,
7FF = +2ꢀꢀ mꢁ, 8ꢀꢀ = −2ꢀꢀ mꢁ, and FFF = ꢀ ꢁ − 1 LSB.
V
V
p-p
p-p
V
IN+
REF
REF
Channels 7 to 9 are twos complement with LSB = ꢀ.25°C, where
ꢀꢀꢀ = ꢀ°C, 7FF = +255.75°C, 8ꢀꢀ = −256°C, and FFF = −ꢀ.25°C.
AD72941
COMMON
MODE
VOLTAGE
V
IN–
ANALOG INPUTS
The AD7294 has a total of four analog inputs. Depending on
the configuration register setup, they can be configured as two
single-ended inputs, two pseudodifferential channels or two
fully differential channels. See the Register Setting section for
further details.
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 13. Differential Input Definition
The amplitude of the differential signal is the difference
between the signals applied to the ꢁIN+ and ꢁIN− pins in each
differential pair (ꢁIN+ − ꢁIN−V. For the various differential
modes, refer to the ADC Channel Allocation section. The
resulting converted data is stored in 2s complement format in
the Result Register. ꢁIN+ and ꢁIN− should be driven
simultaneously by two signals each of amplitude ꢁREF (or 2 ×
ꢁREF, depending on the range chosenV that are 18ꢀ° out of phase.
Assuming the ꢀ to ꢁREF range is selected, the amplitude of the
differential signal is therefore −ꢁREF to +ꢁREF peak-to-peak (2 ×
ꢁREFV, regardless of the common mode (CMV.
Single-Ended Mode
The AD7294 can have four single-ended analog input channels.
In applications where the signal source has high impedance, it is
recommended to buffer the analog input before applying it to
the ADC. The analog input range can be programmed to be
either ꢀ to ꢁREF or ꢀ to 2 × ꢁREF.In 2 × ꢁref mode, the input is
effectively divided by 2 before the conversion takes place, so the
input range becomes ꢀ to 2 × ꢁREF. Note that the voltage on the
input channel pins with respect to GND cannot exceed ꢁDD.
The common mode is the average of the two signals
If the analog input signal to be sampled is bipolar, the internal
reference of the ADC can be used to externally bias up this
signal so that it is correctly formatted for the ADC. Figure 12
shows a typical connection diagram when operating the ADC
in single-ended mode.
(VIN+ + VIN−V/2
And is therefore the voltage on which the two inputs are
centered.
This results in the span of each input being CM ꢁREF/2. This
voltage has to be set up externally, and its range varies with the
reference value, ꢁREF. As the value of ꢁREF increases, the common-
mode range decreases. When driving the inputs with an amplifier,
the actual common-mode range is determined by the amplifier’s
output voltage swing.
Rev. PrB | Page 13 of 45
AD7294
Preliminary Technical Data
When a conversion takes place, the common mode is rejected,
resulting in a virtually noise-free signal of amplitude −ꢁREF to
+ꢁREF, corresponding to the digital codes of ꢀ to 4,ꢀ96. If the
2 × ꢁREF range is used, the input signal amplitude extends from
−2 ꢁREF (ꢁINꢀ = ꢀ ꢁ , ꢁIN1 = ꢁREFV to +2 ꢁREF (ꢁIN1 = ꢀ ꢁ ,
ꢁINꢀ= ꢁREFV.
Using an Op Amp Pair
An op amp pair can be used to directly couple a differential signal
to one of the analog input pairs of the AD7294. The circuit con-
figurations illustrated in Figure 14 and Figure 15 show how a dual
op amp can be used to convert a single-ended signal into a differen-
tial signal for both a bipolar and unipolar input signal, respectively.
The voltage applied to Point A sets up the common-mode voltage.
In both diagrams, Point A is connected to the reference, but any
value in the common-mode range can be input here to set up the
common mode. The AD8ꢀ22 is a suitable dual op amp that can
be used in this configuration to provide differential drive to the
AD7294.
Driving Differential Inputs
The differential modes available on Channels 1 to 4 in Table 7
requires that ꢁIN+ and ꢁIN− be driven simultaneously with two
equal signals that are 18ꢀ° out of phase. The common mode must
be set up externally. The common-mode range is determined by
ꢁREF, the power supply, and the particular amplifier used to drive
the analog inputs. Differential modes of operation with either an
ac or dc input provide the best THD performance over a wide
frequency range. Since not all applications have a signal precon-
ditioned for differential operation, there is often a need to perform
single-ended-to-differential conversion.
Take care when choosing the op amp; the selection depends on
the required power supply and system performance objectives.
The driver circuits in Figure 14 and Figure 15 are optimized for
dc coupling applications requiring best distortion performance.
The circuit configuration shown in Figure 14 converts a unipolar,
single-ended signal into a differential signal. The differential op
amp driver circuit shown in Figure 15 is configured to convert
and level shift a single-ended, ground-referenced (bipolarV signal
to a differential signal centered at the ꢁREF level of the ADC.
3.75V
2.5V
2 × V
REF
p–p
220Ω
V+
440Ω
1.25V
V
REF
27Ω
IN+ AD72941
V
GND
V–
220Ω
220Ω
V+
3.75V
2.5V
1.25V
27Ω
V
D
A/D B
CAP
IN–
CAP
A
V–
10kΩ
0.47µF
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 14. Dual Op Amp Circuit to Convert a Single-Ended Unipolar Signal
into a Differential Signal
3.75V
2.5V
2 × V
REF
p–p
220Ω
V+
440Ω
1.25V
GND
27Ω
IN+ AD72941
V
V–
220Ω
220Ω
V+
220kΩ
3.75V
2.5V
1.25V
27Ω
V
D
A/D B
CAP
IN–
CAP
A
V–
10kΩ
0.47µF
20kΩ
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 15. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
Rev. PrB | Page 14 of 45
Preliminary Technical Data
AD7294
Pseudodifferential Mode
DIGITAL INPUTS
The AD7294 can have two pseudodifferential pairs, see the
Configuration Register section for register details.
The digital inputs applied to the AD7294 are not limited by the
maximum ratings that limit the analog inputs. Instead, the digital
inputs can be applied at up to 7 ꢁ and are not restricted by the
ꢁDD + ꢀ.3 ꢁ limit as are the analog inputs, see the Absolute
Maximum Ratings section for more information. Another advan-
tage of the SDA, SCL, and Aꢀ to A2 not being restricted by the
ꢁDD + ꢀ.3 ꢁ limit is that power supply sequencing issues are
avoided. If one of these digital inputs is applied before ꢁDD
there is no risk of latch-up, as there would be on the analog
inputs if a signal greater than ꢀ.3 ꢁ were applied prior to ꢁDD
Uncommitted input channels 1 and 2 are a pseudodifferential
pair, as are channels 3 and channel 4 . In this mode, ꢁIN+ is
connected to the signal source, which must have amplitude of
ꢁREF (or 2 × ꢁREF, depending on the range chosenV to make use
of the full dynamic range of the part. A dc input is applied to
the ꢁIN− pin. The voltage applied to this input provides an offset
from ground or a pseudoground for the ꢁIN+ input. Which
channel is ꢁIN+ is determined by the ADC channel allocation.
The differential mode must be selected in order to operate in the
pseudodifferential mode. The resulting converted
,
.
VDRIVE
pseudodifferential data is stored in 2s complement format in the
result register.
The AD7294 also has a ꢁDRIꢁE feature to control the voltage at
which the I2C interface operates. Because the I2C pins are open-
drain, there is not a corresponding ꢁDD pin. The ꢁDRIꢁE pin
should be connected to the supply that the I2C bus is pulled up
to. This is not a supply pin in I2C mode—it merely sets up the
input threshold levels. ꢁDRIꢁE allows the ADC to easily interface
to both 3 ꢁ and 5 ꢁ processors. For example, if the AD7294 is
operated with a ꢁDD of 5 ꢁ, the ꢁDRIꢁE pin can be powered from
a 3 ꢁ supply, allowing a large dynamic range with low voltage
digital processors. Thus, the AD7294 can be used with the 2 ×
ꢁREF input range with a ꢁDD of 5 ꢁ while still being able to interface
to 3 ꢁ digital parts.
The governing equation for the pseudodifferential mode, for
channel 1 is:
ꢁOUT = 2(ꢁINꢀ − ꢁIN1V − ꢁREF_ADC
Where ꢁINꢀ is the single-ended signal on channel 1 and ꢁIN1 is
the single-ended signal on channel 2.
The benefit of pseudodifferential inputs is that they separate the
analog input signal ground from the ADC’s ground, allowing dc
common-mode voltages to be cancelled.
Rev. PrB | Page 15 of 45
AD7294
Preliminary Technical Data
DAC OPERATION
R
The AD7294 contains four 12-bit DACs, which provide digital
control with 1.2 mꢁ resolution to control the bias currents of
the power transistors. They can also be used to provide control
voltages for variable gain amplifiers or impedance match
networks in the main signal chain. The DAC core is a thin film
12-bit string DAC with a 5 ꢁ internal buffer to drive the high
voltage output stage. The DAC has a range of ꢀ to 5 ꢁ with a 2.5
ꢁ reference input. The output span of the DAC, which is
controlled by the offset input, can be positioned anywhere
between ꢀ to 15 ꢁ. Figure 16 is a block diagram of the DAC
architecture. The DAC can maintain 12-bit accuracy for up to a
5ꢀꢀ Ω load.
R
R
TO OUTPUT
AMPLIFIER
R
R
1±±K
2±±K
A1
12-Bit
DAC
R
2
V
R
1
VHI
V
REF
DAC
Figure 17. Resistor String Structure
VOUT
A2
2
I
C DATA INPUTS
R
1
Output Amplifier
R
2
VLO
1±±K
2±±K
EXTERNAL
REFERENCE
CAPACITOR
Referring to Figure 16, the purpose of A1 is to buffer the DAC
output range from ꢀ ꢁ to ꢁREF. The second amplifier, A2, is
configured such that when an offset is applied to OFFSET IN,
its output voltage is three times the offset voltage minus twice
the DAC voltage.
OFFSET IN
Figure 16. DAC Architecture
To improve functionality of the device, the DAC output is
digitally inverted. Therefore, although the input coding to the
DAC is straight binary, the ideal output voltage is given by
ꢁOUT = 3ꢁOFFSET − 2ꢁDAC
The DAC word is digitally inverted on-chip such that
ꢁDAC = ꢁREF − ꢁDAC
*
ꢁOUT = 3ꢁOFFSET + 2(ꢁDAC* − ꢁREF
V
⎡
⎣
⎤
⎛ D ⎞
2
⎜
⎝
⎟
⎠
Where ꢁDAC *= VREF
×
⎢
n
⎥
⎦
The user has the option of leaving the offset pin open, in which
case the voltage on the noninverting input of op amp, A2, is set
by the resistor divider, giving
where D is the decimal equivalent of the binary code that is loaded
to the DAC register, and n is the bit resolution of the DAC.
ꢁOUT = 2ꢁDAC
Table 5. DAC Output Code Table
This generates the 5 ꢁ output span from a 2.5 ꢁ reference.
Digitally inverting the DAC allows the circuit to operate as a
generic DAC when no offset is applied.
Digital Input
Analog Output (V)
±±±± ±±±± ±±±±
±±±± ±±±± ±±±1
1±±± ±±±± ±±±±
1111 1111 1111
VREF −VREF (±/4,±96)=VREF
VREF −VREF (1/4,±96)
VREF −VREF (2±48/4,±96) = VREF/2
VREF −VREF (4±95/4,±96)
The DACs provide digital control with 1.2 mꢁ resolution to
control the bias currents of the power transistors. The DAC
output buffer, A2, is capable of driving a 1 nF capacitor with
current source and sink capabilities of 1ꢀ mA to within 2ꢀꢀ mꢁ
off the supply. The output buffer has a supply range of 2ꢀ ꢁ with a
slew rate of 1 ꢁ/μs. Current limiting should take effect at about
4ꢀ mA. Note that a significant amount of power could be dissipated
in this situation; a thermal shutdown circuit will set the DAC
outputs to high impedance if a die temperature of >15ꢀ°C is
measured by the internal temperature sensor.
Resistor String
The resistor string structure is shown in Figure 17. It is simply a
string of 2n resistors, each of value R. The code loaded to the
DAC register determines at which node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. This architecture is inherently
monotonic, voltage out, and low glitch. It is also linear due to
the fact that all of the resistors are of equal value.
Rev. PrB | Page 16 of 45
Preliminary Technical Data
AD7294
converted into a single-ended output voltage by A2. The gain is
internally set with thin-film resistors to 12.5ꢁ/ꢁ. Hence for an
input voltage of 2ꢀꢀ mꢁ an output span of 2.5 ꢁ will be
generated.
CURRENT SENSOR
Two current-sense amplifiers are provided, which can
accurately amplify small differential current shunt voltages in
the presence of rapidly changing common mode voltages. Each
accepts a (ꢁPPV 2ꢀꢀ mꢁ full-scale input voltage and supplies a
(ꢁCC/2V 2.5 ꢁ signal to the ADC.
Note that when using the external reference for the ADC, the
maximum ISENSE input span is 24ꢀ mꢁ with a gain of 12.5 in the
ISENSE amplifier. Therefore, the maximum usable span on the
ADC is 3 ꢁ. If an external reference of 5 ꢁ is required by the
user, only 6ꢀ% the ADC span will be used for the ISENSE
conversion.
The current sense in the AD7294 is a high-side current sense
amplifier, which allows for the monitoring of currents on the ꢁDD
line ranging from AꢁDD up to 48 ꢁ, see Figure 18. The sense
amplifier works correctly for common mode voltages on RS(−V
and RS(+V of between 47 ꢁ (ꢁPP − 1 ꢁV and 48.2 ꢁ (ꢁPP + 2ꢀꢀ
mꢁV. It gives a full scale output to the ADC for a differential
input of 2ꢀꢀ mꢁ, e.g. 48 ꢁ on RS+ and 47.8 on RS−. An input
signal of greater than 24ꢀ mꢁ magnitude should trigger an
alert. An alert will also be triggered if the common mode
voltages on RS+ and RS− go outside the specified limits, as the
amplifier will no longer be in its linear region. The inputs can
be sampled at approximately 6 μs intervals, giving a Nyquist
frequency of approximately 16ꢀ KHz.
Choosing RSENSE
Example calculation:
The AD7294 current sense has a specified full-scale sense range
of 2ꢀꢀ mꢁ. With a ꢁPP of, for example, 48ꢁ and a RLOAD of,
for example, 5ꢀ Ω, the ILOAD is :
ILOAD = ꢁPP / RLOAD = 48 ꢁ / 5ꢀ Ω = ꢀ.96 A
With a full scale sense range of 2ꢀꢀ mꢁ, sense resistor value is:
RSENSE = FSꢁSENSE / ILOAD = 2ꢀꢀ mꢁ / ꢀ.96 A = 2ꢀ8.3 m Ω
I
LOAD
R
SENSE
AVDD to + 48V
RS(+)
RS(-)
In applications monitoring very high currents, RSENSE must be
able to dissipate the I2R losses. If the resistor’s rated power
dissipation is exceeded, its value may drift or it may fail
altogether, causing a differential voltage across the terminals in
excess of the absolute maximum ratings. If ISENSE has a large high
frequency component, care should be taken to choose a resistor
with low inductance. Wire-wound resistors have the highest
inductance, metal-film resistors are somewhat better, and low
inductance metal-film resistors are best suited for these
applications.
AD7294
R1
R2
A
1
Q1
Q2
V
OUT
TO MUX
A
2
R3
R4
Figure 18. High-Side Current Sense
The AD7294 is comprised of two main blocks, a differential and
an instrumentation amplifier. A load current flowing through
the external shunt resistor produces a voltage at the input
terminals of the AD7294. Resistors R1 and R2 connect the input
terminals to the differential amplifier (A1V. A1 nulls the voltage
appearing across its own input terminals by adjusting the
current through R1 and R2 with transistors Q1 and Q2. When
the input signal to the AD7294 is ꢀ, the currents in R1 and R2
are equal. When the differential signal is nonzero, the current
increases through one of the resistors and decreases in the
other. The current difference is proportional to the size and
polarity of the input signal. Since the differential input voltage is
converted into a current, common-mode rejection is no longer
reliant on resistor matching, and high accuracy and
Kelvin Sense Resistor Connection
When using a low value sense resistor for high current
measurement, the problem of parasitic series resistance can
arise. The lead resistance can be a substantial fraction of the
rated resistance, making the total resistance a function of lead
length. This problem can be avoided by using a Kelvin sense
connection. This type of connection separates the current path
through the resistor and the voltage drop across the resistor.
Figure 19 shows the correct way to connect the sense resistor
between the ꢁCC and SENSE pins of the AD7294.
SENSE RESISTOR
CURRENT FLOW
FROM SUPPLY
CURRENT FLOW
TO LOAD
performance is provided throughout the wide common-mode
voltage range. The amplifier is chopper stabilized with a
switching frequency of approximately 3ꢀꢀkHz.
KELVIN SENSE
TRACES
RSX(+)
RSX(-)
AD7294
The differential currents through QI and Q2 are converted into
a differential voltage due to R3 and R4. A2 is configured as an
instrumentation amplifier, and this differential input signal is
Figure 19. Kelvin Sense Connections
Rev. PrB | Page 17 of 45
AD7294
Preliminary Technical Data
This is given by
ΔVBE = KT/q × 1n(NV
where:
K is Boltzmann’s constant.
q is the charge on the carrier.
TEMPERATURE SENSOR
The AD7294 consists of one local and two remote temperature
sensors. The analog input multiplexer can alternately select
either the on-chip band gap temperature sensor, to measure the
temperature of the system, or one of the two remote diode
temperature sensors. The 12-bit ADC digitizes these signals,
and the results are stored in the TSENSEINT, TSENSE1, and TSENSE
registers. These results are compared with their respective
DATALOW, DATAHIGH, and hysteresis registers. Out-of-limit
comparisons generate flags, and further information on these
are stored in the alert registers. A result that exceeds the high
temperature limit, the low temperature limit, or an external
diode fault causes the ALERT output to assert high.
T is the absolute temperature in Kelvin.
N is the ratio of the two currents.
2
If a discrete transistor is used for T1 and Tꢀ, such as a
2N39ꢀ4/2N39ꢀ6, the collector is not grounded and should be
linked to the base. If a PNP transistor is used, the base is
connected to the D− input and the emitter to the D+ input. If
an NPN transistor is used, the emitter is connected to the D−
input and the base to the D+ input. Figure 21 and Figure 22
show how to connect the AD7294 to an NPN or PNP transistor
for temperature measurement. To prevent ground noise from
interfering with the measurement, the more negative terminal
of the sensor is not referenced to ground, but is biased above
ground by an internal diode at the D− input.
V
DD
N*I
I
I-BIAS
MUX
TO ADC
LOW PASS FILTER
fc = 65 KHz
D1 (+)
D0 (+)
LIMIT
REGISTERS
AD7294
T0
T1
TEMP
D0 (-)
D1 (-)
SENSOR
2N3904
NPN
MUX
D+
BIAS
DIODE
D–
REMOTE
SENSING
TRANSISTORS
AD7294
Figure 20. Internal and Remote Temperature Sensors
Figure 21. Measuring Temperature Using an NPN Transistor
CAP ALERT
AD7294
The temperature sensor module on the AD7294 is based on the
3-current principle, see Figure 2ꢀ, where three currents are
passed through a diode and the forward voltage drop is
measured at each diode, allowing the temperature to be
calculated free of errors caused by series resistance.
D+
2N3906
PNP
D–
Figure 22. Measuring Temperature Using a PNP Transistor
Temperature Measurement Method
To measure ΔꢁBE, the sensor is switched between operating
currents of I and N × I. The resulting waveform is passed
through a 65 kHz low-pass filter to remove noise, and to a
chopper-stabilized amplifier that performs the functions of
amplification and rectification of the waveform to produce
a dc voltage proportional to ΔꢁBE. This voltage is measured
by the ADC to give a temperature output in 1ꢀ-bit, twos
complement format.
The AD7294 can measure the temperature of two remote diode
sensors or diode-connected transistors connected from Dꢀ(+V
to Dꢀ(−V and from D1(+V to D1(−V.
The forward voltage of a diode or diode-connected transistor
operated at constant current exhibits a negative temperature
coefficient of about 2 mꢁ/°C. Unfortunately, the absolute value
of ꢁBE varies from device to device, and individual calibration is
required to null this; therefore, the technique is unsuitable for
mass production.
Series Resistance Cancellation
Parasitic resistance to the D+ and D− inputs to the AD7294,
seen in series with the remote diode, is caused by a variety of
factors, including PCB track resistance and track length. This
series resistance appears as a temperature offset in the remote
sensor’s temperature measurement. This error typically causes
a ꢀ.5°C offset per ohm of parasitic resistance in series with the
remote diode.
The technique used in the AD7294 is to measure the change in
ꢁBE when the device is operated at three different currents, see
Figure 2ꢀ.
Rev. PrB | Page 18 of 45
Preliminary Technical Data
AD7294
The AD7294 automatically cancels out the effect of this series
resistance on the temperature reading, giving a more accurate
result, without the need for user characterization of this resis-
tance. The AD7294 is designed to automatically cancel typically
up to 3 kΩ of resistance. By using an advanced temperature
measurement method, this is transparent to the user. This
feature allows resistances to be added to the sensor path to
produce a filter, allowing the part to be used in noisy environ-
ments.
differential inputs, by their very nature, have a high immunity
to noise.
Remote Sensing Diode
To reduce the error due to variations in both substrate and
discrete transistors, a number of factors should be taken into
consideration:
•
The ideality factor, nf, of the transistor is a measure of the
deviation of the thermal diode from ideal behavior. The
AD7294 is trimmed for an nf value of 1.ꢀꢀ8. Use the
following equation to calculate the error introduced at a
temperature T (°CV, when using a transistor whose nf
does not equal 1.ꢀꢀ8. See the processor data sheet for the
nf values.
Temperature Measurement Method
The temperature reading from the ADC is stored in a 1ꢀ-bit
twos complement format and in a sign bit format, D1ꢀ to Dꢀ, to
accommodate both positive and negative temperature measure-
ments. The temperature data format is shown in Table 6, which
shows the achievable temperature measurement range. The
ADC can theoretically measure a 512°C temperature span,
ranging from −256°C to +255.75°C with an LSB of ꢀ.25°C.
∆T = (nf − 1.ꢀꢀ8V × (273.15 K + TV
To factor this in, the user can write the ∆T value to the offset
register. The AD7294 then automatically adds it to or
subtracts it from the temperature measurement.
Table 6. TSENSE Data Format
Digital Input
111 1111 1111
1±± ±±±± ±±±±
±11 1111 1111
±±± ±±±± ±±±±
Bit Weight (ꢁC)
If a discrete transistor is used with the AD7294, the best
accuracy is obtained by choosing devices according to the
following criteria:
−±.25
−256
+255.75
+±.±
•
Base-emitter voltage greater than ꢀ.25 ꢁ at 11 µA, at the
highest operating temperature.
Each input is integrated in turn over a period of several hundred
microseconds. This takes place continuously in the background,
leaving the user free to perform conversions on the other channels.
When integration is complete, a signal is passed to the control
logic to automatically initiate a conversion. If the ADC is in
command mode, the temperature conversion is performed as
soon as the next conversion is completed. In autocycle mode,
the conversion is inserted into an appropriate place in the current
sequence; see the Register Setting section for further details. If
the ADC is idle, the conversion takes place immediately.
•
Base-emitter voltage less than ꢀ.95 ꢁ at 18ꢀ µA, at the
lowest operating temperature.
•
•
Base resistance less than 1ꢀꢀ Ω.
Small variation in hFE (approximately 5ꢀ to 15ꢀV that
indicates tight control of ꢁBE characteristics.
REFERENCE FOR ADC/DAC
The internal reference on the AD7294 is a well regulated, low
ppm 2.5 ꢁ reference with low drift voltage and a stable output.
The reference is common to all four DAC channels and the SAR
ADC. If the application requires an external reference, it can be
applied to the REFOUT/REFIN DAC pin or to the REFOUT/
REFIN ADC pin. If the reference is driving external nodes, a
buffer is required to achieve a low impedance output. For
stability, the reference buffers each require at least 47ꢀ nF on the
output pin. Note that on power up, the ADC and DAC reference
buffers are switched off by default ; note the power-down
register in the Register Setting section.
Three registers store the result of the last conversion on each
temperature channel; these can be read at any time. In addition,
in command mode, one or both of the two external channel
registers can be read out as part of the output sequence. The
MSB of the registers is set if an open-circuit condition is
detected on the input of the external sensors, indicating an
invalid result.
Noise Filtering
For temperature sensors operating in noisy environments,
previous practice was to place a capacitor across the D+ pin and
D− pin to help combat the effects of noise. However, large capaci-
tances affect the accuracy of the temperature measurement,
leading to a recommended maximum capacitor value of 1ꢀꢀꢀ pF.
When using an external reference to achieve the desired
performance from the AD7294, thought should be given to the
choice of a precision voltage reference. There are four possible
sources of error that should be considered when choosing a
voltage reference for high accuracy applications: initial
accuracy, ppm drift, long-term drift, and output voltage noise.
To minimize these errors, a reference with high initial accuracy
This capacitor reduces the noise, but does not eliminate it.
Sometimes, this sensor noise is a problem in a very noisy
environment. In most cases, a capacitor is not required as
Rev. PrB | Page 19 of 45
AD7294
Preliminary Technical Data
is preferred. In addition, choosing a reference with an output
trim adjustment, such as the on-chip internal reference or the
AD431, allows a system designer to trim system errors by
setting a reference voltage to a voltage other than the nominal.
ANALOG COMPARATOR LOOP
The AD7294 consists of two set-point comparators that are
used for independent analog control. The advantage of using
analog control for current sensing is the dynamic speed of the
analog loop vs. the speed of the digital loop, in that the analog
control loop does not have the digital delays inherent in ADC-
to-DAC signal processing. The ISENSEOꢁERRANGE pins signal
whether the instrumentation amplifiers voltage from the
current sense is greater then or less then the set point 24ꢀ mꢁ.
The 24ꢀ mꢁ is the fixed threshold voltage of the over-range
comparator and the current sense amplifier will saturate above
this.
Long-term drift is a measure of how much the reference drifts
over time. A reference with a tight long-term drift specification
ensures that the overall solution remains stable during its entire
lifetime. If choosing an external reference, consider a tight tem-
perature coefficient specification to reduce the temperature
dependence of the system output voltage on ambient conditions.
Rev. PrB | Page 2± of 45
Preliminary Technical Data
APPLICATIONS
AD7294
The AD7294 is used in a power amplifier signal chain to
achieve the optimal bias condition for the LDMOS transistor.
The main factors influencing the bias conditions are
This addition of power gain has an adverse effect on the overall
efficiency of the PA. To minimize the degradation of the PA’s
efficiency, the drivers must be monitored and controlled to
optimize performance.
temperature, supply voltage, gate voltage drift, and general
processing parameters. The overall performance of a power
amplifiers configuration is determined by the inherent tradeoffs
required in efficiency, gain, and linearity. Dynamically
controlling the drain bias current, in order to maintain a
constant value over temperature and time, can significantly
improve the overall performance of the power amplifier.
TYPICAL RF FRONT-END APPLICATION
The circuit in Figure 24 is a typical application for the AD7294.
The device is used to monitor and control the overall
performance of a two final stage amplifiers. The gain control
and phase adjustment of the driver stage are incorporated in the
application and are carried out by the two available
The AD7294 contains all the functions required for general-
purpose monitoring and control of current, voltage, and
temperature. Depending on the signal chain, a number of
amplifiers can be used in predrive and drive modes prior to the
PA final stage to increase the overall power gain of the signal,
see Figure 23 .
uncommitted outputs of the AD7294. Both high-side current
senses measure the amount of current on the respective final
stage amplifiers. The comparator outputs, ISENSE OꢁER-RANGE
pins, are the controlling signals for switches on the RF inputs of
the LDMOS power FETs. If the high-side current sense reads a
value above a specified limit compared with the set-point, the
RF IN signal is switched off by the comparator.
AD7294
By measuring the transmitted power (TxV and the received
power (RxV, the device can dynamically change the drivers and
PA signal to optimize performance. This application requires a
logarithmic detector/controller, such as Analog Devices AD8317.
RF SIGNAL
TO ANTENNA
DRIVER
PRE-DRIVER
2-STAGE FINAL
Figure 23. Typical HPA Signal Chain
R Sense
RF CHOKE
RF CHOKE
VDD
R Sense
RS2(-)
RS1(-)
RS1(+)
RS2(+) RS2(-)
HIGH SIDE
CURRENT
SENSE
HIGH SIDE
CURRENT
SENSE
AD7294*
RF OUT
RF IN
ISENSE2
OVER-RANGE
VOUT A
12-BIT
DAC
FILTER
RF
LDMOS
CUTOFF
ISENSE1
OVER-RANGE
SET-POINT
240mV
RF OUT
VIN 0
VIN 1
RF IN
TX Power
Monitor
TX
POWER
VOUT B
12-BIT
ADC
12-BIT
DAC
FILTER
REF
MUX
LDMOS
VIN 2
VIN 3
RX Power
Monitor
RX
POWER
COMPARATORS &
REGISTERS
REF
VOUT C
VOUT D
12-BIT
DAC
GAIN
CONTROL
D1 (+)
D0 (+)
IMPEDANCE
MATCH
12-BIT
DAC
T0
T1
D0 (-)
D1 (-)
TEMP
SENSOR
* ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Typical HPA Monitor and Control Application
Rev. PrB | Page 21 of 45
AD7294
Preliminary Technical Data
GAIN CONTROL OF PA
ANALOG COMPARATOR LOOP
In this mode, a setpoint voltage, proportional in dB to the
desired output power, is applied to a Logarithmic Amplifier
such as the AD8317, see Figure 25. A sample of the output
power from the PA, via a directional coupler and attenuator (or
by other meansV, is fed to the input of the AD8317. The ꢁOUT is
then connected to the gain control terminal of the PA. Based on
the defined relationship between ꢁOUT and the RF input signal,
the AD8317 will adjust the voltage on ꢁOUT (ꢁOUT is now an
error amplifier outputV until the level at the RF input
Utilizing the internal analog comparator loop allows the
AD7294 to control the RF switch controlling the RF IN signal to
the HPA. The ISENSEOꢁERRANGE 1 pin signals whether the
instrumentation amplifiers voltage from the current sense is
greater then or less then the set point 24ꢀ mꢁ. The 24ꢀ mꢁ is
the fixed threshold voltage of the over-range comparator and
the current sense amplifier will saturate above this. This over-
range signal can be used for the control signal on, for example,
an RF switch such as the ADG9ꢀ1.
R Sense
VPP
corresponds to the applied ꢁSET. The AD7294 completes a
feedback loop, which can track the output of the AD8317 and
adjust the ꢁSET input of the AD8317 accordingly.
RS1(-)
RS1(+)
HIGH SIDE
CURRENT
SENSE
AD7294*
RF CHOKE
ENVELOPE OF
TRANSMITTED
SIGNAL
RF OUT
SET-POINT
240mV
ISENSE1
OVERRANGE
VOUT A
TO ADC
POWER
AMPLIFIER
RF IN
FILTER
LDMOS
DIRECTIONAL
COUPLER
ATTENUATOR
ADG901*
RF CHOKE
RF IN
RF2
RF1
AD7294
50
50
CTRL
VIN
AD8317
Figure 26. Analog Comparator Loop
INHI
VOUT
INLO
VSET
VOUT
This is a useful safety feature available in the AD7294. The
analog control loop senses any high current supplied to the
power amplifier and dynamically cuts the RF signal to the gate
of the device in direct response.
C
FLT
Figure 25. Setpoint Controller Operation
ꢁOUT of the AD8317 is applied to the gain control terminal of
the power amplifier. In order for this output power control loop
to be stable, a ground-referenced capacitor must be connected
to the CFLT pin. This capacitor integrates the error signal (which
is actually a currentV that is present when the loop is not
balanced. In a system where a ꢁariable Gain Amplifier or
ꢁariable ꢁoltage Attenuator feeds the power amp only one
AD8317 is required. In such a case the gain on one of the
parts (ꢁꢁA, PAV is fixed and ꢁOUT feeds the control input of
the other.
Rev. PrB | Page 22 of 45
Preliminary Technical Data
REGISTER SETTING
AD7294
The AD7294 contains 43 internal registers (see Figure 27V that
are used to store conversion results, high and low conversion
limits, and information to configure and control the device.
There are 42 data registers and one address pointer register.
AD7294’s data registers, see Table 11. The first byte following
each write address is the address of one of the data registers,
which is stored in the address pointer register and selects the
data register to which subsequent data bytes are written. On
power-up, the address pointer register contains all ꢀs, pointing
to the command register.
COMMAND REGISTER
RESULT REGISTER
TSENSE RESULT
ADC CHANNEL ALLOCATION
These nine channel address bits select which analog input
channel is to convert using the multiplexer, see Table 7.
Choosing Channels 1 to 4 selects the standard analog voltage
inputs. Channels 5 and 6 represent the analog-input sense
amplifiers for current monitoring. Channel 7 and 8 designate
the use of the external temperature-sensing diodes, whereas
Channel 9 represents the internal temperature sensor.
REGISTERS
x 3
ALERT REGISTERS
x 3
CHANNEL SEQUENCE
REGISTER
D
A
T
ADDRESS
POINTER
REGISTER
CONFIGURATION
REGISTER
A
POWER DOWN
REGISTER
Table 7. ADC Channel Allocation
Channel Function
DATAHIGH / DATALOW
Channel ID
±±±
±±1
±1±
±11
1±±
1±1
11±
111
REGISTERS
x 18
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
VIN± or (VIN± − VIN1)
HYSTERESIS REGISTER
TSENSE OFFSET
VIN1 or (VIN1 − VIN±)
VIN2 or (VIN2 − VIN3)
VIN3 or (VIN3 − VIN2)
REGISTERS
x 2
FUSE BLOCK
REGISTERS
ISENSE
ISENSE
1
2
x 2
SDA
SCL
SERIAL BUS INTERFACE
TSENSE
TSENSE
1
2
Figure 27. AD7294 Register Structure
Each data register has an address to which the address pointer
register points when communicating with it. The command
register and fuse block registers are the only registers that are
write-only registers; the rest are read/write registers.
TSENSEINT
–
There are two modes of operation with respect to the ADC. In
command mode, a sequence is written to the ADC, and on
subsequent reads, the next channel in the sequence is converted
as the current sequence is read out. In autocycle mode, a
sequence is programmed, and then the ADC automatically
cycles through the selected channels, outputting an alert if one
of the channels goes outside its preset range.
ADDRESS POINT REGISTER
The address pointer register does not have and does not require
an address, because it is the register to which the first data byte
of every write operation is written automatically. The address
pointer register is an 8-bit register, in which the 6 LSBs are used
as pointer bits to store an address that points to one of the
Rev. PrB | Page 23 of 45
AD7294
Preliminary Technical Data
COMMAND REGISTER
RESULT REGISTER
Writing in this register puts the part into command mode.
While in command mode, the part cycles through the selected
channels on each subsequent read. If the external TSENSE channels
are selected in the command word, it is not actually requesting
a conversion, but the result of the last automatic conversion
will be output in sequence. See the Channel Sequence Register
section for information on autocycle mode.
The result register is a 16-bit read/write register. The four
uncommitted input channels and the two ISENSE channels
converted results are stored in the result register for reading.
Writing to this register sets the DAC1 output code. The register
consists of bits D14 to D12 to identify the ADC channel
allocation. Bits D11 to Dꢀ, in the result register, are the data bits
sent to DAC1. While the MSB, D15, is reserved as an Alert_Flag
bit. The Alert_Flag bit indicates whether the conversion result
being read or any other channel result has violated the limit
registers associated with it. If an alert occurs, the master may
wish to read the alert status register to obtain more information
on where the alert occurred if the Alert_Flag bit is set.
Table 8. Address Pointer Byte—Command Bits
Parameter Function
C1
C2
C3
C4
C5
C6
C7
C8
Convert on CH1
Convert on CH2
Convert on CH3
Convert on CH4
Convert on ISENSE
Convert on ISENSE
Table 9 shows the contents of the first byte to read from the
AD7294; Table 1ꢀ shows the contents of the second byte read.
1
2
Read out last result from TSENSE
Read out last result from TSENSE
1
2
Table 9. Result Register (First Read)
MSB
LSB
D15
D14
D13
D12
D11
D10
D9
D8
Alert_Flag
CHID2
CHID1
CHID±
B11
B1±
B9
B8
Table 10. Result Register (Second Read)
MSB
LSB
D0
B±
D7
D6
D5
D4
D3
D2
D1
B7
B6
B5
B4
B3
B2
B1
Rev. PrB | Page 24 of 45
Preliminary Technical Data
AD7294
Table 11. AD7294 Register Addresses
P7
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
P6
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
P5
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
1
1
1
1
1
1
1
1
P4
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
±
±
±
±
±
±
±
±
P3
±
±
±
±
±
±
±
±
1
1
1
1
1
1
1
1
±
±
±
±
±
±
±
±
1
1
1
1
1
1
1
1
±
±
±
±
±
±
±
±
P2
±
±
±
±
1
1
1
1
±
±
±
±
1
1
1
1
±
±
±
±
1
1
1
1
±
±
±
±
1
1
1
1
±
±
±
±
1
1
1
1
P1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
P0
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
Registers
Command register (W)
Result register (R)/DAC1 value (W)
TSENSE1 result (R)/DAC2 value (W)
TSENSE2 result (R)/DAC3 value (W)
TSENSEINT result (R)/DAC4 value (W)
Alert Register A (R/W)
Alert Register B (R/W)
Alert Register C (R/W)
Channel sequence register (R/W)
Configuration register (R/W)
Power-down register (R/W)
DATALOW register CH1 (R/W)
DATAHIGH register CH1 (R/W)
Hysteresis register CH1 (R/W)
DATALOW register CH2 (R/W)
DATAHIGH register CH2 (R/W)
Hysteresis register CH2 (R/W)
DATALOW register CH3 (R/W)
DATAHIGH register CH3 (R/W)
Hysteresis register CH3 (R/W)
DATALOW register CH4 (R/W)
DATAHIGH register CH4 (R/W)
Hysteresis register CH4 (R/W)
DATALOW register ISENSE1 (R/W)
DATAHIGH register ISENSE1 (R/W)
Hysteresis register ISENSE1 (R/W)
DATALOW register ISENSE2 (R/W)
DATAHIGH register ISENSE2 (R/W)
Hysteresis register ISENSE2 (R/W)
DATALOW register TSENSE1 (R/W)
DATAHIGH register TSENSE1 (R/W)
Hysteresis register TSENSE1 (R/W)
DATALOW register TSENSE2 (R/W)
DATAHIGH register TSENSE2 (R/W)
Hysteresis register TSENSE2 (R/W)
DATALOW register TSENSEINT (R/W)
DATAHIGH register TSENSEINT (R/W)
Hysteresis register TSENSEINT (R/W)
TSENSE1 offset register (R/W)
TSENSE2 offset register (R/W)
Rev. PrB | Page 25 of 45
AD7294
Preliminary Technical Data
Register A , see Table 13, consists of four channels with two
status bits per channel, one corresponding to each of the
DATAHIGH and DATALOW limits. It stores the alert event data for
Channels 1 to 4, which are the standard voltage inputs. The bit
with a status of 1 shows where the violation occurred—that is,
on which channel—and whether the violation occurred on the
upper or lower limit. If a second alert event occurs on another
channel between receiving the first alert and interrogating the
alert status register, the corresponding bit for that alert event is
also set.
TSENSE1, TSENSE2 RESULT REGISTERS
Registers TSENSE1 and TSENSE2 are 16-bit read/write registers.
General alert is flagged by the MSB, D15. Bits D14 to D12 are
reserved for the ADC channel allocation. D11 is reserved for
flagging diode open-circuits. The temperature reading from the
ADC is stored in a 1ꢀ-bit twos complement format plus a sign
bit, D1ꢀ to Dꢀ. Writing to the TSENSE1 register sets the DAC2
output code while writing to the TSENSE2 register sets the DAC3
output code.
TSENSEINT RESULT REGISTER
Register B, see Table 14, reserves two bits for user input. It also
consists of three channels with two status bits per channel,
representing the specified DATAHIGH and DATALOW limits. Bits B3
to Bꢀ correspond to the high and low limit alerts for the current
sense inputs. Bits B5 to B4 represent the ISENSE over the full-scale
range of 2ꢀꢀ mꢁ.
The TSENSEINT register is a 16-bit read/write register used to
store the ADC data generated from the internal temperature
sensor. Similar to the TSENSE1 and TSENSE2 result registers, this
register stores the temperature readings from the ADC in a
1ꢀ-bit twos complement format and in a sign bit format, D1ꢀ to
Dꢀ, and uses the MSB as a general alert flag. However, Bits D14
to D11 are not used. Conversions take place approximately every
5 ms. Writing to this register sets the DAC4 output code. The
temperature data format in Table 6 also applies to the internal
temperature sensor data.
Register Cs most significant bit, see Table 15, is used to alert the
user if an open diode flag occurs on the external temperature
sensors. An over temperature alert for the external temperature
sensor occupies C6. The remaining 6 bits in this register are
used to store alert event data for TSENSE1, TSENSE2 and TSENSEINT
with two status bits per channel, one corresponding to each of the
DATAHIGH and DATALOW limits.
TSENSE OFFSET REGISTERS
Due to the high frequency clock signals of the system, some
temperature errors can be attributable to noise coupled onto the
D+/D− lines of the remote temperature sensors even when the
layout guidelines are followed. Constant high frequency noise
usually attenuates/increases the temperature measurements by a
linear constant value. The AD7294 has temperature offset 8-bit
The entire contents of the alert status register can be cleared by
writing 1 to bit D1 and 1 to bit D2 in the configuration register,
as shown in Table 17. This can also be achieved by writing all 1s
to the alert status register itself. Therefore, if the alert status
register is addressed for a write operation, which is all 1s, the
contents of the alert status register are cleared or reset to all ꢀs.
twos complement registers for both Remote Channels TSENSE
1
and TSENSE2. By completing a one-time calibration of the system,
the user can determine the offset caused by system board noise
and null it using the offset registers. The offset registers for
TSENSE1 and TSENSE2 are 8-bit read/write registers that store data
in a twos complement format. This data is subtracted from the
temperature readings taken by TSENSE1 and TSENSE2 temperature
sensors. The offset is carried out before the values are stored in
the TSENSE result register.
CHANNEL SEQUENCE REGISTER
The channel sequence register is an 8-bit read/write register that
allows the user to sequence the ADC conversions in autocycle
mode. This mode must first be selected in the configuration
register, see Table 16. This is an extremely useful mode, for
example, when checking for alerts on a channel. On power-up,
the channel sequence register contains all ꢀs, thus disabling
automatic cycle operation of the AD7294. To enable the
automatic cycle mode, the user must write a 1 to the desired
channel.
Table 12. TSENSE Offset Data Format
Digital Input
1111 1111
1±±± ±±±±
±111 1111
±±±± ±±±±
Bit Weight ( ꢁC )
− ±.25
− 32
+ 31.75
+ ±.±
The temperature sense channels, including TSENSEINT, are a
special case. The conversions on these channels take place
automatically, unless the temperature sense circuit is powered
down, either after certain other conversions or in other quiet
times. This is transparent to the user.
ALERT STATUS REGISTERS
The alert status registers are 8-bit read/write registers that
provides information on an alert event. If a conversion results in
activating the ALERT pin or Alert_Flag bit in the result register
or TSENSE registers, the alert status register can be read to gain
further information.
CONFIGURATION REGISTER
The configuration register is a 16-bit read/write register that is
used to set the operating modes of the AD7294. The bit
functions of the configuration register are outlined in. Table 17
Rev. PrB | Page 26 of 45
Preliminary Technical Data
AD7294
Table 13. Alert Status Register A
Alert Bit
A7
A6
A5
A4
A3
A2
A1
A0
Function
CH4
CH4
CH3
CH3
CH2
CH2
CH1
CH1
high alert
low alert
high alert
low alert
high alert
low alert
high alert
low alert
Table 14. Alert Status Register B
Alert Bit
B7
B6
B5
B4
B3
B2
B1
B0
Reserved
Reserved
ISENSE2
ISENSE1
ISENSE2
ISENSE2
ISENSE1
ISENSE1
Function
over-range
over-range
high alert
low alert
high alert
low alert
Table 15. Alert Status Register C
Alert Bit
C7
C6
C5
C4
C3
C2
C1
C0
Function
Open-diode
flag
Over-temp
alert
TSENSEINT
high alert
TSENSEINT
low alert
TSENSE
high alert
2
TSENSE
low alert
2
TSENSE
high alert
1
TSENSE1
low alert
Table 16. Channel Sequence Register
Channel
Bit
D7
D6
Reserved
D5
D4
ISENSE
D3
CH4
D2
CH3
D1
CH2
D0
Reserved
ISENSE
2
1
CH1
Function
Table 17. Configuration Register Bit Function Description
Config.
Bit
Comment
D15
D14
Reserved
Enable noise-delayed sampling. Used to delay critical
sample intervals from occurring when there is
activity on the I2C bus.
D13
Enable noise-delayed bit trials. Used to delay critical
bit trials from occurring when there is activity on the
I2C bus.
Table 18. ALERT/BUSY Function
D2
D1
ALERT/BUSY Pin Configuration
±
±
1
±
1
±
Pin does not provide any interrupt signal.
Pin configuration as a BUSY output
Pin configuration as an ALERT output.
D12
D11
D1±
D9
D8
D7
D6
D5
D4
D3
Enable autocycle mode.
Enable pseudodifferential mode for CH3/CH4
Enable pseudodifferential mode for CH1/CH2
Enable differential mode for CH3/CH4
Enable differential mode for CH1/CH2
Enable 2 VREF range on CH4
Enable 2 VREF range on CH3
Enable 2 VREF range on CH2
Enable 2 VREF range on CH1
Enable I2C filters
1
1
Resets the ALERT output pin, the Alert_Flag
bit in the conversion result register, and the
entire alert status register (if any is active). If
1/1 is written to Bits D2/D1 in the
configuration register to reset the ALERT pin,
the Alert_Flag bit, and the alert status
register, the contents of the configuration
register read 1/± for D2/D1, respectively, if
read back.
D2
D1
D±
Enable alert pin
Enable busy pin (D2 = ±)/clear alerts (D2 = 1)
Sets polarity of alert pin (active high/active low)
Rev. PrB | Page 27 of 45
AD7294
Preliminary Technical Data
either hardware, software or both, depending on the
configurationV if the result moves outside the upper or lower
SAMPLE DELAY AND BIT TRIAL DELAY
It is recommended that no I2C Bus activity occurs when a
conversion is taking place; however, this may not be possible,
for example when operating in automatic cycle mode. To
maintain the performance of the ADC in such cases, Bits D14
and D13 in the configuration register are used to delay critical
sample intervals and bit trials from occurring while there is
activity on the I2C bus. This may increase the conversion time.
When Bits D14 and D13 are both 1, the bit trial-and-sample
interval delaying mechanism are implemented. The default
setting of D14 and D13 is ꢀ. If bit trial delays extend longer than
1 µs, the conversion terminates. When D14 is 1, the sampling
instant delay is implemented. When D13 is 1, the bit trial delay
is implemented. To turn off both the sample delay and bit trial
delay, set D14 and D13 to ꢀ.
limit set by the user.
Table 20. Default values for DATAHIGH and DATALOW
REGISTERS
ADC
Single Ended
Differential
Channel
CH1
CH2
CH3
CH4
±±± and FFF
±±± and FFF
±±± and FFF
±±± and FFF
7FF and 8±±
7FF and 8±±
7FF and 8±±
7FF and 8±±
N/A
I
SENSE1
ISENSE
TSENSE
TSENSE
7FF and 8±± (2’s
Complement)
7FF and 8±± (2’s
Complement)
3FF and 4±± (2’s
Complement)
3FF and 4±± (2’s
Complement)
2
N/A
N/A
N/A
N/A
1
2
POWER-DOWN REGISTER
The power-down register is an 8-bit read/write register that is
used to power down various sections on the AD7294 device.
TSENSEINT
3FF and 4±± (2’s
Complement)
Table 19. Power-Down Register Description
The DATAHIGH register stores the upper limit that activates the
ALERT output and/or the Alert_Flag bit in the conversion
result register. If the value in the conversion result register is
greater than the value in the DATAHIGH register, an alert occurs.
When the conversion result returns to a value of at least N LSB
below the DATAHIGH register value, the ALERT output pin and
Alert_Flag bit are reset. The value of N is taken from the 12-bit
hysteresis register associated with that channel. For the TSENSE
limit registers D11 is equal to ꢀ, as this denotes the diode open-
circuit flag in the TSENSE registers.
Bit
P7
P6
P5
Function
Power down full chip (apart from DACs)
Reserved
Power down ADC reference buffer (to allow
external reference, 1 at power-up)
Power down DAC reference buffer (to allow
external reference, 1 at power-up)
Power down temperature sensor
Power down ISENSE
Power down ISENSE
DAC outputs set to high impedance (set
automatically if die temperature >15±°C)
P4
P3
P2
P1
P±
2
1
The DATALOW register stores the lower limit that activates the
ALERT output and/or the Alert_Flag bit in the conversion
result register. If the value in the conversion result register is less
than the value in the DATALOW register, an alert occurs. When
the conversion result returns to a value of at least N LSB above
the DATALOW register value, the ALERT output pin and
Alert_Flag bit are reset. The value of N is taken from the
hysteresis register associated with that channel.
DATAHIGH/DATALOW REGISTER
The DATAHIGH / DATALOW registers for a channel are 16-bit,
read/write registers. General alert is flagged by the MSB, D15.
D14 – D12 are not used in the register and are read as ꢀs. The
remaining 12-bits set the high/low limits for the relevant
channel. With respect to Channels 1 to 4, for Single Ended
mode, ꢀꢀꢀ and FFF are the defaults values. For differential
The ALERT pin can also be reset by writing to Bits D2 and D1
in the configuration register.
mode on Channels 1 to 4, the default values for DATAHIGH
&
DATALOW are 7FF and 8ꢀꢀ. Note that if the part is configured in
Single Ended mode and the limits are changed, the user must
re-program limits when changing to a different mode.
Table 21. AD7294 DATAHIGH/LOW Register (First R/W)
MSB
LSB
D8
B8
D15
D14 D13 D12 D11
B11
D10 D9
B1± B9
Alert_Flag
±
±
±
Channels 5 and 6 ( ISENSE1 and ISENSE2 V are two’s complement
format and so the default limits will also be 7FF and 8ꢀꢀ. There
is no differential mode for channels 5 and 6.
Table 22. AD7294 DATAHIGH/LOW Register (Second R/W)
MSB
LSB
D0
B±
D7
D6
D5
D4
D3
D2
D1
Channels 7 to 9, (TSENSE1, TSENSE2 and TSENSEINTV default to 3FF
and 4ꢀꢀ for the DATAHIGH and DATALOW limits as they are in
two’s complement 1ꢀ-bit format. Differential mode is not
available for channels 7 to 9. The AD7294 signals an alert (in
B7
B6
B5
B4
B3
B2
B1
Rev. PrB | Page 28 of 45
Preliminary Technical Data
AD7294
Using the Limit Registers to
Store Min/Max Conversion Results
HYSTERESIS REGISTERS
Each hysteresis register is a 16-bit read/write register; only the
12 LSBs of the register are used, with the MSB signaling the
alert event. The hysteresis register stores the hysteresis value, N,
when using the limit registers. Each pair of limit registers has a
dedicated hysteresis register. The hysteresis value determines
the reset point for the ALERT pin/Alert_Flag if a violation of
the limits occurs. For example, if a hysteresis value of 8 LSB is
required on the upper and lower limits of Channel 1, the 16-bit
word ꢀꢀꢀꢀ ꢀꢀꢀꢀ ꢀꢀꢀꢀ 1ꢀꢀꢀ should be written to the hysteresis
register of CH1 (see Table 11V. On power-up, the hysteresis
registers contain a value of 8 LSB for non-temperature result
registers and 8 °C, or 32 LSB, for the TSENSE registers. If a
different hysteresis value is required, that value must be written
to the hysteresis register for the channel in question. For the
TSENSE register D11, in Table 23 is ꢀ.
If full scale—that is, all 1s—is written to the hysteresis register
for a particular channel, the DATAHIGH and DATALOW registers
for that channel no longer act as limit registers as previously
described, but act as storage registers for the maximum and
minimum conversion results returned from conversions on a
channel over any given period of time. This function is useful in
applications where the widest span of actual conversion results
is required rather than using the ALERT to signal that an
intervention is necessary. Note that on power-up, the contents
of the DATAHIGH register for each channel are full scale, whereas
the contents of the DATALOW registers are zero scale by default.
Therefore, minimum and maximum conversion values being
stored in this way are lost if power is removed or cycled.
Table 23. Hysteresis Register (First Read/Write)
MSB
LSB
D8
B8
D15
D14
D13
D12
D11
D10
D9
Alert_Flag
±
±
±
B11
B1±
B9
Table 24. Hysteresis Register (Second Read/Write)
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
B7
B6
B5
B4
B3
B2
B1
B±
Rev. PrB | Page 29 of 45
AD7294
Preliminary Technical Data
SERIAL BUS INTERFACE
to-high transition when the clock is high may be interpreted as
a stop signal. If the operation is a write operation, the first data
byte after the slave address is a command byte. This tells the
slave device what to expect next. It may be an instruction telling
the slave device to expect a block write, or it may be a register
address that tells the slave where subsequent data is to be
written. Because data can flow in only one direction, as defined
by the R/W bit, it is not possible to send a command to a slave
device during a read operation. Before performing a read
operation, it is sometimes necessary to perform a write
operation to tell the slave what sort of read operation to expect
and/or the address from which data is to be read.
Control of the AD7294 is carried out via the I2C-compatible
serial bus. The AD7294 is connected to this bus as a slave device
under the control of a master device.
GENERAL I2C TIMING
Figure 28 shows the timing diagram for general read and write
operations using an I2C-compliant interface. The master initiates
a data transfer by establishing a start condition, defined as a
high-to-low transition on the serial data line (SDAV while the
serial clock line (SCLV remains high. This indicates that a data
stream follows. The master sends a 7-bit slave address (MSB
firstV and an R/W bit that determines the direction of the data
transfer—that is, whether data is written to or read from the
slave device (ꢀ = written, 1 = readV.
When all data bytes have been read or written, stop conditions
are established. In write mode, the master pulls the data line
high during the 1ꢀth clock pulse to assert a stop condition. In
read mode, the master device releases the SDA line during the
low period before the ninth clock pulse, but the slave device
does not pull it low. This is known as a no acknowledge
(NACKV. The master takes the data line low during the low
period before the 1ꢀth clock pulse, and then high during the 1ꢀth
clock pulse to assert a stop condition.
The slave responds by pulling the data line low during the low
period before the ninth clock pulse, known as the acknowledge
bit, and holding it low during the high period of this clock
pulse. All other devices on the bus remain idle while the
selected device waits for data to be read from or written to it.
If the R/W bit is ꢀ, the master writes to the slave device.
If the R/W bit is 1, the master reads from the slave device.
Data is sent over the serial bus in sequences of nine clock
pulses—eight bits of data followed by an acknowledge bit,
which can be from the master or slave device. Data transitions
on the data line must occur during the low period of the clock
signal and remain stable during the high period, because a low-
SCL
SDA
1
1
0
1
1
0
1
P7
P6
P5
P4
P3
P2
P1
P0
R/W
START COND
BY MASTER
ACK. BY
AD7294
ACK. BY
SERIAL BUS ADDRESS BYTE
USER PROGRAMMABLE 5 LSBs
STOP BY
MASTER
REGISTER ADDRESS
MASTER /
SLAVE
Figure 28. General I2C Timing
Rev. PrB | Page 3± of 45
Preliminary Technical Data
AD7294
has a 7-bit serial address. The 5 LSBs are user programmable
by the 3 three-state input pins as shown in Table 25 where Z
refers to a pin left floating.
SERIAL BUS ADDRESS BYTE
The first byte the user writes to the device is the Serial Bus
Address Byte. Like all I2C-compatible devices the AD7294
Table 25. Serial Address control using 3-State Input Pins
AS2
AS1
AS0
A4
±
±
±
±
±
±
±
±
±
±
±
±
±
±
±
1
1
1
1
1
1
1
1
1
1
1
1
A3
±
±
±
±
±
±
±
1
1
1
1
1
1
1
1
±
±
±
±
±
±
±
±
1
1
1
1
A2
±
±
±
1
1
1
1
±
±
±
±
1
1
1
1
±
±
±
±
1
1
1
1
±
±
±
±
A1
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
±
±
1
1
A0
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
1
±
±
±
±
±
1
±
±
Z
±
±
1
±
1
1
±
1
Z
±
±
Z
Z
Z
±
±
1
±
Z
±
1
1
±
1
1
±
Z
±
1
1
1
1
1
1
1
Z
±
1
Z
Z
Z
±
1
1
1
Z
±
Z
Z
Z
Z
Z
Z
Z
Z
Z
±
1
±
Z
±
1
1
1
1
Z
±
Z
Z
Z
1
Z
Rev. PrB | Page 31 of 45
AD7294
Preliminary Technical Data
1. The master device asserts a start condition on SDA.
WRITING/READING TO THE AD7294
The AD7294 uses the following I2C protocols:
2. The master sends the 7-bit slave address followed by
the write (lowV bit.
Writing to the Address Pointer Register
for a Subsequent Read
3. The addressed slave device asserts ACK on SDA.
4. The slave receives a data byte.
In the AD7294, to read from a particular register, the address
pointer register must first contain the address of that register. If
the address pointer is not set, the correct address must be
written to the address pointer register by performing a single
byte write operation, as shown in Figure 29. In this operation,
the slave device receives a single byte from a master as follows:
5. The slave asserts ACK on SDA.
6. The master asserts a stop condition on SDA, and the
transaction ends.
1
9
1
9
SCL
P3
1
1
A4
A3
A2
A1
A0
P7
P6
P5
P2
P1
P0
R/W
P4
SDA
START BY
MASTER
ACK. BY
AD7294
ACK. BY
AD7294
STOP BY
MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
ADDRESS POINTER REGISTER BYTE
Figure 29. Writing to the Address Pointer Register to Select a Register for a Subsequent Read Operation
Rev. PrB | Page 32 of 45
Preliminary Technical Data
AD7294
1. The master device asserts a start condition on SDA.
Reading Data from an 8-Bit Register
Reading the contents from any of the 8-bit registers is a single-
byte read operation, as shown in Figure 3ꢀ. This protocol
assumes that the particular register address has been set up by a
single-byte write operation to the address pointer register (see
Figure 3ꢀV. Once the register address has been set up, any
number of reads can be performed from that particular register
without having to write to the address pointer register again. If a
read from a different address is required, the relevant register
address has to be written to the address pointer register, and
again any number of reads from this register can then be
performed. In this operation, the master device receives a single
byte from a slave device as follows:
2. The master sends the 7-bit slave address followed by
the read bit (highV.
3. The addressed slave device asserts ACK on SDA.
4. The master receives a data byte.
5. The master asserts NACK on SDA so that the slave
knows the data transfer is complete.
6. The master asserts a stop condition on SDA, and the
transaction ends.
1
9
1
9
SCL
D3
A4
A3
A2
A1
A0
D7
D6
D5
D2
D1
D0
1
R/W
D4
1
SDA
START BY
MASTER
ACK. BY
AD7294
NO ACK. BY STOP BY
MASTER MASTER
FRAME 1
SERIAL BUS ADDRESS BYTE
FRAME 2
SINGLE DATA BYTE FROM AD7294
Figure 30. Reading a Single Byte of Data from a Selected Register
Rev. PrB | Page 33 of 45
AD7294
Preliminary Technical Data
4. The master receives a data byte.
Reading Two Bytes of Data from a 16-Bit Register
In this operation, the master device reads two bytes of data
from a slave device. This protocol assumes that the particular
register address has been set up by a single-byte write operation
to the address pointer register, see Figure 31.
5. The master asserts ACK on SDA.
6. The master receives a second data byte.
7. The master asserts NACK on SDA, so the slave knows that
the data transfer is complete.
1. The master device asserts a start condition on SDA.
8. The master asserts a stop condition on SDA to end the
transaction.
2. The master sends the 7-bit slave address followed by the
read bit (highV.
3. The addressed slave device asserts ACK on SDA.
1
9
1
9
SCL
D13
1
1
A4
A3
A2
A1
A0
D12 D11
D10
D9
D8
R/W
D14
SDA
ACK. BY
AD7294
ACK. BY
MASTER
START BY
MASTER
ALERT-
FLAG
FRAME 2
FRAME 1
SERIAL BUS ADDRESS BYTE
MOST SIGNIFICANT DATA BYTE FROM
AD7294
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D3
D1/0 D0/0
D7
D6
D5
D4
D2
NO ACK. BY
MASTER
STOP BY
MASTER
FRAME 2
MOST SIGNIFICANT DATA BYTE FROM
AD7294
Figure 31. Reading Two Bytes of Data from the Conversion Result Register
Rev. PrB | Page 34 of 45
Preliminary Technical Data
AD7294
8. The master sends a register address.
9. The slave asserts ACK on SDA.
Reading Two Bytes of Data from a Result Register
The result register, TSENSE1 result register and the TSENSE2 register
are 16-bit registers used to store the conversion results from the
ADC. The master must first write to the command register to
determine which multiplexed channel to convert on. The
address pointer register is then pointed towards the register to
which to enter the converted data. The master sends a repeated
start to the frame and then enters the two bytes of converted
data into the desired result register. :
1ꢀ. The master device asserts a repeated start condition on
SDA.
11. The master sends the 7-bit slave address followed by the
read bit (highV.
12. The slave asserts ACK on SDA.
1. The master device asserts a start condition on SDA.
13. The master sends the most significant data byte.
14. The master asserts ACK on SDA.
2. The master sends the 7-bit slave address followed by the
write bit (lowV.
15. The master sends the least significant data byte.
3. The addressed slave device asserts ACK on SDA.
16. The master asserts NACK on SDA, so the slave knows that
the data transfer is complete.
4. The master sends a register address of all ꢀs in order to
write to the command register.
17. The master asserts a stop condition on SDA to end the
transaction.
5. The addressed slave device asserts ACK on SDA.
6. The master writes to the command register.
7. The slave asserts ACK on SDA.
1
9
1
0
9
SCL
0
0
0
1
1
A4
A3
A2
A1
A0
0
0
0
0
R/W
SDA
START BY
MA STER
ACK. BY
AD7294
ACK. BY
AD7294
FRAME
2
FRAME
1
COMMAND POINTER REGISTER BYTE
SERIAL BUS ADDRESS BYT E + WRITE
9
1
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
C8
C7
C6
C4
C3
C2
C1
P7
P6
P5
P3
P2
4
P1
P0
C5
P4
ACK. BY
AD7294
ACK. BY
AD7294
FRAME
3
FRAME
COMMAND REGISTER VALUE
POINTER TO RESULT REGISTER
1
1
9
SCL (CONTINUED)
SDA (CONTINUED)
1
A4
A3
A2
A1
A0
R/W
ACK. BY
AD7294
REPEATED START
BY MASTER
FRAME
5
SERIAL BUS ADDRESS BYTE + READ
1
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
CHID
D11
D3
CHID CHID
D10
D9
D8
D7
D6
D5
D4
D2
7
D1
D0
ALERT
ACK. BY
MASTER
NO ACK BY STOP BY
MASTER
MASTER
FRAME
6
FRAME
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
Figure 32. Reading 2-Bytes from Result Register
Rev. PrB | Page 35 of 45
AD7294
Preliminary Technical Data
2ꢀ. The addressed slave device asserts ACK on SDA.
21. The master sends a register address.
22. The slave asserts ACK on SDA.
Writing a Single Byte of Data to an 8-Bit Register
The alert registers, power down register, channel sequence
register, offset registers, and the command register are 8-bit
registers; therefore, only one byte of data can be written to each.
In this operation, the master device sends a byte of data to the
slave device. To write data to the register, the command
sequence is as follows:
23. The master sends a data byte.
24. The slave asserts ACK on SDA.
18. The master device asserts a start condition on SDA.
25. The master asserts a stop condition on SDA to end the
transaction.
19. The master sends the 7-bit slave address followed by the
write bit (lowV.
1
9
1
9
SCL
P3
1
1
A4
A3
A2
A1
A0
P7
P6
P5
P4
P2
P1
P0
R/W
SDA
START BY
MAST ER
ACK. BY
AD7294
ACK. BY
AD7294
FRAME 2
FRAME 1
SERIAL BUS ADDRESS BYTE
ADDRESS POINTER REGISTER BYTE
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D3
D7
D6
D5
D2
D1
D0
D4
ACK. BY
AD7294
STOP BY
MASTER
FRAME 3
DATA BYTE
Figure 33. Single-Byte Write Sequence
Rev. PrB | Page 36 of 45
Preliminary Technical Data
AD7294
4. The master sends a register address. The slave asserts ACK
on SDA.
Writing Two Bytes of Data to a 16-Bit Register
Both types of limit registers, the hysteresis registers, the result
register, the TSENSE result registers, the configuration register,
and the fuse registers are 16-bit registers; therefore, two bytes of
data are required to write a value to any one of these registers.
Writing two bytes of data to one of these registers consists of the
following:
5. The master sends the first data byte
6. The slave asserts ACK on SDA.
7. The master sends the second data byte.
8. The slave asserts ACK on SDA.
1. The master device asserts a start condition on SDA.
9. The master asserts a stop condition on SDA to end the
transaction.
2. The master sends the 7-bit slave address followed by the
write bit (lowV.
3. The addressed slave device asserts ACK on SDA.
1
9
1
9
SCL
P3
0
1
A4
A3
A2
A1
A0
P7
P6
P5
P4
P2
P1
P0
R/W
SDA
START BY
MASTER
ACK. BY
AD7294
ACK. BY
AD7294
FRAME 1
SERIAL BUS ADDRESSBYTE
FRAME 2
ADDRESSPOINTER REGISTER
1
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
0
0
D11
D3
0
0
D10 D9
D8
D7
D6
D5
D2 D1/0 D0/0
D4
ACK. BY
AD7294
ACK. BY
AD7294
STOP BY
MASTER
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
Figure 34. 2-Byte Write Sequence
Rev PrB | Page 37 of 45
AD7294
Preliminary Technical Data
MODES OF OPERATION
register choose the sequence of conversions required. At this
point the ADC will power up and begin channel conversions.
When supplies are first applied to the AD7294 the ADC powers
up in sleep mode and normally rmains in this shutdown state
while not converting. There are two different methods of
initiating a conversion on the AD7294.
Also take note that the address pointer must be re-addressed to
the result register to read the conversions results. For each
channel conversion in the sequence, the frame is re-addressed
to the result register to synchronize the frames. When more
then one channel is selected in the command register. The first
read accesses the data from the conversion on channel1. While
this read takes place, a conversion occurs on channel 2. The
second read accesses this data from channel 2 and so on.
MODE 1 – COMMAND MODE
In this mode the part cycles through the selected channels on
each subsequent read. To setup the command mode the
command register must first be told which ADC channels to
convert on, see Table 7 . In the case of TSENSE1, TSENSE2 and
TSENSEINT, the command mode is not actually requesting a
conversion but outputting the last automatic conversion in
sequence. In the case of the internal temperature sensor
TSENSEINT, it is not possible to read the result via the ADC result
register. The result is stored in the TSENSEINT result register.
Figure 35 illustrates a 2–byte read operation from the result
register. Prior to the read operation, ensure that the address
pointer is pointing to the command register. In the command
The wake-up and conversion time together should take
approximately 5 μs, and the conversion begins when the last bit
in the command register has been clocked in.
1
9
1
0
9
SCL
0
0
0
1
1
A4
A3
A2
A1
A0
0
0
0
0
R/W
SDA
START BY
MA STER
ACK. BY
AD7294
ACK. BY
AD7294
FRAME
2
FRAME
1
COMMAND POINTER REGISTER BYTE
SERIAL BUS ADDRESS BYT E + WRITE
9
1
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
C4
P3
C8
C7
C6
C3
C2
C1
P7
P6
P5
P2
4
P1
P0
C5
P4
ACK. BY
AD7294
ACK. BY
AD7294
FRAME
3
FRAME
COMMAND REGISTER VALUE
POINTER TO RESULT REGISTER
1
1
9
SCL (CONTINUED)
SDA (CONTINUED)
1
A4
A3
A2
A1
A0
R/W
ACK. BY
AD7294
REPEATED START
BY MASTER
FRAME
5
SERIAL BUS ADDRESS BYTE + READ
1
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
CHID
D11
D3
CHID CHID
D10
D9
D8
D7
D6
D5
D2
7
D1
D0
D4
ALERT
ACK. BY
MASTER
NO ACK BY
MASTER
STOP BY
MASTER
FRAME
6
FRAME
MOST SIGNIFICANT DATA BYTE
LEAST SIGNIFICANT DATA BYTE
Figure 35. Command Mode Operation
Rev. PrB | Page 38 of 45
Preliminary Technical Data
AD7294
sequence, starting with the lowest channel. Once the sequence
is complete, the ADC starts converting on the lowest channel
again, continuing to loop through the sequence until the cycle
timer register contents are set to all ꢀs. This mode is useful for
monitoring signals, such as signal power and current sensing,
alerting only when the limits are violated. To exit the autocycle
mode the user must write all zeroes to the channel sequence
register or disable the autocycle mode in the configuration
MODE 2 – AUTOCYCLE MODE
An automatic conversion cycle can be selected and enabled by
initially selecting the enable autocycle mode option in the
configuration register. The desired sequence of the autocycle
mode is controlled using the channel sequence register. The
automatic cycle mode can be set on the four uncommitted
analog input channels along with the two ISENSE channels. When
the 6 LSBs of this register are programmed with any
configuration other than all ꢀs, a conversion takes place every 5
ms. In autocycle mode the sample delay and bit trial delay are
two configuration options which can be used to maintain ADC
performance when I2C bus activity is taking place during a
conversion.
register.
Figure 36 shows the autocycle mode where
only one channel is chosen from the channel sequence register.
Depending on the controller of the I2C interface, it is also
possible to break the long write frame into two shorter frames,
where a second frame can begin after writing to the
configuration register. After writing to the configuration
register, the user can stop the frame, re-address the part and
write to the channel sequence.
If more than one channel bit is set in the channel sequence
register, the ADC automatically cycles through the channel
1
9
1
0
9
SCL
0
0
1
1
1
A4
A3
A2
A1
A0
0
0
0
1
R/W
SDA
START BY
MA ST ER
ACK. BY
AD7294
ACK. BY
AD7294
FRAME
2
FRAME
1
POINTER TO CONFIGURATION REGISTER
SERIAL BUS ADDRESS BYT E + WRITE
9
1
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
D11
D10
D3
D15
D14
D13
1
D9
D8
D7
D6
D5
D4
D2
4
D1
D0
ACK. BY
AD7294
ACK. BY
AD7294
FRAME
3
FRAME
CONFIGURATION REGISTER VALUE MSB
CONFIGURATION REGISTER VALUE LSB
9
1
0
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
0
0
0
0
D3
0
0
D7
D6
D5
D4
D2
6
D1
D0
ACK. BY
AD7294
ACK. BY
AD7294
FRAME
5
FRAME
POINTER TO CHANNEL SEQUENCE REGISTER
CHANNEL SEQUENCE REGISTER
1
9
9
1
0
9
SCL (CONTINUED)
SDA (CONTINUED)
0
0
0
1
1
A4
A3
A2
A1
A0
1
0
0
0
R/W
ACK. BY
AD7294
.
REPEATED START
BY MASTER
FRAME
8
FRAME
7
SERIAL BUS ADDRESS BYTE + READ
POINTER TO RESULT REGISTER
9
1
9
1
9
SCL (CONTINUED)
SDA (CONTINUED)
CHID
D11
D3
CHID CHID
D10
D9
D8
D7
D6
D5
D4
D2
D1
D0
ALERT
NO ACK
.
AD7294
ACK. BY
AD7294
STOP BY
MASTER
FRAME
9
FRAME 10
LEAST SIGNIFICANT DATA BYTE
MOST SIGNIFICANT DATA BYTE
Figure 36. Autocycle Mode Operation
Rev. PrB | Page 39 of 45
AD7294
Preliminary Technical Data
LAYOUT AND CONFIGURATION
The power supply line should have as large a trace as possible to
provide a low impedance path and reduce glitch effects on the
supply line. Clocks and other components with fast switching
digital signals should be shielded from other parts of the board
by a digital ground. Avoid crossover of digital and analog
signals if possible. When traces cross on opposite sides of the
board, ensure that they run at right angles to each other to
reduce feedthrough effects on the board. The best board layout
technique is the microstrip technique where the component
side of the board is dedicated to the ground plane only and the
signal traces are placed on the solder side; however, this is not
always possible with a 2-layer board.
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, carefully consider the
power supply and ground return layout on the board. The
printed circuit board containing the AD7294 should have
separate analog and digital sections, each having its own area
of the board. If the AD7294 is in a system where other devices
require an AGND-to-DGND connection, the connection
should be made at one point only. This ground point should be
as close as possible to the AD7294.
The power supply to the AD7294 should be bypassed with
1ꢀ µF and ꢀ.1 µF capacitors. The capacitors should physically be
as close as possible to the device, with the ꢀ.1 µF capacitor
ideally right up against the device. The 1ꢀ µF capacitors are the
tantalum bead type. It is important that the ꢀ.1 µF capacitor has
low effective series resistance (ESRV and low effective series
inductance (ESIV; common ceramic types of capacitors are
suitable. The ꢀ.1 µF capacitor provides a low impedance path to
ground for high frequencies caused by transient currents due to
internal logic switching.
Rev. PrB | Page 4± of 45
Preliminary Technical Data
AD7294
EVALUATION BOARD FOR THE AD7294
on the AD7294 evaluation board, is available in the EꢁAL-
AD7294EB application note and should be consulted when
evaluating the board.
The AD7294 evaluation board consists of the AD7294 LFCSP
package along with two RSENSE resistors and a number of SMB
sockets and jumpers, which allow access to the various on-chip
functionalities of the AD7294. Other on-board components are
used to interface the part to the PC, such as an EEPROM, a
USB Microcontroller and a voltage regulator. More information,
Rev. PrB | Page 41 of 45
AD7294
Preliminary Technical Data
Figure 37. Evaluation Board Schematic
Rev. PrB | Page 42 of 45
Preliminary Technical Data
AD7294
Figure 38. Component Side Artwork
Figure 39. Component Side SilkScreen
Rev. PrB | Page 43 of 45
AD7294
Preliminary Technical Data
Figure 40. Solder-Side Artwork
Rev. PrB | Page 44 of 45
Preliminary Technical Data
OUTLINE DIMENSIONS
AD7294
0.30
0.23
0.18
8.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
43
42
56
1
PIN 1
INDICATOR
6.25
6.10 SQ
5.95
TOP
VIEW
EXPOSED
7.75
BSC SQ
PAD
(BOTTOM VIEW)
0.50
0.40
0.30
29
28
14
15
0.25 MIN
6.50
REF
0.80 MAX
0.65 TYP
1.00
0.85
0.80
12° MAX
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.50 BSC
0.20 REF
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
Figure 41. LFCSP-56 Pin Package
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR05747-0-3/06(PrB)
Rev. PrB | Page 45 of 45
相关型号：
AD7294-2BSUZ-RL
12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense
ADI
AD7294BCPZRL
12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense
ADI
©2020 ICPDF网 联系我们和版权申明