AD7293_技术文档

12-Bit Power Amplifier Current Controller with

ADC, DACs, Temperature and Current Sensors

Data Sheet

AD7293

FEATURES

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

4 closed-loop power amplifier (PA) drain current controllers

Built-in PA protection, sequencing, and alert features

Compatible with both depletion mode and enhancement mode

power amplifiers

PAV

PRECISION

2.5V

DD

PMOS

CONTROL

PA_ON

REFERENCE

AD7293

1

×

2

1.25V

2.5V

Highly integrated

–

BIPOLAR

DAC

Σ

4 uncommitted 12-bit analog-to-digital converter (ADC) inputs

0.ꢀ LSB typical integral nonlinearity (INL)

Eight 12-bit voltage digital-to-analog converters (DACs)

1.3 μs maximum settling

+

0V TO +5V

–4V TO +1V

–5V TO 0V

12-BIT

SAR ADC

4 high-side current sense amplifiers, 0.1% gain error

2 external temperature sensor inputs, 1.1ꢁC accuracy

Internal temperature sensor, 1.2ꢀꢁC accuracy

2.ꢀ V on-chip reference

MUX

ALERT

AND LIMIT

REGISTERS

UNIPOLAR

DAC

D0+

Flexible monitoring and control ranges

ADC input ranges: 0 V to 1.2ꢀ V, 0 V to 2.ꢀ V, and 0 V to ꢀ V

Bipolar DAC ranges: 0 V to +ꢀ V, −4 V to +1 V, and −ꢀ V to 0 V

Bipolar DAC reset and clamping relative to V_CLAMPxvoltage

Unipolar DAC ranges: 0 V to ꢀ V, 2.ꢀ V to 7.ꢀ V, and ꢀ V to 10 V

Current sense gain: 6.2ꢀ, 12.ꢀ, 2ꢀ, ꢀ0, 100, and more

Adjustable closed-loop setpoint ramp time

High-side voltage current sensing

0V TO 5V

2.5V TO 7.5V

5V TO 10V

D0–

D1+

CONTROL

LOGIC

D1–

RESET

SPI

DIGITAL

LDAC AND

INPUT/OUTPUT CLAMP CONTROL

LOGIC INTERFACE

4 current sense inputs

4 V to AV_SS+ 60 V, 200 mV input range

Small package and flexible interface

Serial port interface (SPI) with V_DRIVEsupporting 1.8 V, 3 V, and

ꢀ V interfaces

ꢀ6-lead LFCSP

Figure 1.

The device also includes limit registers for alert functions and four

high-side current sense amplifiers to measure current across

external shunt resistors. These amplifiers can be optionally set to

operate as part of four independent closed-loop drain current

controllers.

Temperature range: −40ꢁC to +12ꢀꢁC

APPLICATIONS

GaN and GaAs power amplifier monitoring and controls

Base station power amplifiers

General-purpose system monitoring and controls

A high accuracy 2.ꢀ V internal reference is provided to drive the

DACs and the ADC. The 12-bit ADC monitors and digitizes the

internal temperature sensor, and two inputs are included for the

external diode temperature sensors.

GENERAL DESCRIPTION

The AD7293 is a PA drain current controller containing

functionality for general-purpose monitoring and control of

current, voltage, and temperature, integrated into a single chip

solution with an SPI-compatible interface.

Note that throughout this data sheet, multifunction pins, such

as GPIO4/ALERT1, are referred to either by the entire pin name

or by a single function of the pin, for example, ALERT1, when

only that function is relevant.

The device features a 4-channel, 12-bit successive approximation

register (SAR) ADC, eight 12-bit DACs (four bipolar and four

unipolar with output ranges that can be configured to shut

down under external pin control), a 1.2ꢀ5C accurate internal

temperature sensor, and eight general-purpose input/output

(GPIO) pins.

PRODUCT HIGHLIGHTS

1. Four independent closed-loop drain current controllers.

2. Built-in monitoring, sequencing, and alert features.

3. Compatible with both depletion mode and enhancement

mode power amplifiers.

Rev. B

Document Feedback

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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Technical Support

www.analog.com

AD7293

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

AV_DDand AV_SSAlarm................................................................ 30

Maximum and Minimum Pages............................................... 30

Hysteresis..................................................................................... 30

Register Settings.............................................................................. 31

Registers Common to All Pages............................................... 32

Result 0/DAC Input (Page 0x00).............................................. 33

Result 1 (Page 0x01)................................................................... 35

Configuration (Page 0x02)........................................................ 36

Sequence (Page 0x03) ................................................................ 45

High Limit 0 (Page 0x04) .......................................................... 47

High Limit 1 (Page 0x05) .......................................................... 48

Low Limit 0 (Page 0x06)............................................................ 49

Low Limit 1 (Page 0x07)............................................................ 50

Hysteresis 0 (Page 0x08)............................................................ 51

Hysteresis 1 (Page 0x09)............................................................ 52

Minimum 0 (Page 0x0A)........................................................... 53

Minimum 1 (Page 0x0B) ........................................................... 54

Maximum 0 (Page 0x0C) .......................................................... 55

Maximum 1 (Page 0x0D) .......................................................... 56

Offset 0 (Page 0x0E)................................................................... 57

Offset 1 (Page 0x0F)................................................................... 59

Alert (Page 0x10)........................................................................ 60

ALERT0 Pin Routing (Page 0x11) ........................................... 62

ALERT1 Pin Routing (Page 0x12) ........................................... 66

Serial Port Interface........................................................................ 70

Interface Protocol....................................................................... 70

Modes of Opertion..................................................................... 71

Applications Information.............................................................. 75

Base Station Power Amplifier Control .................................... 75

Depletion Mode Amplifier Biasing and Protection............... 76

Loop Component Selection ...................................................... 77

Outline Dimensions....................................................................... 78

Ordering Guide .......................................................................... 78

Applications....................................................................................... 1

General Description......................................................................... 1

Simplified Functional Block Diagram ........................................... 1

Product Highlights ........................................................................... 1

Revision History ............................................................................... 2

Functional Block Diagrams............................................................. 3

Specifications..................................................................................... 5

ADC ............................................................................................... 5

DAC................................................................................................ 6

Temperature Sensor ..................................................................... 7

Current Sensor.............................................................................. 8

Closed-Loop Specifications......................................................... 8

General........................................................................................... 9

Timing Characteristics .............................................................. 10

Absolute Maximum Ratings.......................................................... 12

Thermal Resistance .................................................................... 12

ESD Caution................................................................................ 12

Pin Configuration and Function Descriptions........................... 13

Typical Performance Characteristics ........................................... 16

Theory of Operation ...................................................................... 21

Analog-to-Digital Converter (ADC) Overview..................... 21

ADC Transfer Functions ........................................................... 21

Analog Inputs.............................................................................. 22

Current Sensor............................................................................ 22

Temperature Sensor ................................................................... 23

Internal Channel Monitoring ................................................... 24

DAC Operation........................................................................... 24

Reference ..................................................................................... 26

V_DRIVEFeature .............................................................................. 26

Open-Loop Mode....................................................................... 26

Closed-Loop Mode .................................................................... 26

Digital Input/Output Registers................................................. 28

Load DAC (LDAC Pin).............................................................. 28

Alerts and Limits ........................................................................ 28

REVISION HISTORY

1/2018—Rev. A to Rev. B

Changes to Ordering Guide ......................................................... 78

Changes to Figure 7........................................................................ 13

Changes to Table 11........................................................................ 14

Updated Outline Dimensions ...................................................... 78

6/2016—Revision A: Initial Version

Rev. B | Page 2 of 78

Data Sheet

AD7293

FUNCTIONAL BLOCK DIAGRAMS

REF

V

REFIN

ADC REFOUT

PRECISION

AD7293

2.5V

REFERENCE

BI-V

0

OUT MON

PAV

DD

PMOS

1

OUT MON

CONTROL

PA_ON

RS3+

2

OUT MON

1

2

×

3

OUT MON

CLOSED-LOOP 3

CLOSED-LOOP 2

1.25V

2.5V

RS3–

–

Σ

DACV

DD-BI

BIPOLAR

DAC

BI-V

3

OUT

+

DD-UNI

AV

SS

RS2+

RS2–

AV

DD

–

Σ

BIPOLAR

DAC

V

0

BI-V

2

1

IN

OUT

+

V

1

2

3

RS1+

RS1–

MUX

CLOSED-LOOP 1

CLOSED-LOOP 0

–

Σ

BIPOLAR

DAC

BI-V

OUT

+

D0+

RS0+

RS0–

CONTROL

LOGIC

1

–

Σ

BIPOLAR

DAC

BI-V

0

OUT

+

D0–

D1+

0V TO 5V

UNIPOLAR

DAC

UNI-V

0

OUT

2.5V TO 7.5V

5V TO 10V

UNIPOLAR

DAC

1

D1–

V

UNIPOLAR

DAC

DRIVE

ALERT AND

LIMIT

REGISTERS

2

3

DV

DD

UNIPOLAR

DAC

V

0

1

RESET

SPI

DIGITAL

LDAC AND

CLAMP

LOGIC INTERFACE

INPUT/OUTPUT CLAMP CONTROL

CLAMP

Figure 2. Closed-Loop Functional Block Diagram

Rev. B | Page 3 of 78

AD7293

Data Sheet

REF

V

REFIN

ADC REFOUT

PRECISION

AD7293

2.5V

REFERENCE

BI-V

0

OUT MON

PAV

DD

PMOS

1

OUT MON

CONTROL

PA_ON

RS0+

2

OUT MON

1

2

×

3

OUT MON

CURRENT

SENSOR

1.25V

2.5V

RS0–

DACV

DD-BI

0V TO +5V

–4V TO +1V

–5V TO 0V

BIPOLAR

DAC

BI-V

0

OUT

DD-UNI

AV

SS

RS1+

RS1–

CURRENT

SENSOR

AV

DD

BIPOLAR

DAC

V

0

BI-V

1

2

IN

OUT

V

1

2

3

RS2+

RS2–

CURRENT

SENSOR

MUX

BIPOLAR

DAC

BI-V

OUT

D0+

RS3+

RS3–

CURRENT

SENSOR

CONTROL

LOGIC

1

BIPOLAR

DAC

BI-V

3

OUT

D0–

D1+

0V TO 5V

2.5V TO 7.5V

5V TO 10V

UNIPOLAR

DAC

UNI-V

0

1

2

3

OUT

UNIPOLAR

DAC

D1–

V

UNIPOLAR

DAC

DRIVE

ALERT AND

LIMIT

REGISTERS

DV

DD

UNIPOLAR

DAC

V

0

1

RESET

SPI

DIGITAL

INPUT/OUTPUT

LDAC AND

CLAMP CONTROL

CLAMP

LOGIC INTERFACE

CLAMP

Figure 3. Open-Loop Functional Block Diagram

Rev. B | Page 4 of 78

Data Sheet

AD7293

SPECIFICATIONS

ADC

AV_DD, DV_DD, DACV_DD-BI= 4.5 V to 5.5 V (connect AV_DDand DACV_DD-BIto the same potential), DACV_DD-UNI= 5 V, AV _SS= − 5 V, PAV _DD

5 V, AGND = DGND = 0 V, V_REFIN= 2.5 V internal or external; V_DRIVE= 1.7 V to 5.5 V; T_A= −40°C to +125°C, unless otherwise noted.

=

Table 1.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

DC ACCURACY

Resolution

12

0.5

Bits

LSB

0.99 LSB

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Single-Ended Mode

Zero Code Error

Zero Code Error Mismatch

Full-Scale Error

1

No missing codes

0.4

0.6

2.5

6.5

LSB

Full-Scale Error Mismatch

Differential Mode

1.5

Gain Error

Gain Error Mismatch

Zero Code Error

3

6.5

2

LSB

1.5

0.5

0.6

Zero Code Error Mismatch

DYNAMIC PERFORMANCE

f_IN= 1 kHz sine wave; single-ended mode;

0 V to 4 × REF_ADC

Signal-to-Noise Ratio (SNR)^{1, 2}

Signal-to-Noise + Distortion (SINAD) Ratio^{1, 2}

Total Harmonic Distortion (THD)^{1, 2}

Channel to Channel Isolation²

Full Power Bandwidth²

72

−90.5

95

7

dB

f_IN= 100 Hz to 80 kHz

At 0.1 dB; single-ended mode; 0 V to 4 × REF_ADC

MHz

CONVERSION RATE

Conversion Time²

Track-and-Hold Acquisition Time²

ANALOG INPUT¹

500

100

ns

Voltage inputs in command mode

REF_ADC= 1.25 V

Single-Ended Input Range

0

1.25

2.5

5

1.25

2.5

5

+1.25

+2.5

+5

V

0 V to REF_ADCmode

0 V to 2 × REF_ADCmode

0 V to 4 × REF_ADCmode

0 V to REF_ADCmode

0 V to 2 × REF_ADCmode

0 V to 4 × REF_ADCmode

0 V to REF_ADCmode

3

Pseudo Differential Range (V_IN+− V_IN−

)

4

Differential Range (V_IN+− V_IN−

)

−1.25

−2.5

−5

0 V to 2 × REF_ADCmode

0 V to 4 × REF_ADCmode

V

pF

µA

Input Capacitance²

DC Input Leakage Current

30

1

INTERNAL BI-V_OUTx MONITORING INPUTS

Full-Scale Input Range

Resolution

Gain Error

Offset Error

−5

0

+5

V

Bits

%

12

0.53

14

LSB step size ≈ 2.5 mV

LSB step size ≈ 15.2 mV

mV

INTERNAL RSx+ MONITORING INPUTS

Full-Scale Input Range

Resolution

Gain Error

Offset Error

62.5

V

Bits

%

12

0.06

11

mV

Rev. B | Page 5 of 78

AD7293

Data Sheet

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

INTERNAL SUPPLY MONITORING INPUTS

AV_DD

.

Gain Error

0.33

%

Offset Error

52

mV

AV_SS

Gain Error

Offset Error

0.53

14

%

mV

DACV_DD-UNI

Gain Error

Offset Error

0.16

12

%

mV

DACV_DD-BI

Gain Error

Offset Error

0.33

52

%

mV

INTERNAL REFERENCE²

Reference Output Voltage

Reference Temperature Coefficient

EXTERNAL REFERENCE

Reference Input Voltage Range

DC Input Leakage Current

2.495 2.5

10

2.505

30

V

At T_A= 25°C only

ppm/°C

2.48

2.5

2.52

2

V

µA

¹See the Analog-to-Digital Converter (ADC) Overview section for more details.

²Guaranteed by design and characterization; not production tested.

³V_IN−= 0 V for specified performance.

⁴V_IN+and V_IN−must remain within GND and AV_DD

.

DAC

AV_DD, DV_DD, DACV_DD-BI= 4.5 V to 5.5 V (connect AV_DDand DACV_DD-BIto the same potential), DACV_DD-UNI= 5 V, AV _SS= − 5 V, PAV _DD

=

5 V, AGND = DGND = 0 V, V_REFIN= 2.5 V internal or external; V_DRIVE= 1.7 V to 5.5 V; T_A= −40°C to +125°C, unless otherwise noted.

Table 2.

Parameter

ACCURACY¹

Min

Typ

Max

Unit

Test Conditions/Comments

Resolution

Integral Nonlinearity (INL)

12

Bits

LSB

1

1.7

3

Bipolar

Unipolar

1

0.3

2.5

LSB

mV

Load current 10 mA within 300 mV of supply

Guaranteed monotonic

All 1s loaded to DAC register, no load applied

Differential Nonlinearity (DNL)

Full-Scale (FS) Error

−0.99

+1

0.65

% of FS 10 mA load applied

Offset Error

10

mV

Unipolar, 2.5 V to 7.5 V range, 5 V to 10 V range

10

12

mV

µV/°C

% FSR

ppm/°C

Unipolar, 0 V to 5 V range

Bipolar

Measured in the linear region, T_A= 25°C

Bipolar

2.5

8

Offset Error Temperature Coefficient

Gain Error

0.15

0.4

Unipolar

Gain Error Temperature Coefficient

DAC OUTPUT CHARACTERISTICS

Bipolar Open-Loop DAC Range

3

0

5

+1

0

5

7.5

10

V

BI-V_OUT0, BI-V_OUT1, BI-V_OUT2, and BI-V_OUT3

−4

−5

0

2.5

5

Unipolar DAC Range

UNI-V_OUT0, UNI-V_OUT1, UNI-V_OUT2, and UNI-V_OUT3

Rev. B | Page 6 of 78

Data Sheet

AD7293

Parameter

Min

Typ

40

42

Max

Unit

mA

nF

Test Conditions/Comments

Shorted to AGND or DACV_DD-UNI

Shorted to AV_SSor DACV_DD-BI

Source and/or sink within 300 mV of supply

R_L= ∞

Unipolar DAC Short-Circuit Current

Bipolar DAC Short-Circuit Current

Load Current²

−10

+10

Capacitive Load Stability

DC Output Impedance

AC CHARACTERISTICS

10

1

Ω

Midscale

Output Voltage Settling Time²

1.2

1.3

µs

¼ to ¾ change within 1 LSB, measured from

the last SCLK rising edge, C_L= 200 pF

Slew Rate²

7.5

0.1

0.2

55

110

102

135

V/µs

nV-sec

Digital Feedthrough²

DAC to DAC Crosstalk^{2, 3}

Output Noise Spectral Density^{2, 3}

nV/√Hz f_IN= 10 kHz, bipolar

nV/√Hz f_IN= 10 kHz, unipolar

µV p-p

Output Noise^{2, 3}

Bipolar

Unipolar

CLAMP INPUTS

Clamp Output Voltage²

Controlled by SLEEP0 and SLEEP1 digital pins

−3 ×

V

BI-V_OUTx = −3 × V_CLAMP0, V_CLAMP

1

V_CLAMP0,

V

_CLAMP1

Gain Error

0.2

5

1

%

Within 200 mV of AV_SS

Input Referred Offset Error

V_CLAMP0 and V_CLAMP1 Input Current

Clamp Voltage Range

Output Current²

Clamp to Open-Loop Settling Time²

mV

µA

V

mA

µs

AV_SS

−10

0

+10

5

Source and/or sink within 300 mV of supply

R_L= ∞, C_L= 200 pF, output voltage within 10%,

5 V transition

¹Specification tested with output unloaded. Linearity calculated using best fit line method and based on a reduced code range equivalent to 100 mV within either side

of supply or ground 82 codes.

²Guaranteed by design and characterization; not production tested.

³All unipolar DACs must be enabled with an output code set to a minimum code of 41 LSBs.

TEMPERATURE SENSOR

AV_DD, DV_DD, DACV_DD-BI= 4.5 V to 5.5 V (connect AV_DDand DACV_DD-BIto the same potential), DACV_DD-UNI= 5 V, AV _SS= − 5 V, PAV _DD

5 V, AGND = DGND = 0 V, V_REFIN= 2.5 V internal or external; V_DRIVE= 1.7 V to 5.5 V; T_A= −40°C to +125°C, unless otherwise noted.

=

Table 3.

Parameter

Min Typ

Max Unit Test Conditions/Comments

+125 °C See Figure 30 for −55°C to +125°C operation

INTERNAL TEMPERATURE SENSOR¹

Operating Range²

Accuracy

−40

1.25

0.125

3

°C

Internal temperature sensor, T_A= −40°C to +125°C

T_A= 25°C

Resolution

EXTERNAL TEMPERATURE SENSOR¹

External transistor = 2N3906; no capacitor between Dx−/Dx+ pins, and

no series resistor between transistor and Dx−/Dx+ pins

Operating Range

Accuracy

Resolution

−55

+150 °C

Limited by external transistor

T_A= −40°C to +105°C

LSB size

1.1

0.125

3

°C

¹Guaranteed by design and characterization; not production tested.

²Guaranteed functional to −55°C by design but accuracy is not guaranteed.

Rev. B | Page 7 of 78

AD7293

Data Sheet

CURRENT SENSOR

AV_DD, DV_DD, DACV_DD-BI= 4.5 V to 5.5 V (connect AV_DDand DACV_DD-BIto the same potential), DACV_DD-UNI= 5 V, AV _SS= −5 V, PAV_DD= 5 V,

AGND = DGND = 0 V, V_REFIN= 2.5 V internal or external; V_DRIVE= 1.7 V to 5.5 V; T_A= −40°C to +125°C, gain = 6.25, unless otherwise noted.

Table 4.

Parameter

Min

Typ

Max

Unit

Test Conditions/Comments

RSx+ = AV_DDto AV_SS+ 60 V

AV_SS= 0 V

CURRENT SENSE

Common-Mode Input Voltage Range

4

60

V

4

55

V

AV_SS= −5 V

Differential Input Voltage Range

Gain Error

−200

+200

0.7

mV

%

Gain = 6.25, for gain settings, see Table 44

0.1

Gain Error Temperature Coefficient

Offset Error (Referred to Input, RTI)

Offset Error Drift

DC Common-Mode Rejection

RSx+¹Pin Input Current

RSx−¹Pin Input Current

Differential Input Resistance²

−16

ppm/°C

µV

µV/°C

dB

µA

nA

200

1

100

140

105

10

700

kΩ

¹Where x is 0, 1, 2, or 3.

²Guaranteed by design and characterization; not production tested.

CLOSED-LOOP SPECIFICATIONS

AV_DD, DV_DD, DACV_DD-BI= 4.5 V to 5.5 V (connect AV_DDand DACV_DD-BIto the same potential), DACV_DD-UNI= 5 V, AV _SS= − 5 V, PAV _DD

5 V, AGND = DGND = 0 V, V_REFIN= 2.5 V internal or external; V_DRIVE= 1.7 V to 5.5 V; T_A= −40°C to +125°C, unless otherwise noted.

Power amplifier transconductance = 1 S to 5 S, and external gate filter time constant (τ_G) = 5 µs to 50 µs.

=

Table 5.

Parameter

NORMAL OPERATION^{1, 2}

Min

Typ

Max

Unit

Test Conditions/Comments

Setpoint Resolution

12

Bits

Equivalent to 200 mV/4096 = 49 µV at the current

sense input

Sense Resistor Voltage Range

Setpoint Gain Error

Setpoint Offset Error (RTI)

Integrator Time Constant³

Closed-Loop Update Rate³

Capacitive Load Stability

0

200

mV

%

0.5

100

840

59.6

1

µV

µs

kHz

µF

µs

V

Referred to current sense input; see Figure 31

Programmable; see Table 50

5 Ω series resistance

Within 10%

See the Bipolar DAC (BI-VOUTx) Offset Registers

(Register 0x34 to Register 0x37) section

Closed-Loop to Clamp Settling Time

Bipolar Closed-Loop Output Range

1

AV_SS

AV_DD

Integrator Programmable Voltage Limit Resolution

2.5

mV

See the Closed-Loop Integrator Programmable

Voltage Limit section

START SEQUENCING PA_ON CONTROL²

PA_ON Pin Output Voltage

AGND

PAV_DD

500

V

µs

PA_ON Off State Enable

Measured from AV_SSfailure event, C_L= 1 nF

Measured from SLEEP0 or SLEEP1 pin, 0 to 1

transition, C_L= 1 nF

PA_ON On State Enable

PA_ON Short-Circuit Current

PA_ON Resistance

500

µs

mA

Ω

Measured from SLEEP1 to SLEEP0 transition, C_L= 1 nF

10

250

AV_DD/AV_SSALARM

AV_DDAlarm Threshold

AV_SSAlarm Threshold

3.2

−3.8

3.6

−4.1

3.9

−4.4

V

¹Power amplifier characteristic dependent.

²Guaranteed by design and characterization; not production tested.

³Expressed as a function of the internal oscillator frequency.

Rev. B | Page 8 of 78

Data Sheet

AD7293

GENERAL

DV_DD, AV_DD, DACV_DD-BI= 4.5 V to 5.5 V (connect AV_DDand DACV_DD-BIto the same potential), DACV_DD-BI= 5 V, AV _SS= −5 V, RSx+ = AV_DDto

55 V, AGND = DGND = 0 V, V_REFIN= 2.5 V internal or external, V_DRIVE= 1.7 V to 5.5 V, T_A= −40°C to +125°C, unless otherwise noted.

Table 6.

Parameter

Symbol

Min

Typ

Max

Unit

Test Conditions/Comments

LOGIC INPUTS

Input Voltage

High

V_IH

V_IL

I_IN

0.8 × V_DRIVE

V

µA

pF

Low

0.2 × V_DRIVE

Input Leakage Current

Input Capacitance

LOGIC OUTPUTS¹

1

3

C_IN

GPIO0/IS BLANK, GPIO1/CONVST,

GPIO2/BUSY, GPIO3/ALERT0, and

GPIO4/ALERT1 are open-drain outputs

Output Voltage

High

Low

Floating-State Leakage Current

Floating-State Output Capacitance

GENERAL-PURPOSE OUPUTS

Output Voltage

High

V_OH

V_OL

0.4

0.6

1

V

µA

pF

I_SINK= 3 mA

I_SINK= 6 mA

8

V_OH

V_OL

V_DRIVE− 0.2

0.4

V

I_SINK/I_SOURCE= 1 mA

Low

POWER REQUIREMENTS

Supply Voltages

Positive Analog

Negative Analog

Logic Power

Unipolar DAC

Bipolar DAC

PA_ON Power

RSx+ Voltage

AV_DD

AV_SS

V_DRIVE

DACV_DD-UNI

DACV_DD-BI

PAV_DD

V_RSx+

4.5

−5.5

1.7

4.5

4

5.5

−4.5 or 0

5.5

12.5

5.5

V

Supports 1.8 V, 3 V, and 5 V interfaces

AV_SS+ 60

Supply Currents

All power supplies set to maximum

voltage; ADC on and converting;

DACs enabled with no load applied

AV_DD

AV_SS

V_DRIVE

DACV_DD-UNI

DACV_DD-BI

PAV_DD

AI_DD

AI_SS

I_DRIVE

DACI_DD-UNI

DACI_DD-BI

PAI_DD

9

−4.4

1

2.1

5

81

110

12.5

−5.4

2.1

3

8.2

100

mA

µA

Power Dissipation

mW

¹Guaranteed by design and characterization; not production tested.

Rev. B | Page 9 of 78

AD7293

Data Sheet

TIMING CHARACTERISTICS

SPI Serial Interface

AV_DD, DV_DD, DACV_DD-BI= 4.5 V to 5.5 V (connect AV_DDand DACV_DD-BIto the same potential), DACV_DD-UNI= 2.7 V to 16 V, AV_SS= 0 V,

RSx+ = AV_DDto 55 V, AGND = DGND = 0 V, V_REFIN= 2.5 V internal or external, V_DRIVE= 1.7 V to 5.5 V, T_A= −40°C to +125°C, unless

otherwise noted.

Table 7.

Limit at T_MIN/T_MAX

Parameter

Description

V_DRIVE= 1.7 V to 2.7 V

V_DRIVE= 2.7 V to 5.5 V

Unit

f_SCLK

t₁

t₂

t₃

t₄

Frequency of serial read clock¹

8

15

66.67

26

5

MHz max

ns min

ns max

ns min

ns max

SCLK period

SCLK low

SCLK high

CS falling edge to SCLK rising edge

DIN setup time to SCLK rising edge

DIN hold time after SCLK rising edge

Last SCLK rising edge to CS rising edge

CS high

150

40

5

t₅

t₆

10

5

10

5

2

t₇

t₈

12

1

10

1

3

t₉

CS rising edge to next SCLK rising edge

SCLK falling edge to CS falling edge

t₁₀

t₁₁

1

SCLK falling edge to output data valid delay time from

60

30

high impedance⁴

t₁₂

t₁₃

t₁₄

SCLK falling edge to output data valid delay time⁴

Last SCLK falling edge to DOUT high impedance⁴

CS rising edge to DOUT high impedance⁴

60

20

25

30

20

15

ns max

ns typ

ns max

¹DOUT loaded with 10 pF for DOUT timing specifications.

²Time required for the output to cross 0.2 × V_DRIVEand 0.8 × V_DRIVEwhen V_DRIVE< 2.7 V; time required for the output to cross 0.3 × V_DRIVEand 0.7 × V_DRIVEwhen 2.7 ≤ V_DRIVE≤5.5 V.

³Guaranteed by design and characterization; not production tested.

⁴MISO speed set to maximum in the general register.

Asynchronous Inputs

AV_DD, DV_DD, DACV_DD-BI= 4.5 V to 5.5 V (connect AV_DDand DACV_DD-BIto the same potential), DACV_DD-UNI= 2.7 V to 16 V, AV_SS= 0 V,

RSx+ = AV_DDto 55 V, AGND = DGND = 0 V, V_REFIN= 2.5 V internal or external, V_DRIVE= 1.7 V to 5.5 V, T_A= −40°C to +125°C, unless

otherwise noted.

Table 8.

Limit at T_MIN/T_MAX

Parameter

Description

V_DRIVE= 1.7 V to 2.7 V

V_DRIVE= 2.7 V to 5.5 V

Unit

1

t₁₅

Minimum LDAC pulse width

Minimum CONVST pulse width

Minimum IS BLANK pulse width

Minimum RESET pulse width

90

ns min

t₁₆

t₁₇

t₁₈

¹Guaranteed by design and characterization; not production tested.

Rev. B | Page 10 of 78

Data Sheet

AD7293

Timing Diagrams

t₈

CS

t₇

t₄

t₁

t₉

t₁₀

SCLK

t₃

t₂

t₅

t₆

DIN

P7(W/R)

P0

MSB

LSB

t₁₃

t₁₁

t₁₂

t₁₄

DOUT

LSB

Figure 4. Serial Interface Timing Diagram

LDAC

CONVST

IS BLANK

RESET

t₁₅

t₁₆

t₁₇

t₁₈

Figure 5. Asynchronous Inputs

200µA

I

OL

V

DRIVE

2

TO OUTPUT PIN

C

L

50pF

I

200µA

OH

Figure 6. Load Circuit for Digital Output (DOUT) Timing Specifications

Rev. B | Page 11 of 78

AD7293

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 9.

Stresses at or above those listed under Absolute Maximum

Ratings may cause permanent damage to the product. This is a

stress rating only; functional operation of the product at these

or any other conditions above those indicated in the operational

section of this specification is not implied. Operation beyond

the maximum operating conditions for extended periods may

affect product reliability.

Parameter

Rating

5 V Analog Output Pins (BI-V_OUT0, BI-V_OUT1,

BI-V_OUT2, BI-V_OUT3) to AV_SS

12.5 V Analog Output Pins (UNI-V_OUT0,

UNI-V_OUT1, UNI-V_OUT2, UNI-V_OUT3) to AGND

12.5 V Supply (DACV_DD-UNI) to AGND

2 V Analog Pins (REF_ADC, D1−, D1+, D0−, D0+)

to AGND

AV_SS− 0.3 V to

DACV_DD-BI+ 0.3 V

−0.3 V to

DACV_DD-UNI+ 0.3 V

−0.3 V to +15 V

−0.3 V to +2 V

THERMAL RESISTANCE

5 V Analog Pins (FACTORY TEST, V_REFIN

,

−0.3 V to

AV_DD+ 0.3 V

−0.3 V to

θ_JAis specified for a 4-layer JEDEC 2S2P type printed circuit

board (PCB) with a thermal via, that is, a device soldered in a

circuit board for surface-mount packages, per JESD51-7.

V_REFOUT, V_CLAMP0, V_CLAMP1, V_INx¹) to AGND

5 V Digital Pins (GPIO5/SLEEP0,

GPIO6/SLEEP1, RESET, GPIO7/LDAC, CS,

DOUT) to DGND

5 V Open-Drain Pins (GPIO4/ALERT1, SCLK,

DIN, DV_DD, GPIO3/ALERT0, GPIO2/BUSY,

GPIO1/CONVST, GPIO0/IS BLANK) to DGND

V

_DRIVE+ 0.3 V

Table 10. Thermal Resistance

−0.3 V to +7 V

Package Type

θ_JA

θ_JC

Unit

56-Lead LFCSP

27

0.5

°C/W

5 V Supply Pins²(V_DRIVE, DACV_DD-BI, AV_DD) to

AGND

−5 V Supply Pin (AV_SS) to AGND

60 V Analog Pins (RSx−) to RSx+

−0.3 V to +7 V

−7 V to +0.3 V

(RSx+) − 0.3 V to

(RSx+) + 0.3 V

ESD CAUTION

60 V Digital Pin (PA_ON) to AGND

−0.3 V to

PAV_DD+ 0.3 V

60 V Supply Pins (RSx+, PAV_DD) to AGND

−0.3 V to

AV_SS+ 65 V

Ground Pins (DGND, AGND) to AGND

Operating Temperature Range

Storage Temperature Range

Reflow Profile

Maximum Junction Temperature

ESD Rating, All Pins

−0.3 V to +0.3 V

−40°C to +125°C

−65°C to +125°C

J-STD 20 (JEDEC)

150°C

Human Body Model (HBM)

Field-Induced Charged Device Model

(FICDM)

2 kV

1 kV

¹x = 0, 1, 2, or 3.

²Connect AV_DDand DACV_DD-BIto the same potential.

Rev. B | Page 12 of 78

Data Sheet

AD7293

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

FACTORY TEST

GPIO4/ALERT1

GPIO5/SLEEP0

GPIO6/SLEEP1

RESET

1

2

3

4

5

6

7

8

9

42 REF

41 PAV

ADC

DD

40 PA_ON

39 RS0+

38 RS0–

37 RS1+

36 RS1–

35 AGND

34 RS2+

33 RS2–

32 RS3+

31 RS3–

GPIO7/LDAC

SCLK

AD7293

TOP VIEW

(Not to Scale)

CS

DIN

DOUT 10

DGND 11

V

12

13

14

DRIVE

30 V

0

1

DV

CLAMP

DD

DD-UNI

29 V

DACV

CLAMP

NOTES

1. EXPOSED PAD. THE EXPOSED PAD IS LOCATED ON THE UNDERSIDE OF THE

PACKAGE. CONNECT THE EXPOSED PAD TO AV USING MULTIPLE VIAS OR

SS

LEAVE IT FLOATING.

Figure 7. Pin Configuration

Table 11. Pin Function Descriptions

Pin Number

Mnemonic

Description

1

2

FACTORY TEST

GPIO4/ALERT1

Factory Test Pin. Leave this pin unconnected, or connect it to DGND.

General-Purpose Input/Output 4 Pin (GPIO4, Default as Input).

Alert 1 Pin (ALERT1, Default). When configured as an alert, this pin acts as an out of range

indicator. The polarity of the pin is register selectable. This pin is an open-drain output, and

requires a pull-up resistor connected to V_DRIVE

.

3

4

GPIO5/SLEEP0

GPIO6/SLEEP1

General-Purpose Input/Output 5 Pin (GPIO5, Default as Input).

Sleep 0 Pin (SLEEP0). DAC power-down digital input pin (polarity is register selectable). This

pin can be configured to trigger DAC clamping on any combination of DAC channels.

General-Purpose Input/Output 6 Pin (GPIO6).

Sleep 1 Pin (SLEEP1, Default). DAC power-down digital input pin (polarity is register

selectable). This pin can be configured to trigger DAC clamping on any combination of DAC

channels.

5

6

RESET

Reset Input. Taking this pin low performs a hardware reset.

General-Purpose Input/Output 7 Pin (GPIO7).

GPIO7/LDAC

DAC Load Pin (LDAC, Default). When this input is active, the DAC registers are updated. The

polarity of this pin is register selectable. See the Load DAC (LDAC Pin) section for more

information.

7

8

9

SCLK

CS

SPI Serial Clock Input.

Chip Select Signal. This active low, logic input signal frames the serial data input.

DIN

SPI Serial Data Input. The serial data loaded into the registers is provided on this pin. Data is

clocked into the device on the rising edge of SCLK.

10

11

DOUT

DGND

SPI Serial Data Output. The serial data read from the registers is provided on this pin. Data is

clocked out on the falling edge of SCLK. DOUT is high impedance when it is not outputting

data.

Digital Ground. DGND is the ground reference point for all digital circuitry. Refer all digital

signals to DGND. Connect both the DGND and AGND pins to the ground plane of the system.

Rev. B | Page 13 of 78

AD7293

Data Sheet

Pin Number

Mnemonic

V_DRIVE

DV_DD

Description

12

13

14

Drive Voltage Reference Level of the SPI Bus from 1.7 V to 5.5 V.

Digital Supply Voltage from 4.5 V to 5.5 V.

DAC Positive Supply Pin for the Unipolar DAC Output Amplifiers on UNI-V_OUT0, UNI-V_OUT1, UNI-

V_OUT2, and UNI-V_OUT3.

DACV_DD-UNI

15, 16, 18, 19 UNI-V_OUT0, UNI-V_OUT1,

UNI-V_OUT2, UNI-V_OUT3,

Unipolar DAC Outputs. The clamp and power-on reset voltage for these DACs is 0 V.

17, 22, 35, 43 AGND

Analog Ground. Connect both the AGND and DGND pins to the ground plane of the system.

Reference Input to the Device. Connect this pin to an external reference voltage, or tie this

20

V_REFIN

pin to V_REFOUT

.

21

V_REFOUT

2.5 V Reference Output. Connect to V_REFINto operate in internal reference mode. An optional

10 nF capacitor is recommended between the reference output and AGND for noise filtering.

23, 24, 27, 28 BI-V_OUT0, BI-V_OUT1,

Bipolar DAC Outputs in Open-Loop Mode and Integrator Outputs in Closed-Loop Mode. The

clamp and power-on reset voltage for these DACs is dictated by the V_CLAMPx pins.

BI-V_OUT2, BI-V_OUT

3

25

26

AV_SS

DAC Negative Supply Pin for the BI-V_OUT0, BI-V_OUT1, BI-V_OUT2, and BI-V_OUT3 DAC Output

Amplifiers.

Analog Supply Pin for BI-V_OUT0, BI-V_OUT1, BI-V_OUT2, and BI-V_OUT3. Connect AV_DDand DACV_DD-BIto

the same potential.

DACV_DD-BI

29

30

V_CLAMP

RS3−, RS2−, RS1−, RS0−

RS3+, RS2+, RS1+, RS0+

PA_ON

1

0

Power-On Reset and Clamp Voltage for BI-V_OUT2 and BI-V_OUT3.

Power-On Reset and Clamp Voltage for BI-V_OUT0 and BI-V_OUT1.

Negative Connection for External Shunt Resistors.

31, 33, 36, 38

32, 34, 37, 39

40

Positive Connection for External Shunt Resistors.

Power Amplifier On. This pin drives an external, positive channel metal oxide semiconductor

(PMOS) switch capable of turning on/off the drain current to a PA transistor. The maximum

voltage is set by PAV_DDand limited to AV_SS+ 60 V. The power amplifier is turned on when the

output is low. The AV_SSand AV_DDsupply alarms can be configured to automatically trigger

PA_ON. An alert condition can be configured to trigger PA_ON. Additionally, PA_ON can be

turned on/off by issuing a register write.

41

42

PAV_DD

REF_ADC

Power Supply for the PA_ON Control Signal. This pin is limited to 4 V to AV_SS+ 60 V.

Internal ADC Reference Voltage. The output at this pin is half the reference value (V_REFIN),

1.25 V. Connect decoupling capacitors to this pin to decouple the reference buffer. For best

performance, connect a 4.7 µF compensation capacitor between REF_ADCand AGND. For

stability, the amplifier requires a minimum capacitance of 220 nF (X7R/C0G ceramic)

connected between REF_ADCand AGND, located as close to the AD7293 as possible (no more

than 1 Ω of interconnect resistance).

44

AV_DD

Supply Voltage for All of the Analog Circuitry on the AD7293. The operating range is 4.5 V to

5.5 V. Connect AV_DDand DACV_DD-BIto the same potential.

45 to 48

V_IN3, V_IN2, V_IN1, V_IN0

ADC Analog Inputs. Unused inputs must not be left floating. The input range of these pins is

register selectable: 0 V to 1.25 V, 0 V to 2.5 V, or 0 V to 5 V.

49, 50, 51, 52 D1−, D1+, D0−, D0+

Temperature Sensor Analog Inputs. Connect these pins to the external temperature sensing

transistor. Tie these pins to AGND if unused.

53

54

55

GPIO3/ALERT0

General-Purpose Input/Output 3 Pin (GPIO3, Default as Input).

Alert 0 Pin (ALERT0). When ALERT0 is configured as an alert, this pin acts as an out of range

indicator. Open-drain output whether in GPIO mode or alert mode. The polarity of this pin is

register selectable. A pull-up resistor connected to V_DRIVEis required.

GPIO2/BUSY

General-Purpose Input/Output 2 Pin (GPIO2, Default as Input).

Busy Pin (BUSY). When BUSY is configured as a busy output, this pin becomes active when a

conversion is in progress. Open-drain output whether in GPIO mode or busy mode. The

polarity of this pin is register selectable. A pull-up resistor connected to V_DRIVEis required.

General-Purpose Input/Output 1 Pin (GPIO1, Default as Input). This pin is an open-drain

output in GPIO mode. The polarity of this pin is register selectable.

GPIO1/CONVST

ADC External Convert Start Input Pin (CONVST). CONVST triggers conversions via this pin. The

CONVST pin is useful for synchronizing the ADC sampling instant with an external source. A

pull-up resistor connected to V_DRIVEis required in GPIO mode or if unused.

56

GPIO0/IS BLANK

General-Purpose Input/Output 0 Pin (GPIO0, Default as Input). This pin is an open-drain

output in GPIO mode. The polarity of this pin is register selectable. A pull-up resistor

connected to V_DRIVEis required in GPIO mode or if unused.

Current Sensor Conversion Blank Pin (IS BLANK). This pin can blank current sensor

conversions and the polarity of this pin is register selectable.

Rev. B | Page 14 of 78

Data Sheet

AD7293

Pin Number

Mnemonic

EPAD

Description

Exposed Pad. The exposed pad is located on the underside of the package. Connect the

exposed pad to AV_SSusing multiple vias or leave it floating.

Rev. B | Page 15 of 78

AD7293

Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

0

1.0

0.8

M = 131072 SAMPLES

f_S= 131.072kHz

f_IN= 1.005kHz

–20

f_IN= 1.005kHz

RUNS = 20

0.6

NONCOHERENT SAMPLING

–40

EFFECTIVE SAMPLES = 2621440

HITS/CODE = 640

SEVEN-TERM BLACKMAN-HARRIS WINDOW USED

M = 131072 SAMPLES

0.4

–60

f_S= 131.072kHz

0.2

f_IN= 1.005kHz

–80

–100

–120

–140

–160

–180

SNR = 72.6366dB

THD = –91.63dB

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

10

20

30

40

50

60

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

FREQUENCY (kHz)

Figure 8. Signal-to-Noise Ratio, Single-Ended Input, 2 × REF_ADCRange

Figure 11. ADC INL Single-Ended, REF_ADCRange

0

2.5

2.0

f_IN= 1.005kHz

–20

1.5

NONCOHERENT SAMPLING

–40

SEVEN-TERM BLACKMAN-HARRIS WINDOW USED

M = 131072 SAMPLES

1.0

–60

f_S= 131.072kHz

0.5

f_IN= 1.005kHz

–80

–100

–120

–140

–160

–180

SNR = 73.5961dB

THD = –90.23dB

0

–0.5

–1.0

–1.5

–2.0

–2.5

–40

–20

0

20

40

60

80

100

120

0

10

20

30

40

50

60

TEMPERATURE (°C)

FREQUENCY (kHz)

Figure 12. ADC Zero Code Error vs. Temperature

Figure 9. Signal-to-Noise Ratio, Differential Input, REF_ADCRange

0

1.0

M = 131072 SAMPLES

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–6.0

–6.5

f_S= 131.072kHz

0.8

0.6

f_IN= 1.005kHz

RUNS = 20

EFFECTIVE SAMPLES = 2621440

HITS/CODE = 640

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–40

–20

0

20

40

60

80

100

120

140

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

TEMPERATURE (°C)

Figure 13. ADC Full-Scale Error vs. Temperature

Figure 10. ADC DNL Single-Ended, REF_ADCRange

Rev. B | Page 16 of 78

Data Sheet

AD7293

1.0

400

350

300

250

200

150

100

50

EXTERNAL REFERENCE, 0V TO +5V, UNIPOLAR DAC

INTERNAL REFERENCE, +5V TO +10V, UNIPOLAR

INTERNAL REFERENCE, –5V TO 0V, BIPOLAR DAC

EXTERNAL REFERENCE, –5V TO 0V, BIPOLAR DAC

EXTERNAL REFERENCE, +5V TO +10V, UNIPOLAR DAC

INTERNAL REFERENCE, 0V TO +5V, BIPOLAR DAC

BIPOLAR DNL, –5V TO 0V

BIPOLAR INL, –5V TO 0V

BIPOLAR DNL, –4V TO +1V

BIPOLAR INL, –4V TO +1V

BIPOLAR DNL, 0V TO +5V

BIPOLAR INL, 0V TO +5V

0.8

0.6

0.4

EXTERNAL REFERENCE, 0V TO +5V, BIPOLAR DAC

INTERNAL REFERENCE, 0V TO +5V, UNIPOLAR DAC

INTERNAL REFERENCE, –4V TO +1V, BIPOLAR DAC

EXTERNAL REFERENCE, –4V TO +1V, BIPOLAR DAC

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

0

40

540

1040

1540

2040

2540

3040

3540

4040

0

500 1000 1500 2000 2500 3000 3500 4000 4500

CODE

Figure 14. Bipolar DAC INL and DNL

Figure 17. 0.1 Hz to 10 Hz DAC Output Noise vs. Code

3

4.00

3.75

3.50

BIPOLAR, 0nF

BIPOLAR, 1nF

BIPOLAR, 10nF

UNIPOLAR, 0nF

UNIPOLAR, 1nF

UNIPOLAR, 10nF

2

1

0

–1

–2

–3

DNL UNIPOLAR, 2.5V TO 7.5V

INL UNIPOLAR, 5V TO 10V

INL UNIPOLAR, 2.5V TO 7.5V

DNL UNIPOLAR, 0V TO 5V

DNL UNIPOLAR, 5V TO 10V

INL UNIPOLAR, 0V TO 5V

40

540

1040

1540

2040

2540

3040

3540

4040

0

2

4

6

8

10

12

14

16

28

20

CODE

TIME (µs)

Figure 15. Unipolar DAC INL and DNL

Figure 18. Zoomed In Settling Time for a ¼ to ¾ Output Voltage Step

40

5.05

0V TO 5V, CODE 4095 (FULL SCALE)

0V TO 5V, CODE 3850 (FULL SCALE – 300mV)

30

20

5.00

4.95

4.90

4.85

4.80

4.75

4.70

4.65

10

0

–10

–20

–30

–40

0

5

10

15

20

25

30

35

40

0

2

4

6

8

10

12

14

16

TIME (Seconds)

LOAD CURRENT (mA)

Figure 16. 0.1 Hz to 10 Hz DAC Output Noise, Input Code 0x000

Figure 19. DAC4 Output (Full Scale) vs. Load Current

Rev. B | Page 17 of 78

AD7293

Data Sheet

–4.65

–4.70

–4.75

–4.80

–4.85

–4.90

–4.95

–5.00

16

14

12

10

8

UNIPOLAR OFFSET ERROR 0V TO +5V

UNIPOLAR OFFSET ERROR +2.5V TO +7.5V

UNIPOLAR OFFSET ERROR +5V TO +10V

BIPOLAR OFFSET ERROR 0V TO +5V

BIPOLAR OFFSET ERROR –4V TO +1V

BIPOLAR OFFSET ERROR –5V TO 0V

–5V TO 0V, CODE 246 (ZERO SCALE + 300mV)

–5V TO 0V, CODE 0 (ZERO SCALE)

6

4

2

0

–2

–5.05

–16

–4

–40

–14

–12

–10

–8

–6

–4

–2

0

–20

0

20

40

60

80

100

120

LOAD CURRENT (mA)

TEMPERATURE (°C)

Figure 20. BI-V_OUT0 Output Voltage (Zero Scale) vs. Load Current

Figure 23. DAC Offset Error vs. Temperature

6

4

12

11

10

9

–4.45

–4.50

–4.55

–4.60

–4.65

–4.70

–4.75

–4.80

–4.85

–4.90

–4.95

–5.00

–5.05

–5.10

AV

DD

PA_ON

AV

8

2

SS

DAC BIPOLAR OUTPUT

7

6

0

5

4

–2

3

2

BI-V

0 0/4 SCALE

0 1/4 SCALE

0 2/4 SCALE

0 3/4 SCALE

0 4/4 SCALE

OUT

–4

1

0

–1

–6

–80

0

5

10

15

20

25

30

35

40

–60

–40

–20

0

20

40

60

80

TIME (ms)

LOAD CURRENT (mA)

Figure 24. Bipolar DAC Response to AV_DDFailure

Figure 21. BI-V_OUT0 Output Voltage vs. Load Current

10

500

400

UNIPOLAR GAIN ERROR, +2.5V TO +7.5V

UNIPOLAR GAIN ERROR, +5V TO +10V

UNIPOLAR GAIN ERROR, 0V TO +5V

BIPOLAR GAIN ERROR, 0V TO +5V

BIPOLAR GAIN ERROR, –4V TO +1V

BIPOLAR GAIN ERROR, –5V TO 0V

5

0

300

200

100

–5

0

–100

–200

–300

–400

–500

–10

–15

–20

UNIPOLAR, 0V TO 5V, HIGH TO LOW

UNIPOLAR, 5V TO 10V, LOW TO HIGH

UNIPOLAR, 0V TO 5V, LOW TO HIGH

BIPOLAR, 0V TO 5V, HIGH TO LOW

UNIPOLAR, 5V TO 10V, HIGH TO LOW

BIPOLAR, 0V TO 5V, LOW TO HIGH

0

500

1000 1500 2000 2500 3000 3500 4000

CODE

–40

–20

0

20

40

60

80

100

120

TEMPERATURE (°C)

Figure 25. DAC Glitch Energy vs. Code

Figure 22. DAC Gain Error vs. Temperature

Rev. B | Page 18 of 78

Data Sheet

AD7293

1.0

0.5

–60

–65

0

–70

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

–5.5

–75

–80

–85

–90

–95

–100

–105

–110

–115

–120

SENSOR RESULT AT +25°C

–6.0

–6.5

–7.0

–7.5

SENSOR RESULT AT +105°C

SENSOR RESULT AT +150°C

SENSOR RESULT AT –40°C

100

1k

10k

100k

1M

10M

100M

10

100

1000

10000

FREQUENCY (Hz)

CAPACITANCE (pF)

Figure 26. Temperature Error vs. Capacitance from Dx+ to Dx−

Figure 29. High-Side Current Sensor at Common-Mode Rejection Ratio (CMRR)

5.0

2.504

2.503

2.502

2.501

SENSOR RESULT AT +150°C

SENSOR RESULT AT +105°C

SENSOR RESULT AT +25°C

SENSOR RESULT AT –40°C

SENSOR RESULT AT –55°C

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0

2.500

2.499

2.498

2.497

2.496

2.495

TESTER TRIMMED DUT1

TESTER TRIMMED DUT2

TESTER TRIMMED DUT3

TESTER TRIMMED DUT4

TESTER TRIMMED DUT5

TESTER TRIMMED DUT6

TESTER TRIMMED DUT7

TESTER TRIMMED DUT8

TESTER TRIMMED DUT9

TESTER TRIMMED DUT10

TESTER TRIMMED DUT11

TESTER TRIMMED DUT12

TESTER TRIMMED DUT13

–0.5

–60 –40 –20

0

20

40

60

80

100 120 140

0

1

2

3

4

5

6

7

8

9

10

TEMPERATURE (°C)

SERIES RESISTANCE (kΩ)

Figure 27. Temperature Error vs. Series Resistance for Typical Devices

Figure 30. ADC Reference vs. Temperature

1.0

0.8

0.10022

0.10020

0.10018

0.10016

0.10014

0.10012

0.10010

0.10008

0.10006

0.10004

0.10002

MIDSCALE DRIFT WITH EXTERNAL REFERENCE

MIDSCALE DRIFT WITH INTERNAL REFERENCE

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

–40

–20

0

20

40

60

80

100

120

–40

–20

0

20

40

60

80

100

120

DUT TEMPERATURE (°C)

TEMPERATURE (°C)

Figure 28. Temperature Sensor Error vs. Device Under Test (DUT)

Temperature

Figure 31. Closed-Loop R_SENSEVoltage Regulation vs. Temperature

Rev. B | Page 19 of 78

AD7293

Data Sheet

0.8

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

–5.0

BIPOLAR CHANNEL 0

10% LINE

1% LINE POSITIVE

1% LINE NEGATIVE

TIME ZERO

0.3

–0.2

–0.7

–1.2

–1.7

DNL: +25°C

INL: +25°C

DNL: +125°C

INL: +125°C

DNL: –40°C

INL: –40°C

0

1

2

3

4

5

6

7

8

9

10

TIME (µs)

DAC (Codes)

Figure 32. Closed-Loop INL and DNL

Figure 34. Closed Loop to Clamp Settling Time

–1.5

–2.0

–2.5

–3.0

–3.5

–4.0

–4.5

BIPOLAR CHANNEL 0

10% LINE

1% LINE POSTIVE

1% LINE NEGATIVE

TIME ZERO

–5.0

0

1

2

3

4

5

6

7

8

9

10

TIME (µs)

Figure 33. Open Loop to Clamp Settling Time

Rev. B | Page 20 of 78

Data Sheet

AD7293

THEORY OF OPERATION

ANALOG-TO-DIGITAL CONVERTER (ADC)

OVERVIEW

1LSB = 2 × REF

ADC

/4096

011...111

011...110

The AD7293 provides the user with a multichannel multiplexer,

an on-chip track-and-hold, and a successive approximation

ADC based around a capacitive DAC. The analog input range

000...001

000...000

for the ADC is selectable as a 0 V to REF_ADC, 0 V to 2 × REF_ADC

,

111...111

or 0 V to 4 × REF_ADCinput single-ended input, where REF_ADC

=

1.25 V.

100...010

100...001

The various monitored and uncommitted input signals are

multiplexed into the ADC. The AD7293 has four uncommitted

analog input channels, V_IN0 to V_IN3.

100...000

–REF

+ 1LSB

0

REF

– 1LSB

ADC

ANALOG INPUT

ADC TRANSFER FUNCTIONS

Figure 36. Differential Transfer Characteristics

The designed code transitions occur at successive integer least

significant bit (LSB) values (1 LSB, 2 × LSB, and so on). The

reference voltage for the ADC is referred from the main 2.5 V

reference through an amplifier that attenuates the voltage by

one half. REF_ADC= 1.25 V.

Table 12. Code Transition and Voltage

Code

Transition

Single-Ended

Voltage (V_IN)

Differential Voltage

(V_IN+ − V_IN−)

0x000 to 0x001 REF_ADC× Range/4096

−REF_ADC× Range ×

2047/2048

In single-ended mode, the LSB size is REF_ADC/4096 when the

0 V to REF_ADCrange is selected, 2 × REF_ADC/4096 when the 0 V

to 2 × REF_ADCrange is selected, and 4 × REF_ADC/4096 when the

0 V to 4 × REF_ADCrange is selected (which is the default value).

Figure 35 shows the ideal transfer characteristic for the ADC

when outputting straight binary coding.

0x7FF to 0x800 REF_ADC× Range/2

0 V

0xFFE to 0xFFF

REF_ADC× Range ×

4095/4096

+REF_ADC× Range ×

2047/2048

For V_IN0 to V_IN3 in single-ended mode, the output code is

straight binary, and the ideal input voltage is given by

V_IN= ((Code + 0.5)/ 4096) × REF_ADC× Range

The differential code is shown in Table 12, and the associated

voltage is calculated by

111...111

111...110

V

_IN+− V_IN−= ((Code − 2047.5)/2048) × REF_ADC× Range

111...000

where:

1LSB = REF

/4096

ADC

Code is the decimal equivalent of the binary code read from the

ADC register.

011...111

REF_ADC= 1.25 V.

000...010

000...001

000...000

Range = 1 when in the 0 V to REF_ADCrange.

Range = 2 when in the 0 V to 2 × REF_ADCrange.

Range = 4 when in the 0 V to 4 × REF_ADCrange.

REF

– 1LSB

ADC

1LSB

0V

ANALOG INPUT

NOTES

1.REF

Table 13. ADC Range Selected vs. LSB Size

IS REF

, 2 × REF

, OR 4 × REF .

ADC

Single-Ended

ADC LSB

Differential

ADC LSB

Figure 35. Single-Ended Transfer Characteristics

Range

00

01

10

11

Value

1

4 × REF_ADC

2 × REF_ADC

4 × REF_ADC/4096

2 × REF_ADC/4096

REF_ADC/4096

8 × REF_ADC/4096

4 × REF_ADC/4096

2 × REF_ADC/4096

In differential mode, the LSB size is 2 × REF_ADC/4096 when the

0 V to REF_ADCrange is selected, 4 × REF_ADC/4096 when the 0 V to

2 × REF_ADCrange is selected, and 8 × REF_ADC/4096 when the 0 V

to 4 × REF_ADCrange is selected. Figure 36 shows the ideal transfer

characteristic for the ADC when outputting differential coding

(with the 2 × REF_ADCrange).

1

REF_ADC

¹REF_ADC= 1.25 V.

Rev. B | Page 21 of 78

AD7293

Data Sheet

Pseudo Differential Mode

ANALOG INPUTS

The four uncommitted analog input channels can be configured

as two pseudo differential pairs. Two uncommitted inputs, V_IN0

and V_IN1, are a pseudo differential pair, as are V_IN2 and V_IN3. In

this mode, V_IN+is connected to the signal source, which can have

The AD7293 has four analog inputs, V_IN3 to V_IN0. Depending

on the configuration register setup, they can be configured as

four single-ended inputs or two fully differential channels.

Single-Ended Mode

a maximum amplitude of REF_ADC, 2 × REF_ADC, or 4 × REF_ADC

,

The AD7293 can have four single-ended analog input channels.

In applications where the signal source is high impedance, it is

recommended to buffer the analog input before applying it to the

ADC. The analog input range is programmed to the following

modes: 0 V to REF_ADC, 0 V to 2 × REF_ADC, or 4 × REF_ADCmode.

The voltage, with respect to AGND on the ADC analog input

pins, cannot exceed AV_DD.

depending on the range that is chosen, to make use of the full

dynamic range of the device. A dc input is applied to V_IN−. The

voltage applied to this input provides an offset from ground or a

pseudo ground for the V_IN+input. The ADC channel allocation

determines the channel specified as V_IN+. The differential mode

must be selected to operate in the pseudo differential mode. The

resulting converted pseudo differential data is stored in twos

complement format in the result register.

Differential Mode

The AD7293 can have two differential input pairs (V_IN3 and V_IN2,

V_IN1 and V_IN0). The amplitude of the differential signal is the

difference between the signals at V_IN+and V_IN−(V_IN0 and V_IN1,

or V_IN3 and V_IN2). Simultaneously drive V_IN+and V_IN−by two

For V_IN0, the governing equation for the pseudo differential

mode is

V

_OUT= 2(V_IN+− V_IN−) − REF_ADC

where:

signals, each of amplitude REF_ADC, 2 × REF_ADC, or 4 × REF_ADC

,

V

_IN+is the single-ended signal.

_IN−is a dc voltage.

depending on the range chosen, which are 180° out of phase.

REF_ADC= 1.25 V.

ADC

p-p

V

IN+

REF

AD7293¹

The benefit of pseudo differential inputs is that they separate

the analog input signal ground from the ADC ground, allowing

dc common-mode voltages to be cancelled.

COMMON-MODE

VOLTAGE

V

IN–

1

ADDITIONAL PINS OMITTED FOR CLARITY.

AD7293¹

V

p-p

Figure 37. Differential Input (V_IN+/V_IN−Refer to V_IN0 to V_IN3)

REF

V

IN+

Assuming that the 0 V to REF_ADCrange is selected, the amplitude

of the differential signal is, therefore, −REF_ADCto +REF_ADCpeak

to peak, regardless of the common-mode voltage (V_CM).

V

IN–

DC INPUT

VOLTAGE

The common-mode voltage is the average of the two signals.

1

ADDITIONAL PINS OMITTED FOR CLARITY.

(V_IN++ V_IN−)/2

Figure 38. Pseudo Differential Input (V_IN+/V_IN−Refer to V_IN0 to V_IN3)

The common-mode voltage is the voltage on which the two

inputs are centered. The result is that the span of each input is

V_CMREF_ADC/2. This common-mode voltage must be set up

externally.

CURRENT SENSOR

Four bidirectional high-side current sense amplifiers are

provided that can accurately amplify differential current shunt

voltages in the presence of high common-mode voltages from

AV_DDup to AV_SS+ 60 V. The current sensors can be read

directly, or optionally, they can be set to operate as part of the four

independent closed-loop, drain current controllers. See the

Closed-Loop section for more information.

When a conversion takes place, the common-mode voltage is

rejected, resulting in a virtually noise free signal of amplitude

−REF_ADCto +REF_ADC, corresponding to the digital output codes

of −2048 to +2047 in twos complement format.

When using the 2 × REF_ADCrange, the input signal amplitude

extends from −2 × REF_ADC(V_IN+= 0 V and V_IN−= REF_ADC) to

+2 × REF_ADC(V_IN−= 0 V and V_IN+= REF_ADC).

In open-loop operation, the current sense amplifiers measure

the current through a shunt resistor. Each amplifier can accept

differential inputs up to 200 mV. A selectable gain amplifies

the measured voltage drop across the current sensor.

Similarly, when using the 4 × REF_ADCrange, the input signal

amplitude extends from −4 × REF_ADC(V_IN+= 0 V and V_IN−

=

REF_ADC) to +4 × REF_ADC(V_IN−= 0 V and V_IN+= REF_ADC).

Rev. B | Page 22 of 78

Data Sheet

AD7293

The AD7293 high-side current sense amplifier is configured as

V

_RSx−is the voltage for the RSx− pins.

a differential integrator.

REF_ADC= 1.25 V.

RESET

Gain can be set between 6.25 and 781.25 as shown in Table 14.

I_SENSELSB = 2 × (REF_ADC/(Gain × 4096 × R_SENSE))

where:

RESET, HOLD

6pF

224kΩ

RSx+

RSx–

+

–

I

_SENSELSB is the current sense input channel LSB size in

amperes.

_SENSEis the external sense resistor.

Choosing the External Sense Resistor (R_SENSE

224kΩ

+

R

6pF

)

The resistor values used in conjunction with the current sense

amplifiers on the AD7293 are determined by the specific applica-

tion requirements in terms of voltage, current, and power.

RESET

Figure 39. Current Sensor Internal Diagram

Small resistors minimize power dissipation, have low induct-

ance to prevent induced voltage spikes, and have good tolerance,

which reduces current variations. The final values chosen are a

compromise between low power dissipation and good accuracy.

Low value resistors have less power dissipation and good accu-

racy; however, higher value resistors may be required to use the

full input range of the ADC.

Before each measurement, the integrator is held in a reset state

for 9.2 µs. The input is then connected and measured for a

programmable amount of time, resulting in a gain equal to the

following:

Gain = Integration Time/(224 kΩ × 6 pF)

Table 14. Current Sensor Gain Settings

Typical

When the sense current is known, the voltage range of the

AD7293 current sensor is divided by the maximum sense

current to yield a suitable resistor value. If the power dissipation

in the shunt resistor is too large, the shunt resistor can be

reduced, in which case, the current sensor gain can be increased

to maximize the ADC input range used.

Typical Voltage Across Integration

Code

0000 (Default)

0001

0010

0011

0100

0101

0110

0111

Gain

6.25

12.5

18.75

25

37.5

50

75

100

200

400

781.25

R_SENSE¹(mV)

200

100

66.67

50

33.33

25

16.67

12.5

6.25

3.125

1.6

Time (µs)

8.4

16.8

25.2

33.6

50.4

67.2

100.8

134.4

268.8

537.6

1050

R

_SENSEmust be able to dissipate the I²R losses. If the power

dissipation rating of the resistor is exceeded, its value may drift,

or the resistor may be damaged, resulting in an open circuit. If

the power dissipation of the resistor is exceeded, it can result in

a differential voltage across the AD7293 terminals in excess of

the absolute maximum ratings.

1000

1001

1010

Current Sensor Input Voltage Range

R_SENSE

≤

I_SENSE(MAX)

¹R_SENSEis the external sense resistor.

When integration is complete, the input switches open, keeping

the output constant until the ADC completes its conversion of

the output signal. If no other ADC channels are enabled, the

conversion takes an additional 4.2 µs. Otherwise, the current

sense amplifier waits for its turn in the ADC conversion

sequence before resetting and starting a new measurement.

where:

_SENSEis the value of the current sense resistor in Ω.

Current Sensor Input Voltage Range is the current sensor

amplifier input voltage range as dictated by the gain setting

chosen (see Table 14).

R

I

_{SENSE (MAX)}is the maximum current required in A.

Keep the external source impedance low with respect to the

input resistance of the integrator to avoid creating a gain error.

TEMPERATURE SENSOR

The AD7293 contains one local and two remote temperature

sensors. The temperature sensors can continuously monitor the

three temperature inputs, and new readings are automatically

available every 5 ms.

Calculate the current sensor input channel LSB as follows:

V

_SENSELSB = (2 × REF_ADC)/(Gain × 4096)

V

_RSx+− V_RSx−= −REF_ADC/Gain, with DOUT = 0x000

_RSx+− V_RSx−= 0 V, with DOUT = 0x7FF

The on-chip temperature sensor measures the device die

temperature. The internal temperature sensor measures

between −40°C and 125°C, where the LSB size is 0.125°C.

V

_RSx+− V_RSx−= REF_ADC/Gain, with DOUT = 0xFFF

where:

The AD7293 includes two remote temperate sensors. The

device is factory calibrated to work with 2N3906 discrete

transistors.

V

_SENSELSB is the current sense input channel LSB size in volts.

_RSx+is the voltage for the RSx+ pins.

Rev. B | Page 23 of 78

AD7293

Data Sheet

For RF applications, the use of high Q capacitors functioning as

a filter protects the integrity of the measurement. Connect these

capacitors between the base and the emitter, as close to the

external device as possible. However, large capacitances affect

the accuracy of the temperature measurement; therefore, the

recommended maximum capacitor value is 100 pF. In most

cases, a capacitor is not required; the selection of any capacitor

is dependent on the noise frequency level.

and 0xFFFF equates to approximately +2.5 V. R E F _ADC= 1.25 V.

For RSx+_MON(internal monitoring of the voltage on the RS0+ to

RS3+ pins), divide by 50 to scale them to the 0 V to REF_ADC

range. Use the ADC in single-ended mode. The RSx+_MONmonitor

result registers store the 12-bit ADC results for the current sense

supply channels (see Figure 42).

0V TO +62.5V

–5V TO +5V

0V TO +1.25V

RS0+

RS1+

RS2+

RS3+

MON

The AD7293 automatically cancels out the effect of parasitic,

base, and collector resistance on the temperature reading. This

cancelation gives a more accurate result, without the need for

any user characterization of the parasitic resistance. The AD7293

can compensate for up to 4 kΩ series resistance typically.

BI-V

0

OUT MON

–5V TO +5V

1

12-BIT

SAR ADC

OUT MON

MUX

–5V TO +5V

2

OUT MON

–5V TO +5V

3

OUT MON

0V TO +6.25V

0V TO 25V

AD7293

DACV

DD-BI

DACV

DD-UNI

–7.5V TO +2.5V

0V TO +6.25V

2N3904

NPN

AV

SS

Dx+

10pF

AV

DD

Dx–

Figure 42. Internal Channel Monitoring

Figure 40. Measuring Temperature Using a NPN Transistor

DAC OPERATION

The AD7293 contains eight 12-bit DACs, four bipolar DACs,

and four unipolar DACs. These provide digital control with 12 bits

of resolution combined with offset range select registers and a

2.5 V internal reference. The DAC core is a 12-bit string DAC. The

resistor string structure consists of a string of resistors, each of

Value R. The code loaded to the DAC register determines at

which node on the string the voltage is tapped off to be fed into

the output amplifier. When one of the switches connecting the

string to an amplifier is closed, the voltage is tapped off. This

architecture is inherently monotonic and linear. The eight DACs

are split into two groups based on their output range.

AD7293

Dx+

10pF

2N3906

Dx–

PNP

Figure 41. Measuring Temperature Using a PNP Transistor

Table 15. Temperature Sensor Data Format

Temperature

(°C)

T_SENSEx Result Registers (Page 0x00,

Register 0x20 to Register 0x22), Bits[D15:D4]

−40

−25

−10

−0.125

0

+0.125

+10

+25

+50

+75

0110 1100 0000

0111 0011 1000

0111 1011 0000

0111 1111 1111

1000 0000 0000

1000 0000 0001

1000 0101 0000

1000 1100 1000

1001 10 01 0000

1010 0101 1000

1011 0010 0000

1011 1110 1000

Bipolar DACs

The bipolar DACs (BI-V_OUT0, BI-V_OUT1, BI-V_OUT2, and BI-V_OUT3)

can be configured through the offset range registers to 0 V to

+5 V, −5 V to 0 V, or −4 V to +1 V (see Table 85).

Writing to these register addresses sets the 12-bit DAC output

voltage. There is also a load bit and a copy bit (see Table 27).

If the load bit is set to 1, the device waits for LDAC to become

active before loading the voltage codes onto the DACs rather than

immediately after the write operation. If the copy bit is set to 1

when writing to a bipolar DAC register, it sets all bipolar DAC

registers to the same value in open-loop mode only.

+100

+125

INTERNAL CHANNEL MONITORING

The ADC can internally read the outputs of the four bipolar

DACs, AV_DD, DACV_DD-UNI, DACV_DD-BI, AV_SS, and the voltage on

the RS0+ to RS3+ pins in the background. A sequencer is

available that allows multiple channels to be converted in a

predetermined sequence.

D



















V_OUT= 2×V

×

+V

OFFSET



REFIN

2ⁿ





where:

_REFIN= 2.5 V.

V

D is the decimal equivalent of the binary code that is loaded to

the DAC register (0 to 4095 for the 12-bit AD7293).

n is the resolution of the DAC.

The ADC is used in its single-ended mode. The LSB size varies

with the different supply monitoring registers. AV_DDand DACV_DD-BI

are divided by 5, and DACV_DD-UNIis divided by 20 to scale within

the 0 V to REF_ADCrange. AV_SSis level shifted to within a −7.5 V

to +2.5 V range, where 0x0000 equates to approximately −7.5 V,

V

_OFFSET= 0 V (0 V to +5 V range), −4 V (−4 V to +1 V range), or

−5 V (−5 V to 0 V range).

Rev. B | Page 24 of 78

Data Sheet

AD7293

Table 16. Bipolar DAC Voltage Offset Ranges

Table 17. Unipolar DAC Voltage Offset Ranges

Range (V)

0x000

0xFFF

V_OFFSET(V )

Range (V)

0x000

0xFFF

V_OFFSET(V)

0 to +5

−4 to +1

−5 to 0

0 V

2 V × V_REFIN

0.4 V × V_REFIN

0 V

0

−4

−5

0 to 5

2.5 to 7.5

5 to 10

0 V

V_REFIN

2 V × V_REFIN

3 V × V_REFIN

4 V × V_REFIN

0

2.5

5

−1.6 V × V_REFIN

−2 V × V_REFIN

The ADC can also monitor these four outputs.

DAC Enabling and Clamping

The bipolar DACs in addition to the four current sensors in the

PA controller can operate as four independent closed-loop

drain current controllers (see the Closed-Loop Mode section).

CLAMP/

On power-up, the DAC outputs default to their clamp values

(see Table 18). All DACs can be enabled and disabled/clamped

via the DAC enable register (common to all pages).

DAC

0V TO +5V

Table 18. Clamp Values

RANGE

ENABLE

2.5V

REF

–4V TO +1V

–5V TO 0V

SELECT

DAC Output

Clamp Value

REF(+)

UNI-V_OUT

0

1

2

3

0 V

BI-V

X

OUT

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

REF(–)

–3

V

X

BI-V_OUT

0

1

2

3

−3 × V_CLAMP

0

1

CLAMP

Figure 43. Bipolar DAC Architecture Block Diagram

Unipolar DACs

The unipolar DAC outputs, UNI-V_OUT0, UNI-V_OUT1, UNI-

All DACs (bipolar DACs only on power-up) can be set to clamp

using the digital SLEEP0 and SLEEP1 pins. The DAC outputs

controlled by the digital SLEEP0 and SLEEP1 pins are selectable by

writing to the corresponding sleep bit in the DAC snooze/SLEEPx

pin register (see Table 45) in the configuration page. When the

SLEEPx pin is pulled active, the corresponding unipolar and

bipolar DACs associated with the pin are forced into clamp.

Clamping does not clear the DAC output register value, making

it possible to return to the same voltage as before the clamp

event. While in clamp mode, the DAC registers can be updated.

When a SLEEPx pin is used, a snooze function is available that

clears the DAC registers and requires an additional write to the

DAC enable register to wake up the DAC after clearing the clamp

condition.

V_OUT2, and UNI-V_OUT3, can be configured through the offset

range registers to 0 to 5 V, 2.5 V to 7.5 V, or 5 V to 10 V (see

Table 84).

The DACs have one control register to control the interaction

between two registers: input registers and output registers. The

output registers contain the digital code used by the resistor

strings as well as a copy and load bit. Writing to these register

addresses sets the 12-bit DAC output voltage codes.

If the load bit is set to one, the device waits for LDAC to become

active before loading the voltage codes onto the DACs rather than

immediately after the write operation. If the copy bit is set to 1,

writing to a unipolar DAC registers sets all the other unipolar

DAC registers to the same value.

The bipolar DACs power-on reset and clamp value is dependent

on the V_CLAMP0 and V_CLAMP1 voltage level. After a power-on reset

or when the digital SLEEP0 or SLEEP1 pin is configured to trigger

a clamp, the bipolar DAC outputs reset to the clamp value (see

Table 18).

D



















V_OUT= 2×V

×

+V

OFFSET



REFIN

2ⁿ





where:

_REFIN= 2.5 V.

V

D is the decimal equivalent of the binary code that is loaded to

the DAC register (0 to 4095 for the 12-bit AD7293).

n is the resolution of the DAC.

After a power-on reset or when the digital SLEEP0 or SLEEP1

pin is configured to trigger clamping, the unipolar DAC outputs

default to 0 V.

V

_OFFSET= 0 V (0 V to 5 V range), 2.5 V (2.5 V to 7.5 V range), or

Software Clamping: Internal ALERT0 Routing

5 V (5 V to 10 V range).

CLAMP/

DAC

ENABLE

There is an option to allow the ALERT0 alert to trigger the

clamp function. The DACs power back up when the alert is

cleared without an additional write to the DAC enable registers.

Bit D1 of the general register in the configuration page allows

ALERT0 control over the clamping function of the four bipolar

DACs.

0V TO 5V

RANGE

SELECT

2.5V

REF

2.5V TO 7.5V

5V TO 10V

REF(+)

UNI-V

X

OUT

INPUT

REGISTER

DAC

REGISTER

RESISTOR

STRING

REF(–)

Figure 44. Unipolar DAC Architecture Block Diagram

Rev. B | Page 25 of 78

AD7293

Data Sheet

PMOS Drain Switch Control

OPEN-LOOP MODE

The AD7293 PA_ON output pin is capable of driving an

external PMOS switch. This external PMOS turns on or off the

drain current to a PA field effect transistor (FET). The PA_ON

output pin controls the device during power-up and power-down.

This feature can also be used as a protection feature when an

alert condition is detected because ALERT0 alerts or an AV_SSor

AV_DDsupply failure can be used to trigger the PA_ON pin.

PAV_DDdetermines the maximum voltage at the output of the

PA_ON pin. The off state is equal to PAV_DDwhile the on state is

equal to AGND. The default state of the PA_ON signal is off.

V p-p

In open-loop mode, the default mode of operation, the current

sense amplifiers and bipolar DACs operate independently.

CLOSED-LOOP MODE

Alternatively, the AD7293 current sensors and bipolar DACs

can operate as four independent closed-loop drain current

controllers (closed-loop mode).

In closed-loop operation, the drain current through the PA FET

is set and automatically maintained by the PA controller through a

regulation circuit that includes the DAC and current sense moni-

tor. The control loop sets the PA bias current and continuously

maintains a constant voltage across the sense resistor (V_SENSE

=

PAV

DD

I

_SENSE× R_SENSE). When the DAC current updates, the closed-loop

PMOS

CONTROL

adjusts the gate voltage of the PA until the drain current matches

the corresponding DAC code. The continuous regulation of the

loop compensates for variations of the PA threshold or voltage

drop on the LPF due to the PA gate current. The integrator

leads to a smooth transition on the output of the pin.

PMOS

DRAIN

SWITCH

PA_ON

RSx+

CURRENT

SENSOR

R

SENSE

RSx–

AD7293

RF IN

RF OUT

PA FET

RSx+

FILTER

RSx–

Figure 45. PMOS Drain Switch Control

REFERENCE

The AD7293 has one high performance, 2.5 V on-chip reference

accessed via the V_REFOUTpin. Noise performance can be improved

by the addition of a 10 nF capacitor between the V_REFOUTpin and

the AGND pin. Connect V_REFOUTto the V_REFINpin to use the

on-chip reference of the AD7293. An internal amplifier attenu-

BIPOLAR

DAC

Σ

(PROGRAMMABLE

RAMP TIME)

LPF

Figure 46. Closed-Loop Control

ates to the ADC core, making the voltage at the ADC, REF_ADC

1.25 V, half of V_REFIN= 2.5 V. Use the REF_ADCpin for measurement

purposes only.

=

Each of the four current closed loops consists of a DAC, an

error amplifier, and an integrator in the forward path to drive

the gate of the PA FET. A high-side current sense amplifier in

the feedback path senses that PA drain bias current and closes

the loop.

A 220 nF capacitor is required on the REF_ADCpin and must be

placed as close to the AD7293 as possible with no vias. The

internal reference typically requires 20 ms to power up and settle

when using a 220 nF decoupling capacitor on the REF_ADCpin.

An external gate filter can be introduced between the gate of the

power amplifier and the integrator output pins when operating

in closed-loop mode to limit the noise bandwidth and to ensure

PA stability. The gate filter time constant (τ_G) must be between

5 µs and 50 µs.

Buffer the internal reference before it is used by external circuitry.

The AD7293 can also operate with an external reference of

2.5 V connected to the V_REFINpin.

Adjustable Closed-Loop Setpoint Ramp Time

If using an external reference, select a low temperature coefficient

specification, such as the ADR4525, to reduce the temperature

dependence of the system output voltage on ambient conditions.

The transition between two successive setpoints of the DAC are

interpolated in a linear manner with the aid of a ramp generator.

When moving to a new closed-loop setpoint, limiting the rate of

change of the drain current is often required. To facilitate this,

the AD7293 can automatically generate a linear ramp between

the old and new DAC settings, over a programmable duration.

Write to the ramp time register to enable this feature, which

allows ramp times of between 4 ms and 31.75 ms to generate,

programmable in 250 µs steps. If a value of less than 4 ms is

written to the register, the ramp generator disables, and the new

V_DRIVEFEATURE

The AD7293 also has a V_DRIVEfeature that controls the voltage at

which the SPI operates. Connect the V_DRIVEpin to the supply to

which the SPI bus is pulled. The V_DRIVEpin sets the input and

output threshold levels for the digital logic pins. The V_DRIVE

feature allows the AD7293 to interface with 1.8 V, 3.3 V, and 5 V

processors.

Rev. B | Page 26 of 78

Data Sheet

AD7293

target DAC code is set immediately. Depending on the overall

loop time constant, an additional settling time can be required

after the end of the ramp for the drain current to reach the

ramp generator disables, and the DAC jumps to the target

value quickly.

3. Release the DACs out of clamp by writing to the DAC

enable register (Register 0x04) and wait 5 ms for the PAs to

settle to the initial drain current. At this point, ensure that

the programmed ramp time is 0, such that the ramp generator

is disabled, and the DAC resolves to the target value.

4. Program the desired ramp times for each channel by writing

to the corresponding ramp time registers (Register 0x2A to

Register 0x2D) from the configuration page.

prescribed set point.

SETTLING

TIME

RAMP TIME

DAC RAMP

5. Program the target drain current by writing to the DAC

registers. In addition to the ramp time, allow a delay of

1 ms before checking whether the PA drain current

corresponds to the intended target current. During the

active ramp period, if the DAC input register (Page 0x00,

Register 0x30 to Register 0x37) is read back, it is seen as

ramping up or ramping down to the target code.

R

VOLTAGE

S

Figure 47. Programmable Ramp Time Representation

If the user writes a new target drain current while the ramp is

active, the device restarts the internal timer and aims to reach

the new drain current within the programmed ramp time.

Fast Ramp Feature

To accelerate the initial settling of the closed loop, the fast ramp

feature can be enabled. When the ramp time register is programmed

to 0x0000, the ramp generator disables. In this mode, when the

current sense reading is less than 0x00F, the integrator time

constant is reduced to 408 µs, allowing the gate control voltage

to reach the PA threshold voltage as quickly as possible. When

above this current, the time constant automatically returns to its

programmed value. When a different switching threshold is

desired, use the current sense offset register to allow Code 0x00F to

represent a higher or lower current. This features may be useful to

prevent unwanted overshoot (lower threshold) or to speed up

settling (higher threshold).

If the device is configured in closed-loop mode, the ADC runs

conversions on the corresponding current sensor channel in the

background. In addition to the current sensor conversions,

additional channels can be configured to run background

conversions (via the corresponding background enable registers).

The user can read back the conversion results via the channel

specific result registers in Page 0x00 and Page 0x01.

Closed-Loop Integrator Programmable Voltage Limit

The AD7293 ADC can monitor the voltage at the output of the

integrator by writing to a register (Register 0x23) from the

configuration page (see Table 46).

Closed-Loop Sequencing

The integrator voltage limit feature allows the user to set upper

and lower limits on the integrator output voltage in closed-loop

mode of operation. When the integrator limit is active, the

integrator pauses and the output voltage holds constant. The

polarity of the error amplifier (comparison between measured

current and target current) determines when it is safe to deactivate

the soft limit. For example, a lower target current is programmed,

which makes the integrator output decrease, making it safe to

deactivate the integrator limit.

On power-up or following a reset, the system is configured as

follows:

•

The four bipolar outputs (BI-V_OUT0 to BI-V_OUT3) are set to

their clamp value, regardless of the levels of the SLEEP0 or

the SLEEP1 pin.

•

All of the DAC data registers are set to 0x0000, and the

bipolar DACs operate in open loop.

The PA_ON signal is set to the off state.

It is recommended to use the hysteresis registers (see Table 66

and Table 69) to avoid the device switching in and out of the

alert condition close to the limits. Additionally, the integrator

limit feature can be made a function of the upper/lower limits

only by ignoring the polarity of the error amplifier (via D2 of

the general register (Register 0x14) from the configuration page).

The integrator limit feature does not enable by default and can

be enabled by writing to the integrator limit and closed-loop

control register (Register 0x28).

To enter closed-loop operation, it is important to follow these steps:

1. Configure the AD7293 for closed-loop operating mode by

writing to the integrator limit and closed-loop control register

(Register 0x28) from the configuration page. Additionally,

if PMOS drain switch control is used, set the PA_ON signal

to the on state by writing to the PA_ON control register

(Register 0x29) from the same page.

2. The DACs must be programmed at this point. Choose the

target drain current such that the PA is within its operating

region. The I_SENSEgain setting must be left at the default

value of 6.25 in closed-loop mode. At this point, setting the

corresponding ramp time to 0 may be required so that the

Rev. B | Page 27 of 78

AD7293

Data Sheet

Closed-Loop Range Upper Voltage Limit

LOAD DAC (LDAC PIN)

An analog circuit within the output integrator creates a

hardware range upper limit on the output voltage of either 0 V or

1 V, as shown in Table 19. If the hardware limiting circuitry is

active, an alert appears on the INT_LIMITxand AV_SS/AV_DDalert

register (Register 0x1A). See the INTLIMITx and AVSS/AVDD

Alert Register (Register 0x1A) section.

The AD7293 DACs have doubled buffered interfaces consisting

of two banks of registers: input registers and DAC registers. The

user can write to any combination of the input registers. If the

load bit is held high when writing to a DAC, updates to the

DAC register are controlled by the LDAC pin.

Instantaneous DAC Updating (Asynchronous)

Table 19. Closed-Loop Range Upper Voltage Limit

In this operation mode, the SPI data is clocked into the DAC

input register on the rising edge of the SCLK. The output register is

updated, and the output begins to change. Instantaneous DAC

updating is only applicable when the load bit is not set when

writing to the DAC register. Hold the LDAC pin in its false state.

Operation

Open Loop

Closed Loop

Bipolar DAC Range (V)

X = don’t care

0 to +5

−4 to +1

−5 to 0

Range Limit

Off

On (1 V)

On (0 V)

Deferred DAC Updating (Synchronous)

DIGITAL INPUT/OUTPUT REGISTERS

In this mode, the SPI data is clocked into the DAC input registers

on the rising edge of the SCLK. However, the update of the

output registers can be blocked during the SPI write by setting

the load bit. The output registers can be synchronously updated

(data is transferred from the DAC input register to the DAC

output register) by taking the LDAC pin to its true state.

Eight pins can be set as GPIOs or can perform various digital

functions. Three registers located on the configuration page set

up the functionality of the GPIO interface. GPIO0 to GPIO3

default to the GPIOs on power-up. ALERT1, SLEEP0, SLEEP1,

and LDAC default to digital functions on power-up.

The GPIO register (Register 0x5) configures the GPIOs in the

device. In GPIO mode, and with the output drivers enabled, the

GPIO outputs reflect the value written to this register. In

functional mode, any write to this register has no effect on the

GPIO outputs. See the GPIO Register (Register 0x05) section.

ALERTS AND LIMITS

The high and low limit pages comprise registers that set the

high and low alerts for the analog input channels, the current

sensors, the internal supply monitoring channels, the internal

bipolar DAC monitoring channels, and the RSx+ monitoring

channels. Each register is 16 bits in length; values are 12-bit, left

justified (padded with 0s as the four LSBs). On power-up, the

low limit registers contain all zeros, whereas the high limit

registers contain 0xFFF0.

The digital output enable register (Register 0x11) enables the

output drivers of the GPIO pins; therefore, when using one of

the pins as an output in GPIO mode or functional mode (for

alerts and busy), the corresponding bit must be set. See the

Digital Output Enable Register (Register 0x11) section.

The alert high limit registers on Page 0x04 (High Limit 0) and

Page 0x05 (High Limit 1) store the upper limit that activates an

alert (see the High Limit 0 (Page 0x04) section and the High Limit

1 (Page 0x05) section). If the conversion result is greater than the

value in the alert high limit register, an alert triggers. The alert low

registers on Page 0x06 (Low Limit 0) and Page 0x07 (Low Limit 1)

store the low limit that activates an alert (see the Low Limit 0

(Page 0x06) section and the Low Limit 1 (Page 0x07) section). If

the conversion result is less than the value in the alert low limit

register, an alert triggers.

The digital input/output function register (Register 0x12) allows the

user to put the relevant pin into GPIO mode or functional mode.

See the Digital Input/Output Function Register (Register 0x12)

section.

The digital functional polarity register (Register 0x13) sets the

polarity of the digital input/output pins in functional mode only.

The associated input/output signal can be made active low or

active high. See the Digital Functional Polarity Register

(Register 0x13) section.

READ

DAC CHANNEL

DAC INPUT

REGISTER

DAC OUTPUT

REGISTER

WRITE

SCLK

DAC

VOUTx

SCLK

LOAD BIT

GPIO7/LDAC

1

LDAC

POLARITY

1

PROVIDED THE GPIO7/LDAC PIN IS CONFIGURED AS AN LDAC PIN.

Figure 48. Simplified Diagram of Input Loading Circuitry for a Single DAC

Rev. B | Page 28 of 78

Data Sheet

AD7293

If a conversion result exceeds the high or low limit set in the

alert limits register, the AD7293 signals an alert in one or more

of the following ways:

V

3 HIGH ALERT

2 HIGH ALERT

1 HIGH ALERT

0 HIGH ALERT

3 LOW ALERT

D11

D10

D9

IN

V

IN

D8

ALERT

REGISTER

V

D3

•

Via hardware using the GPIO3/ALERT0 and

GPIO4/ALERT1 pins

IN

V

2 LOW ALERT

1 LOW ALERT

0 LOW ALERT

D2

V

D1

•

Via software using the alert bits or registers on the alert

page (Page 0x10).

D0

T

D1 HIGH ALERT

D0 HIGH ALERT

D10

D9

D8

D2

D1

D0

SENSE

T

SENSE

ALERT

REGISTER

T

INT HIGH ALERT

D1 LOW ALERT

ALERTx Pins

SENSE

T

SENSE

Two pins can be configured as ALERTx pins. On power-up,

Pin 2 (GPIO4/ALERT1) is configured as an alert whereas

Pin 53 is configured as a GPIO (GPIO3/ALERT0). When these

pins are configured as ALERTx pins, any combination of high

and low alerts on any of the ADC channels can route to these

pins. The polarity of the alert output pins can be set to active

high or active low via the digital function polarity register on

the configuration page.

T

D0 HIGH ALERT

INT LOW ALERT

SENSE

T

SENSE

I

D11

D10

D9

3 HIGH ALERT

SENSE

I

2 HIGH ALERT

1 HIGH ALERT

0 HIGH ALERT

3 LOW ALERT

2 LOW ALERT

1 LOW ALERT

0 LOW ALERT

SENSE

I

SENSE

ALERT

REGISTER

D8

I

D3

SENSE

I

D2

I

D1

ALERT

FLAG

D0

OR

BI-V

3

HIGH ALERT

D15

D14

D13

D12

D11

D10

D9

OUT MON

If an alert pin signals an alert event and the contents of the alert

flags registers are not read before the next conversion is completed,

the contents of the register may change if the out of range signal

returns to the specified range. In this case, the ALERT0 or

ALERT1 pin no longer signals the occurrence of an alert event.

2

OUT MON

1

OUT MON

0

OUT MON

AV HIGH ALERT

SS

DACV

HIGH ALERT

LOW ALERT

DD-BI

SUPPLY

AND

DACV

DD-UNI

AV

DD

D8

BI-V

x

OUT MON

ALERT

REGISTER

D7

Software Alerts Page

BI-V

3

OUT MON

D6

BI-V

2

OUT MON

The alert summary register (Register 0x10) contains a summary of

alerts for the voltage, temperature sensor, current sensor, and

other monitoring inputs that have violated limits. See the Alert

Summary (ALERTSUM) Register (Register 0x10) section.

D5

1

OUT MON

D4

0

OUT MON

D3

AV LOW ALERT

SS

D2

DACV

LOW ALERT

DD-BI

D1

DACV

DD-UNI

D0

AV

DD

To gather more detailed information, the remaining registers

contain two individual status bits per channel: one corresponding

to the high limit and the other corresponding to the low limit.

A bit with a status of one shows the channel on which the

violation occurred and whether the violation occurred on the

high or low limit.

D11

D10

D9

D8

D3

D2

D1

D0

D9

D8

D2

D1

D0

RS3+

HIGH ALERT

LOW ALERT

MON

RS2+

RS1+

RS0+

RSx+

ALERT

REGISTER

MON

RS3+

RS2+

RS1+

RS0+

MON

INT

3 HIGH ALERT

2 HIGH ALERT

1 HIGH ALERT

0 HIGH ALERT

LIMIT

INT

AND

LIMIT

AV /AV

SS

DD

ALERT

REGISTER

AV /AV ALARM

SS

DD

Figure 49. Software Alerts Page

GPIO0 to GPIO3 Routing to ALERT1

A bit in the general register allows the GPIO0 to GPIO3 status

to route to the ALERT1 pin. Set GPIO0 to GPIO3 up as inputs

(bit set to 0 in the digital output enable register). If the GPIO is

read as 1, this read appears on ALERT1, and the GPIO register

can be read for the status of the pin to detect which pin has

caused ALERT1 to become active.

Rev. B | Page 29 of 78

AD7293

Data Sheet

AV_DDAND AV_SSALARM

MAXIMUM AND MINIMUM PAGES

There are comparators on AV_DD(+3.6 V typical) and AV_SS

(−4.1 V typical) that can be routed to the ALERTx pins or can

be used to control the PA_ON state and to put the bipolar

DACs/integrator outputs in the clamp state. By default, these

alarms are enabled.

The maximum and minimum pages contain storage registers

for the maximum and minimum conversion results. This

function is useful when monitoring the minimum and maxi-

mum conversion values over time is required.

HYSTERESIS

When AV_SSis greater than −4.1 V, there is a mask register

available whereby an alert of AV_SSor AV_DDis not creating an

alert on the ALERTx pin.

The hysteresis value determines the reset point for the ALERTx

pin and/or software alert bit if a violation of the limits occurs. The

hysteresis register stores the hysteresis value when using the

limit registers. Each pair of limit registers has a dedicated hysteresis

register (see Figure 50). If software is periodically polling the

device to detect an alert, the hysteresis can be useful to ensure

that no out of limit condition is missed.

HIGH LIMIT

HIGH LIMIT – HYSTERESIS

INPUT SIGNAL

LOW LIMIT + HYSTERESIS

LOW LIMIT

ALERT SIGNAL

TIME

Figure 50. Hysteresis

Rev. B | Page 30 of 78

Data Sheet

AD7293

REGISTER SETTINGS

The register structure for the AD7293 is partitioned using pages.

There are 19 pages in total. Each contains a different number

of registers that are used to store and access information to

configure and control the device. Each page and subregister

have an address that an 8-bit address pointer register points

to when communicating with it. The address pointer register is

an 8-bit register. The six LSBs (D5 to D0) are the pointer

address bits that point to one of the AD7293 data registers, and

the MSB (D7) is the read (high)/write (low) bit. There are read

only and read/write registers.

NO OP

PAGE SELECT POINTER

CONVERSION COMMAND

RESULT

PAGE 0x00

RESULT 0/DAC INPUT

DAC ENABLE

GPIO

DEVICE ID

PAGE 0x01

RESULT 1

...

PAGE 0x02

CONFIGURATION

PAGE 0x03

SEQUENCE

NO OP

PAGE 0x04

HIGH LIMIT 0

PAGE SELECT POINTER

CONVERSION COMMAND

RESULT

PAGE 0x05

HIGH LIMIT 1

DAC ENABLE

GPIO

DEVICE ID

PAGE 0x06

...

LOW LIMIT 0

ADDRESS

POINTER

REGISTER

PAGE 0x07

LOW LIMIT 1

PAGE 0x08

HYSTERESIS 0

PAGE 0x09

HYSTERESIS 1

PAGE 0x0A

MINIMUM 0

PAGE 0x0B

MINIMUM 1

PAGE 0x0C

MAXIMUM 0

PAGE 0x0D

MAXIMUM 1

PAGE 0x0E

OFFSET 0

PAGE 0x0F

OFFSET 1

PAGE 0x10

ALERT

PAGE 0x11

ALERT0 PIN

PAGE 0x12

ALERT1 PIN

DIN

SCLK

DOUT

CS

SERIAL BUS INTERFACE

NOTES

1. EACH PAGE CONTAINS 7 COMMMON REGISTERS IN ADDITION TO PAGE SPECIFIC REGISTERS.

2. THE CONFIGURATION PAGE CONTAINS THE REGISTERS THAT SELECT THE BACKGROUND MODE

CYCLE OF CHANNELS TO BE CONVERTED BY THE ADC. THE SEQUENCE PAGE APPLIES TO COMMAND MODE ONLY.

Figure 51. Register Structure

Rev. B | Page 31 of 78

AD7293

Data Sheet

Table 20. DAC Enable Register

REGISTERS COMMON TO ALL PAGES

Bit Number(s)

Bit Name

Description

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

A number of registers is common to all pages. The register

function is the same for all pages.

D7

BI-V_OUT

3

2

1

0

No Op Register (Register 0x00)

D6

D5

D4

D3

D2

D1

D0

The no op register does not physically exist and this address

space is reserved to prevent any writes to the device when the

input data line is held low.

Page Select Pointer Register (Register 0x01)

This 8-bit pointer register selects the page that the user is trying

to access. A read of this register indicates the page the user is

currently pointing to. The two MSBs are reserved and the six

LSBs can be written to select any of the pages.

UNI-V_OUT

3

2

1

0

Conversion Command (Register 0x02)

The conversion command register is a special 8-bit register used

to initiate a conversion. To command a conversion, write the

command register address to the device with the MSB read bit

set. When the device address pointer register receives a special

conversion command, the previous contents of the address pointer

are retained and used to determine which channel to convert. If

pointing to the sequence register, the next channel in the sequence

converts.

Table 21. GPIO Register

Bit Number(s)

D7

Bit Name

Description

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

0: disable.

1: enable.

GPIO7

Result Register (Register 0x03)

D6

D5

D4

D3

D2

D1

D0

GPIO6

GPIO5

GPIO4

GPIO3

GPIO2

GPIO1

GPIO0

The 16-bit, read only ADC data register provides read access to

the most recent ADC conversion result in command mode.

Otherwise, it is necessary for the application software to keep

track of what channel was converted.

DAC Enable Register (Register 0x04)

This 8-bit register enables the DACs. See Table 20.

GPIO Register (Register 0x05)

This 8-bit register configures the GPIOs in the device. In GPIO

mode, and with the output drivers enabled, the GPIO outputs

reflect the value written to this register. In functional mode, any

write to this register has no effect on the GPIO outputs. The status

(high/low) of the GPIO pins can be read back by reading this

register (both in functional and GPIO modes). See Table 21.

Device ID Register (Register 0x0C)

Table 22. Device ID Register

This 16-bit read-only register stores the Device ID assigned to

Analog Devices, Inc. See Table 22 for more information.

Bit Number(s)

Bit Name

Description

Analog Devices,

[15:0]

ID register

Device ID = 0x0018

Software Reset Register (Register 0x0F)

Table 23. Software Reset Register

To issue a software reset write a specific value, 0x7293, to this

Bit Number(s)

Bit Name

Description

Software reset =

0x7293

CS

16-bit register and pull

high. The user must write 0x0000 to

[15:0]

Reset register

this register to clear it following the software reset. See Table 23.

Rev. B | Page 32 of 78

Data Sheet

AD7293

Voltage Input (V_INx) Result Registers (Register 0x10 to

Register 0x13)

RESULT 0/DAC INPUT (PAGE 0x00)

Result 0/DAC input is located at Page 0x00. It contains result

registers for the ADC, the temperature sensor, and the current

sensor channel. The page also contains DAC input registers to

set the output voltage.

These registers store the 12-bit ADC results from the four input

channels.

In single-ended mode, the LSB size is REF_ADC/4096 when the

0 V to REF_ADCrange is selected, 2 × REF_ADC/4096 when the 0 V

to 2 × REF_ADCrange is selected, and 4 × REF_ADC/4096 when the

0 V to 4 × REF_ADCrange is selected (which is the default value).

REF_ADC= 1.25 V. See the ADC Transfer Functions section for

more information. See Table 25 for more information.

Table 24. Result 0/DAC Input (Page 0x0)

Address

(Hex)

Access

Default

Value¹

0x00

N/A

0x0000

0x00

Name

Byte¹Type¹

0x00

No op

N/A

1

2

1

2

N/A

R/W

W

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x20

0x21

0x22

0x28

0x29

0x2A

0x2B

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

Page select pointer

Conversion command²

Result

DAC enable

GPIO

Device ID

Software reset

V_IN0

V_IN1

V_IN2

V_IN3

T_SENSEINT

T_SENSED0

Temperature Sensor (T_SENSEINT and T_SENSEDx) Result

Registers (Register 0x20 to Register 0x22)

R

R/W

R

R/W

R

R/W

These registers store the 12-bit ADC results from the three

temperature sensor channels. 1 LSB = 0.125°C. See Table 26 for

more information.

0x0018

0x0000

Current Sensor (I_SENSEx) Result Registers (Register 0x28 to

Register 0x2B)

These registers store the 12-bit ADC results from the four

current sensor channels. See Table 25 for more information.

DAC Input (UNI-V_OUTx and BI-V_OUTx) Registers

(Register 0x30 to Register 0x37)

T_SENSED1

Writing to these register addresses sets the 12-bit DAC output

voltage codes, as shown in Table 27.

I_SENSE

0

1

2

3

If the load bit is set to 1, the device waits for the DAC load pin

(GPIO7/LDAC) before loading the voltage codes onto the

DACs rather than immediately after the write operation. If the

copy bit is set to 1, writing to any of the four DAC registers

(unipolar and bipolar are grouped separately) sets all the other

DAC registers to the same value.

UNI-V_OUT

BI-V_OUT

0

1

2

3

0

1

2

3

While reading back the DAC result registers, only the 12-bit

internal DAC output register value is visible to the user.

Bits[D3:D0] read 0 irrespective of the status of the copy and

load bits.

¹N/A means not applicable.

²Not a physical register.

Table 25. Voltage Input (Register 0x10 to Register 0x13) and Current Sensor (Register 0x28 to Register 0x2B) Result Registers

MSB

D15

B11

LSB

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 33 of 78

AD7293

Data Sheet

Table 26. Temperature Sensor Result Register

Bit Number(s)

Bit Name

Description

0: −256°C

1: 0°C

D15

B11

D14

D13

D12

D11

D10

D9

B10

B9

0: 0°C

1: 128°C

0: 0°C

1: 64°C

0: 0°C

1: 32°C

0: 0°C

1: 16°C

0: 0°C

1: 8°C

B8

B7

B6

B5

0: 0°C

1: 4°C

D8

B4

0: 0°C

1: 2°C

D7

B3

0: 0°C

1: 1°C

D6

B2

0: 0°C

1: 0.5°C

0: 0°C

D5

B1

1: 0.25°C

0: 0°C

D4

B0

1: 0.125°C

Reserved

[D3:D0]

Reserved

Table 27. DAC Input Register

MSB

LSB

D15

D14

D13

D12

B8

D11

D10

D9

D8

D7

D6

D5

B1

D4

[D3:D2]

D1

D0

B11

B10

B9

B7

B6

B5

B4

B3

B2

B0

Reserved

Copy

Load

Table 28. Copy and Load Bit Descriptions

Bit Number(s)

[D15:D4]

D1

Bit Name

B11 to B0

Copy

Description

Data bits

0: no action

1: copies data to all DAC registers

0: all channels updated with latest results

D0

Load

1: input register loaded but output voltage dependent on LDAC

Rev. B | Page 34 of 78

Data Sheet

AD7293

Voltage Supply Monitor Result Registers (Register 0x10

to Register 0x13)

RESULT 1 (PAGE 0x01)

Table 29. Result 1 (Page 0x01)

The ADC is used in its single-ended mode. The LSB size varies

with the different supply monitoring registers. AV_DDand

DACV_DD-BIare divided by 5, and DACV_DD-UNIis divided by 20 to

scale within the 0 V to REF_ADCrange. AV_SSis level shifted to

within a −7.5 V to +2.5 V range, where 0x0000 equates to

approximately −7.5 V and 0xFFFF equates to approximately

+2.5 V. R E F _ADC= 1.25 V.

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

No op

N/A

1

2

1

2

N/A

R/W

W

R

R/W

R

Page select pointer

Conversion command²

Result

DAC enable

GPIO

Device ID

Software reset

AV_DD

DACV_DD-UNI

DACV_DD-BI

AV_SS

BI-V_OUT0_MON

BI-V_OUT1_MON

BI-V_OUT2_MON

BI-V_OUT3_MON

RS0+_MON

0x00

N/A

0x0000

0x00

Bipolar DAC Internal Monitor Result (BI-V_OUT0_MONto

BI-V_OUT3_MON) Registers (Register 0x14 to Register 0x17)

0x0018

0x0000

R/W

R

These registers store the 12-bit ADC results from the four

internal inputs for monitoring the bipolar DAC outputs in

open-loop mode or the integrator outputs in closed-loop mode.

The DAC monitoring channel voltages between −5 V and +5 V

are level shifted to the 0 V to REF_ADCrange before conversions.

R

RSx+_MONResult Registers (Register 0x28 to

Register 0x2B)

The voltages on the RSx+ pins (RSx+_MON) are divided by 50 to

scale them to the 0 V to REF_ADCrange. Use the ADC in single-

ended mode. The RSx+_MONmonitor result registers store the 12-

bit ADC results for the current sense supply channels.

RS1+_MON

RS2+_MON

RS3+_MON

2

R

¹N/A means not applicable.

²Not a physical register.

Table 30. Monitor Register Configuration

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Reserved

Rev. B | Page 35 of 78

AD7293

Data Sheet

Digital Output Enable Register (Register 0x11)

CONFIGURATION (PAGE 0x02)

This 16-bit register enables the output drivers of the GPIO pins

by setting the corresponding bit to one. When using one of the

pins as an output in GPIO mode or functional mode (for alerts

or busy), the corresponding bit must be set.

This page contains the registers that configure the device

operation.

Table 31. Configuration (Page 0x2)

Address

(Hex)

Access

Type¹

Default

Value¹

Digital Input/Output Function Register (Register 0x12)

Name

Byte¹

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x11

0x12

No op

N/A

1

2

1

2

N/A

R/W

W

0x00

N/A

0x0000

0x00

All GPIOs are in either functional mode (power-up) or GPIO

mode. The relevant GPIO pin is in GPIO mode when the

corresponding bit in this register is set to 1. The relevant GPIO

pin is in functional mode when the corresponding bit in this

register is cleared to 0. Four pins are in functional mode and

four pins are in GPIO mode after a power-on reset.

Page select pointer

Conversion command²

Result

DAC enable

GPIO

Device ID

Software reset

Digital output enable

Digital input/output

function

Digital functional

polarity

General

V_INx Range 0

V_INx Range 1

V_INx differential/

single-ended enable

V_INx filter

V_INx background enable

Conversion delay

T_SENSEx background

enable

I_SENSEx background

enable

I_SENSEx gain

DAC snooze/SLEEP0

R

R/W

R

R/W

0x00

0x0018

0x0000

0x0010

0x000F

Digital Functional Polarity Register (Register 0x13)

This register sets the polarity of the digital input/output pins in

functional mode only. The associated input/output signal can be

made active low by setting the corresponding bit in this register

to 1. Functional mode is set up in the digital input/output

function register (Register 0x12).

2

0x13

2

R/W

0x0090

0x14

0x15

0x16

0x17

2

R/W

0x0000

General Register (Register 0x14)

This 16-bit register selects the internal ADC reference or an

external reference and other general functions. The status on

GPIO0 to GPIO3 can be routed to ALERT1. Error amplifier

control over the integrator limit feature is also configurable in

this register. ALERT0 can be routed internally to clamp the

bipolar DACs.

0x18

0x19

0x1A

0x1B

2

R/W

0x0000

V_INx Range x Registers (Register 0x15 and Register 0x16)

0x1C

2

R/W

0x0000

These two 16-bit registers combine together to specify the input

range of the V_INx channels. The default range is 4 × REF_ADC. If

either of the corresponding range bits from the two range

registers is set to one, the analog input voltage range is set to

2 × REF_ADC. If both the bits are set to one, the analog input

voltage range is REF_ADC. See Table 36 and Table 37 for range

selection. REF_ADC= 1.25 V.

0x1D

0x1F

2

R/W

0x0000

0xFF00

0x20

0x23

DAC snooze/SLEEP1

RSx+_MON, supply

2

R/W

0xFF00

0x0000

monitor, BI-V_OUT

x

background enable

Integrator limit and

closed-loop control

V_INx Differential/Single-Ended Enable Register

(Register 0x17)

0x28

2

R/W

0x0000

This register runs the ADC conversions for the voltage input

channels in differential and pseudo differential mode. The

corresponding differential pairs for the channels are as follows:

V_IN0 to V_IN1 for Channel 0, V_IN1 to V_IN0 for Channel 1, V_IN2 to

V_IN3 for Channel 2, and V_IN3 to V_IN2 for Channel 3. The

differential mode bits are ignored when the device is in pseudo

differential mode.

0x29

0x2A

0x2B

0x2C

0x2D

0x2E

PA_ON control

Ramp Time 0

Ramp Time 1

Ramp Time 2

Ramp Time 3

Closed-loop fast ramp

and integrator time

constant

2

R/W

0x0130

0x0000

0xBBBB

V_INx Filter Register (Register 0x18)

0x2F

INT_LIMITxand AV_SS/

AV_DDalarm mask

2

R/W

0x0000

A digital filter can be applied to the conversion result of all four

V_INx channels. Set the corresponding filter bit to 1 to apply the

digital filter.

¹N/A means not applicable.

²Not a physical register.

V_INx Background Enable Register (Register 0x19)

Set the corresponding enable bit to 1 to convert the V_INx channels

in the background.

Rev. B | Page 36 of 78

Data Sheet

AD7293

Conversion Delay Register (Register 0x1A)

Integrator Limit and Closed-Loop Control Register

(Register 0x28)

This register can add a conversion delay (during the acquisition

phase) to the V_INx channels in command mode conversions.

The resolution of this register is 320 ns. That is, each bit adds

320 ns to the conversion delay.

This register configures the device in closed-loop mode and

controls the integrator limit function as described in the

Closed-Loop Integrator Programmable Voltage Limit section.

PA_ON Control Register (Register 0x29)

Temperature Sensor (T_SENSEx) Background Enable

Register (Register 0x1B)

This register controls the PA_ON pin and allows AVss/AV_DD

alarm control over the PA_ON pin. Note that the AV_SS/AV_DD

alarm must be cleared before the PA_ON pin can switch back to

the on state.

To enable the temperature sensor conversions, write to the

corresponding bit from this register. To enable digital filtering,

also write to the corresponding bit.

Current Sensor (I_SENSEx) Background Enable Register

(Register 0x1C)

This register also allows clamp pin control over the PA_ON pin.

Setting the clamp bit to 1 allows control of the PA_ON pin via

the SLEEP0 and SLEEP1 pins, where, if the pin goes high, the

PA_ON pin goes to the off state. If the snooze bit is set to 1, an

additional write to this register is required to set the PA_ON pin

to the on state after clearing the corresponding SLEEP0 and

SLEEP1 pins.

To enable the I_SENSEx conversions, write to the corresponding bit

from this register. To enable digital filtering, also write to the

corresponding bit.

Current Sensor (I_SENSEx) Gain Register (Register 0x1D)

The I_SENSEx gain register is a 16-bit register that controls the gain

settings for the four current sense channels.

Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to

Register 0x2D)

DAC Snooze/SLEEP0 Pin Register (Register 0x1F)

These 16-bit registers (Ramp Time 0 to Ramp Time 3) configure

the ramp time for the closed-loop channels. The resolution of

each bit is 250 µs and the maximum programmable ramp time

is 31.75 ms.

To clamp the relevant DAC output via the GPIO5/SLEEP0 pin

set the corresponding bit in this register to 1. The snooze bits

determine the power-up/power-down condition of the DACs

after removing the clamp signal. If any of the snooze bits are set

to 1, an additional write to the DAC enable register is required

to wake up the corresponding DAC. If the snooze bits are not

set, directly use the SLEEP0 pin to wake up the DAC.

The minimum programmable ramp time for each channel is

4 ms. Enter 0x0000 to disable the ramp circuitry and to have the

DAC resolve the target value immediately.

Closed-Loop Fast Ramp and Integrator Time Constant

Register (Register 0x2E)

DAC Snooze/SLEEP1 Pin Register (Register 0x20)

To clamp the relevant DAC output via the GPIO6/SLEEP1 pin,

set the corresponding bit in this register to 1.

Use this register to disable or to enable the fast ramp scheme for

the closed-loop channels when they release from clamp. The

integrator time constant can trim to the values shown in Table 50.

RSx+_MON, Supply Monitor, BI-V_OUTx Background Enable

Register (Register 0x23)

Integrator Limit Active Status (INT_LIMITx) and AV_SS/AV_DD

Alarm Mask Register (Register 0x2F)

The RSx+_MONand voltage supply channels can convert in the

background by setting the corresponding enable bit to 1.

Use this 16-bit register to mask any of the closed-loop integrator

limit active status values or the AVss/AV_DDalarm. When masked,

the status values are not visible when reading back the correspond-

ing alert registers, or if the status values are routed to any of the

ALERTx pins.

Table 32. Digital Output Enable Register (Register 0x11)

Bit Number(s)

Bit Name

Description

[D15:D8]

D7

Reserved

GPIO7/LDAC (Pin 6)

GPIO6/SLEEP1 (Pin 4)

GPIO5/SLEEP0 (Pin 3)

GPIO4/ALERT1 (Pin 2)

GPIO3/ALERT0 (Pin 53)

GPIO2/BUSY (Pin 54)

GPIO1/CONVST (Pin 55)

GPIO0/IS BLANK (Pin 56)

1: enable output drivers. 0: disable output drivers.

1: enable output drivers (default). 0: disable output drivers.

1: enable output drivers. 0: disable output drivers.

D6

D5

D4

D3

D2

D1

D0

Rev. B | Page 37 of 78

AD7293

Data Sheet

Table 33. Digital Input/Output Function Register (Register 0x12)

Bit Number(s)

[D15:D8]

D7

Bit Name

Reserved

Pin 6

Description

Reserved

0: LDAC (default)

1: GPIO7

D6

D5

D4

D3

D2

D1

D0

Pin 4

0: SLEEP1 (default)

1: GPIO6

Pin 3

0: SLEEP0 (default)

1: GPIO5

Pin 2

0: ALERT1 (default)

1: GPIO4

Pin 53

Pin 54

Pin 55

Pin 56

0: ALERT0

1: GPIO3 (default)

0: BUSY

1: GPIO2 (default)

0: CONVST

1: GPIO1 (default)

0: IS BLANK

1: GPIO0 (default)

Table 34. Digital Functional Polarity Register (Register 0x13)

Bit Number(s)

[D15:D8]

D7

Bit Name

Reserved

LDAC

Description

Reserved

0: LDAC is active high

1: LDAC is active low (default)

0: SLEEP1 is active high (default)

1: SLEEP1 is active low

D6

D5

D4

D3

D2

D1

D0

SLEEP1

SLEEP0

ALERT1

ALERT0

BUSY

0: SLEEP0 is active high (default)

1: SLEEP0 is active low

0: ALERT1 is active high

1: ALERT1 is active low (default)

0: ALERT0 is active high (default)

1: ALERT0 is active low

0: BUSY is active high (default)

1: BUSY is active low

CONVST

IS BLANK

0: CONVST is active high (default)

1: CONVST is active low

0: IS BLANK is active high (default)

1: IS BLANK is active low

Table 35. General Register (Register 0x14)

Bit Number(s) Bit Name

Description

[D15:D8]

Reserved

D7

ADC_REF

0: external reference (default)

1: internal reference

0: feature disabled (default)

D6

GPIO ALERT1 routing

MISO speed

1: GPIO0 to GPIO3 status routed to ALERT1 if configured as general-purpose input

[D5:D4]

00: maximum (default)

01: fast

10: slow

11: minimum

Rev. B | Page 38 of 78

Data Sheet

AD7293

Bit Number(s) Bit Name

Description

D3

D2

D1

D0

T_SENSEdiode check

0: external check on (default)

1: external check off

Limit control

ALERT0 clamp

Reserved

0: alert control over software limit feature (default)

1: alert and error amplifier control over software limit feature

0: no control (default)

1: ALERT0 routed internally to clamp bipolar DACs

Reserved

Table 36. Voltage Input (V_INx) Range 0 Voltage Input Range Register (Register 0x15)

Bit Number(s)

Bit Name

Description^{1, 2}

[D15:D4]

D3

D2

D1

D0

Reserved

V_IN3 Range 0

V_IN2 Range 0

V_IN1 Range 0

V_IN0 Range 0

Used in conjunction with V_IN3 Range 1 bit (see Table 37) to specify the input range of V_IN3

Used in conjunction with V_IN2 Range 1 bit (see Table 37) to specify the input range of V_IN2

Used in conjunction with V_IN1 Range 1 bit (see Table 37) to specify the input range of V_IN1

Used in conjunction with V_IN0 Range 1 bit (see Table 37) to specify the input range of V_IN0

¹REF_ADC= 1.25 V.

²See Table 38 for bit descriptions.

Table 37. V_INx Range 1 Voltage Input Range Register (Register 0x16)

Bit Number(s)

Bit Name

Description^{1, 2}

[D15:D4]

D3

D2

D1

D0

Reserved

V_IN3 Range 1

V_IN2 Range 1

V_IN1 Range 1

V_IN0 Range 1

Used in conjunction with V_IN3 Range 0 bit (see Table 36) to specify the input range of V_IN3

Used in conjunction with V_IN2 Range 0 bit (see Table 36) to specify the input range of V_IN2

Used in conjunction with V_IN1 Range 0 bit (see Table 36) to specify the input range of V_IN1

Used in conjunction with V_IN0 Range 0 bit (see Table 36) to specify the input range of V_IN0

¹REF_ADC= 1.25 V.

²See Table 38 for bit descriptions.

Table 38. V_INx Range 1 and V_INRange 0 Bit Descriptions

V_INRange 0, V_INx¹Range Bit

V_INRange 1, V_INx¹Range Bit

V_INx¹Input Range Bit

4 × REF_ADC(default)

2 × REF_ADC

REF_ADC

0

1

0

1

0

1

¹x = 3, 2, 1, or 0.

Table 39. V_INx Differential/Single-Ended Enable Register (Register 0x17)

Bit Number(s)

[D15:D10]

D9

Bit Name

Reserved

Description

Reserved

V_IN2_V_IN3_PDIFF

V_IN2 and V_IN3 pseudo differential mode

0: disable (default)

1: enable

D8

V_IN0_V_IN1_PDIFF

V_IN0 and V_IN1 pseudo differential mode

0: disable (default)

1: enable

[D7:D2]

D1

Reserved

V_IN2_V_IN3_DIFF

V_IN2 and V_IN3 differential mode

0: disable (default)

1: enable

D0

V_IN0_V_IN1_DIFF

V_IN0 and V_IN1 differential mode

0: disable (default)

1: enable

Rev. B | Page 39 of 78

AD7293

Data Sheet

Table 40. V_INx Filter Register (Register 0x18)

Bit Number(s)

[D15:D4]

D3

Bit Name

Reserved

V_IN3 filter

Description

Reserved

0: disable (default)

1: enable

D2

D1

D0

V_IN2 filter

V_IN1 filter

V_IN0 filter

0: disable (default)

1: enable

0: disable (default)

1: enable

0: disable (default)

1: enable

Table 41. V_INx Background Enable Register (Register 0x19)

Bit Number(s)

[D15:D4]

D3

Bit Name

Reserved

Description

Reserved

V_IN3_BG_EN

0: disable background conversions (default)

1: enable background conversions

D2

D1

D0

V_IN2_BG_EN

V_IN1_BG_EN

V_IN0_BG_EN

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

Table 42. Temperature Sensor (T_SENSEx) Background Enable Register (Register 0x1B)

Bit Number(s) Bit Name

Description

[D15:D11]

D10

Reserved

T_SENSED1 filter

0: disable digital filtering (default)

1: enable digital filtering

D9

D8

T_SENSED0 filter

T_SENSEINT filter

0: disable digital filtering (default)

1: enable digital filtering

0: disable digital filtering (default)

1: enable digital filtering

[D7:D3]

D2

Reserved

T_SENSED1_EN

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

D1

D0

T_SENSED0_EN

T_SENSEINT_EN

Table 43. Current Sensor (I_SENSEx) Background Enable Register (Register 0x1C)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

I_SENSE3 filter

0: disable digital filtering (default)

1: enable digital filtering

0: disable digital filtering (default)

1: enable digital filtering

0: disable digital filtering (default)

1: enable digital filtering

0: disable digital filtering (default)

1: enable digital filtering

D10

D9

I_SENSE2 filter

I_SENSE1 filter

I_SENSE0 filter

D8

Rev. B | Page 40 of 78

Data Sheet

AD7293

Bit Number(s) Bit Name

Description

[D7:D4]

D3

Reserved

I_SENSE3_EN

Reserved

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

D2

D1

D0

I_SENSE2_EN

I_SENSE1_EN

I_SENSE0_EN

Table 44. I_SENSEx Gain Register (Register 0x1D)

Bit Number(s)

Bit Name

Description

These bits control the gain settings for the four current sense channels.

[D15:D12], [D11:D8],

[D7:D4], [D3:D0]

I_SENSE3 gain, I_SENSE2 gain,

I_SENSE1 gain, I_SENSE0 gain

Code

0000 (default)

0001

Gain Value

6.25

12.5

18.75

25

Voltage Across R_SENSE(mV)

200

100

0010

0011

66.67

50

0100

0101

37.5

50

33.33

25

0110

0111

1000

1001

1010

Others

75

100

200

400

781.25

6.25

16.67

12.5

6.25

3.125

1.6

200

Table 45. DAC Snooze/SLEEP0 Pin Register (Register 0x1F) and DAC Snooze/SLEEP1 Pin Register (Register 0x20)

Bit Number(s) Bit Name

Description

D15

D14

D13

D12

D11

D10

D9

BI-V_OUT

snooze

3

0: no control

1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)

BI-V_OUT

2

0: no control

snooze

1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)

BI-V_OUT

1

0: no control

snooze

1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)

BI-V_OUT

0

0: no control

snooze

UNI-V_OUT

snooze

UNI-V_OUT

snooze

UNI-V_OUT

snooze

UNI-V_OUT

snooze

1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)

3

2

1

0

0: no control

1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by SLEEP1 pin (Register 0x20) (default)

0: no control

1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)

0: no control

1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)

0: no control

1: snooze enabled when clamped by the SLEEP0 pin (Register 0x1F) or by the SLEEP1 pin (Register 0x20) (default)

0: no control (default)

1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)

0: no control (default)

1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)

0: no control (default)

D8

D7

BI-V_OUT

sleep

3

2

1

D6

BI-V_OUT

sleep

D5

BI-V_OUT

sleep

1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)

Rev. B | Page 41 of 78

AD7293

Data Sheet

Bit Number(s) Bit Name

Description

D4

D3

D2

BI-V_OUT

sleep

0

0: no control (default)

1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)

0: no control (default)

1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)

0: no control (default)

UNI-V_OUT

sleep

3

2

UNI-V_OUT

sleep

1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)

D1

D0

UNI-V_OUT

sleep

1

0: no control (default)

1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)

0: no control (default)

1: can be clamped by the SLEEP0 pin (Register 0x1F) or clamped by the SLEEP1 pin (Register 0x20)

UNI-V_OUT

sleep

0

Table 46. RSx+_MON, Supply Monitor, BI-V_OUTx Background Enable Register (Register 0x23)

Bit Number(s)

[D15:D12]

D11

Bit Name

Reserved

RS3+_MON

Description

Reserved

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

0: disable background conversions (default)

1: enable background conversions

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RS2+_MON

RS1+_MON

RS0+_MON

BI-V_OUT3_MON

BI-V_OUT2_MON

BI-V_OUT1_MON

BI-V_OUT0_MON

AV_SS

DACV_DD-BI

DACV_DD-UNI

AV_DD

Table 47. Integrator Limit and Closed-Loop (CL) Control Register (Register 0x28)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

INT_CL_LIMIT_CH3 0: no control (default)

1: the soft closed-loop limit for the channel is enabled

INT_CL_LIMIT_CH2 0: no control (default)

1: the soft closed-loop limit for the channel is enabled

INT_CL_LIMIT_CH1 0: no control (default)

1: the soft closed-loop limit for the channel is enabled

INT_CL_LIMIT_CH0 0: no control (default)

1: the soft closed-loop limit for the channel is enabled

Reserved Reserved

D10

D9

D8

[D7:D4]

Rev. B | Page 42 of 78

Data Sheet

AD7293

Bit Number(s) Bit Name

Description

D3

D2

D1

D0

Closed-Loop 3

0: closed loop is disabled (default)

1: closed loop is enabled

Closed-Loop 2

Closed-Loop 1

Closed-Loop 0

0: closed loop is disabled (default)

1: closed loop is enabled

0: closed loop is disabled (default)

1: closed loop is enabled

0: closed loop is disabled (default)

1: closed loop is enabled

Table 48. PA_ON Control Register (Register 0x29)

Bit Number(s)

[D15:D10]

D9

Bit Name

Description

Reserved

PA_ON enable

0: PA_ON signal is in the off state (default)

1: PA_ON signal is in the on state

0: no control

D8

PA_ON trigger

1: AV_SS/AV_DDalarm or ALERT0 triggers PA_ON (default)

Reserved

[D7:D6]

D5

Reserved

SLEEP1 snooze

0: no control

1: PA_ON snooze after SLEEP1 enable (default)

0: no control

D4

SLEEP0 snooze

1: PA_ON snooze after SLEEP0 enable (default)

Reserved

[D3:D2]

D1

Reserved

PA_ON SLEEP1

0: no control (default)

1: PA_ON controlled by the SLEEP1 pin

0: no control (default)

D0

PA_ON SLEEP0

1: PA_ON controlled by the SLEEP0 pin

Table 49. Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to Register 0x2D)

Bit Number(s)

Bit Name

Reserved

B6 to B0

Description

[D15:D7]

Reserved

[D6:D0]

Ramp time bits configure the ramp time for the DACs in closed-loop mode

0000000 = no ramp function (default)

0000001 to 0010000 = 4 ms

0010001 = 4.25 ms

…

1111110 = 31.5 ms

1111111 = 31.75 ms

Table 50. Closed-Loop Fast Ramp and Integrator Time Constant Register (Register 0x2E)

Bit Number(s) Bit Name

Description

D15

CL3_FR

0: Closed-Loop 3 fast ramp disable

1: Closed-Loop 3 fast ramp enable (default)

[D14:D12]

CL3_CAP_TRIM[2:0] 000: not applicable

001: 2.352 ms

010: 1.218 ms

011: 840 µs (default)

100: 650 µs

101: 538 µs

110: 462 µs

111: 408 µs

Rev. B | Page 43 of 78

AD7293

Data Sheet

Bit Number(s) Bit Name

Description

D11

CL2_FR

0: Closed-Loop 2 fast ramp disable

1: Closed-Loop 2 fast ramp enable (default)

[D10:D8]

CL2_CAP_TRIM[2:0] 000: not applicable

001: 2.352 ms

010: 1.218 ms

011: 840 µs (default)

100: 650 µs

101: 538 µs

110: 462 µs

111: 408 µs

D7

CL1_FR

0: Closed-Loop 1 fast ramp disable

1: Closed-Loop 1 fast ramp enable (default)

[D6:D4]

CL1_CAP_TRIM[2:0] 000: not applicable

001: 2.352 ms

010: 1.218 ms

011: 840 µs (default)

100: 650 µs

101: 538 µs

110: 462 µs

111: 408 µs

D3

CL0_FR

0: Closed-Loop 0 fast ramp disable

1: Closed-Loop 0 fast ramp enable (default)

[D2:D0]

CL0_CAP_TRIM[2:0] 000: not applicable

001: 2.352 ms

010: 1.218 ms

011: 840 µs (default)

100: 650 µs

101: 538 µs

110: 462 µs

111: 408 µs

Table 51. Integrator Limit Active Status (INT_LIMITx) and AV_SS/AV_DDAlarm Mask Register (Register 0x2F)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

INT_LIMIT

3

2

1

0

0: no masking (default)

1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or

if routed to ALERTx pins

D10

D9

0: no masking (default)

1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or

if routed to ALERTx pins

0: no masking (default)

1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or

if routed to ALERTx pins

D8

0: no masking (default)

1: masks alerts such that they are not visible when reading back the corresponding alert registers and/or

if routed to ALERTx pins

[D7:D1]

D0

Reserved

AV_SS/AV_DDalarm 0: no masking (default)

1: masks alert

Rev. B | Page 44 of 78

Data Sheet

AD7293

Voltage Input (V_INx) Sequence Register (Register 0x10)

SEQUENCE (PAGE 0x03)

This 16-bit register allows the user to sequence the ADC

conversions for the four input channels in command mode.

The sequence page contains registers that allow the user to

sequence and read back the conversions results from selected

channels in command mode.

Current Sensor (I_SENSEx) and Temperature Sensor (T_SENSEx)

Sequence Register (Register 0x11)

Table 52. Sequence (Page 0x03)

Address

(Hex)

Access Default

This 16-bit register allows the user to sequence the results read

back for the four current sense and three temperature sensor

channels. The range for the current sense and temperature

sense channels is fixed at 0 V to REF_ADC(1.25 V). However, the

corresponding bit from the enable registers on the configuration

page must be set to run a conversion for a temperature sensor

or current sensor channel in command mode.

Name

Byte¹Type¹

Value¹

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

No op

N/A

1

2

1

2

N/A

R/W

W

Page select pointer

Conversion command²

Result

DAC enable

GPIO

Device ID

Software reset

V_INx sequence

0x00

N/A

R

0x0000

0x00

0x0018

0x0000

R/W

R

R/W

RSx+_MON, Supply Monitor, and BI-V_OUTx Monitor Sequence

Register (Register 0x12)

This 16-bit register allows the user to sequence and read back

the ADC conversion results for the four RSx+ pins, four voltage

supplies, and the four DAC monitor channels in command mode.

I_SENSEx and T_SENSE

sequence

x

2

0x12

RSx+_MON, supply

2

R/W

0x0000

monitor, and BI-V_OUT

monitor sequence

x

¹N/A means not applicable.

²Not a physical register.

Table 53. V_INx Sequence Register (Register 0x10)

Bit Number(s) Bit Name

Description

[D15:D4]

D3

Reserved

V_IN3

Reserved

1: command mode sequencing enabled

0: command mode sequencing disabled (default)

1: command mode sequencing enabled

0: command mode sequencing disabled (default)

1: command mode sequencing enabled

0: command mode sequencing disabled (default)

1: command mode sequencing enabled

D2

D1

D0

V_IN2

V_IN1

V_IN0

0: command mode sequencing disabled (default)

Table 54. I_SENSEx and T_SENSEx Sequence Register (Register 0x11)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

I_SENSE

3

2

1

0

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

D10

D9

D8

1: command mode sequencing enabled

Reserved

[D7:D3]

D2

Reserved

T_SENSED1

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

D1

D0

T_SENSED0

T_SENSEINT

1: command mode sequencing enabled

Rev. B | Page 45 of 78

AD7293

Data Sheet

Table 55. RSx+_MON, Supply Monitor, and BI-V_OUTx Monitor Sequence Register (Register 0x12)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

RS3+_MON

Reserved

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

RS2+_MON

RS1+_MON

RS0+_MON

BI-V_OUT3_MON

BI-V_OUT2_MON

BI-V_OUT1_MON

BI-V_OUT0_MON

AV_SS

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

1: command mode sequencing enabled

0: no control (default)

DACV_DD-BI

DACV_DD-UNI

AV_DD

1: command mode sequencing enabled

Rev. B | Page 46 of 78

Data Sheet

AD7293

Temperature Sensor (T_SENSEx) High Limit Registers

(Register 0x20 to Register 0x22)

HIGH LIMIT 0 (PAGE 0x04)

Table 56. High Limit 0 (Page 0x04)

These read/write 16-bit registers set the high limits for the three

temperature sensor channels. The default value of these

registers is 0xFFF0.

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x20

0x21

0x22

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

No op

N/A

1

2

1

2

N/A

R/W

W

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

Table 57. Temperature Sensor High Limit Registers

(Register 0x20 to Register 0x22)

R

0x0000

0x00

Bit Number(s)

Bit Name

Description

R/W

R

D15

B11

0: −256°C

1: 0°C (default)

0: 0°C

1: 128°C (default)

0: 0°C

1: 64°C (default)

0: 0°C

1: 32°C (default)

0: 0°C

1: 16°C (default)

0: 0°C

1: 8°C (default)

0: 0°C

Device ID

0x0018

0x0000

0xFFF0

D14

D13

D12

D11

D10

D9

B10

B9

Software reset

V_IN0 high limit

V_IN1 high limit

V_IN2 high limit

V_IN3 high limit

T_SENSEINT high limit

T_SENSED0 high limit

T_SENSED1 high limit

I_SENSE0 high limit

I_SENSE1 high limit

I_SENSE2 high limit

I_SENSE3 high limit

R/W

B8

B7

B6

B5

2

1: 4°C (default)

0: 0°C

D8

B4

¹N/A means not applicable.

²Not a physical register.

1: 2°C (default)

0: 0°C

D7

B3

V_INx High Limit Registers (Register 0x10 to Register 0x13)

1: 1°C (default)

0: 0°C

These read/write 16-bit registers set the high limits for the four

input channels. The default value of these registers is 0xFFF0.

D6

B2

1: 0.5°C (default)

0: 0°C

D5

B1

1: 0.25°C (default)

0: 0°C

D4

B0

1: 0.125°C (default)

Reserved

[D3:D0]

Reserved

Current Sensor (I_SENSEx) High Limit Registers (Register 0x28

to Register 0x2B)

These read/write 16-bit registers set the high limits for the four

current sensor channels. The default value of these registers is

0xFFF0.

Table 58. V_INx (Register 0x10 to Register 0x13) and I_SENSEx High Limit Registers (Register 0x28 to Register 0x2B)

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 47 of 78

AD7293

Data Sheet

AV_DD, DAC Supply (DACV_DD-UNI/DACV_DD-BI) and AV_SSHigh

Limit Registers (Register 0x10 to Register 0x13)

HIGH LIMIT 1 (PAGE 0x05)

Table 59. High Limit 1 (Page 0x05)

These read/write 16-bit registers set the high limits for the four

voltage supply conversions. The default value of these registers

is 0xFFF0.

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

No op

N/A

1

2

1

2

N/A

R/W

W

BI-V_OUT0_MONto BI-V_OUT3_MONHigh Limit Registers

(Register 0x14 to Register 0x17)

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

R

0x0000

0x00

These registers store the high limits for the four internal inputs

for monitoring the bipolar DAC outputs in open-loop mode or

the integrator outputs in closed-loop mode.

R/W

R

Device ID

0x0018

0x0000

0xFFF0

RSx+_MONHigh Limit Registers (Register 0x28 to

Register 0x2B)

Software reset

AV_DDhigh limit

DACV_DD-UNIhigh limit

DACV_DD-BIhigh limit

AV_SShigh limit

BI-V_OUT0_MONhigh limit

BI-V_OUT1_MONhigh limit

BI-V_OUT2_MONhigh limit

BI-V_OUT3_MONhigh limit

RS0+_MONhigh limit

RS1+_MONhigh limit

RS2+_MON

R/W

These registers store the high limits for the RSx+_MONmonitoring

channels.

2

RS3+_MON

¹N/A means not applicable.

²Not a physical register.

Table 60. AV_DD, DAC Supply, AV_SS, BI-V_OUTx_MON, and RSx+_MONHigh Limit Registers (Register 0x10 to Register 0x2B)

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 48 of 78

Data Sheet

AD7293

Temperature Sensor (T_SENSEx) Low Limit Registers

(Register 0x20 to Register 0x22)

LOW LIMIT 0 (PAGE 0x06)

Table 61. Low Limit 0 (Page 0x06)

These read/write 16-bit registers set the low limits for the three

temperature sensor channels.

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x20

0x21

0x22

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

No op

N/A

1

2

1

2

N/A

R/W

W

Table 62. Temperature Sensor Low Limit Registers

(Register 0x20 to Register 0x22)

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

Bit Number(s)

Bit Name

Description

0: −256°C (default)

1: 0°C

R

0x0000

0x00

D15

B11

R/W

R

D14

D13

D12

D11

D10

D9

B10

B9

0: 0°C (default)

1: 128°C

Device ID

0x0018

0x0000

Software reset

V_IN0 low limit

V_IN1 low limit

V_IN2 low limit

V_IN3 low limit

T_SENSEINT low limit

T_SENSED0 low limit

T_SENSED1 low limit

I_SENSE0 low limit

I_SENSE1 low limit

I_SENSE2 low limit

I_SENSE3 low limit

R/W

0: 0°C (default)

1: 64°C

B8

0: 0°C (default)

1: 32°C

B7

0: 0°C (default)

1: 16°C

B6

0: 0°C (default)

1: 8°C

B5

0: 0°C (default)

1: 4°C

2

D8

B4

0: 0°C (default)

1: 2°C

¹N/A means not applicable.

²Not a physical register.

D7

B3

0: 0°C (default)

1: 1°C

V_INx Low Limit Registers (Register 0x10 to Register 0x13)

D6

B2

0: 0°C (default)

1: 0.5°C

These read/write 16-bit registers set the low limits for the four

input channels.

D5

B1

0: 0°C (default)

1: 0.25°C

D4

B0

0: 0°C (default)

1: 0.125°C

[D3:D0]

Reserved

Current Sensor (I_SENSEx) Low Limit Registers (Register 0x28

to Register 0x2B)

These read/write 16-bit registers set the low limits for the four

current sensor channels.

Table 63. V_INx and Current Sensor Low Limit Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)

MSB

D15

B11

LSB

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Reserved

Rev. B | Page 49 of 78

AD7293

Data Sheet

AV_DD, DAC Supply (DACV_DD-UNI/DACV_DD-BI), and AV_SSLow

Limit Registers (Register 0x10 to Register 0x13)

LOW LIMIT 1 (PAGE 0x07)

Table 64. Low Limit 1 (Page 0x07)

These read/write 16-bit registers set the low limits for the four

supply channels.

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

BI-V_OUT0_MONto BI-V_OUT3_MONLow Limit Registers

(Register 0x14 to Register 0x17)

No op

N/A

1

2

1

2

N/A

R/W

W

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

These registers store the low limits from the four internal inputs

for monitoring the bipolar DAC outputs, although the intention

is to monitor the bipolar DAC outputs in open-loop mode or

the integrator outputs in closed-loop mode.

R

0x0000

0x00

R/W

R

Device ID

0x0018

0x0000

RSx+_MONLow Limit Registers (Register 0x28 to

Register 0x2B)

Software reset

AV_DDlow limit

DACV_DD-UNIlow limit

DACV_DD-BIlow limit

AV_SSlow limit

BI-V_OUT0_MONlow limit

BI-V_OUT1_MONlow limit

BI-V_OUT2_MONlow limit

BI-V_OUT3_MONlow limit

RS0+_MONlow limit

RS1+_MONlow limit

RS2+_MONlow limit

RS3+_MONlow limit

R/W

These registers store the low limits for the RSx+_MONmonitoring

channels.

2

¹N/A means not applicable.

²Not a physical register.

Table 65. AV_DD, DAC Supply, AV_SS, BI-V_OUTx_MON, and RSx+_MONLow Limit Registers (Register 0x10 to Register 0x2B)

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 50 of 78

Data Sheet

AD7293

Temperature Sensor (T_SENSEx) Hysteresis Registers

(Register 0x20 to Register 0x22)

HYSTERESIS 0 (PAGE 0x08)

Table 66. Hysteresis 0 (Page 0x08)

These read/write 16-bit registers set the hysteresis values for the

three temperature sensor channels. The MSB of this register

must be set to 1.

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x20

0x21

0x22

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

No op

N/A

1

2

1

2

N/A

R/W

W

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

Table 67. Temperature Sensor Hysteresis Registers

(Register 0x20 to Register 0x22)

R

0x0000

0x00

Bit Number(s)

Bit Name

Reserved

B10

Description

Reserved. Must be set to 1.

0: 0°C (default)

1: 128°C

R/W

R

D15

D14

Device ID

0x0018

0x0000

Software reset

V_IN0 hysteresis

V_IN1 hysteresis

V_IN2 hysteresis

V_IN3 hysteresis

T_SENSEINT hysteresis

T_SENSED0 hysteresis

T_SENSED1 hysteresis

I_SENSE0 hysteresis

I_SENSE1 hysteresis

I_SENSE2 hysteresis

I_SENSE3 hysteresis

R/W

D13

D12

D11

D10

D9

B9

0: 0°C (default)

1: 64°C

B8

0: 0°C (default)

1: 32°C

B7

0: 0°C (default)

1: 16°C

B6

0: 0°C (default)

1: 8°C

B5

0: 0°C (default)

1: 4°C

2

D8

B4

0: 0°C (default)

1: 2°C

¹N/A means not applicable.

²Not a physical register.

D7

B3

0: 0°C (default)

1: 1°C

V_INx Hysteresis Registers (Register 0x10 to Register 0x13)

D6

B2

0: 0°C (default)

1: 0.5°C

These read/write 16-bit registers set the hysteresis values for the

four input channels.

D5

B1

0: 0°C (default)

1: 0.25°C

D4

B0

0: 0°C (default)

1: 0.125°C

[D3:D0]

Reserved

Current Sensor (I_SENSEx) Hysteresis Registers

(Register 0x28 to Register 0x2B)

These read/write 16-bit registers set the hysteresis values for the

four current sensor channels.

Table 68. V_INx and Current Sensor Hysteresis Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)

MSB

D15

B11

LSB

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 51 of 78

AD7293

Data Sheet

AV_DD, DAC Supply (DACV_DD-UNI/DACV_DD-BI), and AV_SS

Hysteresis Registers (Register 0x10 to Register 0x13)

HYSTERESIS 1 (PAGE 0x09)

Table 69. Hysteresis 1 (Page 0x09)

These read/write 16-bit registers set the hysteresis values for the

four supply voltage conversions.

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

BI-V_OUT0_MONto BI-V_OUT3_MONHysteresis Registers

(Register 0x14 to Register 0x17)

No op

N/A

1

2

1

2

N/A

R/W

W

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

These read/write 16-bit registers set the hysteresis values for the

four DAC monitoring conversions.

R

0x0000

0x00

R/W

R

RSx+_MONHysteresis Registers (Register 0x28 to

Register 0x2B)

Device ID

0x0018

0x0000

These read/write 16-bit registers set the hysteresis values for the

four RSx+ conversions.

Software reset

AV_DDhysteresis

DACV_DD-UNIhysteresis

DACV_DD-BIhysteresis

AV_SShysteresis

BI-V_OUT0_MONhysteresis

BI-V_OUT1_MONhysteresis

BI-V_OUT2_MONhysteresis

BI-V_OUT3_MONhysteresis

RS0+_MONhysteresis

RS1+_MONhysteresis

RS2+_MONhysteresis

RS3+_MONhysteresis

R/W

2

¹N/A means not applicable.

²Not a physical register.

Table 70. AV_DD, DAC Supply, AV_SS, BI-V_OUTx_MON, and RSx+_MONHysteresis Registers (Register 0x10 to Register 0x2B)

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 52 of 78

Data Sheet

AD7293

Temperature Sensor (T_SENSEx) Minimum Registers

(Register 0x20 to Register 0x22)

MINIMUM 0 (PAGE 0x0A)

Table 71. Minimum 0 (Page 0x0A)

These 16-bit registers store the minimum ADC conversion results

for the relevant temperature sensor channel. The default value

of these registers is 0xFFF0. These registers can be set back to

their default value by writing to them (the 12-bit write value is

not written to these registers).

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x20

0x21

0x22

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

No op

N/A

1

2

1

2

N/A

R/W

W

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

R

0x0000

0x00

Table 72. Temperature Sensor Minimum Registers

(Register 0x20 to Register 0x22)

R/W

R

Bit Number(s)

Bit Name

Description

0: −256°C

1: 0°C

Device ID

0x0018

0x0000

0xFFF0

D15

B11

Software reset

V_IN0 minimum

V_IN1 minimum

V_IN2 minimum

V_IN3 minimum

T_SENSEINT minimum

T_SENSED0 minimum

T_SENSED1 minimum

I_SENSE0 minimum

I_SENSE1 minimum

I_SENSE2 minimum

I_SENSE3 minimum

R/W

D14

D13

D12

D11

D10

D9

B10

B9

0: 0°C

1: 128°C

0: 0°C

1: 64°C

0: 0°C

1: 32°C

0: 0°C

1: 16°C

0: 0°C

1: 8°C

B8

B7

B6

2

B5

0: 0°C

¹N/A means not applicable.

²Not a physical register.

1: 4°C

D8

B4

0: 0°C

V_INx Minimum Registers (Register 0x10 to Register 0x13)

1: 2°C

These 16-bit registers store the minimum ADC conversion

results for the relevant input channel. The default value of these

registers is 0xFFF0. These registers can be set back to their

default value by writing to them (the 12-bit write value is not

written to these registers).

D7

B3

0: 0°C

1: 1°C

D6

B2

0: 0°C

1: 0.5°C

0: 0°C

D5

B1

1: 0.25°C

0: 0°C

D4

B0

1: 0.125°C

Reserved

[D3:D0]

Reserved

Current Sensor (I_SENSEx) Minimum Registers

(Register 0x28 to Register 0x2B)

These 16-bit registers store the minimum ADC conversion

results for the relevant current sensor channel. The default value

of these registers is 0xFFF0. These registers can be set back to

their default value by writing to them (the 12-bit write value is

not written to these registers).

Table 73. V_INx and Current Sensor Minimum Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)

MSB

D15

B11

LSB

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 53 of 78

AD7293

Data Sheet

AV_DD, DAC Supply (DACV_DD-UNI/DACV_DD-BI), and AV_SS

Minimum Registers (Register 0x10 to Register 0x13)

MINIMUM 1 (PAGE 0x0B)

Table 74. Minimum 1 (Page 0x0B)

These 16-bit registers store the minimum ADC conversion

results for the relevant channels. These registers can be set back

to their default value by writing to them.

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

No op

N/A

1

2

1

2

N/A

R/W

W

BI-V_OUT0_MONto BI-V_OUT3_MONMinimum Registers

(Register 0x14 to Register 0x17)

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

These 16-bit registers store the minimum ADC conversion

results for the relevant DAC monitoring channels. These

registers can be set back to their default value by writing to

them.

R

0x0000

0x00

R/W

R

Device ID

0x0018

0x0000

0xFFF0

Software reset

AV_DDminimum

DACV_DD-UNIminimum

DACV_DD-BIminimum

AV_SSminimum

BI-V_OUT0_MONminimum

BI-V_OUT1_MONminimum

BI-V_OUT2_MONminimum

BI-V_OUT3_MONminimum

RS0+_MONminimum

RS1+_MONminimum

RS2+_MONminimum

RS3+_MONminimum

R/W

RSx+_MONMinimum Registers (Register 0x28 to

Register 0x2B)

These 16-bit registers store the minimum ADC conversion

results for the relevant channels. These registers can be set back

to their default value by writing to them.

2

¹N/A means not applicable.

²Not a physical register.

Table 75. AV_DD, DAC Supply, AV_SS, BI-V_OUTx_MON, and RSx+_MONMinimum Registers (Register 0x10 to Register 0x2B)

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 54 of 78

Data Sheet

AD7293

Temperature Sensor (T_SENSEx) Maximum Registers

(Register 0x20 to Register 0x22)

MAXIMUM 0 (PAGE 0x0C)

Table 76. Maximum 0 (Page 0x0C)

These 16-bit registers store the maximum ADC conversion

results for the relevant temperature sensor channel. These

registers can be set back to their default value by writing to

them (the 12-bit write value is not written to these registers).

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x20

0x21

0x22

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

Value¹

0x00

No op

N/A

1

2

1

2

N/A

R/W

W

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

Table 77. Temperature Sensor Maximum Registers

(Register 0x20 to Register 0x22)

R

0x0000

0x00

R/W

R

Bit

Number(s) Name

Description

0: −256°C

1: 0°C

Device ID

0x0018

0x0000

D15

D14

D13

D12

D11

D10

D9

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Software reset

V_IN0 maximum

V_IN1 maximum

V_IN2 maximum

V_IN3 maximum

T_SENSEINT maximum

T_SENSED0 maximum

T_SENSED1 maximum

I_SENSE0 maximum

I_SENSE1 maximum

I_SENSE2 maximum

I_SENSE3 maximum

R/W

0: 0°C

1: 128°C

0: 0°C

1: 64°C

0: 0°C

1: 32°C

0: 0°C

1: 16°C

0: 0°C

1: 8°C

2

0: 0°C

1: 4°C

¹N/A means not applicable.

²Not a physical register.

D8

0: 0°C

1: 2°C

V_INx Maximum Registers (Register 0x10 to Register 0x13)

These 16-bit registers store the maximum ADC conversion

results for the relevant input channel. These registers can be set

back to their default value by writing to them (the 12-bit write

value is not written to these registers).

D7

0: 0°C

1: 1°C

D6

0: 0°C

1: 0.5°C

0: 0°C

1: 0.25°C

0: 0°C

D5

D4

1: 0.125°C

[D3:D0]

Reserved Reserved

Current Sensor (I_SENSEx) Maximum Registers

(Register 0x28 to Register 0x2B)

These 16-bit registers store the maximum ADC conversion

results for the relevant current sensor channel. These registers can

be set back to their default value by writing to them (the 12-bit

write value is not written to these registers).

Table 78. V_INx and Current Sensor Maximum Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)

MSB

D15

B11

LSB

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 55 of 78

AD7293

Data Sheet

AV_DD, DAC Supply (DACV_DD-UNI/DACV_DD-BI), and AV_SS

Maximum Registers (Register 0x10 to Register 0x13)

MAXIMUM 1 (PAGE 0x0D)

Table 79. Maximum 1 (Page 0x0D)

These 16-bit registers store the maximum ADC conversion

results for the relevant channels.

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x28

0x29

0x2A

0x2B

Name

Byte¹Type¹

N/A

1

2

1

2

Value¹

0x00

BI-V_OUT0_MONto BI-V_OUT3_MONMaximum Registers

(Register 0x14 to Register 0x17)

No op

N/A

R/W

W

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

These 16-bit registers store the maximum ADC conversion

results for the relevant DAC monitoring channels. These

registers can be set back to their default value by writing to

them.

R

0x0000

0x00

R/W

R

Device ID

Software reset

0x0018

0x0000

RSx+_MONMaximum Registers (Register 0x28 to

Register 0x2B)

R/W

AV_DDmaximum

DACV_DD-UNImaximum

DACV_DD-BImaximum

AV_SSmaximum

BI-V_OUT0_MONmaximum

BI-V_OUT1_MONmaximum

BI-V_OUT2_MONmaximum

BI-V_OUT3_MONmaximum

RS0+_MONmaximum

RS1+_MONmaximum

RS2+_MONmaximum

RS3+_MONmaximum

These 16-bit registers store the maximum ADC conversion

results for the relevant channels. These registers can be set back

to their default value by writing to them.

2

¹N/A means not applicable.

²Not a physical register.

Table 80. AV_DD, DAC Supply, AV_SS, BI-V_OUTx_MON, and RSx+_MONMaximum Registers (Register 0x10 to Register 0x2B)

MSB

LSB

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

[D3:D0]

Reserved

B11

B10

B9

B8

B7

B6

B5

B4

B3

B2

B1

B0

Rev. B | Page 56 of 78

Data Sheet

AD7293

V_INx Offset Registers (Register 0x10 to Register 0x13)

OFFSET 0 (PAGE 0x0E)

These read/write 8-bit registers store the offset values for the

relevant input channel.

Table 81. Offset 0 (Page 0x0E)

Address

Access Default

(Hex)

0x00

0x01

Name

No op

Page select

pointer

Byte¹

N/A

1

Type¹

N/A

Value¹

0x00

Temperature Sensor (T_SENSEx) Offset Registers

(Register 0x20 to Register 0x22)

R/W

0x00

These read/write 8-bit registers store the offset values for the

relevant temperature sensor channel.

0x02

Conversion

command²

1

W

N/A

Current Sensor (I_SENSEx) Offset Registers (Register 0x28 to

Register 0x2B)

0x03

0x04

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x20

0x21

0x22

0x28

0x29

0x2A

0x2B

0x30

0x31

0x32

0x33

0x34

0x35

0x36

0x37

Result

DAC enable

GPIO

Device ID

Software reset

V_IN0 offset

V_IN1 offset

V_IN2 offset

V_IN3 offset

T_SENSEINT offset

T_SENSED0 offset

T_SENSED1 offset

I_SENSE0 offset

I_SENSE1 offset

I_SENSE2 offset

I_SENSE3 offset

UNI-V_OUT0 offset

UNI-V_OUT1 offset

UNI-V_OUT2 offset

UNI-V_OUT3 offset

BI-V_OUT0 offset

BI-V_OUT1 offset

BI-V_OUT2 offset

BI-V_OUT3 offset

2

1

2

R

0x0000

0x00

R/W

R

These read/write 8-bit registers store the offset values for the

relevant current sensor channel.

0x0018

0x0000

Unipolar DAC (UNI-V_OUTx) Offset Registers (Register 0x30

to Register 0x33)

R/W

These read/write registers store the offset values for the

corresponding DAC output. If the copy bit is set to 1, writing to

any of the DAC offset registers sets all the other unipolar DAC

offset registers to the same value.

Bipolar DAC (BI-V_OUTx) Offset Registers (Register 0x34 to

Register 0x37)

These read/write registers store the offset values for the

corresponding DAC output. If the copy bit is set to 1, writing to

any of the DAC offset registers sets all the other bipolar DAC

offset registers to the same value. Any write to these registers

affects the DAC range in open-loop mode and the integrator

limit in closed-loop mode.

¹N/A means not applicable.

²Not a physical register.

Table 82. V_INx and Current Sensor Offset Registers (Register 0x10 to Register 0x13, and Register 0x28 to Register 0x2B)

Bit Number(s) Bit Name

Description

0: 0 LSB (default)

1: −128 LSB

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

0: 0 LSB (default)

1: 64 LSB

0: 0 LSB (default)

1: 32 LSB

0: 0 LSB (default)

1: 16 LSB

0: 0 LSB (default)

1: 8 LSB

0: 0 LSB (default)

1: 4 LSB

0: 0 LSB (default)

1: 2 LSB

0: 0 LSB (default)

1: 1 LSB

Rev. B | Page 57 of 78

AD7293

Data Sheet

Table 83. Temperature Sensor Offset Registers (Register 0x20 to Register 0x22)

Bit Number(s) Bit Name

Description

0: 0°C (default)

1: −16°C

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

0: 0°C (default)

1: 8°C

0: 0°C (default)

1: 4°C

0: 0°C (default)

1: 2°C

0: 0°C (default)

1: 1°C

0: 0°C (default)

1: 0.5°C

0: 0°C (default)

1: 0.25°C

0: 0°C (default)

1: 0.125°C

Table 84. Unipolar DAC Offset Registers (Register 0x30 to Register 0x33)

Bit Number(s) Bit Name

Description

[D7:D6]

[D5:D4]

Reserved

Offset

Reserved

00: 0 V to 5 V (default)

01: 2.5 V to 7.5 V

10: 5 V to 10 V

11: 5 V to 10 V

[D3:D2]

D1

Reserved

Copy

Reserved

0: do not copy (default)

1: sets all unipolar DACs to same value

Reserved

D0

Reserved

Table 85. Bipolar DAC Offset Registers (Register 0x34 to Register 0x37)

Bit Number(s) Bit Name

Description

[D7:D6]

[D5:D4]

Reserved

Offset

Reserved

00: 0 V to +5 V (default)

01: −4 V to +1 V

10: −5 V to 0 V

11: 0 V to +5 V in open loop, disables upper voltage limit in closed loop

[D3:D2]

D1

Reserved

Copy

Reserved

0: do not copy (default)

1: sets all bipolar DACs to same value

Reserved

D0

Reserved

Rev. B | Page 58 of 78

Data Sheet

AD7293

AV_DD, DAC Supply (DACV_DD-UNI/DACV_DD-BI), and AV_SSOffset

Registers (Register 0x10 to Register 0x13)

OFFSET 1 (PAGE 0x0F)

Table 86. Offset 1 (Page 0x0F)

These read/write 8-bit registers store the offset values for the

relevant supply voltage monitoring channels.

Address

Access

Default

Value¹

0x00

N/A

(Hex)

0x00

0x01

0x02

Name

No op

Page select pointer

Conversion

command²

Byte¹Type¹

N/A

1

N/A

R/W

W

BI-V_OUT0_MONto BI-V_OUT3_MONOffset Registers (Register 0x14

to Register 0x17)

1

These read/write 8-bit registers store the offset values for the

relevant DAC monitoring channels.

0x03

0x04

Result

DAC enable

2

1

R

R/W

0x0000

0x00

RSx+_MONOffset Registers (Register 0x28 to Register 0x2B)

These read/write 8-bit registers store the offset values for the

relevant DAC monitoring channels. Note that, prior to

conversion, the RSx+_MONvoltages are divided by 50.

0x05

0x0C

0x0F

0x10

0x11

0x12

0x13

0x14

0x15

0x16

0x17

0x28

0x29

0x2A

0x2B

GPIO

Device ID

1

2

1

R/W

R

0x00

0x0018

0x0000

Software reset

AV_DDoffset

DACV_DD-UNIoffset

DACV_DD-BIoffset

AV_SSoffset

BI-V_OUT0_MONoffset

BI-V_OUT1_MONoffset

BI-V_OUT2_MONoffset

BI-V_OUT3_MONoffset

RS0+_MONoffset

RS1+_MONoffset

RS2+_MONoffset

RS3+_MONoffset

R/W

¹N/A means not applicable.

²Not a physical register.

Table 87. AV_DD, DAC Supply, AV_SS, BI-V_OUTx_MON, and RSx+_MONOffset Registers (Register 0x10 to Register 0x2B)

Bit Number(s) Bit Name

Description

0: 0 LSB (default)

1: −128 LSB

D7

D6

D5

D4

D3

D2

D1

D0

B7

B6

B5

B4

B3

B2

B1

B0

0: 0 LSB (default)

1: 64 LSB

0: 0 LSB (default)

1: 32 LSB

0: 0 LSB (default)

1: 16 LSB

0: 0 LSB (default)

1: 8 LSB

0: 0 LSB (default)

1: 4 LSB

0: 0 LSB (default)

1: 2 LSB

0: 0 LSB (default)

1: 1 LSB

Rev. B | Page 59 of 78

AD7293

Data Sheet

Alert Summary (ALERTSUM) Register (Register 0x10)

ALERT (PAGE 0x10)

This 16-bit register stores the summary from the channel

dedicated alert registers. If any of the bits from the corresponding

alert register are set, the register bit is set to 1 (OR function of

individual alert register bits). When 1 is written to any of the

register bits, this bit is cleared, that is, removing alerts and the

alert bits from the corresponding alert register. This write is a

quick way to clear any alerts in the device. The upper byte

contains the high alerts, whereas the lower byte contains the low

alerts. This format is applicable to the individual alert registers

as well. The default value of this register is 0x0000.

Table 88. Alert (Page 0x10)

Address

Access Default

(Hex)

0x00

0x01

0x02

0x03

0x04

0x05

0x0C

0x0F

0x10

0x12

0x14

0x15

0x18

Name

No op

Byte¹Type¹

N/A

1

2

1

2

Value¹

0x00

N/A

R/W

W

Page select pointer

Conversion command²

Result

DAC enable

GPIO

0x00

N/A

R

0x0000

0x00

0x0018

0x0000

R/W

R

R/W

Device ID

Software reset

ALERTSUM

V_INx alert

T_SENSEx alert

I_SENSEx alert

V_INx Alert Register (Register 0x12)

This 16-bit register stores the V_INchannel related high and low

alerts. When 1 is written to any of the register bits, this bit

clears, removing the corresponding alert.

Temperature Sensor (T_SENSEx) Alert Register (Register 0x14)

Supply and BI-V_OUTx_MON

alert

2

This 16-bit register stores the temperature sensor related high

and low alerts. When 1 is written to any of the register bits, this

bit clears, removing the corresponding alert.

0x19

0x1A

RSx+_MONalert

INT_LIMITx and AV_SS/AV_DD

alert

2

R/W

0x0000

Current Sensor (I_SENSEx) Alert Register (Register 0x15)

¹N/A means not applicable.

²Not a physical register.

This 16-bit register stores the current sensor related high and

low alerts. When 1 is written to any of the register bits, this bit

clears, removing the corresponding alert.

Table 89. Alert Summary (ALERTSUM) Register (Register 0x10), Bit D15 to Bit D8

D15

D14

D13

D12

D11

D10

D9

D8

RSx+ high

AV_DD/BI-V_OUTx high

INT_LIMITx active

AV_SS/AV_SSalarm

I_SENSEx high

T_SENSEx high

Reserved

V_INx high

Table 90. Alert Summary (ALERTSUM) Register (Register 0x10), Bit D7 to Bit D0

D7

D6

D5

D4

D3

D2

D1

D0

RSx+ low

AV_DD/BI-V_OUTx low

Reserved

I_SENSEx low

T_SENSEx low

Reserved

V_INx low

Table 91. V_INx Alert Register (Register 0x12)

MSB

LSB

[D15:D12]

D11

D10

D9

D8

[D7:D4]

D3

D2

D1

D0

Reserved

V_IN3 high

V_IN2 high

V_IN1 v

V_IN0 high

Reserved

V_IN3 low

V_IN2 low

V_IN1 low

V_IN0 low

Table 92. Temperature Sensor Alert Register (Register 0x14)

MSB

LSB

D0

[D15:D11]

D10

D9

D8

[D7:D3]

D2

T_SENSED1 low

D1

Reserved

T_SENSED1 high

T_SENSED0 high

T_SENSEINT high

Reserved

T_SENSED0 low

T_SENSEINT low

Table 93. Current Sensor Alert Register (Register 0x15)

MSB

LSB

[D15:D12]

D11

D10

D9

D8

[D7:D4]

D3

I_SENSE3 low

D2

D1

D0

Reserved

I_SENSE3 high I_SENSE2 high I_SENSE1 high I_SENSE0 high Reserved

I_SENSE2 low

I_SENSE1 low

I_SENSE0 low

Rev. B | Page 60 of 78

Data Sheet

AD7293

Supply and BI-V_OUTx_MONAlert Register (Register 0x18)

RSx+_MONAlert Register (Register 0x19)

This 16-bit register stores the AV_DD, DACV_DD-UNI, DAC_VDD-BI

,

This 16-bit register stores the RSx+ high and low alerts. When 1

is written to any of the register bits, this bit clears, removing the

corresponding alert.

AV_SS, BI-V_OUTx_MONhigh and low alerts. When 1 is written to any

of the register bits, this bit clears, removing the corresponding

alert.

INT_LIMITx and AV_SS/AV_DDAlert Register (Register 0x1A)

This 16-bit register stores the closed-loop integrator limit active

status and AV_SS/AV_DDalarm status.

Table 94. Supply and BI-V_OUTx_MONAlert Register (Register 0x18), Bit D15 to Bit D8

D15

D14

D13

D12

D11

D10

D9

D8

BI-V_OUT3_MONhigh

BI-V_OUT2_MONhigh

BI-V_OUT1_MONhigh

BI-V_OUT0_MONhigh

AV_SShigh

DACV_DD-BIhigh

DACV_DD-UNIhigh

AV_DDhigh

Table 95. Supply and BI-V_OUTx_MONAlert Register (Register 0x18), Bit D7 to Bit D0

D7

D6

D5

D4

D3

D2

D1

D0

BI-V_OUT3_MONlow

BI-V_OUT2_MONlow

BI-V_OUT1_MONlow

BI-V_OUT0_MONlow

AV_SSlow

DACV_DD-BIlow

DACV_DD-UNIlow

AV_DDlow

Table 96. RSx+_MONAlert Register (Register 0x19)

MSB

LSB

D0

[D15:D12] D11

Reserved

RS3+_MON

high

D10

D9

D8

[D7:D4]

D3

D2

D1

RS2+_MON

high

RS1+_MON

high

RS0+_MON

high

Reserved RS3+_MON

low

RS2+_MON

low

RS1+_MON

low

RS0+_MON

low

Table 97. INT_LIMITx and AV_SS/AV_DDAlert Register (Register 0x1A)

MSB

LSB

[D15:D12]

D11

D10

D9

D8

[D7:D1]

Reserved

D0

Reserved

INT_LIMIT3 high

INT_LIMIT2 high

INT_LIMIT1 high

INT_LIMIT0 high

AV_SS/AV_DDalarm

Rev. B | Page 61 of 78

AD7293

Data Sheet

V_INx ALERT0 Register (Register 0x12)

ALERT0 PIN ROUTING (PAGE 0x11)

This 16-bit register allows routing of the V_INx generated alerts

to the ALERT0 pin.

All the registers from this page allow routing of the alert signals

generated by the corresponding inputs/channels to the GPIO3/

ALERT0 pin of the device. The upper byte controls the high

alerts routing, whereas the lower byte controls the low alerts

routing.

Temperature Sensor (T_SENSEx) ALERT0 Register

(Register 0x14)

This 16-bit register allows routing of the temperature sensor

generated alerts to the ALERT0 pin.

Table 98. ALERT0 Pin Routing (Page 0x11)

Address

(Hex)

0x00

0x01

0x02

Access

Default

Value¹

0x00

N/A

Current Sensor (I_SENSEx) ALERT0 Register (Register 0x15)

Name

No op

Page select pointer

Conversion

command²

Result

DAC enable

GPIO

Byte¹Type¹

N/A

1

This 16-bit register allows routing of the current sensor

generated alerts to the ALERT0 pin.

N/A

R/W

W

Supply and BI-V_OUTx_MONALERT0 Register (Register 0x18)

1

This 16-bit register allows routing of the supply channels and

the bipolar DAC monitor channels generated alerts to the

ALERT0 pin.

0x03

0x04

0x05

0x0C

0x0F

0x12

0x14

0x15

0x18

2

1

2

R

0x0000

0x00

0x0018

0x0000

R/W

R

R/W

RSx+_MONALERT0 Register (Register 0x19)

Device ID

This 16-bit register allows routing of the RSx+_MONalerts to the

ALERT0 pin.

Software reset

V_INx ALERT0

T_SENSEx ALERT0

I_SENSEx ALERT0

Supply and

BI-V_OUTx_MONALERT0

INT_LIMITx and AVss/AV_DDALERT0 Register (Register 0x1A)

This 16-bit register allows routing of the closed-loop integrator

limit and AV_SS/AV_DDalerts to the ALERT0 pin.

0x19

0x1A

RSx+_MONALERT0

INT_LIMITx and

2

R/W

0x0000

AVss/AV_DDALERT0

¹N/A means not applicable.

²Not a physical register.

Table 99. V_INx ALERT0 Register (Register 0x12)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

V_IN3 high

Reserved

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D10

D9

V_IN2 high

V_IN1 high

V_IN0 high

D8

1: high alert on the corresponding channel routes to the ALERT0 pin

Reserved

[D7:D4]

D3

Reserved

V_IN3 low

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D2

D1

D0

V_IN2 low

V_IN1 low

V_IN0 low

1: low alert on the corresponding channel routes to the ALERT0 pin

Rev. B | Page 62 of 78

Data Sheet

AD7293

Table 100. Temperature Sensor ALERT0 Register (Register 0x14)

Bit Number(s) Bit Name

Description

[D15:D11]

D10

Reserved

T_SENSED1 high

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D9

D8

T_SENSED0 high

T_SENSEINT high

1: high alert on the corresponding channel routes to the ALERT0 pin

Reserved

[D7:D3]

D2

Reserved

T_SENSED1 low

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D1

D0

T_SENSED0 low

T_SENSEINT low

1: low alert on the corresponding channel routes to the ALERT0 pin

Table 101. Current Sensor ALERT0 Register (Register 0x15)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

I_SENSE3 high

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D10

D9

I_SENSE2 high

I_SENSE1 high

I_SENSE0 high

D8

1: high alert on the corresponding channel routes to the ALERT0 pin

Reserved

[D7:D4]

D3

Reserved

I_SENSE3 low

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D2

D1

D0

I_SENSE2 low

I_SENSE1 low

I_SENSE0 low

1: low alert on the corresponding channel routes to the ALERT0 pin

Rev. B | Page 63 of 78

AD7293

Data Sheet

Table 102. Supply and BI-V_OUTx_MONALERT0 Register (Register 0x18)

Bit Number(s) Bit Name

Description

BI-V_OUT3_MONhigh 0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

BI-V_OUT2_MONhigh 0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

BI-V_OUT1_MONhigh 0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

BI-V_OUT0_MONhigh 0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D15

D14

D13

D12

D11

D10

D9

AV_SShigh

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

DACV_DD-BIhigh

DACV_DD-UNIhigh

AV_DDhigh

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D8

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D7

BI-V_OUT3_MONlow

BI-V_OUT2_MONlow

BI-V_OUT1_MONlow

BI-V_OUT0_MONlow

AV_SSlow

D6

D5

D4

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D3

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D2

DACV_DD-BIlow

DACV_DD-UNIlow

AV_DDlow

D1

D0

1: low alert on the corresponding channel routes to the ALERT0 pin

Rev. B | Page 64 of 78

Data Sheet

AD7293

Table 103. RSx+_MONALERT0 Register (Register 0x19)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

RS3+_MONhigh

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D10

D9

RS2+_MONhigh

RS1+_MONhigh

RS0+_MONhigh

D8

1: high alert on the corresponding channel routes to the ALERT0 pin

Reserved

[D7:D4]

D3

Reserved

RS3+_MONlow

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT0 pin

0: no routing (default)

D2

D1

D0

RS2+_MONlow

RS1+_MONlow

RS0+_MONlow

1: low alert on the corresponding channel routes to the ALERT0 pin

Table 104. INT_LIMITx and AVss/AV_DDALERT0 Register (Register 0x1A)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

INT_LIMIT

3

2

1

0

0: no routing (default)

1: integrator limit active status routed to the ALERT0 pin

0: no routing (default)

1: integrator limit active status routed to the ALERT0 pin

0: no routing (default)

1: integrator limit active status routed to the ALERT0 pin

0: no routing (default)

D10

D9

D8

1: integrator limit active status routed to the ALERT0 pin

Reserved

[D7:D1]

D0

Reserved

AV_SS/AV_DD

0: no routing (default)

1: AV_SSor AV_DDalarm is routed to the ALERT0 pin

Rev. B | Page 65 of 78

AD7293

Data Sheet

V_INx ALERT1 Register (Register 0x12)

ALERT1 PIN ROUTING (PAGE 0x12)

This 16-bit register allows routing of the V_INx generated alerts

to the ALERT1 pin.

All the registers from this page allow routing of the alert signals

generated by the corresponding inputs/channels to the GPIO4/

ALERT1 pin of the device. The upper byte controls the high

alerts routing, whereas the lower byte controls the low alerts

routing.

Temperature Sensor (T_SENSEx) ALERT1 Register

(Register 0x14)

This 16-bit register allows routing of the temperature sensor

generated alerts to the ALERT1 pin.

Table 105. ALERT1 Pin Routing (Page 0x12)

Address

(Hex)

0x00

Access

Default

Value¹

0x00

Current Sensor (I_SENSEx) ALERT1 Register (Register 0x15)

Name

No op

Page select

pointer

Byte¹Type¹

N/A

1

This 16-bit register allows routing of the current sensor

generated alerts to the ALERT1 pin.

N/A

R/W

0x01

0x00

Supply and BI-V_OUTx_MONALERT1 Register (Register 0x18)

0x02

Conversion

command²

Result

DAC enable

GPIO

Device ID

Software reset

V_INx ALERT1

T_SENSEx ALERT1

I_SENSEx ALERT1

Supply and

BI-V_OUTx_MON

ALERT1

1

W

N/A

This 16-bit register allows routing of the supply channels and

the bipolar DAC monitor channels generated alerts to the

ALERT1 pin.

0x03

0x04

0x05

0x0C

0x0F

0x12

0x14

0x15

0x18

2

1

2

R

0x0000

0x00

0x0018

0x0000

R/W

R

R/W

RSx+_MONALERT1 Register (Register 0x19)

This 16-bit register allows routing of the RSx+_MONalerts to the

ALERT1 pin.

INT_LIMITx and AV_SS/AV_DDALERT1 Register (Register 0x1A)

This 16-bit register allows routing of the closed-loop integrator

limit and AV_SS/AV_DDalerts to the ALERT1 pin.

0x19

0x1A

RSx+_MONALERT1

2

R/W

0x0000

INT_LIMITx and

AVss/AV_DD

ALERT1

¹N/A means not applicable.

²Not a physical register.

Table 106. V_INx ALERT1 Register (Register 0x12)

Bit Number(s)

[D15:D12]

D11

Bit Name

Reserved

V_IN3 high

Description

Reserved

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

D10

D9

V_IN2 high

V_IN1 high

V_IN0 high

D8

1: high alert on the corresponding channel routes to the ALERT1 pin

Reserved

[D7:D4]

D3

Reserved

V_IN3 low

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

D2

D1

D0

V_IN2 low

V_IN1 low

V_IN0 low

1: low alert on the corresponding channel routes to the ALERT1 pin

Rev. B | Page 66 of 78

Data Sheet

AD7293

Table 107. Temperature Sensor ALERT1 Register (Register 0x14)

Bit Number(s) Bit Name

Description

[D15:D11]

D10

Reserved

T_SENSED1 high

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin.

0: no routing (default)

D9

D8

T_SENSED0 high

T_SENSEINT high

1: high alert on the corresponding channel routes to the ALERT1 pin.

Reserved

[D7:D3]

D2

Reserved

T_SENSED1 low

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

D1

D0

T_SENSED0 low

T_SENSEINT low

1: low alert on the corresponding channel routes to the ALERT1 pin

Table 108. Current Sensor ALERT1 Register (Register 0x15)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

I_SENSE3 high

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

D10

D9

I_SENSE2 high

I_SENSE1 high

I_SENSE0 high

D8

1: high alert on the corresponding channel routes to the ALERT1 pin

Reserved

[D7:D4]

D3

Reserved

I_SENSE3 low

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

D2

D1

D0

I_SENSE2 low

I_SENSE1 low

I_SENSE0 low

1: low alert on the corresponding channel routes to the ALERT1 pin

Table 109. Supply and BI-V_OUTx_MONALERT1 Register (Register 0x18)

Bit Number(s) Bit Name Description

BI-V_OUT3_MONhigh 0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

BI-V_OUT2_MONhigh 0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

BI-V_OUT1_MONhigh 0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

BI-V_OUT0_MONhigh 0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

D15

D14

D13

D12

D11

AV_SShigh

1: high alert on the corresponding channel routes to the ALERT1 pin

Rev. B | Page 67 of 78

AD7293

Data Sheet

Bit Number(s) Bit Name

Description

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

DACV_DD-BIhigh

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pi.

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

DACV_DD-UNIhigh

AV_DDhigh

BI-V_OUT3_MONlow

BI-V_OUT2_MONlow

BI-V_OUT1_MONlow

BI-V_OUT0_MONlow

AV_SSlow

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

DACV_DD-BIlow

DACV_DD-UNIlow

AV_DDlow

1: low alert on the corresponding channel routes to the ALERT1 pin

Table 110. RSx+_MONALERT1 Register (Register 0x19)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

RS3+_MONhigh

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: high alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

D10

D9

RS2+_MONhigh

RS1+_MONhigh

RS0+_MONhigh

D8

1: high alert on the corresponding channel routes to the ALERT1 pin

Reserved (default)

[D7:D4]

D3

Reserved

RS3+_MONlow

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

1: low alert on the corresponding channel routes to the ALERT1 pin

0: no routing (default)

D2

D1

D0

RS2+_MONlow

RS1+_MONlow

RS0+_MONlow

1: low alert on the corresponding channel routes to the ALERT1 pin

Rev. B | Page 68 of 78

Data Sheet

AD7293

Table 111. INT_LIMITx and AVss/AV_DDALERT1 Register (Register 0x1A)

Bit Number(s) Bit Name

Description

[D15:D12]

D11

Reserved

INT_LIMIT

3

2

1

0

0: no routing (default)

1: integrator limit active status routed to the ALERT1 pin

0: no routing (default)

1: integrator limit active status routed to the ALERT1 pin

0: no routing (default)

1: integrator limit active status routed to the ALERT1 pin

0: no routing (default)

D10

D9

D8

1: integrator limit active status routed to the ALERT1 pin

Reserved

[D7:D1]

D0

Reserved

AV_SS/AV_DD

0: no routing (default)

1: AV_SSor AV_DDalarm is routed to the ALERT1 pin

Rev. B | Page 69 of 78

AD7293

Data Sheet

SERIAL PORT INTERFACE

The AD7293 SPI allows the user to configure the device for

specific functions and operations through an internal structured

Table 112. Address Pointer

D7

D6

X¹

D5

D4

D3

D2

D1

D0

CS

register space. The interface consists of four signals: , SCLK,

R/W

Register/page select

DIN, and DOUT. The device is capable of interfacing within a

range of 1.7 V to 5.5 V, which is set by the V_DRIVEpin. SCLK is the

serial clock input for the device. All data transfers on DIN or

DOUT take place with respect to SCLK. The chip select input

¹X means don’t care.

Bit D5 to Bit D0 of the address pointer specify the register

address for the read or write operation.

CS

pin ( ) is an active low control. For the interface to be active,

After the address pointer, the data to be written to the device is

supplied in bytes. The register structure of the AD7293 is page

based and divided according to their specific functions. Some

registers are common to all pages, whereas the rest of the

registers are contained within a particular page. To select a

page, write to the 8-bit page select register. When a particular

page is selected, the user does not have to rewrite to the page

select register every time prior to writing to a register from the

same page. Figure 52 to Figure 54 show the read and write data

formats for the AD7293.

the chip select must be low. Data is clocked into the AD7293 on

the SCLK rising edge and is loaded into the device MSB first.

The length of each SPI frame can vary according to the command

being sent. A no op command is available for interface flexibil-

ity. Data is clocked out of the AD7293 on DOUT in the same

frame as the read command, on the falling edge of SCLK,

CS

while

when

is low. The SCLK and DIN signals are ignored

is high, and the DOUT line becomes high impedance.

INTERFACE PROTOCOL

When reading from or writing to the AD7293, the first byte

contains the address pointer. Bit D7 of the address pointer is the

read (high) and write (low) bit.

For a register write, the read/write bit is zero, and the DOUT

line remains high impedance. Upon completion of a read or

write, the AD7293 is ready to accept a new register address;

CS

alternatively, to terminate the operation, take the

pin high.

CS

0

X

PAGE SELECT[D5:D0]

PAGE NUMBER[D7:D0]

DIN

DOUT

NOTES

1. R/W IS CLEARED WHEN WRITING TO THE PAGE SELECT REGISTER.

2. THE ADDRESS OF THE PAGE SELECT REGISTER IS 0x01.

3. X = DON’T CARE.

Figure 52. Accessing a Page

CS

DIN

R/W

X

REG ADDRESS[D5:D0]

NO OP(0x00) [D7:D0]

DOUT[D7:D0]

DOUT

NOTES

1. R/W IS SET WHEN READING FROM A REGISTER AND CLEARED WHEN

WRITING TO A REGISTER.

2. X = DON’T CARE.

Figure 53. Accessing an 8-Bit Register

CS

DIN

R/W

X

REG ADDRESS[D5:D0]

DIN[D15:D8]

DIN[D7:D0]

1

DOUT

DOUT[D15:D0]

NOTES

1. R/W IS SET WHEN READING FROM A REGISTER AND CLEARED WHEN

WRITING TO A REGISTER.

2. X = DON’T CARE.

Figure 54. Accessing a 16-Bit Register

Rev. B | Page 70 of 78

Data Sheet

AD7293

When the conversion command is received, the AD7293 uses

the current values in the registers on the sequence page to

determine which channel to convert on and subsequently read

back from. The common result register is updated with the

result of the current conversion channel, which allows the user

to continuously read back the conversion results in command

mode. The ADC command mode sequencer prioritizes in this

order: V_IN0 to V_IN3, T_SENSEINT, T_SENSED0, T_SENSED1, I_SENSE0 to

MODES OF OPERTION

There are two methods of initiating a conversion on the

AD7293: background mode and command mode.

Background Mode (BG)

The AD7293 can be configured to continuously convert on a

programmable cycle of channels, making it the ideal mode of

operation for system monitoring. These conversions take place

in the background and are transparent to the master. Typically,

this mode is used to automatically monitor a selection of channels

with either the limit registers programmed to signal an out of

range condition via the alert function or with the minimum/

maximum recorders tracking the variation over time of a

particular channel. Reads and writes can be performed at any

time during this mode (the result registers contains the most

recent conversion results).

I

_SENSE3, voltage supply monitoring, BI-V_OUT0_MONto BI-V_OUT3_MON,

and RS0+_MONto RS3+_MON. The sequencer can be reset by writing

to any of the sequence registers.

In the example in Figure 55, to initiate the continuous conversion

command mode, point to the sequence page and write to the

relevant sequence registers. The ADC sequence register is

programmed to convert on analog input channels, V_IN0 to V_IN2,

in this example. The first conversion takes place when the AD7293

enters command mode after the special command byte. Every

subsequent conversion is initiated after the result readback

frame, as shown in Figure 55.

On power-up, this mode is disabled. This mode can be enabled

by writing to the background enable bits (V_INx background enable

register; temperature sensor background enable register; current

sensor background enable register; and the RS+_MON, supply

monitor, and BI-V_OUTx background enable register) from the

configuration page. The background conversions are active only

Figure 56 shows another example for a command mode conver-

sion with a fixed 24-bit SPI frame length. The first conversion is

initiated when the device enters the command mode after the

special command byte, which is followed by a 24-bit readback

of the conversion result. The device exits command mode

CS

when

is pulled high, that is, the interface is not active.

is pulled low, the conversions pauses and resumes

CS

When

CS

when

is pulled high, although the sequencer is not reset.

from the last channel in the cycle when

is pulled high again.

Every subsequent conversion is initiated by reentering the

command mode via the special command byte after which the

user must wait long enough to allow the device to finish any

conversions before reading back the next result.

The user can read back the conversion results via the channel

specific result registers.

If a command mode conversion is requested while the background

mode is active, the scheduled background mode conversion

Current Sensor and Temperature Sensor Conversions

CS

from the cycle pauses while is low and tags onto the command

mode conversion. Conversion is reflected in the ADC busy

signal, which stays true for the combined duration of the

command mode conversion and the background mode.

Conversions on the temperature and current sensor channels

can be enabled only via one set of registers, T_SENSEx background

enable and I_SENSEx background enable, respectively, unlike the

other channels, because the current sense and temperature

sense amplifiers work by integrating the input voltage for a

fixed amount of time, depending on the gain required. At the

end of this integration period, a request is sent to the ADC for a

conversion to be performed. The ADC deals with these requests

in the order in which they arrive. For the other channels, the

ADC starts converting immediately. The corresponding sequence

register for these channels is used only to put the temperature

and current sensor results in the command mode readback

sequence and not to enable conversions on these channels.

If the background conversions are enabled during the closed-

CS

loop mode operation, they run continuously irrespective of

status. However, the results of the ADC conversions are only

CS

stored if

is pulled high.

The ADC background cycle prioritizes in the following order:

V_IN0 to V_IN3, T_SENSEINT, T_SENSED0, T_SENSED1, I_SENSE0 to I_SENSE3,

voltage supply monitoring, BI-V_OUT0_MONto BI-V_OUT3_MON, and

RS0+_MONto RS3+_MON

.

Command Mode

Command mode is useful for controlling the sampling instant

on the V_INx channels if an ac waveform is being converted. To

enter this mode and initiate a conversion on a channel, the

special command byte, 0x82, must be written to the device.

Rev. B | Page 71 of 78

AD7293

Data Sheet

CS

1

8

16

24

SCLK

DIN

WRITE TO ADC SEQUENCE REGISTER

DOUT

BUSY

CS

24

32

40

48

56

1

8

16

SCLK

READ FROM ADC DATA REGISTER

PREVIOUS CONVERSION RESULT

CONVERSION COMMAND

DIN

DOUT

CONVERSION RESULT FOR V 0 D15:D0

IN

BUSY

CONVERT

IN

V

0

CS

16

1

8

16

1

8

16

SCLK

DIN

CONVERSION RESULT FOR V 1 D15:D0

IN

CONVERSION RESULT FOR V 2 D15:D0

IN

DOUT

CONVERT

IN

CONVERT

BUSY

V

1

V

2

IN

Figure 55. Continuous Conversion Command Mode Example

CS

1

8

16

24

1

8

16

24

SCLK

DIN

0

X

0

1

0

1

0

X

0

1

0

1

PAGE SELECT POINTER

SEQUENCE PAGE

NO OP

ADC SEQUENCE

REGISTER WRITE

V

3 V 2 V

IN IN IN

1

V 0 SELECTED

IN

DOUT

CS

1

8

16

24

1

8

16

24

SCLK

0

1

0

1

0

1

X

0

1

0

DIN

NO OP

CONVERSION COMMAND

RESULT REGISTER READ

NO OP

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

X

DOUT

V

0 RESULT

16

IN

CS

SCLK

DIN

1

8

16

24

1

8

24

0

1

0

1

0

1

X

0

1

0

NO OP

CONVERSION COMMAND

RESULT REGISTER READ

NO OP

b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

1 RESULT

NO OP

X

DOUT

V

IN

CS

Figure 56. Command Mode Read Example (24-Bit Fixed Frame, Taken High After Each Conversion)

Conversion Timing

Current Sense and Temperature Sense Channel

Integration Time

Table 113 shows the approximate conversion times for each type

of channel under nominal conditions. Note that the temperature

and current sensor channels, when enabled, are background

conversions that are added on in command mode because the

integration/sense times are greater than other ADC reads.

The internal current sense and temperature sense amplifiers

function by integrating the input voltage for a fixed amount of

time depending on the gain required. At the end of the integration

period, a request is sent to the ADC for a conversion to be

performed. The ADC deals with these requests in the order in

which they arrive.

Table 113. Typical Conversion Time

Channel

Command Mode

Background Mode (µs)

V_INx

0.7 µs

2.3

4.2

2.3

4.0

I_SENSE

T_SENSE

Monitor

x

Not applicable

4.0 µs

Rev. B | Page 72 of 78

Data Sheet

AD7293

Table 114. Current Sensor Integration Time

Conversion and Integration Timing Example 2

Code Gain

Clocks

Typical Integration Time (µs)

In this example, in addition to the three current sense channels,

three monitor channels are also enabled, as shown in Figure 58.

The ADC is busy all the time; therefore, the time it takes to

complete a cycle of conversions is the sum of all the conversion

times: (4.2 µs × 3 + 4.0 µs × 3) = 24.6 µs.

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

6.25

12.5

18.75

25

37.5

50

440

650

860

1070

1490

1910

2750

3590

6950

13670

17.6

26.0

34.4

42.8

59.6

76.4

110.0

143.6

278.0

546.8

1059.2

If the temperature sensor is also enabled, when the output of the

temperature sensor is ready (once every 1 ms to 2 ms depending

on which channels are selected), the ADC sequencer waits for

its turn in the sequence before initiating a conversion on the

particular T_SENSEx channel. The combination of conversions

increases the duration of that particular cycle from 24.6 µs to

(24.6 µs + 2.3 µs) = 26.9 µs in this example.

75

100

200

400

781.25 26480

Table 115. Temperature Sensor Integration time

Digital Filtering

Channel

T_SENSEINT

T_SENSED0

T_SENSED1

Clocks

30523

60987

Typical Integration Time (µs)

A digital filter is available on the ADC channels. The digital

filter consists of a simple low-pass filter function to help reduce

unwanted noise on dc signals. This low-pass filter has a −3 dB

cutoff frequency of

1220.92

2439.48

Each current sense channel has its own integrator, whereas

there is only one integrator for all three temperature channels.

Therefore, temperature inputs that are enabled are measured

sequentially. This means that, for example, if all are enabled, the

update time is (1220.92 µs + 2 × 2439.48 µs) = 6099.88 µs

f_S

f_−3dB

=

≈

2π × 64 400

where f_Sis the sample frequency. The sample frequency depends

on the type of channel, how many other channels are enabled,

and whether it is in background mode or command mode (for

example, if the internal temperature sensor channel is enabled

alone, the update period is 1220.92 µs typically, which is close to

f_S≈ 819 Hz). If V_IN0, V_IN1, V_IN2, and V_IN3 are also enabled in

background mode, a conversion then takes place on V_IN0 every

9.2 µs (2.3 µs × 4), meaning f_S≈ 1 ÷ 9.2 µs ≈ 108.7 kHz. To

avoid aliasing of high frequencies at the input, use an antialias

filter to reject input frequencies above f_S/2.

Conversion and Integration Timing Example 1

Enable three of the current sense channels with a gain of 6.25.

All three integrations start as soon as the enable register is

written to. After 17.6 µs, all three voltages are ready to be

converted by the ADC. The I_SENSE0 channel is converted first,

while the I_SENSE1 channel and the I_SENSE2 channel are held in the

queue. After the I_SENSE0 conversion is complete, the I_SENSE

0

amplifier is released to start a new integration, and the ADC

moves on to convert the I_SENSE1 voltage.

The AD7293 settles into a routine, converting the three I_SENSE

x

channels, each with an update time of (17.6 µs + 4.2 µs) = 21.8 µs.

See Figure 57 for more details.

Rev. B | Page 73 of 78

AD7293

Data Sheet

17.6µs

4.2µs

21.8µs

I

x

SENSE

ENABLE

I

0

SENSE

INTEGRATOR OUT

I

0

SENSE

READY

I

1

SENSE

INTEGRATOR OUT

I

1

SENSE

READY

I

2

SENSE

INTEGRATOR OUT

I

2

SENSE

READY

ADC BUSY

0

1

2

0

1

2

0

1

2

0

1

2

Figure 57. Conversation and Integration Internal Timing Example 1

I

0

SENSE INTEGRATION

24.6µs

I

x

SENSE

ENABLE

V

x

IN

ENABLE

I

0

SENSE

INTEGRATOR OUT

I

0

SENSE CONVERSION

I

0

SENSE

READY

I

1

SENSE

INTEGRATOR OUT

I

1

SENSE

READY

I

2

SENSE

INTEGRATOR OUT

I

2

SENSE

READY

ADC BUSY

V0 V1 V2 I0 I1 I2 V0 V1 V2 I0 I1 I2 V0 V1 V2 I0 I1 I2 V0 V1 V2 I0 I1 I2

Figure 58. Conversion and Integration Internal Timing Example 2

Rev. B | Page 74 of 78

Data Sheet

AD7293

APPLICATIONS INFORMATION

The AD7293 contains all the functions required for general-

purpose monitoring and control of current, voltage, and

temperature. With its 60 V maximum common-mode range,

the device is useful in applications where current sensing in the

presence of a high common-mode voltage is required. Closed-

loop mode is designed for monitoring and controlling, for

example, the power amplifier in a cellular base station.

the functionality of eight discrete components, providing

considerable board area savings over discrete solutions.

The circuit shown in Figure 59 is the typical power amplifier

control application diagram for the AD7293. The device

monitors and controls the overall performance of four final

stage amplifiers. The gain control and phase adjustment of the

driver stage are incorporated in the application and are carried

out by the four available uncommitted outputs of the AD7293.

The high-side current sensor measures the amount of current

on the respective final stage amplifiers while the closed-loop

system maintains the programmed current across the sense

resistor. Furthermore, the PA_ON provides optional control for

a cutoff switch on the supply. The ALERTx pins can be configured

to trigger when current readings are more than a specified limit

and the RF input signal can be switched off by the ALERTx pin.

The alert feature can also be routed internally to clamp the DAC

outputs and turn off the power.

BASE STATION POWER AMPLIFIER CONTROL

The AD7293 is used in a signal chain to achieve the optimal

bias conditioning for enhancement mode or depletion mode

power amplifiers. The main factors influencing the bias

conditions are temperature, supply voltage, gate voltage drift,

and general processing parameters. The overall performance of

a power amplifier configuration is determined by the inherent

trade-offs required in efficiency, gain, and linearity. The high

level of integration as well as the intelligent features offered by

the AD7293 allows the use of a single chip to dynamically

control the drain bias current to maintain a constant value over

temperature and time, thus significantly improving the overall

performance of the power amplifier. The AD7293 incorporates

By measuring the transmitted (Tx) power and the received (Rx)

power, the device can dynamically change the drivers and PA

signal to optimize performance.

Rev. B | Page 75 of 78

AD7293

Data Sheet

V

PP

REF

V

REFIN

ADC REFOUT

PAV

DD

PRECISION

2.5V

REFERENCE

PMOS

CONTROL

BI-V

0

OUT MON

PA_ON

RS3+

1

OUT MON

2

OUT MON

3

R

OUT MON

1

×

SENSE

RFOUT

RS3–

2

DACV

DD-BI

–

BI-V

3

2

2.5V

RFIN

OUT

1.25V

BIPOLAR

DAC

GaN

FILTER

+

DACV

DD-UNI

RS2+

RS2–

AV

SS

DD

R

SENSE

RFOUT

AV

–

BI-V

OUT

RFIN

BIPOLAR

DAC

GaN

FILTER

V

0

IN

Tx POWER

MONITOR

RS1+

AD7293

V

1

2

R

IN

SENSE

RFOUT

RS1–

BI-V

Rx POWER

MONITOR

IN

–

1

0

RFIN

OUT

BIPOLAR

DAC

GaN

FILTER

V

3

MUX

IN

RS0+

RS0–

R

CONTROL

LOGIC

SENSE

D0+

BI-V

1

OUT

RFIN

BIPOLAR

DAC

GaN

FILTER

D0–

D1+

UNI-V

0

1

GAIN

OUT

UNIPOLAR

DAC

CONTROL

GAIN

UNIPOLAR

DAC

CONTROL

D1–

2

3

GAIN

UNIPOLAR

DAC

CONTROL

ALERT AND LIMIT

REGISTERS

UNI-V

GAIN

OUT

0

UNIPOLAR

DAC

CONTROL

V

DRIVE

DAC

CLAMP

SPI

INTERFACE

RESET

LOGIC

DIGITALI/Os

CLAMP

DV

DD

CONTROL

V

1

CLAMP

Figure 59. Typical Power Amplifier Control Application

The AD7293 was designed for depletion mode power amplifier

biasing. Bipolar DAC outputs enable negative voltage biasing of

the gate on the depletion mode device. A closed-loop mode

combined with a low temperature drift reference ensures that

the loop is steady over temperature.

DEPLETION MODE AMPLIFIER BIASING AND

PROTECTION

Depletion mode devices (for example, gallium nitride (GaN) or

gallium arsenide (GaAs)) require temperature compensated

gate biasing voltages similar to enhancement mode devices (for

example, laterally diffused metal oxide semiconductor (LDMOS))

to maintain constant quiescent drain current with temperature.

The most important consideration for a depletion mode device

is the biasing sequence. If the gate of a depletion mode device is

at 0 V and the drain voltage is applied, the device may be

damaged by drawing excessive current. It is also likely that a

device may become potentially unstable at lower drain source

voltages. Therefore, decreasing the gate voltage to less than the

pinch off voltage while the drain voltage is being powered on

and off is necessary.

The AD7293 works to ensure that instability or destruction of

the depletion mode device is avoided. A PA_ON signal allows

the user the option to control an external PMOS switch to turn

on and off the drain current. This signal is set to the off state on

power-up. Because depletion mode devices require a negative

bias to remain at an acceptable level, and bipolar DACs transmit

on the AV_SSsupply for proper operation, PA_ON can be triggered

when AV_SSexceeds an acceptable level.

In the event of an AV_DDvoltage supply failure, the bipolar DACs

clamp to the AV_SSsupply (−5 V), which ensures that the PA

Rev. B | Page 76 of 78

Data Sheet

AD7293

threshold voltage is not exceeded in the event of AV_DDvoltage

supply failure.

To optimize the loop response from this point, the R_S, τ_I, τ_G, and

τ_Svalues can be adjusted (see Table 116).

The on-chip bipolar DAC clamping circuitry ensures that the

four bipolar outputs are set to their clamp value on power-up,

and the DACs can be triggered to clamp by the external SLEEPx

pins at any stage by the user.

Table 116. R_S, τ_I, τ_G, and τ_SAdjustment Values

Parameter Benefit of Increasing

Benefit of Decreasing

R_S

Setpoint resolution

increased, improved

dynamic range, and

faster settling

Reduced overshoot,

reduced power

dissipation, and allows

The voltage monitoring of the supply voltages can help to

quickly detect any system issues. The bipolar DAC output

monitoring can be useful in closed-loop mode to sense the

voltage output controlling the PA gate. Monitoring of the RSx+

pins voltages helps in detecting issues on the high side of the

sense resistor.

higher τ_Gand τ_S

τ_I

Reduced overshoot,

Faster settling

allows higher τ_Gand τ_S

τ_G

τ_S

Reduced noise from

current control loop

Reduced overshoot,

allows lower τ_I

Improved filtering of

disturbances at current

sense input

Reduced overshoot,

allows lower τ_I

To adhere to radio standards, it may be necessary to control the

rate at which the PA gain changes. A ramp register is available

that allows the user to control the slew rate of the DAC in

closed-loop mode. Additionally, a closed-loop sequence is

provided in the Closed-Loop Sequencing section to ensure the

protection of the power amplifier from an overvoltage.

When setting τ_G, do not exceed the maximum load capacitance

specification (10 nF when R_G= 0 Ω, and 1 µF when R_G= 5 Ω).

Include the PA gate capacitance in the calculation.

AD7293

V

PP

LOOP COMPONENT SELECTION

To select the loop component, use the following conditions:

R_S≤ 0.2/I_DS(MAX)

RSx+

RSx–

τ_S

R

S

R_S≤ τ_I/(52.5 µs × g_m(MAX)

)

τ_I

τ_G≤ τ_I/(25 × g_m(MAX)× R_S)

τ_S≤ (1/10) × τ_G

DAC

BI-V

x

τ_G

OUT

Figure 60. Loop Component Selection and Filtering

where:

R_Sis the value of the current sense resistor in ohms.

_DS(MAX)is the PA drain current at the maximum required PA

I

gain in amperes.

τ_Iis the integrator time constant (default value = 840 μs) in

seconds.

g_m(MAX)is the PA transconductance at the maximum required PA

gain in Siemens.

τ_Gis the gate filter time constant in seconds.

τ_Sis the current sense filter time constant in seconds.

Rev. B | Page 77 of 78

AD7293

Data Sheet

OUTLINE DIMENSIONS

DETAIL A

(JEDEC 95)

8.10

0.30

0.25

0.20

8.00 SQ

7.90

PIN 1

INDICATOR

PIN 1

43

56

INDIC AT

OR AREA OPTIONS

(SEE DETAIL A)

42

1

0.50

BSC

*

5.90

EXPOSED

PAD

5.80 SQ

5.70

29

14

28

15

0.50

0.40

0.30

0.20 MIN

TOP VIEW

BOTTOM VIEW

6.50 REF

0.80

0.75

0.70

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.05 MAX

0.02 NOM

COPLANARITY

0.08

SECTION OF THIS DATA SHEET.

SEATING

PLANE

0.203 REF

*

COMPLIANT TO JEDEC STANDARDS MO-220-WLLD-2

WITH EXCEPTION TO EXPOSED PAD DIMENSION.

Figure 61. 56-Lead Lead Frame Chip Scale Package [LFCSP],

8 mm × 8 mm Body and 0.75 mm Package Height

(CP-56-8)

Dimensions Shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range Package Description

Package Option

AD7293BCPZ

AD7293BCPZ-RL

EVAL-AD7293SDZ

EVAL-SDP-CB1Z

−40°C to +125°C

56-Lead Lead Frame Chip Scale Package [LFCSP]

Evaluation Control Board

CP-56-8

Controller Board

¹Z = RoHS Compliant Part.

registered trademarks are the property of their respective owners.

D13016-0-1/18(B)

Rev. B | Page 78 of 78


型号：	AD7293
厂家：	ADI
描述：	12-Bit Power Amplifier Current Controller
文件：	总78页 (文件大小：1562K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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