AD1847JST_技术文档

Serial-Port 16-Bit

SoundPort Stereo Codec

a

AD1847

FEATURES

I

Single-Chip Integrated ⌺⌬ Digital Audio Stereo Codec

Supports the Microsoft Window s Sound System *

Multiple Channels of Stereo Input

Analog and Digital Signal Mixing

Program m able Gain and Attenuation

On-Chip Signal Filters

Digital Interpolation and Decim ation

Analog Output Low -Pass

Sam ple Rates from 5.5 kHz to 48 kHz

44-Lead PLCC and TQFP Packages

Operation from +5 V Supplies

S

A

ASIC

AD1847

B

U

S

DSP

Figure 1. Exam ple System Diagram

External circuit requirements are limited to a minimal number

of low cost support components. Anti-imaging DAC output

filters are incorporated on-chip. Dynamic range exceeds 70 dB

over the 20 kHz audio band. Sample rates from 5.5 kHz to

48 kHz are supported from external crystals.

Serial Digital Interface Com patible w ith ADSP-21xx

Fixed-Point DSP

T he Codec includes a stereo pair of ∑∆ analog-to-digital con-

verters (ADCs) and a stereo pair of ∑∆ digital-to-analog con-

verters (DACs). Inputs to the ADC can be selected from four

stereo pairs of analog signals: line 1, line 2, auxiliary (“aux”)

line # 1, and post-mixed DAC output. A software-controlled

programmable gain stage allows independent gain for each

channel going into the ADC. T he ADCs’ output can be digitally

mixed with the DACs’ input.

P RO D UCT O VERVIEW

T he AD1847 SoundPort^®Stereo Codec integrates key audio

data conversion and control functions into a single integrated

circuit. T he AD1847 is intended to provide a complete, low

cost, single-chip solution for business, game audio and multi-

media applications requiring operation from a single +5 V sup-

ply. It provides a serial interface for implementation on a

computer motherboard, add-in or PCMCIA card. See Figure 1

for an example system diagram.

T he pair of 16-bit outputs from the ADCs is available over a se-

rial interface that also supports 16-bit digital input to the DACs

and control/status information. T he AD1847 can accept and

generate 16-bit twos-complement PCM linear digital data, 8-bit

unsigned magnitude PCM linear data, and 8-bit µ-law or A-law

companded digital data.

*Windows Sound System is a registered trademark of Microsoft Corp.

SoundPort is a registered trademark of Analog Devices, Inc.

(Continued on page 7)

FUNCTIO NAL BLO CK D IAGRAM

CLOCK

OUT

ANALOG DIGITAL

SUPPLY SUPPLY

CRYSTALS

ANALOG

I/O

DIGITAL

I/O

2

RESET

L

R

L

LINE 1

INPUT

OSCILLATORS

POWER

DOWN

LINE 2

INPUT

M

U

X

L

∑∆ A/D

µ/A

R

L

BUS

MASTER

GAIN

CONVERTER

LAW

AUX 1

INPUT

S

E

R

I

A

L

R

TIME SLOT

INPUT

R

µ/A

LAW

∑∆ A/D

CONVERTER

TIME SLOT

OUTPUT

SERIAL DATA

OUTPUT

ATTEN

GAIN/ATTEN/MUTE

SERIAL DATA

INPUT

P

O

R

T

L

µ/A

∑∆ D/A

ATTEN/

MUTE

ATTEN

∑

2

∑

LAW

L

CONVERTER

EXTERNAL

CONTROL

LINE

R

∑∆ D/A

CONVERTER

µ/A

LAW

ATTEN/

MUTE

OUTPUT

∑

SERIAL BIT

CLOCK

R

GAIN/ATTEN

/MUTE

L

FRAME

SYNC

AUX 2

INPUT

GAIN/ATTEN

/MUTE

AD1847

REFERENCE

2.25V

R

REV. B

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

® Analog Devices, Inc., 1996

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700 Fax: 617/ 326-8703

AD1847–SPECIFICATIONS

STAND ARD TEST CO ND ITIO NS UNLESS O TH ERWISE NO TED

T emperature

Digital Supply (V_DD

Analog Supply (V_CC

Word Rate (F_S

Input Signal

Analog Output Passband

25

°C

V

kHz

DAC Output Conditions

0 dB Attenuation

Full-Scale Digital Inputs

16-Bit Linear Mode

No Output Load

)

5.0

48

1007

20

)

Hz

Hz to 20 kHz

Mute Off

FFT Size

V_IH

V_IL

V_OH

V_OL

4096

2.4

0.8

2.4

0.4

ADC Input Conditions

0 dB Gain

V

–3.0 dB Relative to Full Scale

Line Input

16-Bit Linear Mode

ANALO G INP UT

Min

Typ

Max

Units

Full-Scale Input Voltage (RMS Values Assume Sine Wave Input)

Line1, Line2, AUX1, AUX2

1

2.8

V rms

V p-p

2.54

10

3.10

Input Impedance

Line1, Line2, AUX1, AUX2†

Input Capacitance†

kΩ

pF

15

P RO GRAMMABLE GAIN AMP LIFIER—AD C

Min

Typ

Max

Units

Step Size (All Steps T ested, –30 dB Input)

PGA Gain Range Span†

1.10

21.0

1.5

1.90

24.0

dB

AUXILIARY INP UT ANALO G AMP LIFIERS/ATTENUATO RS

Min

Typ

Max

Units

Step Size (+12 dB to –28.5 dB, Referenced to DAC Full Scale)

(–30 dB to –34.5 dB, Referenced to DAC Full Scale)

Input Gain/Attenuation Range Span†

1.3

1.1

45.5

10

1.5

1.7

1.9

47.5

dB

kΩ

AUX Input Impedance†

D IGITAL D ECIMATIO N AND INTERP O LATIO N FILTERS†

Min

Max

Units

Passband

0

–0.1

0.4 ϫ F_S

0.6 ϫ F_S

74

0.4 ϫ F_S

+0.1

0.6 ϫ F_S

∞

Hz

dB

Hz

dB

Passband Ripple

T ransition Band

Stopband

Stopband Rejection

Group Delay

30/F_S

0

Group Delay Variation Over Passband

µs

–2–

REV. B

AD1847

ANALO G-TO -D IGITAL CO NVERTERS

Min

Typ

Max

Units

Resolution

16

Bits

dB

%

Dynamic Range (–60 dB Input, T HD+N Referenced to Full Scale, A-Weighted)

T HD+N (Referenced to Full Scale)

70

0.040

–68

dB

Signal-to-Intermodulation Distortion†

83

dB

ADC Crosstalk†

Line Inputs (Input L, Ground R, Read R; Input R, Ground L, Read L)

Line1 to Line2 (Input Line1, Ground and Select Line2, Read Both Channels)

Line to AUX1

Line to AUX2

Line to DAC

–80

±10

±0.2

±55

dB

%

Gain Error (Full-Scale Span Relative to V_REFI

)

Interchannel Gain Mismatch (Difference of Gain Errors)

DC Offset

dB

LSB

D IGITAL-TO -ANALO G CO NVERTERS

Min

Typ

Max

Units

Resolution

16

Bits

dB

%

dB

%

dB

Dynamic Range (–60 dB Input, T HD+N Referenced to Full Scale, A-Weighted)

T HD+N (Referenced to Full Scale)

76

0.025

–72

Signal-to-Intermodulation Distortion†

Gain Error (Full-Scale Span Relative to V_REFI

Interchannel Gain Mismatch (Difference of Gain Errors)

DAC Crosstalk† (Input L, Zero R, Measure R_OUT ; Input R, Zero L, Measure L_OUT )

T otal Out-of-Band Energy† (Measured from 0.6 ϫ F_Sto 100 kHz)

86

)

±10

±0.2

–80

–50

–55

Audible Out-of-Band Energy (Measured from 0.6 ϫ F_Sto 22 kHz, T ested at F_S= 5.5 kHz)

D AC ATTENUATO R

Min

Typ

Max

Units

Step Size (0 dB to –22.5 dB) (T ested at Steps 0 dB, –19.5)

Step Size (–24 dB to –94 dB)

Output Attenuation Range Span†

1.3

1.0

–93

1.5

1.7

2.0

95

dB

D IGITAL MIX ATTENUATO R

Min

Typ

Max

Units

Step Size (0 dB to –22.5 dB) (T ested at Steps 0 dB, –19.5)

Step Size (–24 dB to –94 dB)

Output Attenuation Range Span†

1.3

1.0

–93.5

1.5

1.7

2.0

95.5

dB

ANALO G O UTP UT

Min

Typ

Max

Units

Full-Scale Line Output Voltage

V_REFI= 2.35*

0.707

2

V rms

V p-p

Ω

kΩ

pF

V

µA

V

1.80

10

2.20

600

Line Output Impedance†

External Load Impedance

Output Capacitance†

External Load Capacitance

V_REF(Clock Running)

V_REFCurrent Drive

15

100

2.50

2.00

100

2.35

V_REFI

Mute Attenuation of 0 dB

Fundamental† (LOUT )

Mute Click†

–80

8

dB

mV

(| Muted Output Minus Unmuted

Midscale DAC Output| )

*Full-scale line output voltage scales with V_REF(e.g., V_OUT(typ) – 2.0 V ϫ (V_REF/2.35)).

†Guaranteed, Not T ested.

REV. B

–3–

AD1847

SYSTEM SP ECIFICATIO NS

Min

Typ

Max

Units

System Frequency Response†

(Line In to Line Out, 20 Hz to 20 kHz)

Differential Nonlinearity†

±0.3

dB

±1/2

Bit

Phase Linearity Deviation†

1

Degrees

STATIC D IGITAL SP ECIFICATIO NS

Min

Max

Units

High Level Input Voltage (V_IH

Digital Inputs

XT AL1/2I

)

2.0

2.4

V

Low Level Input Voltage (V_IL)

0.8

V

High Level Output Voltage (V_OH) I_OH= 1 mA

Low Level Output Voltage (V_OL) I_OL= 4 mA

Input Leakage Current (GO/NOGO T ested)

Output Leakage Current (GO/NOGO T ested)

2.4

V_DD

0.4

+10

V

µA

–10

TIMING P ARAMETERS (Guaranteed O ver O perating Tem perature Range)

Min

Typ

Max

Units

Serial Frame Sync Period (t₁)

Clock to Frame Sync [SDFS] Propagation Delay (t_PD1

Data Input Setup T ime (t_S)

1/0.5 F_S

µs

ns

)

20

15

Data Input Hold T ime (t_H)

Clock to Output Data Valid (t_DV

Clock to Output T hree-State [High-Z] (t_HZ

Clock to T ime Slot Output [T SO] Propagation Delay (t_PD2

)

25

20

)

RESET and PWRDOWN Lo Pulse Width (t_RPWL

)

100

P O WER SUP P LY

Min

Max

Units

Power Supply Range – Digital & Analog

Power Supply Current – Operating (10 kΩ Line Out Load)

Analog Supply Current – Operating (10 kΩ Line Out Load)

Digital Supply Current – Operating (10 kΩ Line Out Load)

Analog Power Supply Current – Power Down

4.75

5.25

140

70

V

mA

µA

mW

70

400

750

4

Digital Power Supply Current – Power Down

Power Dissipation – Operating (Current ϫ Nominal Supply)

Power Dissipation – Power Down (Current ϫ Nominal Supply)

Power Supply Rejection (@ 1 kHz)†

(At Both Analog and Digital Supply Pins, ADCs)

(At Both Analog and Digital Supply Pins, DACs)

45

55

dB

CLO CK SP ECIFICATIO NS†

Min

Max

Units

Input Clock Frequency

Recommended Clock Duty Cycle

27

±10

MHz

%

Initialization/Sample Rate Change T ime

16.9344 MHz Crystal Selected at Power-Up

24.576 MHz Crystal Selected at Power-Up

16.9344 MHz Crystal Selected Subsequently

24.576 MHz Crystal Selected Subsequently

171

6

ms

6

†Guaranteed, not tested.

Specifications subject to change without notice.

–4–

REV. B

AD1847

ABSO LUTE MAXIMUM RATINGS*

Min Max

O RD ERING GUID E

Units

Tem perature

P ackage

Model

Range

D escription

O ption*

Power Supplies

Digital (V_DD

Analog (V_CC

Input Current

(Except Supply Pins)

Analog Input Voltage (Signal Pins) –0.3 (VA+) + 0.3

Digital Input Voltage (Signal Pins) –0.3 (VD+) + 0.3

)

–0.3 6.0

V

AD1847JP

AD1847JST

0°C to +70°C

44-Lead PLCC

44-Lead T QFP

P-44A

ST -44

*P = PLCC; ST = T QFP.

±10.0

mA

V

Ambient T emperature (Operating)

Storage T emperature

0

+70

°C

–65 +150

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in

the operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD1847 features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

P INO UTS

44-Lead P LCC

44-Lead TQFP

6

5

4

3

2

1

44 43 42 41 40

TSO

TSI

7

8

9

39 V

DD

38 GNDD

37 XCTL1

36 XCTL0

35 GNDD

1

2

3

4

33

V

TSO

TSI

V

PIN 1 IDENTIFIER

DD

32 GNDD

GNDD 10

RESET 11

XCTL1

XCTL0

GNDD

V

31

30

29

DD

GNDD

RESET

AD1847JP

5

6

Top View

(Not to Scale)

12

13

34

33

PWRDOWN

V

DD

V

28

27

26

25

24

23

PWRDOWN

AD1847JST

Top View

(Not to Scale)

DD

V

BM

V

CC

7

8

BM

CC

L_AUX2

R_AUX2

L_OUT

GNDA

GNDA 14

32 L_AUX2

31 R_AUX2

V

9

REFI

V

15

16

17

REFI

V

10

11

REF

30

29

V

L_OUT

N/C

R_LINE1

N/C

REF

R_LINE1

18 19

21 22

24 25 26

28

27

20

23

N/C = NO CONNECT

REV. B

–5–

AD1847

P IN D ESCRIP TIO NS

P ar allel Inter face

P in Nam e

P LCC TQFP

I/O D escription

SCLK

1

39

I/O Serial Clock. SCLK is a bidirectional signal that supplies the clock as an output to the

serial bus when the Bus Master (BM) pin is driven HI and accepts the clock as an input

when the BM pin is driven LO. T he serial clock output is fixed at 12.288 MHz when

XT AL1 is selected, and 11.2896 MHz when XT AL2 is selected. SCLK runs continu-

ously. An AD1847 should always be configured as the serial bus master unless it is a slave

in a daisy-chained multiple codec system.

SDFS

6

44

I/O Serial Data Frame Sync. SDFS is a bidirectional signal that supplies the frame synchroni-

zation signal as an output to the serial bus when the Bus Master (BM) pin is driven HI

and accepts the frame synchronization signal as an input when the BM pin is driven LO.

T he SDFS frequency powers up at one half of the AD1847 sample rate (i.e., FRS bit = 0)

with two samples per frame and can be programmed to match the sample rate (i.e., FRS

bit = 1) with one sample per frame. An AD1847 should always be configured as the serial

bus master unless it is a slave in a daisy-chained multiple codec system.

SDI

4

42

43

5

I

Serial Data Input. SDI is used by peripheral devices such as the host CPU or a DSP to

supply control and playback data information to the AD1847. All control and playback

transfers are 16 bits long, MSB first.

SDO

5

O

I

Serial Data Output. SDO is used to supply status/index readback and capture data infor-

mation to peripheral devices such as the host CPU or a DSP. All status/index readback

and capture data transfers are 16 bits long, MSB first. T hree-state output driver.

Reset. T he RESET signal is active LO. T he assertion of this signal will initialize the

on-chip registers to their default values. See the “Control Register Definitions” section for

a description of the contents of the control registers after RESET is deasserted.

Powerdown. T he PWRDOWN signal is active LO. T he assertion of this signal will reset

the on-chip control registers (identically to the RESET signal) and will also place the

AD1847 in a low power consumption mode. V_REFand all analog circuitry are disabled.

Bus Master. T he assertion (HI) of this signal indicates that the AD1847 is the serial bus

master. T he AD1847 will then supply the serial clock (SCLK) and the frame sync (SDFS)

signals for the serial bus. One and only one AD1847 should always be configured as the

serial bus master. If BM is connected to logic LO, the AD1847 is configured as a bus

slave, and will accept the SCLK and SDFS signals as inputs. An AD1847 should only be

configured as a serial bus slave when an AD1847 serial bus master already exists, in

daisy-chained multiple codec systems.

RESET

PWRDOWN

BM

11

12

33

6

I

27

I

T SO

T SI

7

8

1

2

O

I

T ime Slot Output. T his signal is asserted HI by the AD1847 coincidentally with the LSB

of the last time slot used by the AD1847. Used in daisy-chained multiple codec systems.

T ime Slot Input. T he assertion of this signal indicates that the AD1847 should immedi-

ately use the next three time slots (T SSEL = 1) or the next six time slots (T SSEL = 0)

and then activate the T SO pin to enable the next device down the T DM chain. T SI

should be driven LO when the AD1847 is the bus master or in single codec systems. Used

in daisy-chained multiple codec systems.

CLKOUT

44

38

O

Clock Output. T his signal is the buffered version of the crystal clock output and the fre-

quency is dependent on which crystal is selected. T his pin can be three-stated by driving

the BM pin LO or by programming the CLKT S bit in the Pin Control Register. See the

“Control Registers” section for more details. T he CLKOUT frequency is 12.288 MHz

when XT AL1 is selected and 16.9344 MHz when XT AL2 is selected.

Analog Signals

P in Nam e

P LCC

TQFP

I/O

D escription

L_LINE1

R_LINE1

L_LINE2

R_LINE2

L_AUX1

R_AUX1

L_AUX2

R_AUX2

L_OUT

23

17

22

18

26

27

32

31

30

28

17

11

16

12

20

21

26

25

24

22

I

Left Line Input # 1. Line level input for the # 1 left channel.

Right Line Input # 1. Line level input for the # 1 right channel.

Left Line Input # 2. Line level input for the # 2 left channel.

Right Line Input # 2. Line level input for the # 2 right channel.

Left Auxiliary Input # 1. Line level input for the AUX1 left channel.

Right Auxiliary Input # 1. Line level input for the AUX1 right channel.

Left Auxiliary Input # 2. Line level input for the AUX2 left channel.

Right Auxiliary Input # 2. Line level input for the AUX2 right channel.

Left Line Output. Line level output for the left channel.

O

R_OUT

Right Line Output. Line level output for the right channel.

–6–

REV. B

AD1847

Miscellaneous

P in Nam e

P LCC

TQFP

I/O

D escription

XT AL1I

XT AL1O

XT AL2I

XT AL2O

XCT L1:O

40

41

42

43

34

35

36

37

I

24.576 MHz Crystal # 1 Input.

24.576 MHz Crystal # 1 Output.

16.9344 MHz Crystal # 2 Input.

16.9344 MHz Crystal # 2 Output.

O

I

O

37 & 36 31 & 30

External Control. T hese T T L signals reflect the current status of register bits inside the

AD1847. T hey can be used for signaling or to control external logic.

V_REF

16

10

O

Voltage Reference. Nominal 2.25 volt reference available externally as a voltage datum

for dc-coupling and level-shifting. V_REFshould not have any signal dependent load.

V_REFI

15

21

9

I

Voltage Reference Internal. Voltage reference filter point for external bypassing only.

L_FILT

15

Left Channel Filter Capacitor. T his pin requires a 1.0 µF capacitor to analog ground

for proper operation.

R_FILT

NC

19

29

13

23

I

Right Channel Filter Capacitor. T his pin requires a 1.0 µF capacitor to analog ground

for proper operation.

No Connect. Do not connect.

P ower Supplies

P in Nam e

P LCC

TQFP

I/O

D escription

V_CC

13 & 25

7 & 19

I

Analog Supply Voltage (+5 V).

Analog Ground.

GNDA

V_DD

14, 20, 24

2, 9, 34, 39

3, 10, 35, 38

8, 14, 18

40, 3, 28, 33

41, 4, 29, 32

Digital Supply Voltage (+5 V).

Digital Ground.

GNDD

(Continued from page 1)

Analog Mixing

AUX1 and AUX2 analog stereo signals can be mixed in the ana-

log domain with the DAC output. Each channel of each auxil-

iary analog input can be independently gained/attenuated from

+12 dB to –34.5 dB in –1.5 dB steps or completely muted. T he

post-mixed DAC output is available on L_OUT and R_OUT

externally and as an input to the ADCs.

T he ∑∆ DACs are preceded by a digital interpolation filter. An

attenuator provides independent user volume control over each

DAC channel. Nyquist images are removed from the DACs’

analog stereo output by on-chip switched-capacitor and

continuous-time filters. T wo stereo pairs of auxiliary line-level

inputs can also be mixed in the analog domain with the DAC

output.

Even if the AD1847 is not playing back data from its DACs, the

analog mix function can still be active.

T he AD1847 serial data interface uses a T ime Division Multi-

plex (T DM) scheme that is compatible with DSP serial ports

configured in Multi-Channel Mode with 32 16-bit time slots

(i.e., SPORT 0 on the ADSP-2101, ADSP-2115, etc.).

Analog-to-D igital D atapath

T he ∑∆ ADCs incorporate a proprietary fourth-order modula-

tor. A single pole of passive filtering is all that is required for

antialiasing the analog input because of the ADC’s high 64

times oversampling ratio. T he ADCs include digital decimation

filters that low-pass filter the input to 0.4 ϫ F_S. (“F_S’’ is the

word rate or “sampling frequency.”) ADC input overrange con-

ditions will cause status bits to be set that can be read.

AUD IO FUNCTIO NAL D ESCRIP TIO N

T his section overviews the functionality of the AD1847 and is

intended as a general introduction to the capabilities of the de-

vice. As much as possible, detailed reference information has

been placed in “Control Registers” and other sections. T he user

is not expected to refer repeatedly to this section.

D igital-to-Analog D atapath

T he ∑∆ DACs contain a programmable attenuator and a low-

pass digital interpolation filter. T he anti-imaging interpolation

filter oversamples and digitally filters the higher frequency im-

ages. T he attenuator allows independent control of each DAC

channel from 0 dB to –94.5 dB in 1.5 dB steps plus full mute.

T he DACs’ ∑∆ noise shapers also oversample and convert the

signal to a single-bit stream. T he DAC outputs are then filtered

in the analog domain by a combination of switched-capacitor

and continuous-time filters. T hese filters remove the very high

frequency components of the DAC bitstream output. No exter-

nal components are required.

Analog Inputs

T he AD1847 SoundPort Stereo Codec accepts stereo line-level

inputs. All inputs should be capacitively coupled (ac-coupled) to

the AD1847. LINE1, LINE2, and AUX1, and post-mixed DAC

output analog stereo signals are multiplexed to the internal pro-

grammable gain amplifier (PGA) stage.

T he PGA following the input multiplexer allows independent

selectable gains for each channel from 0 to 22.5 dB in +1.5 dB

steps. T he Codec can operate either in a global stereo mode or

in a global mono mode with left-channel inputs appearing at

both channel outputs.

REV. B

–7–

AD1847

Changes in DAC output attenuation take effect only on zero

crossings of the digital signal, thereby eliminating “zipper” noise

on playback. Each channel has its own independent zero-crossing

detector and attenuator change control circuitry. A timer guar-

antees that requested volume changes will occur even in the ab-

sence of an input signal that changes sign. T he time-out period

is 8 milliseconds at a 48 kHz sampling rate and 48 milliseconds

at an 8 kHz sampling rate. (T ime-out [ms] ≈ 384/F_S[kHz]).

specified in the Codec’s internal registers. Note that when µ-law

compressed data is expanded to a linear format, it requires 14

bits. A-law data expanded requires 13 bits.

8

7

15

0

COMPRESSED

INPUT DATA

MSB

LSB

3/2 2/1

LSB

15

0

D igital Mixing

MSB

EXPANSION

DAC INPUT

Stereo digital output from the ADCs can be mixed digitally with

the input to the DACs. Digital output from the ADCs going out

of the serial data port is unaffected by the digital mix. Along the

digital mix datapath, the 16-bit linear output from the ADCs is

attenuated by an amount specified with control bits. Both chan-

nels of the monitor data are attenuated by the same amount.

(Note that internally the AD1847 always works with 16-bit

PCM linear data, digital mixing included; format conversions

take place at the input and output.)

3/2 2/1

MSB

LSB

0 0 0 / 0 0

Figure 2. A-Law or µ-Law Expansion

When 8-bit companding is specified, the ADCs’ linear output is

compressed to the format specified.

15

0

Sixty-four steps of –1.5 dB attenuation are supported to

–94.5 dB. T he digital mix datapath can also be completely

muted, preventing any mixing of the digital input with the digi-

tal output. Note that the level of the mixed signal is also a func-

tion of the input PGA settings, since they affect the ADCs’

output.

MSB

LSB

ADC OUTPUT

15

3/2 2/1

LSB

0

MSB

TRUNCATION

T he attenuated digital mix data is digitally summed with the

DAC input data prior to the DACs’ datapath attenuators. T he

digital sum of digital mix data and DAC input data is clipped at

plus or minus full scale and does not wrap around. Because

both stereo signals are mixed before the output attenuators, mix

data is attenuated a second time by the DACs’ datapath

attenuators.

15

8

7

MSB

COMPRESSION

LSB

0 0 0 0 0 0 0 0

Figure 3. A-Law or µ-Law Com pression

Note that all format conversions take place at input or output.

Internally, the AD1847 always uses 16-bit linear PCM represen-

tations to maintain maximum precision.

Analog O utputs

P ower Supplies and Voltage Refer ence

A stereo line-level output is available at external pins. Other

output types such as headphone and speaker must be imple-

mented in external circuitry. T he stereo line-level outputs

should be capacitively coupled (ac-coupled) to the external cir-

cuitry. Each channel of this output can be independently

muted. When muted, the outputs will settle to a dc value near

T he AD1847 operates from +5 V power supplies. Independent

analog and digital supplies are recommended for optimal perfor-

mance though excellent results can be obtained in single-supply

systems. A voltage reference is included on the Codec and its

2.25 V buffered output is available on an external pin (V_REF).

T he reference output can be used for biasing op amps used in

dc coupling. T he internal reference must be externally bypassed

to analog ground at the V_REFIpin, and must not be used to bias

external circuitry.

V_REF, the midscale reference voltage.

D igital D ata Types

T he AD1847 supports four global data types: 16-bit twos-

complement linear PCM, 8-bit unsigned linear PCM,

companded µ-law, and 8-bit companded A-law, as specified by

control register bits. Eight-bit data is always left-justified in 16-

bit fields; in other words, the MSBs of all data types are always

aligned; in yet other words, full-scale representations in all four

formats correspond to equivalent full-scale signals. The eight

least significant bit positions of 8-bit data in 16-bit fields are ig-

nored on digital input and zoned on digital output (i.e., truncated).

Clocks and Sam ple Rates

T he AD1847 operates from two external crystals, XT AL1 and

XT AL2. T he two crystal inputs are provided to generate a wide

range of sample rates. T he oscillators for these crystals are on

the AD1847, as is a multiplexer for selecting between them.

T hey can be overdriven with external clocks by the user, if so

desired. At a minimum, XT AL1 must be provided since it is se-

lected as the reset default. If XT AL2 is not used, the XT AL2

input pin should be connected to ground. T he recommended

crystal frequencies are 16.9344 MHz and 24.576 MHz. From

them, the following sample rates can be selected: 5.5125, 6.615,

8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8,

44.1, 48 kHz.

T he 16-bit PCM data format is capable of representing 96 dB of

dynamic range. Eight-bit PCM can represent 48 dB of dynamic

range. Companded µ-law and A-law data formats use nonlinear

coding with less precision for large-amplitude signals. T he loss

of precision is compensated for by an increase in dynamic range

to 64 dB and 72 dB, respectively.

On input, 8-bit companded data is expanded to an internal lin-

ear representation, according to whether µ-law or A-law was

–8–

REV. B

AD1847

CO NTRO L REGISTERS

Contr ol Register Mapping

Figure 5 shows the mapping of the Control Word, Status Word/

Index Readback and Data registers to time slots when T SSEL =

1. Note that the six 16-bit registers “share” three time slots.

T SSEL = 1 is used when the SDI and SDO pins are indepen-

dent inputs and output (i.e., “2-wire” system). T his configura-

tion is inefficient in terms of component interconnect (two

unidirectional wires for serial data input and output), but effi-

cient in terms of time slot usage (three slots consumed on each

of two unidirectional T DM serial buses). When T SSEL = 1, se-

rial data input to the AD1847 occurs concurrently with serial

data output from the AD1847 (i.e., Control Word reception on

the SDI pin occurs simultaneously with Status Word/lndex

Readback transmission on the SDO pin).

T he AD1847 has six 16-bit and thirteen 8-bit on-chip user-

accessible control registers. Control information is sent to the

AD1847 in the 16-bit Control Word. Status information is sent

from the AD1847 in the 16-bit Status Word. Playback Data and

Capture Data each have two 16-bit registers for the right and

left channels. Additional 8-bit Index Registers are accessed via

indirect addressing in the AD1847 Control Word. [Index Regis-

ters are reached with indirect addressing.] T he contents of an

indirect addressed Index Register may be readback by the host

CPU or DSP (during the Status Word/Index Readback time

slot) by setting the Read Request (RREQ) bit in the Control

Word. Note that each 16-bit register is assigned its own time

slot, so that the AD1847 always consumes six 16-bit time slots.

Figure 4 shows the mapping of the Control Word, Status Word/

Index Readback and Data registers to time slots when TSSEL = 0.

T SSEL = 0 is used when the SDI and SDO pins are tied to-

gether (i.e., “1-wire” system). T his configuration is efficient in

terms of component interconnect (one bidirectional wire for se-

rial data input and output), but inefficient in terms of time slot

usage (six slots consumed on single bidirectional T ime Division

Multiplexed [T DM] serial bus). When T SSEL = 0, serial data

input to the AD1847 occurs sequentially with serial data output

from the AD1847 (i.e., Control Word, Left Playback and Right

Playback data is received on the SDI pin, then the Status Word/

lndex Readback, Left Capture and Right Capture data is trans-

mitted on the SDO pin).

Slot

Register Nam e (16-Bit)

0

1

2

0

1

2

Control Word Input

Left Playback Data Input

Right Playback Data Input

Status Word/Index Readback Output

Left Capture Data Output

Right Capture Data Output

Figure 5. Control Register Mapping with TSSEL = 1

An Index Register readback request to an invalid index address

(11, 14 and 15) will return the contents of the Status Word. At-

tempts to write to an invalid index address (11, 14 and 15) will

have no effect on the AD1847. As mentioned above, the RREQ

bit of the Control Word is used to request Status Word output

or Index Register readback output during either time slot 3

(T SSEL = 0) or time slot 0 (T SSEL = 1). RREQ is set for In-

dex Register readback output, and reset for Status Word output.

When Index Register readback is requested, the Index Readback

bit format is the same as the Control Word bit format. All status

bits are updated by the AD1847 before a new Control Word is

received (i.e., at frame boundaries). T hus, if T SSEL = 0 and

the Control Word written at slot 0 causes some status bits to

change, the change will show up in the Status Word transmitted

at slot 3 of the same sample.

Slot

Register Nam e (16-Bit)

0

1

2

3

4

5

Control Word Input

Left Playback Data Input

Right Playback Data Input

Status Word/Index Readback Output

Left Capture Data Output

Right Capture Data Output

Figure 4. Control Register Mapping with TSSEL = 0

REV. B

–9–

AD1847

Contr ol Wor d (16-Bit)

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

CLOR

MCE

RREQ

res

IA3

IA2

IA1

IA0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

DAT A7

DAT A6

DAT A5

DAT A4

DAT A3

DAT A2

DAT A1

DAT A0

DAT A7:0 Index Register Data. T hese bits are the data for the desired AD1847 Index Register referenced by the Index Address.

Written by the host CPU or DSP to the AD1847.

IA3:0

Index Register Address. T hese bits define the indirect address of the desired AD1847 Index Register. Written by the host

CPU or DSP to the AD1847.

RREQ

Read Request. Setting this bit indicates that the current transfer is a request by the host CPU or DSP for readback of the

contents of the indirect addressed Index Register. When this bit is set (RREQ = HI), the AD1847 will not transmit its

Status Word in the following Status Word Index readback slot, but will instead transmit the data in the Index Register

specified by the Index Address. Although the Index Readback is transmitted in the following Status Word/Index

Readback time slot, the format of the Control Word is used (i.e., CLOR, MCE, RREQ and the Index Register Address

in the most significant byte, and the readback Index Register Data in the least significant byte). When this bit is reset

(RREQ = LO), the AD1847 will transmit its Status Word in the following Status Word Index Readback time slot.

A read request is serviced in the next available Index Readback time slot. If T SSEL = 0, the Index Register readback

data is transmitted in slot 3 of the same sample. If T SSEL = 1, Index Register readback data is transmitted in slot 0 of

the next sample. If T SSEL changes from 0 to 1, Index Register readback will occur twice, in slot 3 of the current sample,

and slot 0 of the next. If T SSEL changes from 1 to 0, the last read request is lost.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

MCE

Mode Change Enable. T his bit must be set (MCE = HI) whenever protected control register bits of the AD1847 are

changed. T he Data Format register, the Miscellaneous Information register, and the ACAL bit of the Interface Configu-

ration register can NOT be changed unless this bit is set. T he DAC outputs will be muted when MCE is set. T he user

must mute the AUX1 and AUX2 channels when this bit is set (no audio activity should occur). Written by the host CPU

or DSP to the AD1847. T his bit is HI after reset.

CLOR

Clear Overrange. When this bit is set (CLOR = HI), the overrange bits in the Status Word are updated every sample.

When this bit is reset (CLOR = LO), the overrange bits in the Status Word will record the largest overrange value. T he

largest overrange value is sticky until the CLOR bit is set. Written by the host CPU or DSP to the AD1847. Since there

can be up to 2 samples in the data pipeline, a change to CLOR may take up to 2 samples periods to take effect. T his bit

is HI after reset.

Immediately after reset, the contents of this register is: 1100 0000 0000 0000 (C000h).

Left/Right P layback/Captur e D ata (16-Bit)

T he data formats for Left Playback, Right Playback, Left Capture and Right Capture are all identical.

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

D AT A15

D AT A14

D AT A13

D AT A12

D AT A11

D AT A10

D AT A9

D AT A8

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

DAT A7

DAT A6

DAT A5

DAT A4

DAT A3

DAT A2

DAT A1

DAT A0

DAT A15:0 Data Bits. T hese registers contain the 16-bit, MSB first data for capture and playback. T he host CPU or DSP reads the

capture data from the AD1847. T he host CPU or DSP writes the playback data to the AD1847. For 8-bit linear or 8-bit

companded modes, only DAT A15:8 contain valid data; DAT A7:0 are ignored during capture, and are zeroed during

playback. Mono mode plays back the same audio sample on both left and right channels. Mono capture only captures

data from the left audio channel. See “Serial Data Format” T iming Diagram.

Immediately after reset, the content of these registers is: 0000 0000 0000 0000 (0000h).

–10–

REV. B

AD1847

Status Wor d (16-Bit)

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

res

RREQ

res

ID 3

ID 2

ID 1

ID 0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

res

ORR1

ORR0

ORL1

ORL0

ACI

IN IT

INIT

Initialization. T his bit is an indication to the host that frame syncs will stop and the serial bus will be shut down. INIT is

set HI on the last valid frame. It is reset LO for all other frames. Read by the host CPU or DSP from the AD1847.

T he INIT bit is set HI on the last sample before the serial interface is inactivated. T he only condition under which the

INIT bit is set is when a different sample rate is programmed. If FRS = 0 (32 slots per frame, two samples per frame)

and the sample rate is changed in the first sample of the 32 slot frame (i.e., during slots 0 through 15), the INIT bit will

be set on the second sample of that frame (i.e., during slots 16 through 31). If FRS = 0 and the sample rate is changed in

the second sample of the 32 slot frame, the INIT bit will be set on the second sample of the following frame.

ACI

Autocalibrate In-Progress. T his bit indicates that autocalibration is in progress or the Mode Change Enable (MCE) state

has been recently exited. When exiting the MCE state with the ACAL bit set, the ACI bit will be set HI for 384 sample

periods. When exiting the MCE state with the ACAL bit reset, the ACAL bit will be set HI for 128 sample periods, indi-

cating that offset and filter values are being restored. Read by the host CPU or DSP from the AD1847.

0

1

Autocalibration not in progress

Autocalibration is in progress

ACI clear (i.e., reset or LO) should be recognized by first polling for a HI on the sample after the MCE bit is reset, and

then polling for a LO. Note that it is important not to start polling until one sample after MCE is reset, because if MCE

is set while ACI is HI, an ACI LO on the following sample will suggest a false clear of ACI.

ORL1:0

Overrange Left Detect. T hese bits indicate the overrange on the left input channel. Read by the host CPU or DSP from

the AD1847.

0

1

2

3

Greater than –1.0 dB underrange

Between –1.0 dB and 0 dB underrange

Between 0 dB and 1.0 dB overrange

Greater than 1.0 dB overrange

ORR1:0

Overrange Right Detect. T hese bits indicate the overrange on the right input channel. Read by the host CPU or DSP

from the AD1847.

0

1

2

3

Greater than –1.0 dB underrange

Between –1.0 dB and 0 dB underrange

Between 0 dB and 1.0 dB overrange

Greater than 1.0 dB overrange

ID3:0

RREQ

res

AD1847 Revision ID. T hese four bits define the revision level of the AD1847. T he first version of the AD1847 is desig-

nated ID = 0001. Read by the host CPU or DSP from the AD1847.

T his bit is reset LO for the Status Word, echoing the RREQ state written by the host CPU or DSP in the previous Con-

trol Word. Read by the host CPU or DSP from the AD1847.

Reserved for future expansion. All reserved bits read zero (LO).

Immediately after reset, the contents of this register is: 0000 0001 0000 0000 (0100h).

REV. B

–11–

AD1847

Index Readback (16-Bit)

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

CLOR

MCE

RREQ

res

IA3

IA2

IA1

IA0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

DAT A7

DAT A6

DAT A5

DAT A4

DAT A3

DAT A2

DAT A1

DAT A0

DAT A7:0 Index Register Data. T hese bits are the readback data from the desired AD1847 Index Register referenced by the Index

Address from the previous Control Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.

IA3:0

Index Register Address. T hese bits echo the indirect address (written during the previous Control Word (with the RREQ

bit set) of the desired AD1847 Index Register to be readback. Read by the host CPU or DSP from the AD1847.

RREQ

Read Request. T his bit is set HI for Index Readback, echoing the RREQ state written by the host CPU or DSP in the

previous Control Word. Read by the host CPU or DSP from the AD1847.

res

Reserved for future expansion. All reserved bits read zero (LO).

MCE

Mode Change Enable. T his bit echoes the MCE state written by the host CPU or DSP during the previous* Control

Word (with the RREQ bit set). Read by the host CPU or DSP from the AD1847.

CLOR

Clear Overrange. T his bit echoes the CLOR state written by the host CPU or DSP during the previous Control Word

(with the RREQ bit set). Read by the host CPU or DSP from the AD1847.

Immediately after reset, the contents of this register is: 1110 0000 0000 0000 (E000h).

Indir ect Mapped Register s

Following in Figure 6 is a table defining the mapping of AD1847 8-bit Index Registers to Index Address. T hese registers are accessed

by writing the appropriate 4-bit Index Address in the Control Word.

Index

Register Nam e

0

1

2

3

4

Left Input Control

Right Input Control

Left Aux # 1 Input Control

Right Aux # l Input Control

Left Aux # 2 Input Control

Right Aux # 2 Input Control

Left DAC Control

5

6

7

8

Right DAC Control

Data Format

9

Interface Configuration

Pin Control

Invalid Address

Miscellaneous Information

Digital Mix Control

Invalid Address

10

11

12

13

14

15

Invalid Address

Figure 6. Index Register Mapping

A detailed description of each of the Index Registers is given below.

–12–

REV. B

AD1847

Left Input Contr ol Register (Index Addr ess 0)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

LIG 0

0000

LSS1

LSS0

res

LIG 3

LIG 2

LIG 1

LIG3:0 Left Input Gain Select. T he least significant bit of this 16-level gain select represents +1.5 dB. Maximum gain is

+22.5 dB.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

LSS1:0 Left Input Source Select. T hese bits select the input source for the left gain stage preceding the left ADC.

0

1

2

3

Left Line 1 Source Selected

Left Auxiliary 1 Source Selected

Left Line 2 Source Selected

Left Line 1 Post-Mixed Output Loopback Source Selected

T his register’s initial state after reset is: 0000 0000 (00h).

Right Input Contr ol Register (Index Addr ess 1)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0001

RSS1

RSS0

res

RIG 3

RIG 2

RIG 1

RIG 0

RIG3:0 Right Input Gain Select. T he least significant bit of this 16-level gain select represents +1.5 dB. Maximum gain is

+22.5 dB.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

RSS1:0 Right Input Source Select. T hese bits select the input source for the right gain stage preceding the right ADC.

0

1

2

3

Right Line 1 Source Selected

Right Auxiliary 1 Source Selected

Right Line 2 Source Selected

Right Line 1 Post-Mixed Output Loopback Source Selected

T his register’s initial state after reset is: 0000 0000 (00h).

Left Auxiliar y # 1 Input Contr ol Register (Index Addr ess 2)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0010

LMX1

res

LX1G 4

LX1G 3

LX1G 2

LX1G 1

LX1G 0

LX1G4:0 Left Auxiliary Input # 1 Gain Select. T he least significant bit of this 32-level gain/attenuate select represents –1.5 dB.

LX1G4:0 = 0 produces a +12 dB gain. LX1G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is

–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

LMX1

Left Auxiliary # 1 Mute. T his bit, when set HI, will mute the left channel of the Auxiliary # 1 input source. T his bit is set

HI after reset.

T his register’s initial state after reset is: 1000 0000 (80h).

Right Auxiliar y # 1 Input Contr ol Register (Index Addr ess 3)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0011

RMX1

res

RX1G 4

RX1G 3

RX1G 2

RX1G 1

RX1G 0

RX1G4:0 Right Auxiliary Input # 1 Gain Select. T he least significant bit of this 32-level gain/attenuate select represents –1.5 dB.

RX1G4:0 = 0 produces a +12 dB gain. RX1G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is

–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

RMX1

Right Auxiliary # 1 Mute. T his bit, when set to HI, will mute the right channel of the Auxiliary # 1 input source. T his bit is

set to HI after reset.

T his register’s initial state after reset is: 1000 0000 (80h).

REV. B

–13–

AD1847

Left Auxiliar y # 2 Input Contr ol Register (Index Addr ess 4)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0100

LMX2

res

LX2G 4

LX2G 3

LX2G 2

LX2G 1

LX2G 0

LX2G4:0 Left Auxiliary # 2 Gain Select. T he least significant bit of this 32-level gain/attenuate select represents –1.5 dB.

LX2G4:0 = 0 produces a +12 dB gain. LX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is

–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

LMX2

Left Auxiliary # 2 Mute. T his bit, when set HI, will mute the left channel of the Auxiliary # 2 input source. T his bit is HI

after reset.

T his register’s initial state after reset is: 1000 0000 (80h).

Right Auxiliar y # 2 Input Contr ol Register (Index Addr ess 5)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0101

RMX2

res

RX2G 4

RX2G 3

RX2G 2

RX2G 1

RX2G 0

RX2G4:0 Right Auxiliary # 2 Gain Select. T he least significant bit of this 32-level gain/attenuate select represents –1.5 dB.

RX2G4:0 = 0 produces a +12 dB gain. RX2G4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is

–34.5 dB. Gains referred to 2.0 V p-p full-scale output level.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

RMX2

Right Auxiliary # 2 Mute. T his bit, when set HI, will mute the right channel of the Auxiliary # 2 input source. T his bit is

HI after reset.

T his register’s initial state after reset is: 1000 0000 (80h).

Left D AC Contr ol Register (Index Addr ess 6)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0110

LD M

res

LD A5

LD A4

LD A3

LD A2

LD A1

LD A0

LDA5:0 Left DAC Attenuate Select. T he least significant bit of this 64-level attenuate select represents –1.5 dB. LDA5:0 = 0 pro-

duces a 0 dB attenuation. Maximum attenuation is –94.5 dB.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

LDM

Left DAC Mute. T his bit, when set HI, will mute the left channel output. Auxiliary inputs are muted independently with

the Left Auxiliary Input Control Registers. T his bit is HI after reset.

T his register’s initial state after reset is: 1000 0000 (80h).

Right D AC Contr ol Register (Index Addr ess 7)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0111

RDM

res

RDA5

RDA4

RDA3

RDA2

RDA1

RDA0

RDA5:0 Right DAC Attenuate Select. T he least significant bit of this 64-level attenuate select represents –1.5 dB. RDA5:0 = 0

produces a 0 dB attenuation. Maximum attenuation must be at least –94.5 dB.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

RDM

Right DAC Mute. T his bit, when set HI, will mute the right DAC output. Auxiliary inputs are muted independently with

the Right Auxiliary Input Control Registers. T his bit is HI after reset.

T his register’s initial state after reset is: 1000 0000 (80h).

–14–

REV. B

AD1847

D ata For m at Register (Index Addr ess 8)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

1000

res

FM T

C/L

S/M

C FS2

C FS1

C FS0

CSL

The contents of this register can NOT be changed except when the AD1847 is in the Mode Change Enable (MCE) state (i.e., the MCE bit in

the Control Word is HI). Write attempts to this register when the AD1847 is not in the MCE state will not be successful.

CSL

Clock Source Select. T his bit selects the clock source to be used for the audio sample rate.

0

1

XT AL1 (24.576 MHz)

XT AL2 (16.9344 MHz)

CFS2:0 Clock Frequency Divide Select. T hese bits select the audio sample rate frequency. T he audio sample rate depends on

which clock source is selected and the frequency of the clock source.

D ivide

Factor

XTAL1

24.576 MH z

XTAL2

16.9344 MH z

CFS2:0

0

1

2

3

4

5

6

7

3072

1536

896

768

448

384

512

2560

8.0 kHz

16.0 kHz

5.5125 kHz

11.025 kHz

18.9 kHz

22.05 kHz

37.8 kHz

44.1 kHz

33.075 kHz

6.615 kHz

27.42857 kHz

32.0 kHz

Not Supported

48.0 kHz

9.6 kHz

Note that the AD1847’s internal oscillators can be overdriven by external clock sources at the crystal inputs. T his is the

configuration used by serial bus slave codecs in daisy-chained multiple codec systems. If an external clock source is ap-

plied, it will be divided down by the selected Divide Factor. T he external clock need not be at the recommended crystal

frequencies.

S/M

C/L

Stereo/Mono Select. T his bit determines how the audio data streams are formatted. Selecting stereo will result with alter-

nating samples representing left and right audio channels. Mono playback plays the same audio sample on both channels.

Mono capture only captures data from the left audio channel.

0

1

Mono

Stereo

Companded/Linear Select. T his bit selects between a linear digital representation of the audio signal or a nonlinear, com-

panded format for all input and output data. T he type of linear PCM or the type of companded format is defined by the

FMT bits.

0

1

Linear PCM

Companded

FMT

Format Select. T his bit defines the format for all digital audio input and output based on the state of the C/L bit.

Linear P CM (C/L = 0)

Com panded (C/L = 1)

0

1

8-bit unsigned linear PCM

16-bit signed linear PCM

8-bit µ-law companded

8-bit A-law companded

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

T his register’s initial state after reset is: 0000 0000 (00h).

REV. B

–15–

AD1847

Inter face Configur ation Register (Index Addr ess 9)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

1001

res

ACAL

res

P EN

PEN

Playback Enable. T his bit will enable the playback of data in the format selected. PEN may be set and reset without

setting the MCE bit.

0

1

Playback Disabled

Playback Enabled

ACAL

Autocalibrate Enable. T his bit determines whether the AD1847 performs an autocalibrate when exiting from the Mode

Change Enable (MCE) state. If the ACAL bit is not set, the previous autocalibration values are used when returning from

the Mode Change Enable (MCE) state and no autocalibration takes place. Autocalibration must be preformed after initial

power-up for proper operation. T his bit is HI after reset.

0

1

No autocalibration

Autocalibration allowed

NOT E: T he ACAL bit can only be changed when the AD1847 is in the Mode Change Enable (MCE) state.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

T his register’s initial state after reset is: 0000 1000 (08h).

P in Contr ol Register (Index Addr ess 10)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

1010

XC T L1

XC T L0

CLKT S

res

CLKT S Clock T hree-State. If the BM bit is HI, and the CLKT S bit is HI, then the CLKOUT pin will be three-stated. If the BM

bit is HI, and the bit CLKT S is LO, then the CLKOUT pin is not three-stated. If the BM bit is LO, then the CLKOUT

pin is always three-stated.

XCT L1:0 External Control. T he state of these independent bits is reflected on the respective XCT L1 and XCT L0 pins of the

AD1847.

0

1

T T L logic LO on XCT L1, XCT L0 pins

T T L logic HI on XCT L1, XCT L0 pins

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

T his register’s initial state after reset is: 0000 0000 (00h).

Invalid Addr ess (Index Addr ess 11)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

1011

inval

Writes to this index address are ignored. Index readback of this index address will return the Status Word.

–16–

REV. B

AD1847

Miscellaneous Infor m ation Register (Index Addr ess 12)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

1100

FRS

T SSEL

res

The Miscellaneous Information Register can only be changed when the AD1847 is in the Mode Change Enable (MCE) state. Changes to this

register are updated at the next Serial Data Frame Sync (SDFS) boundary. If FRS is LO (i.e., 32 slots per frame), and either TSSEL or FRS

change in the first sample of a frame, the change is not updated at the second sample of the same frame, but at the first sample of the next frame.

T SSEL

T ransmit Slot Select. T his bit determines which T DM time slots the AD1847 should transmit on.

0

1

T ransmit on time slots 3, 4 and 5. Used when SDI and SDO are tied together (i.e., “1-wire” system).

T ransmit on slots 0, 1 and 2. Used when SDI and SDO are independent inputs and outputs

(i.e., “2-wire” system).

FRS

res

Frame Size. T his bit selects the number of time slots per frame.

0

1

Selects 32 slots per frame (two samples per frame sync or frame sync at half the sample rate).

Selects 16 slots per frame (one sample per frame sync or frame sync at the sample rate).

Reserved for future expansion. Write zeros (LO) to all reserved bits.

T his register’s initial state after reset is: 0000 0000 (00h).

D igital Mix Contr ol Register (Index Addr ess 13)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

1101

DMA5

DMA4

DMA3

DMA2

DMA1

DMA0

res

D M E

DME

Digital Mix Enable. T his bit enables the digital mix of the ADCs’ output with the DACs’ input. When enabled, the data

from the ADCs is digitally mixed with other data being delivered to the DACs (regardless of whether or not playback

[PEN] is enabled, i.e., set). If there is a capture overrun, then the last sample captured before overrun will be used for

the digital mix. If playback is enabled (PEN set) and there is a playback underrun, then a midscale zero will be added to

the digital mix data.

0

1

Digital mix disabled (muted)

Digital mix enabled

DMA5:0 Digital Mix Attenuation. T hese bits determine the attenuation of the ADC output data mixed with the DAC input data.

T he least significant bit of this 64-level attenuate select represents –1.5 dB. Maximum attenuation is –94.5 dB.

res

Reserved for future expansion. Write zeros (LO) to all reserved bits.

T his register’s initial state after reset is: 0000 0000 (00h).

Invalid Addr ess (Index Addr ess 14)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

1110

inval

Writes to this index address are ignored. Index readback of this index address will return the Status Word.

Invalid Addr ess (Index Addr ess 15)

IA3:0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

1111

inval

Writes to this index address are ignored. Index readback of this index address will return the Status Word.

REV. B

–17–

AD1847

Ser ial D ata Inter face

Note that in this “1-wire” system example, the Digital Signal

Processor (DSP) and ISA Bus Interface ASIC (ASIC) use the

same slots to communicate to the AD1847. T his reduces the

number of total time slots required and eliminates the need for

the AD1847 to distinguish between DSP data and ASIC data.

Also, in this example the ASIC and the DSP do not send data to

the AD1847 at the same time, so separate slots are unnecessary.

T he AD1847 serial data interface uses a T ime Division Multi-

plex (T DM) scheme that is compatible with DSP serial ports

configured in Multi-Channel Mode with either 32 or 16 16-bit

time slots. An AD1847 is always the serial bus master, transmit-

ting the serial clock (SCLK) and the serial data frame sync

(SDFS). T he AD1847 always receives control and playback

data in time slots 0, 1 and 2. T he AD1847 will transmit status

or index register readback and capture data in time slots 0, 1

and 2 if T SSEL = 1, and will transmit status or index register

readback and capture data in time slots 3, 4 and 5 if T SSEL =

0. T he following table in Figure 7 shows an example of how the

time slots might be assigned.

T he digital data in the serial interface is pipelined up to 2

samples deep. T his pipelining is required to properly resolve the

interface between the relatively fast fixed SCLK rate, and the

relatively slow sample rates (and therefore frame sync rates) at

which the AD1847 is capable of running. At low sample rates,

two samples of data can be serviced in a fraction of a sample pe-

riod. For example, at an 8 kHz sample rate, 32 time slots only

consume 32 × 16 × (1/12.288 MHz) = 41.67 µs out of a 125 µs

period. T he two-deep data pipeline thus allows sample overrun

(capture) and sample underrun (playback) to be avoided.

In this example design, which uses the ADSP-21xx DSP, each

frame is divided into 32 time slots of 16-bits each (FRS = 0).

T wo audio samples are contained in the 32 time slots, with a

single frame sync (SDFS) at the beginning of the frame. T he

ADSP-21xx serial port (SPORT 0) supports 32 time slots. T he

format of the first 16 time slots (sample N) is the same as the

format of the second 16 time slots (sample N+1). In this ex-

ample, 24 time slots are used, as indicated below. Note that

time slots 12 through 15 and 28 through 31 are unused in this

example, and that Figure 7 presumes that T SSEL = 0 (“1-wire”

system).

Figure 8 represents a logical view of the slot utilization between

devices.

AD1847

0, 1, 2, 16, 17, 18

SDI

ASIC

SDO

3, 4, 5, 19, 20, 21

0, 1, 2,

3, 4, 5,

19, 20, 21

Slot Num ber Sou r ce

D estin ation For m at

AD1847 Control Word

16, 17, 18

0, 16

6, 7, 8,

22, 23, 24

9, 10, 11,

25, 26, 27

ADSP-21XX

1, 17

2, 18

3, 19

ASIC

AD 1847

Left Playback Data

Right Playback Data

AD1847 Status Word/

Index Readback

Left Capture Data

Right Capture Data

AD1847 Control Word

Left Playback Data

Right Playback Data

AD1847 Status Word/

Index Readback

Left Capture Data

Right Capture Data

DSP Control

DR

DT

DR

NOTE: DSP MUST HAVE TWO SERIAL PORTS

4, 20

5, 21

0, 16

1, 17

2, 18

3, 19

AD 1847 ASIC

Figure 8. Tim e Slot Allocation Exam ple

DSP

AD 1847

Note that this is a system specific 1-wire example. For non-DSP

operation, the DSP is either not present or disabled. If the DSP

is present, the ASIC configures the DSP through slot 6 (and slot

22) to three-state its outputs in time slots 0, 1 and 2 (and slots

16, 17 and 18). T he ASIC can then enable its drivers for time

slots 0, 1 and 2 (and slots 16, 17 and 18). For DSP operation,

the ASIC three-states its outputs for time slots 0, 1 and 2 (and

slots 16, 17 and 18) and enables the DSP drivers for slots 0, 1

and 2 (and slots 16, 17, and 18).

4, 20

5, 21

6, 22

7, 23

AD 1847 DSP

ASIC

DSP

Left Processed

Playback Data

8, 24

Right Processed

Playback Data

An application note is available from Analog Devices with addi-

tional information on interfacing to the AD1847 serial port.

T his application note can be obtained through your local Ana-

log Devices representative, or downloaded from the DSP Bulle-

tin Board Service at (617) 461-4258 (8 data bits, no parity, 1

stop bit, 300/1200/2400/4600 baud).

9, 25

DSP Status

10, 26

ASIC

Left Processed

Capture Data

11, 27

Right Processed

Capture Data

Figure 7. Tim e Slot Assignm ent Exam ple

–18–

REV. B

AD1847

Contr ol Wor d

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

CLOR

MCE

RREQ

res

IA3

IA2

IA1

IA0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

DAT A7

DAT A6

DAT A5

DAT A4

DAT A3

DAT A2

DAT A1

DAT A0

Left P layback D ata

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

D AT A15

D AT A14

D AT A13

D AT A12

D AT A11

D AT A10

D AT A9

D AT A8

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

DAT A7

DAT A6

DAT A5

DAT A4

DAT A3

DAT A2

DAT A1

DAT A0

Right P layback D ata

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

D AT A15

D AT A14

D AT A13

D AT A12

D AT A11

D AT A10

D AT A9

D AT A8

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

DAT A7

DAT A6

DAT A5

DAT A4

DAT A3

DAT A2

DAT A1

DAT A0

Status Wor d

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

res

RREQ

res

ID 3

ID 2

ID 1

ID 0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

res

ORR1

ORR0

ORL1

ORL0

ACI

IN IT

Index Readback

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

CLOR

MCE

RREQ

res

IA3

IA2

IA1

IA0

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

DAT A7

DAT A6

DAT A5

DAT A4

DAT A3

DAT A2

DAT A1

DAT A0

Left Captur e D ata

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

D AT A15

D AT A14

D AT A13

D AT A12

D AT A11

D AT A10

D AT A9

D AT A8

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

DAT A7

DAT A6

DAT A5

DAT A4

DAT A3

DAT A2

DAT A 1

DAT A0

Right Captur e D ata

D ata 15

D ata 14

D ata 13

D ata 12

D ata 11

D ata 10

D ata 9

D ata 8

D AT A15

D AT A14

D AT A13

D AT A12

D AT A11

D AT A10

D AT A9

D AT A8

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

DAT A7

DAT A6

DAT A5

DAT A4

DAT A3

DAT A2

DAT A1

DAT A0

REV. B

–19–

AD1847

IA3:0

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

D ata 7

LSS1

RSS1

LMX1

RMX1

LMX2

RMX2

LD M

RDM

res

D ata 6

LSS0

RSS0

res

D ata 5

res

D ata 4

res

D ata 3

LIG 3

RIG 3

LX1G 3

RX1G 3

LX2G 3

RX2G 3

LD A3

RDA3

C FS2

ACAL

res

D ata 2

LIG 2

RIG 2

LX1G 2

RX1G 2

LX2G 2

RX2G 2

LD A2

RDA2

C FS1

res

D ata 1

LIG 1

RIG 1

LX1G 1

RX1G 1

LX2G 1

RX2G 1

LD A1

RDA1

C FS0

res

D ata 0

LIG 0

RIG 0

LX1G 0

RX1G 0

LX2G 0

RX2G 0

LD A0

RDA0

CSL

Index

0

1

res

LX1G 4

RX1G 4

LX2G 4

RX2G 4

LD A4

RDA4

S/M

2

res

3

res

4

res

5

res

LD A5

RDA5

C/L

6

res

7

FM T

res

8

res

P EN

9

XC T L1

inval

XC T L0

inval

T SSEL

DMA4

inval

CLKT S

inval

res

10

11

12

13

14

15

inval

FRS

res

DMA5

inval

DMA3

inval

DMA2

inval

DMA1

inval

DMA0

inval

res

D M E

inval

Figure 9. Register Map Sum m ary

Contr ol Register Mapping Sum m ar y

A detailed map of the control register bit assignments is summa-

rized for reference in Figure 9.

Figure 10 illustrates the connection between master and slave(s)

in a daisy-chained, multiple Codec system. Note that the T SI

pin of the master Codec should be tied to digital ground. T he

XT AL1I pin of the slaves should be connected to digital

ground, and XT AL1O pin should be left unconnected, while

the XT AL2I pin should be connected to the CLKOUT pin of

the AD1847 master, and the XT AL2O pin generates a driven

version of the CLKOUT signal applied to the XT AL2I pin.

D aisy-Chained Multiple Codecs

Multiple AD1847s can be configured in a daisy-chain system

with a single master Codec and one or more slave Codecs.

Codecs in a daisy-chained configuration are synchronized at the

sample level.

T he master and slave AD1847s should be powered-up together.

If this is not possible, the slave(s) should power-up before the

master Codec, such that the slave(s) are ready when the master

starts to drive the serial interface, and a serial data frame sync

(SDFS) can synchronize the master and slave(s).

INITIALIZATIO N AND P RO CED URES

Reset and P ower D own

A total reset of the AD1847 is defined as any event which

requires both the digital and analog section of the AD1847 to

return to a known and stable state. T otal reset mode, as well as

power down, occurs when the PWRDOWN pin of the AD1847

has been asserted low for minimum power consumption. When

the PWRDOWN signal is deasserted, the AD1847 must be cali-

brated by setting the ACAL bit and exiting from the Mode

Change Enable (MCE) state.

T he sample rate for the master and slave(s) should be pro-

grammed together. If this is not possible, the slave(s) should be

programmed before the master AD1847. A slave AD1847 enters

a time-out period after a new sample rate has been selected.

During this time-out period, a slave will ignore any activity on

the SDFS signal (i.e., frame syncs). T here is no software means

to determine when a slave has exited from this time-out period

and is ready to respond to frame syncs. However, as long as the

AD1847 master is driving the serial interface, a frame sync will

not occur before the slave Codec(s) are ready.

T he reset occurs, and only resets the digital section of the

AD1847, when the RESET pin of the AD1847 has been as-

serted LO to initialize all registers to known values. See the reg-

ister definitions for the exact values initialized. T he register reset

defaults include T SSEL = 0 (1-wire system) and FRS = 0

(32 slots per frame). If the target application requires a 2-wire

system design or 16 slots per frame, the AD1847 can be

bootstrapped into these configurations.

Note that the time slots for all slave AD1847s must be assigned

to those slots which immediately follow the time slots consumed

by the master AD1847 so that the T SO (T ime Slot Output)/T SI

(T ime Slot Input) signaling operates properly. For example, in a

2-wire system with one master and one slave, the time slot as-

signment should be 0, 1, 2 (16, 17, 18) for the master AD1847,

and 3, 4, 5 (19, 20, 21) for the slave AD1847.

–20–

REV. B

AD1847

MCE bit set HI, IA3:0 = “1100” to address the Miscellaneous

Information Index Register, and DAT A7:0 = “1X00 0000” to

set the FRS bit HI.

24.576

MHz

16.9344

MHz

2

T he host CPU or DSP must maintain the MCE bit set HI in

slot 16, which is the Control Word of the second sample of

the frame, so that the AD1847 does not initiate autocalibration

prematurely. At the next frame sync, the AD1847 will be

reconfigured.

XTAL1I,O XTAL2I,O

SCLK

TSI

SDFS

AD1847

(MASTER)

SDI

SDO

TSO

CLKOUT

T he AD1847 must be reset after power up. When the RESET

signal is deasserted, the AD1847 will autocalibrate when the

MCE bit is reset LO (i.e., when exiting the Mode Change En-

able state) only if the ACAL bit is set. If the ACAL bit is not

set, the previous autocalibration values will be used.

TSI

XTAL2I

SCLK

SDFS

SDI

XTAL1O

XTAL2O

N/C

(SLAVE 1)

XTAL1I

SDO

T he AD1847 will not function properly unless an auto-

calibration is performed after power up.

TSO

During power down, the serial port digital output pins and the

analog output pins take the following states:

TSI

XTAL2I

SCLK

SDFS

SDI

XTAL1O

XTAL2O

N/C

SCLK–LO if BM is HI (i.e., bus master), input pin if BM is

LO (i.e., bus slave)

SDFS–LO if BM is HI, input pin if BM is LO

SDO–three-state

(SLAVE 2)

XTAL1I

SDO

TSO

T SO–three-state

CLKOUT –LO if BM HI, three-state if BM is LO

V

_REF–pulled to analog ground

Figure 10a. One-Wire Daisy-Chained Codec Interconnect

L_OUT , R_ OUT – pulled to analog ground

24.576

MHz

16.9344

MHz

Clock Connections and Clock Rates

When the AD1847 is configured as a bus slave (BM = LO), the

XT AL1I pin should be connected to digital ground, and the

XT AL2I pin should be tied to the CLKOUT of the AD1847

bus master. T he XT AL1O and the XT AL2O pins should be left

unconnected. When the AD1847 is configured as a bus master

(BM = HI), the XT AL1I and the XT AL1O pin should be con-

nected to a 24.576 MHz crystal, and the XT AL2I and

XT AL2O pin should be connected to a 16.9344 MHz crystal.

2

XTAL1I, O XTAL2I, O

SCLK

TSI

SDFS

AD1847

(MASTER)

SDI

SDO

TSO

CLKOUT

When XT AL1 is selected (by resetting the CSL bit LO in the

Data Format Register) as the clock source, the SCLK pin will

generated a serial clock at 12.288 MHz (or one half of the crys-

tal frequency applied at XT AL1), and the CLKOUT pin will

also generate a clock output at 12.288 MHz when the AD1847

is in bus master mode (BM = HI). When XT AL2 is selected (by

setting the CSL bit HI in the Data Format Register) as the clock

source, the SCLK pin will generate a serial clock at 11.2896 MHz

(or two thirds of the crystal frequency applied at XT AL2), and

the CLKOUT pin will generate a clock output at 16.9344 MHz

when the AD1847 is in bus master mode (BM = H I). The

CLKOUT pin will be three-stated when the AD1847 is placed

in bus slave mode (BM = LO).

TSI

XTAL2I

SCLK

SDFS

SDI

XTAL1O

XTAL2O

N/C

(SLAVE 1)

XTAL1I

SDO

TSO

TSI

XTAL2I

SCLK

SDFS

SDI

XTAL1O

XTAL2O

N/C

(SLAVE 2)

XTAL1I

SDO

TSO

When the selected frame size is 32 slots per frame (by resetting

the FRS bit LO in the Miscellaneous Information Register), the

SDFS pin will generate a serial data frame sync at the frequency

of the selected sample rate divided by two, when the AD1847 is

in bus master mode (BM = HI). When the selected frame size is

16 slots per frame (by setting the FRS bit HI in the Miscella-

neous Information Register), the SDFS pin will generate a serial

data frame sync at the frequency of the selected sample rate,

when the AD1847 is in bus master mode (BM = HI).

Figure 10b. Two-Wire Daisy-Chained Codec Interconnect

T o bootstrap into T SSEL = 1 (i.e., 2-wire system design), the

host CPU or DSP must transmit to the AD1847 in slot 0 a

Control Word with the MCE bit set HI, IA3:0 = “1100” to

address the Miscellaneous Information Index Register, and

DAT A7:0 = “X100 000” to set the T SSEL bit HI. T o bootstrap

into FRS = 1 (i.e., 16 slots per frame), the host CPU or DSP

must transmit to the AD1847 in slot 0 a Control Word with the

REV. B

–21–

AD1847

When the AD1847 is in bus slave mode (BM = LO), the T SI

pin should be connected to the T SO pin of the AD1847 master

or slave which has been assigned to the preceding time slots.

T he signal on the T SO pin is essentially the signal received on

the T SI pin, but delayed by 3 or 6 time slots from T SI (depend-

ing on the state of T SSEL). T he frequency of the transitions on

the T SI and T SO lines is equivalent to the frequency on the

SDFS pin.

If ACAL is not set, the AD1847 is muted for 128 sample peri-

ods after resetting the MCE bit, and the ACI bit in the Status

Word is set HI during this 128 sample periods. Autocalibration

must be performed after power-up to ensure proper operation of

the AD1847.

Exiting from the MCE state always causes ACI to go HI. If the

ACAL bit is set when MCE state is exited, then the ACI bit will

be HI for 384 sample periods. If the ACAL bit is reset when

MCE is exited, then the ACI bit will be HI for 128 sample

periods.

When the AD1847 is in bus master mode (BM = HI), the T SI

pin should be connected to digital ground. T he signal on the

T SO pin is essentially the same as the signal output on the

SDFS pin, but delayed by 3 or 6 time slots from SDFS (again,

depending on the state of T SSEL).

Changing Sam ple Rates

T he internal states of the AD1847 are synchronized by the

selected sample frequency defined in the Data Format Register.

T he changing of either the clock source or the clock frequency

divide requires a special sequence for proper AD1847 operation.

Mode Change Enable State

T he AD1847 must be in the Mode Change Enable (MCE) state

before any changes to the ACAL bit of the Interface Configura-

tion Register, the Data Format Register, or the Miscellaneous

Information Register are allowed. Note that the MCE bit does

not have to be reset LO in order for changes to take effect.

1. Mute the outputs of the AD1847 and enter the Mode Change

Enable (MCE) state by setting the MCE bit of the AD1847

Control Word.

2. During a single atomic or nondivisible write cycle, change the

Clock Frequency Divide Select (CFS) and/or the Clock

Source Select (CSL) bits of the Data Format Register to the

desired values. CFS and CSL can be programmed in the

same Control Word as MCE.

D igital Mix

Digital mix is enabled via the DME bit in the Digital Mix Con-

trol Register. T he digital mix routes the digital data from the

ADCs to the DACs. T he mix can be digitally attenuated via bits

also in the Digital Mix Control Register. T he ADC data is

summed with the DAC data supplied at the digital bus inter-

face. When digital mix is enabled and the PEN bit is not set,

ADC data is summed with zeros to produce the DAC output.

3. T he INIT bit in the Status Word will be set HI at the last

sample of the next frame to indicate that the serial port will be

disabled for a timeout period.

4. T he AD1847 requires a period of time to resynchronize its

internal states to the newly selected clock. During this time,

the AD1847 will be unable to respond at its serial interface

port (i.e., no frame syncs will be generated). T he time-out

period is 2²¹ϫ SCLK ≈ 170 ms after power-up, and ≈ 5 ms

for subsequent changes of sample rate.

If the sum of the digital mix (ADC output and DAC input from

the serial bus interface) is greater than full scale, the AD1847

will send a positive or negative full scale value to the DACs,

whichever is appropriate (clipping).

Autocalibr ation

T he AD1847 has the ability to calibrate its ADCs and DACs for

greater accuracy by minimizing dc offsets. Autocalibration oc-

curs whenever the AD1847 exits from the Mode Change Enable

(MCE) state AND the ACAL bit in the Interface Configuration

Register has been set.

5. Exit the Mode Change Enable state by resetting the MCE bit.

Upon exiting the MCE state, an autocalibration of duration

384 sample periods or an output mute of duration 128 sample

periods occurs, depending on the state of the ACAL bit.

6. Poll the ACI bit in the AD1847 Status Word for a HI (indi-

cating that autocalibration is in progress) then poll the ACI

bit for a LO (indicating that autocalibration has completed).

Once the ACI bit has been read back LO, normal operation of

the Codec can resume.

T he completion of the autocalibration sequence can be deter-

mined by polling the Autocalibration In-Progress (ACI) bit in

the Status Word. T his bit will be HI while the autocalibration is

in progress and LO once autocalibration has completed. T he

autocalibration sequence will take at least 384 sample periods.

T he CSL and CFS bits cannot be changed unless the AD1847

is in the Mode Change Enable state (i.e., the MCE bit in the

AD1847 Control Word is set). Attempts to change the contents

of the Data Format Register without MCE set will result in the

write cycle not being recognized (the bits will not be updated).

T he autocalibration procedure is as follows:

1. Mute both left and right AUX1 and AUX2 inputs via the Left

Auxiliary Input and Right Auxiliary Input Control Registers.

2. Place the AD1847 in the Mode Change Enable (MCE) state

using the MCE bit of the AD1847 Control Word. Set the

ACAL bit in the Interface Configuration Register.

T he MCE bit should not be reset until after the INIT bit in the

AD1847 Status Word is detected HI. After the INIT bit is de-

tected HI, the serial port is disabled. When the next frame sync

arrives (after the time-out period), all internal clocks are stable

and the serial port is ready for normal operation.

3. Exit from the Mode Change Enable state by resetting the

MCE bit.

4. Poll the ACI bit in the AD1847 Status Word for a HI

(autocalibration in progress), then poll the ACI bit for a LO

(autocalibration complete).

5. Unmute the AUX inputs, if used.

–22–

REV. B

AD1847

D ATA FO RMAT D EFINITIO NS

8-Bit Com panded For m ats

T here are four data formats supported by the AD1847: 16-bit

signed, 8-bit unsigned, 8-bit companded µ-law, and 8-bit com-

panded A-law. The AD1847 supports these four formats because

each of them have found wide use in important applications.

T he 8-bit companded formats (µ-law and A-law) are used in the

telecommunications industry. Both of these formats are used in

ISDN communications and workstations; µ-law is the standard

for the United States and Japan while A-law is used in Europe.

Companded audio allows either 64 dB or 72 dB of dynamic

range using only 8-bits per sample. T his is accomplished using a

nonlinear formula which assigns more digital codes to lower am-

plitude analog signals at the expense of resolution of higher am-

plitude signals. T he µ-law format of the AD1847 conforms to

the Bell System µ = 255 companding law while the A-law format

conforms to CCIT T “A” law models. Figure 13 shows approxi-

mately how both the µ-law and A-law companding schemes be-

have. Refer to the standards mentioned above for an exact

definition.

16-Bit Signed For m at

T he 16-bit signed format (also called 16-bit twos-complement)

is the standard method of representing 16-bit digital audio. T his

format yields 96 dB of dynamic range and is common in con-

sumer compact disk audio players. T his format uses the value

– 32768 (8000h) to represent minimum analog amplitude while

32767 (7FFFh) represents maximum analog amplitude. Inter-

mediate values are a linear interpolation between minimum and

maximum amplitude values.

MAX

MIN

00h

2Ah

8000h

0000h

7FFFh

FFh

D5h

80h µ-law

AAh A-law

DIGITAL VALUE

Figure 11. 16-Bit Signed Form at

8-Bit Unsigned For m at

Figure 13. 8-Bit Com panded Form at

T he 8-bit unsigned format is commonly used in the personal

computer industry. T his format delivers 48 dB of dynamic

range. T he value 0 (00h) is used to represent minimum analog

amplitude while 255 (FFh) is used to represent maximum ana-

log amplitude. Intermediate values are a linear interpolation be-

tween minimum and maximum amplitude values. T he least

significant byte of the 16-bit internal data is truncated to create

the 8-bit output samples.

AP P LICATIO NS CIRCUITS

T he AD1847 Stereo Codec has been designed to require a mini-

mum of external circuitry. T he recommended circuits are shown

in Figures 14 through 22. Analog Devices estimates that the to-

tal cost of all the components shown in these Figures, including

crystals, to be less than $3 in 10,000 quantities.

Industry-standard compact disc “line-levels” are 2 V_rmscentered

around analog ground. (For other audio equipment, “line level”

is much more loosely defined.) T he AD1847 SoundPort is a

+5 V only powered device. Line level voltage swings for the

AD1847 are defined to be 1 V_rmsfor a sine wave ADC input and

0.707 V_rmsfor a sine wave DAC output. T hus, 2 V_rmsinput ana-

log signals must be attenuated and either centered around the

reference voltage intermediate between 0 V and +5 V or

MAX

ac-coupled. T he V_REFpin will be at this intermediate voltage,

nominally 2.25 V. It has limited drive but can be used as a volt-

age datum to an op amp input. Note, however, that dc-coupled

inputs are not recommended, as they provide no performance

benefits with the AD1847 architecture. Furthermore, dc offset

differences between multiple dc-coupled inputs create the po-

tential for “clicks” when changing the input mux selection.

MIN

00h

7Fh

FFh

DIGITAL VALUE

Figure 12. 8-Bit Unsigned Form at

REV. B

–23–

AD1847

Circuits for 2 V_rmsline-level inputs and auxiliaries are shown in

Figure 14 and Figure 15. Note that these are divide-by-two

resistive dividers. T he input resistor and 560 pF (1000 pF)

capacitor provide the single-pole of antialias filtering required

for the ADCs. If line-level inputs are already at the 1 V_rmslevels

expected by the AD1847, the resistors in parallel with the

560 pF (1000 pF) capacitors can be omitted. If the application

does not route the AUX2 inputs to the ADCs, then no antialias

filtering is required (only the 1 µF ac coupling capacitor).

Figure 17 shows ac-coupled line outputs. T he resistors are

used to center the output signals around analog ground. If

dc-coupling is desired, V_REFcould be used with op amps as

mentioned previously.

1µF

L_OUT

47k

1µF

R_OUT

0.33 µF

5.1k

L_LINE1

L_LINE2

47k

560pF

5.1k

NPO

Figure 17. Line Output Connections

0.33 µF

5.1k

R_LINE1

R_LINE2

A circuit for headphone drive is illustrated in Figure 18. Drive is

supplied by +5 V operational amps. T he circuit shown ac

couples the headphones to the line output.

560pF

5.1k

NPO

18k

20k

470µF

L_OUT

Figure 14. 2 V_{rm s}Line-Level Input Circuit for Line Inputs

HEADPHONE

LEFT

V

SSM2135

18k

REF

1µF

3.3k

L_AUX1

L_AUX2

20k

HEADPHONE

RIGHT

R_OUT

1000pF

4.3k

NPO

1µF

3.3k

R_AUX1

Figure 18. Headphone Drive Connections

R_AUX2

1000pF

4.3k

Figure 19 illustrates reference bypassing. V_REFIshould only be

connected to its bypass capacitors.

NPO

V

REF

REFI

0.1µF

10µF

Figure 15. 2 V_rmsLine-Level Input Circuit for AUX Inputs

Figure 16 illustrates one example of how an electret condenser

microphone requiring phantom power could be connected to

the AD1847. V_REFis shown buffered by an op amp; a transistor

like a 2N4124 will also work well for this purpose. Note that if a

battery-powered microphone is used, the buffer and R2s are not

needed. T he values of R1, R2, and C should be chosen in light

of the mic characteristics and intended gain. T ypical values for

these might be R1 = 20 kΩ, R2 = 2 kΩ, and C = 220 pF.

Figure 19. Voltage Reference Bypassing

Figure 20 illustrates signal-path filtering capacitors, L_FILT

and R_FILT . T he AD1847 must use 1.0 µF capacitors. T he

1.0 µF capacitors required by the AD1847 can be of any type.

LFILT

RFILT

C

1.0µF

R1

1µF

5k

0.33µF

L_LINE1

L_LINE2

Figure 20. External Filter Capacitor Connections

1/2 SSM2135

OR AD820

R2

LEFT

V_REF

ELECTRET

CONDENSER

MICROPHONE

INPUT

1/2 SSM2135

OR AD820

C

R2

R1

1µF

5k

0.33µF

RIGHT

ELECTRET

CONDENSER

MICROPHONE

INPUT

R_LINE1

R_LINE2

1/2 SSM2135

OR AD820

V_REF

Figure 16. “Phantom -Powered” Microphone Input Circuit

–24–

REV. B

AD1847

T he crystals shown in the crystal connection circuitry of Figure

21 should be fundamental-mode and parallel-tuned. T wo

sources for the exact crystals specified are Component Market-

ing Services in Massachusetts, U.S. at 617/762-4339 and

Cardinal Components in New Jersey, U.S. at 201/746-0333.

Note that using the exact data sheet frequencies is not required

and that external clock sources can be used to overdrive the

AD1847s internal oscillators. (See the description of the CFS2:0

control bits above.) If using an external clock source, apply it to

the crystal input pins while leaving the crystal output pins un-

connected. Attention should be paid to providing low-jitter ex-

ternal input clocks .

Analog Devices recommends a split ground plane as shown in

Figure 23. T he analog plane and the digital plane are connected

directly under the AD1847. Splitting the ground plane directly

under the SoundPort Codec is optimal because analog pins will

be located directly above the analog ground plane and digital

pins will be located directly above the digital ground plane for

the best isolation. T he digital and analog grounds should be tied

together in the vicinity of the AD1847. Other schemes may also

yield satisfactory results. If the split ground plane recommended

here is not possible, the AD1847 should be entirely over the

analog ground plane with the ASIC and DSP over the digital

plane.

XTAL1I

XTAL1O

XTAL2I

XTAL2O

DIGITAL

GROUND

PLANE

ANALOG

GROUND

PLANE

BM

L_AUX2

20 64pF

24.576MHz

16.9344MHz

AD1847

Figure 21. Crystal Connections

Analog Devices also recommends a pull-down resistor on the

PWRDOWN signal.

V

PWRDOWN

CC

Good, standard engineering practices should be applied for

power-supply decoupling. Decoupling capacitors should be

placed as close as possible to package pins. If a separate analog

power supply is not available, the circuit shown in Figure 22 is

recommended when using a single +5 V supply. Ferrite beads

suffice for the inductors shown. T his circuitry should be as close

to the supply pins as is practical.

Figure 23. Recom m ended Ground Plane

FERRITE

+5V SUPPLY

1µF

0.1µF

V

DD

1.6

FERRITE

1µF

0.1µF

1µF

0.1µF

V

CC

Figure 22. Recom m ended Power Supply Bypassing

REV. B

–25–

AD1847

FREQ UENCY RESP O NSE P LO TS

10

0

10

0

–10

–20

–30

–40

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

–110

–120

–50

dB

–60

–70

–80

–90

–100

–110

–120

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

SAMPLE FREQUENCY – F

S

Figure 24. AD1847 Analog-to-Digital Frequency Response

(Full-Scale Line-Level Inputs, 0 dB Gain)

Figure 26. AD1847 Digital-to-Analog Frequency Response

(Full-Scale Inputs, 0 dB Attenuation)

10

0

10

0

–10

–20

–30

–40

–10

–20

–30

–40

–50

dB

–50

dB

–60

–70

–80

–90

–80

–90

–100

–110

–120

–110

–120

0.40

0.44

0.48

0.52

0.56

0.60

0.64

0.68 0.70

0.40

0.44

0.48

0.52

0.56

0.60

0.64

0.68 0.70

SAMPLE FREQUENCY – F

SAMPLE FREQUENCY – F_S

S

Figure 25. AD1847 Analog-to-Digital Frequency Response

–Transition Band (Full-Scale Line-Level Inputs, 0 dB Gain)

Figure 27. AD1847 Digital-to-Analog Frequency Response

–Transition Band (Full-Scale Inputs, 0 dB Attenuation)

–26–

REV. B

AD1847

t_RPWL

RESET

PWRDOWN

SCLK

SDFS

Figure 30. Reset and Power Down Tim ing Diagram

t_S

t_PD1

t_H

TIME

SLOT 0

SLOT 1

SLOT 2

BIT 15

BIT 0

t_HZ

BIT 0

BIT 14

t_DV

SDI

SCLK

SDO

BIT 14

BIT 15

SDFS

SDI/

Figure 28. Tim e Slot Tim ing Diagram

LEFT

RIGHT

CONTROL

STATUS

PLAYBACK

16-BIT

STEREO

LEFT

CAPTURE

RIGHT

PLAYBACK

SCLK

SDFS

SDO

LEFT

CONTROL

STATUS

SDI/

PLAYBACK

16-BIT

MONO

LEFT

CAPTURE

LEFT

CAPTURE

SDO

t

PD1

SDI or

SDO

15 14 13

3 2 1 0 15 14 13

LEFT

PB

RIGHT

PB

CONTROL

STATUS

SDI/

8-BIT

STEREO

LEFT

0

RIGHT

0

SDO

CAP

LAST VALID TIME SLOT

TSO

LEFT

PB

CONTROL

STATUS

SDI/

8-BIT

MONO

t

PD2

LEFT

0

LEFT

0

SDO

CAP

Figure 29. TSO Tim ing Diagram

Figure 31. Serial Data Form at, 2-Wire System (TSSEL = 1)

TIME

SLOT 0

SLOT 1

SLOT 2

SLOT 3

SLOT 4

SLOT 5

SCLK

SDFS

16-BIT

STEREO

SDI/

SDO

CONTROL

LEFT

RIGHT

STATUS

LEFT

RIGHT

LEFT

SDI/

16-BIT

SDO MONO

SDI/

SDO STEREO

8-BIT

LEFT

0

RIGHT

0

8-BIT

MONO

SDI/

SDO

CONTROL

STATUS

LEFT

CAPTURE

PLAYBACK

Figure 32. Serial Data Form at, 1-Wire System (TSSEL = 0)

REV. B

–27–

AD1847

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

IND E X

P AG E

PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . 1

AD1847 SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . . . 2

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PINOUT S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

PIN DESCRIPT IONS . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

AUDIO FUNCT IONAL DESCRIPT ION . . . . . . . . . . . 7

Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Analog Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . 7

Digital-to-Analog Datapath . . . . . . . . . . . . . . . . . . . . . 7

Digital Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Digital Data T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Power Supplies and Voltage Reference . . . . . . . . . . . . . 8

Clocks and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . 8

CONT ROL REGIST ERS . . . . . . . . . . . . . . . . . . . . . . . . 9

Control Register Mapping . . . . . . . . . . . . . . . . . . . . . . 9

Control Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Left/Right Playback/Capture Data . . . . . . . . . . . . . . . 10

Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . : 11

Index Readback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Indirect Mapped Registers . . . . . . . . . . . . . . . . . . . . . 12

Left Input Control Register . . . . . . . . . . . . . . . . . . . . 13

Right Input Control Register . . . . . . . . . . . . . . . . . . . 13

Left Auxiliary # 1 Input Control Register . . . . . . . . . . 13

Right Auxiliary # 1 Input Control Register . . . . . . . . . 13

Left Auxiliary # 2 Input Control Register . . . . . . . . . . 14

Right Auxiliary # 2 Input Control Register . . . . . . . . . 14

Left DAC Control Register . . . . . . . . . . . . . . . . . . . . . 14

Right DAC Control Register . . . . . . . . . . . . . . . . . . . . 14

Data Format Register . . . . . . . . . . . . . . . . . . . . . . . . . 15

Interface Configuration Register . . . . . . . . . . . . . . . . . 16

Pin Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Invalid Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Miscellaneous Information Register . . . . . . . . . . . . . . 17

Digital Mix Control Register . . . . . . . . . . . . . . . . . . . 17

Invalid Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Serial Data Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Control Register Mapping Summary . . . . . . . . . . . . . 20

Daisy-Chained Multiple Codecs . . . . . . . . . . . . . . . . . 20

INIT IALIZAT ION AND PROCEDURES . . . . . . . . . . 21

Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . 21

Clock Connections and Clock Rates . . . . . . . . . . . . . . 21

Mode Change Enable State . . . . . . . . . . . . . . . . . . . . 22

Digital Mix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Changing Sample Rates . . . . . . . . . . . . . . . . . . . . . . . 22

DAT A FORMAT DEFINIT IONS . . . . . . . . . . . . . . . . 23

16-Bit Signed Format . . . . . . . . . . . . . . . . . . . . . . . . . 23

8-Bit Unsigned Format . . . . . . . . . . . . . . . . . . . . . . . . 23

8-Bit Companded Formats . . . . . . . . . . . . . . . . . . . . . 23

APPLICAT IONS CIRCUIT S . . . . . . . . . . . . . . . . . . . . 23

FREQUENCY RESPONSE PLOT S . . . . . . . . . . . . . . . 26

T IMING DIAGRAMS . . . . . . . . . . . . . . . . . . . . . . . . . 27

OUT LINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . 28

44-Lead P LCC

(P -44A)

0.180 (4.57)

0.165 (4.19)

0.048 (1.21)

0.042 (1.07)

0.056 (1.42)

0.042 (1.07)

0.025 (0.63)

0.015 (0.38)

6

40

39

7

0.048 (1.21)

PIN 1

0.021 (0.53)

0.013 (0.33)

IDENTIFIER

0.042 (1.07)

0.63 (16.00)

0.59 (14.99)

0.032 (0.81)

TOP VIEW

0.026 (0.66)

0.050

(1.27)

BSC

29

28

17

18

0.020

(0.50)

R

0.040 (1.01)

0.025 (0.64)

0.656 (16.66)

0.650 (16.51)

SQ

0.110 (2.79)

0.085 (2.16)

0.695 (17.65)

0.685 (17.40)

44-Ter m inal P lastic Thin Q uad Flatpack (TQ FP )

(ST-44)

0.063 (1.60)

MAX

0.472 (12.00) SQ

0.030 (0.75)

0.018 (0.45)

33

23

34

22

SEATING

PLANE

0.394

(10.0)

SQ

TOP VIEW

(PINS DOWN)

44

12

1

11

0.006 (0.15)

0.002 (0.05)

0.018 (0.45)

0.012 (0.30)

0.031 (0.80)

BSC

0.057 (1.45)

0.053 (1.35)

All brand or product names mentioned are trademarks or regis-

tered trademarks of their respective holders.

–28–

REV. B


型号：	AD1847JST
厂家：	ADI
描述：	Serial-Port 16-Bit SoundPort Stereo Codec 串行端口16位SoundPort立体声编解码器解码器编解码器
文件：	总28页 (文件大小：313K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD1847JST [ADI]

相关型号：

AD1848

AD1848K

AD1848KP

AD1848KST

AD1848XP

AD1849

AD1849K

AD1849KP

AD1849KP-REEL

AD1849KPZ

AD1849KST

AD1851