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AD1848 [ADI]

Parallel-Port 16-Bit SoundPort Stereo Codec; 并口16位SoundPort立体声编解码器
AD1848
型号： AD1848
厂家： ADI    ADI
描述：

Parallel-Port 16-Bit SoundPort Stereo Codec
并口16位SoundPort立体声编解码器

解码器 编解码器
文件： 总28页 (文件大小：323K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
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Parallel-Port 16-Bit  
SoundPort Stereo Codec  
a
AD1848K  
supply. It provides a direct, byte-wide interface to both ISA  
(“AT ”) and EISA computer buses for simplified implementa-  
tion on a computer motherboard or add-in card. T he AD1848K  
generates enable and direction controls for IC buffers such as  
74_245.  
FEATURES  
Single-Chip Integrated ∑∆ Digital Audio Stereo Codec  
Supports the Microsoft Window s Sound System ®  
Multiple Channels of Stereo Input  
Analog and Digital Signal Mixing  
Program m able Gain and Attenuation  
On-Chip Signal Filters  
T he AD1848K SoundPort Stereo Codec supports a DMA re-  
quest/grant architecture for transferring data with the host com-  
puter bus. One or two DMA channels can be supported.  
Programmed I/O (PIO) mode is also supported for control  
register accesses and for applications lacking DMA control. T wo  
input control lines support mixed direct and indirect addressing  
of twenty-one internal control registers over this asynchronous  
interface.  
Digital Interpolation  
Analog Output Low -Pass  
Sam ple Rates from 5.5 kHz to 48 kHz  
68-Lead PLCC and 68-Lead TQFP Packages  
Operation from +5 V Supplies  
Byte-Wide Parallel Interface to ISA and EISA Buses  
Supports One or Tw o DMA Channels and  
Program m ed I/ O  
External circuit requirements are limited to a minimal number  
of low cost support components. Anti-imaging DAC output fil-  
ters are incorporated on-chip. Dynamic range exceeds 80 dB  
over the 20 kHz audio band. Sample rates from 5.5 kHz to  
48 kHz are supported from external crystals.  
P RO D UCT O VERVIEW  
T he Parallel-Port AD1848K SoundPort® Stereo Codec inte-  
grates the key audio data conversion and control functions into  
a single integrated circuit. T he AD1848K is intended to provide  
a complete, single-chip audio solution for business audio and  
multimedia applications requiring operation from a single +5 V  
T he Codec includes a stereo pair of ∑∆ analog-to-digital  
converters and a stereo pair of ∑∆ digital-to-analog converters.  
Inputs to the ADC can be selected from four stereo pairs of  
SoundPort is a registered trademark of Analog Devices, Inc.  
(Continued on page 9)  
FUNCTIO NAL BLO CK D IAGRAM  
DIGITAL  
SUPPLY  
ANALOG  
SUPPLY  
CRYSTALS  
POWER DOWN  
2
2
ANALOG  
DIGITAL  
L_LINE  
R_LINE  
OSCILLATORS  
L
PLAYBACK REQ  
PLAYBACK ACK  
CAPTURE REQ  
16  
16  
∑∆ A/D  
µ/  
A
L
A
W
GAIN  
GAIN  
CONVERTER  
20  
dB  
L_MIC  
R_MIC  
P
A
R
A
L
L
E
L
MUX  
R
∑∆ A/D  
CONVERTER  
L_AUX1  
R_AUX1  
CAPTURE ACK  
2
ADR1:0  
DATA7:0  
CS  
DIGITAL  
MIX  
8
GAIN/ATTEN/MUTE  
L
P
∑∆ D/A  
CONVERTER  
O
R
T
ATTEN/  
ANALOG  
FILTER  
µ/  
A
L
∑
L_OUT  
R_OUT  
∑
INTERPOL  
ATTENUATE  
ATTENUATE  
WR  
RD  
MUTE  
R
A
W
BUS DRIVER  
CONTROL  
2
∑∆ D/A  
CONVERTER  
ATTEN/  
MUTE  
ANALOG  
FILTER  
∑
INTERPOL  
∑
HOST DMA  
INTERRUPT  
L_AUX2  
R_AUX2  
CONTROL  
REGS  
REFERENCE  
2.25V  
GAIN/ATTEN/MUTE  
2
EXTERNAL  
CONTROL  
REV. 0  
Inform ation furnished by Analog Devices is believed to be accurate and  
reliable. However, no responsibility is assum ed by Analog Devices for its  
use, nor for any infringem ents of patents or other rights of third parties  
which m ay result from its use. No license is granted by im plication or  
otherwise under any patent or patent rights of Analog Devices.  
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.  
Tel: 617/ 329-4700 Fax: 617/ 326-8703  
AD1848K–SPECIFICATIONS  
STAND ARD TEST CO ND ITIO NS UNLESS  
O TH ERWISE NO TED  
DAC Input Conditions  
Post-Autocalibrated  
0 dB Attenuation  
T emperature  
25  
5.0  
°C  
V
Digital Supply (VDD  
Analog Supply (VCC  
Word Rate (FS)  
Input Signal  
)
)
–2.0 dB Relative to Full Scale  
16-Bit Linear Mode  
No Output Load  
5.0  
V
48  
1008  
kHz  
Hz  
Mute Off  
Analog Output Passband  
ADC FFT Size  
DAC FFT Size  
VIH  
VIL  
20 Hz to 20 kHz  
ADC Input Conditions  
Post-Autocalibrated  
0 dB Gain  
2048  
8192  
2.4  
0.8  
2.4  
V
V
V
V
–3.0 dB Relative to Full Scale  
Line Input  
16-Bit Linear Mode  
VOH  
VOL  
0.4  
ANALO G INP UT  
Min  
Typ  
Max  
Units  
Input Voltage (RMS Values Assume Sine Wave Input)  
Line  
1
V rms  
V p-p  
V rms  
V p-p  
V rms  
V p-p  
kΩ  
2.6  
2.8  
0.1  
0.28  
1
3.0  
0.3  
3.0  
15  
Mic with +20 dB Gain (MGE = 1)  
Mic with 0 dB Gain (MGE = 0)  
0.26  
2.6  
20  
2.8  
Input Impedance  
Input Capacitance  
pF  
P RO GRAMMABLE GAIN AMP LIFIER—AD C  
Min  
Typ  
Max  
Units  
Step Size (0 dB to 22.5 dB)  
(All Steps T ested, –30 dB Input)  
PGA Gain Range Span*  
1.3  
1.5  
1.7  
dB  
21.5  
22.5  
23.5  
dB  
AUXILIARY INP UT ANALO G AMP LIFIERS/ATTENUATO RS  
Min  
Typ  
Max  
Units  
Step Size (+12.0 dB to –33.0 dB)  
(All Steps T ested, –14.5 dB Input)  
Auxiliary Gain/Attenuation Range Span*  
1.3  
1.5  
1.7  
dB  
45.5  
46.5  
47.5  
dB  
–2–  
REV. 0  
AD1848K  
D IGITAL D ECIMATIO N AND INTERP O LATIO N FILTERS*  
Min  
Max  
Units  
Passband  
0
0.45 
؋
 FS  
±0.1  
0.55 
؋
 FS  
∞
Hz  
dB  
Hz  
Hz  
dB  
Passband Ripple  
T ransition Band  
Stopband  
Stopband Rejection  
Group Delay  
0.45 
؋
 FS  
0.55 
؋
 FS  
74  
30/FS  
0.0  
Group Delay Variation Over Passband  
µs  
ANALO G-TO -D IGITAL CO NVERTERS  
Min  
Typ  
Max  
Units  
Resolution (No Missing Codes from  
±10 LSB Ramp Around Midscale)*  
Dynamic Range (–60 dB Input,  
16  
86  
Bits  
80  
dB  
T HD+N Referenced to Full Scale)  
T HD+N (Referenced to Full Scale)  
0.022  
–73  
90  
%
dB  
dB  
–77  
Signal-to-Intermodulation Distortion*  
ADC Crosstalk*  
Line Inputs (Input L, Ground R, Read R;  
Input R, Ground L, Read L)  
Line to MIC (Input LINE, Ground and  
Select MIC, Read Both Channels)  
Line to AUX1  
–80  
–80  
dB  
dB  
–80  
–80  
±5  
dB  
dB  
%
Line to AUX2  
Gain Error (Full-Scale Span Relative to Nominal)  
Interchannel Gain Mismatch  
(Difference of Gain Errors)  
±0.5  
dB  
ADC Offset Error  
50  
LSBs  
D IGITAL-TO -ANALO G CO NVERTERS  
Min  
Typ  
Max  
Units  
Resolution*  
16  
87  
Bits  
dB  
Dynamic Range (–60 dB Input,  
T HD+N Referenced to Full Scale)  
T HD+N (Referenced to Full Scale)  
80  
0.02  
–74  
90  
±5  
±0.5  
%
–76  
dB  
dB  
%
Signal-to-Intermodulation Distortion*  
Gain Error (Full-Scale Span Relative to Nominal)  
Interchannel Gain Mismatch  
dB  
(Difference of Gain Errors)  
DAC Crosstalk* (Input L, Zero R, Measure  
R_OUT ; Input R, Zero L, Measure L_OUT )  
T otal Out-of-Band Energy*  
(Measured from 0.55 × FS to 100 kHz)  
Audible Out-of-Band Energy*  
–80  
–45  
–70  
dB  
dB  
dB  
(Measured from 0.55 × FS to 22 kHz,  
All Selectable Sampling Frequencies)  
*Guaranteed Not T ested.  
Specifications subject to change without notice.  
REV. 0  
–3–  
AD1848K  
D AC ATTENUATO R  
Min  
Typ  
Max  
Units  
Step Size (0 dB to –34.5 dB)  
Step Size (–60 dB to –94.5 dB)*  
Output Attenuation Range Span*  
1.3  
1.0  
93.5  
1.5  
1.5  
94.5  
1.7  
2.0  
95.5  
dB  
dB  
dB  
ANALO G O UTP UT  
Min  
Typ  
Max  
Units  
Full-Scale Output Voltage  
0.707  
2.0  
Vrms  
V p-p  
Ω
kΩ  
pF  
pF  
V
µA  
kΩ  
dB  
1.85  
10  
2.1  
600  
Output Impedance  
External Load Impedance  
Output Capacitance  
External Load Capacitance  
VREF  
15  
100  
2.40  
2.10  
2.25  
100  
4
VREF Current Drive  
VREF Output Impedance  
Mute Attenuation of 0 dB  
Fundamental* (OUT )  
Mute Click  
–80  
5
mV  
(| Muted Output Minus Unmuted  
Midscale DAC Output| )  
SYSTEM SP ECIFICATIO NS  
Min  
Typ  
Max  
Units  
Peak-to-Peak Frequency Response Ripple*  
(Line In to Line Out)  
1.0  
dB  
Differential Nonlinearity*  
±1  
Bit  
Phase Linearity Deviation*  
5
Degrees  
STATIC D IGITAL SP ECIFICATIO NS  
Min  
Max  
Units  
High Level Input Voltage (VIH  
Digital Inputs  
XT AL1/2I  
)
2.4  
2.4  
–0.3  
2.4  
(VD+) + 0 3  
(VD+) + 0 3  
0.8  
V
V
V
V
V
µA  
Low Level Input Voltage (VIL)  
High Level Output Voltage (VOH) at IOH = –2 mA  
Low Level Output Voltage (VOL) at IOL = 2 mA  
Input Leakage Current  
(GO/NOGO T ested)  
Output Leakage Current  
0.4  
10  
–10  
–10  
10  
µA  
(GO/NOGO T ested)  
–4–  
REV. 0  
AD1848K  
TIMING P ARAMETERS (GUARANTEED O VER O P ERATING TEMP ERATURE RANGE AND VD D = VCC = 5.0 V ؎5%)  
Min  
Max  
Units  
WR/RD Strobe Width (tST W  
WR/RD Rising to WR/RD Falling (tBWND  
Write Data Setup to WR Rising (tWDSU  
)
110  
110  
22  
30  
10  
0
10  
10  
60  
0
25  
0
15  
0
50  
50  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
)
)
RD Falling to Valid Read Data (tRDDV  
)
70  
CS Setup to WR/RD Falling (tCSSU  
CS Hold from WR/RD Rising (tCSHD  
Adr Setup to WR/RD Falling (tADSU  
Adr Hold from WR/RD Rising (tADHD  
)
)
)
)
DAK Rising to WR/RD Falling (tSUDK1  
DAK Falling to WR/RD Rising (tSUDK2  
)
)
DAK Setup to WR/RD Falling (tDKSU  
Data Hold from RD Rising (tDHD1  
Data Hold from WR Rising (tDHD2  
DRQ Hold from WR/RD Falling (tDRHD  
DAK Hold from WR Rising (tDKHDa  
DAK Hold from RD Rising (tDKHDb  
)
)
)
20  
25  
)
)
)
DBEN/DBDIR delay from WR/RD Falling (tDBDL  
)
30  
P O WER SUP P LY  
Min  
Max  
Units  
Power Supply Range – Analog  
Power Supply Range – 5 V Digital  
Power Supply Current – 5 V Operating  
(5 V Supplies, 10 kΩ Load)  
4.75  
4.75  
5.25  
5.25  
120  
V
V
mA  
Analog Supply Current – 5 V Operating (10 kΩ Load)  
Digital Supply Current – 5 V Operating (10 kΩ Load)  
Digital Power Supply Current – Power Down  
Analog Power Supply Current – Power Down  
Power Dissipation – 5 V Operating  
65  
55  
1
1
600  
mA  
mA  
mA  
mA  
mW  
(Current • Nominal Supplies)  
Power Dissipation – Power Down  
(Current • Nominal Supplies)  
10  
mW  
Power Supply Rejection (100 mV p-p Signal @ 1 kHz)*  
(At Both Analog and Digital Supply Pins, Both ADCs  
and DACs)  
40  
dB FS  
CLO CK SP ECIFICATIO NS*  
Min  
Max  
Units  
Input Clock Frequency  
Recommended Clock Duty Cycle T olerance  
Initialization T ime  
27  
±10  
MHz  
%
16.9344 MHz Crystal Selected  
24.576 MHz Crystal Selected  
70  
90  
ms  
ms  
*Guaranteed, not tested  
Specifications subject to change without notice.  
REV. 0  
–5–  
AD1848K  
O RD ERING GUID E  
ABSO LUTE MAXIMUM RATINGS*  
Min Max  
Units  
Tem perature  
Range  
P ackage  
D escription  
P ackage  
O ption  
Power Supplies  
Model  
Digital (VDD  
Analog (VCC  
)
)
–0.3 6.0  
–0.3 6.0  
V
V
AD1848KP  
AD1848KST  
–40°C to +85°C 68-Lead PLCC P-68A  
–40°C to +85°C 64-Lead T QFP ST -64  
Input Current  
(Except Supply Pins)  
±10.0  
mA  
V
V
°C  
°C  
Analog Input Voltage (Signal Pins) –0.3 (VA+) + 0.3  
Digital Input Voltage (Signal Pins) –0.3 (VD+) + 0.3  
Ambient T emperature (Operating) –40 +85  
Storage T emperature  
–65 +150  
ESD T olerance (Human Body  
Model per Method 3015.2  
of MIL-ST D-883B)  
1000  
V
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause  
permanent damage to the device. T his is a stress rating only and functional  
operation of the device at these or any other conditions above those indicated in  
the operational section of this specification is not implied. Exposure to absolute  
maximum rating conditions for extended periods may affect device reliability.  
CAUTIO N  
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily  
accumulate on the human body and test equipment and can discharge without detection.  
Although the AD1848K features proprietary ESD protection circuitry, permanent damage may  
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD  
precautions are recommended to avoid performance degradation or loss of functionality.  
WARNING!  
ESD SENSITIVE DEVICE  
68-Lead P lastic Leaded Chip Carrier P inout  
64-Lead Thin Quad Flatpack P inout  
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49  
9
8
7
6
5
4
3
2
1
68 67 66 65 64 63 62 61  
10  
60 RD  
59 CS  
ADR0  
ADR0  
CDAK  
CDRQ  
PDAK  
PDRQ  
1
2
3
48  
WR  
CDAK 11  
47 RD  
46 CS  
12  
XCTL1  
58  
CDRQ  
13  
57 INT  
56  
PDAK  
4
5
45  
XCTL1  
PDRQ 14  
V
XCTL0  
44 INT  
43 XCTL0  
42 NC  
V
55  
54  
15  
16  
17  
18  
NC  
V
DD  
V
6
7
DD  
GNDD  
DD  
GNDD  
XTAL1I  
XTAL1O  
53  
AD1848K  
TOP VIEW  
GNDD  
XTAL1I  
8
41  
DD  
AD1848K  
TOP VIEW  
XTAL1O  
52 NC  
51  
50 NC  
49  
48 NC  
9
40 GNDD  
V
NC  
19  
20  
21  
22  
V
DD  
10  
11  
NC  
NC  
NC  
V
39  
38  
37  
36  
35  
DD  
GNDD  
XTAL2I  
XTAL2O  
GNDD  
NC  
XTAL2I 12  
XTAL2O  
13  
DD  
47  
46  
45  
44  
PWRDWN 23  
NC  
NC  
PWRDWN  
14  
GNDD  
V
24  
25  
26  
DD  
GNDD  
R_FILT  
V
15  
16  
34 R_AUX2  
33  
DD  
V
DD  
GNDD  
R_AUX1  
GNDD  
40 41 42 43  
27 28 29 30 31 32 33 34 35 36 37 38 39  
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
NC = NO CONNECT  
NC = NO CONNECT  
–6–  
REV. 0  
AD1848K  
P IN D ESCRIP TIO N  
P ar allel Inter face  
P in Nam e  
P LCC  
TQFP  
I/O  
D escription  
CDRQ  
12  
3
O
Capture Data Request. T he assertion of this signal indicates that the Codec has a cap-  
tured audio sample from the ADC ready for transfer. T his signal will remain asserted un-  
til all the bytes from the capture buffer have been transferred.  
CDAK  
11  
14  
2
5
I
Capture Data Acknowledge. T he assertion of this active LO signal indicates that the RD  
cycle occurring is a DMA read from the capture buffer.  
PDRQ  
O
Playback Data Request. T he assertion of this signal indicates that the Codec is ready for  
more DAC playback data. T he signal will remain asserted until all the bytes needed for a  
playback sample have been transferred.  
PDAK  
13  
4
I
I
Playback Data Acknowledge. T he assertion of this active LO signal indicates that the WR  
cycle occurring is a DMA write to the playback buffer.  
ADR1:0  
9 & 10  
1 & 64  
Codec Addresses. T hese address pins are asserted by the Codec interface logic during a  
control register/PIO access. T he state of these address lines determine which register is  
accessed.  
RD  
WR  
60  
61  
59  
47  
48  
46  
I
I
I
Read Command Strobe. T his active LO signal defines a read cycle from the Codec. T he  
cycle may be a read from the control/PIO registers, or the cycles could be a read from the  
Codec’s DMA sample registers.  
Write Command Strobe. T his active LO signal indicates a write cycle to the Codec. T he  
cycle may be a write to the control/PIO registers, or the cycle could be a write to the  
Codec’s DMA sample registers.  
CS  
AD1848K Chip Select. T he Codec will not respond to any control/PIO cycle accesses  
unless this active LO signal is LO. T his signal is ignored during DMA transfers.  
DAT A7:0  
DBEN  
3–6 &  
65–68  
52–55 & I/O  
58–61  
Data Bus. T hese pins transfer data and control information between the Codec and the  
host.  
63  
50  
O
Data Bus Enable. T his pin enables the external bus drivers. T his signal is normally HI.  
For control register/PIO cycles,  
DBEN = (WR or RD) and CS  
For DMA cycles,  
DBEN = (WR or RD) and (PDAK or CDAK)  
DBDIR  
62  
49  
O
Data Bus Direction. T his pin controls the direction of the data bus transceiver. HI  
enables writes from the host to the AD1848K; LO enables reads from the AD1848K to  
the host bus. T his signal is normally HI.  
For control register/PIO cycles,  
DBDIR = RD and CS  
For DMA cycles,  
DBDIR = RD and (PDAK or CDAK)  
REV. 0  
–7–  
AD1848K  
Analog Signals  
P in Nam e  
P LCC  
TQFP  
I/O  
D escription  
L_LINE  
R_LINE  
L_MIC  
30  
27  
29  
21  
18  
20  
I
I
I
Left Line Input. Line level input for the left channel.  
Right Line Input. Line level input for the right channel.  
Left Microphone Input. Microphone input for the left channel. T his signal  
can be either line level or –20 dB from line level.  
R_MIC  
28  
19  
I
Right Microphone Input. Microphone input for the right channel. T his  
signal can be either line level or –20 dB from line level.  
L_AUX1  
R_AUX1  
L_AUX2  
R_AUX2  
L_OUT  
39  
42  
38  
43  
40  
41  
30  
33  
29  
34  
31  
32  
I
Left Auxiliary # 1 Line Input  
Right Auxiliary # 1 Line Input  
Left Auxiliary # 2 Line Input  
Right Auxiliary # 2 Line Input  
Left Line Level Output  
I
I
I
O
O
R_OUT  
Right Line Level Output  
Miscellaneous  
P in Nam e  
P LCC  
TQFP  
I/O  
D escription  
XT AL1I  
17  
18  
21  
22  
23  
8
I
24.576 MHz Crystal # 1 Input  
24.576 MHz Crystal # 1 Output  
16.9344 MHz Crystal # 2 Input  
16.9344 MHz Crystal # 2 Output  
XT AL1O  
XT AL2I  
9
O
I
12  
13  
14  
XT AL2O  
PWRDWN  
O
I
Power-Down Signal. Active LO control places AD1848K in its lowest  
power consumption mode. All sections of the AD1848K, including the  
digital interface, are shut down and consume minimal power.  
INT  
57  
44  
O
O
Host Interrupt Pin. T his signal is used to notify the host that the DMA  
Current Count Register has underflowed.  
XCT L1:O  
56 & 58  
43 & 45  
External Control. T hese signals reflect the current status of register bits  
inside the AD1848K. T hey can be used for signaling or to control external  
logic.  
VREF  
32  
23  
O
Voltage Reference. Nominal 2.25 volt reference available for dc-coupling  
and level-shifting. VREF should not be used where it will sink or source  
current.  
V
REF_F  
33  
24  
I
I
I
Voltage Reference Filter. Voltage reference filter point for external  
bypassing only.  
L_FILT  
R_FILT  
N/C  
31  
22  
Left Channel Filter Input. T his pin requires a 1.0 µF capacitor to analog  
ground for proper operation.  
26  
17  
Right Channel Filter Input. T his pin requires a 1.0 µF capacitor to analog  
ground for proper operation.  
46–52, 55  
37–39, 42  
No Connect. Do not connect.  
P ower Supplies  
P in Nam e  
P LCC  
TQFP  
I/O  
D escription  
VCC  
35 & 36  
34 & 37  
26 & 27  
25 & 28  
I
I
I
Analog Supply Voltage (+5 V)  
Analog Ground  
GNDA  
VDD  
1, 7, 15, 19,  
24, 45, 54  
6, 10, 15, 36,  
41, 56  
Digital Supply Voltage (+5 V)  
GNDD  
2, 8, 16, 20,  
25, 44, 53, 64  
7, 11, 16, 35,  
40, 51, 63  
I
Digital Ground  
–8–  
REV. 0  
AD1848K  
(Continued from page 1)  
+20 dB prior to the PGA to compensate for the voltage swing  
difference between line levels and typical condenser micro-  
phones. Alternatively, the mic inputs can bypass the +20 dB  
fixed gain block and go straight to the input multiplexer.  
analog signals: line, microphone (“mic”), auxiliary (“aux”) # 1,  
and post-mixed DAC output. T he microphone inputs can pass  
through optional 20 dB gain blocks. A software-controlled pro-  
grammable gain stage allows independent gain for each channel  
going into the ADC. T he ADCs’ output can be digitally mixed  
with the DACs’ input.  
T he PGA following the input multiplexer allows independent se-  
lectable gains for each channel from 0 to 22.5 dB in +1.5 dB  
steps. T he Codec can operate either in a global stereo mode or  
in a global mono mode with left channel inputs appearing at  
both channel outputs.  
ADDRESS  
DECODE  
AEN  
18  
AD1848K  
CS  
Analog Mixing  
SA19:2  
A1  
AUX1 and AUX2 analog stereo signals can be mixed in the ana-  
log domain with the DAC output. Each channel of each auxil-  
iary analog input can be independently gained/attenuated from  
+12 dB to –34.5 dB in –1.5 dB steps or completely muted. T he  
post mixed DAC output is available on OUT externally and as  
an input to the ADCs.  
SA1  
A0  
SA0  
WR  
IOWC  
RD  
IORC  
7
4
8
8
DATA7:0  
DBDIR  
DBEN  
DATA7:0  
DIR  
G
Even if the AD1848K is not playing back data from its DACs,  
the analog mix function can still be active.  
2
4
5
ISA BUS  
B
A
Analog-to-D igital D atapath  
PDRQ  
CDRQ  
PDAK  
CDAK  
INT  
DRQ<X>  
DRQ<Y>  
DAK<X>  
DAK<Y>  
IRQ<Z>  
T he AD1848K ∑∆ ADCs incorporate a fourth order modulator.  
A single pole of passive filtering is all that is required for  
anti-aliasing the analog input due to the ADC’s high 64 times  
oversampling ratio. T he ADCs include linear phase digital deci-  
mation filters that low-pass filter the input to 0.45 × FS (“FS” is  
the word rate or “sampling frequency.”) ADC input overrange  
conditions will cause register bits to be set that can be read.  
Figure 1. Interface to ISA Bus  
D igital-to-Analog D atapath  
T he pair of 16-bit outputs from the ADCs is available over a  
byte-wide bidirectional interface that also supports 16-bit digital  
input to the DACs and control information. T he AD1848K can  
accept and generate 16-bit twos-complement PCM linear digital  
data, 8-bit unsigned magnitude PCM linear data, and 8-bit  
µ-law or A-law companded digital data.  
T he ∑∆ DACs contain a programmable attenuator and a low-  
pass digital interpolation filter. T he anti-imaging interpolation  
filter nominally oversamples by 64 and digitally filters the higher  
frequency images. T he interpolation ratio is increased at low  
sample rates to ensure that the shaped quantization noise is  
inaudible. T his feature of the AD1848K represents an improve-  
ment over the earlier AD1848J. T he attenuator allows indepen-  
dent control of each DAC channel from 0 dB to –94.5 dB in  
1.5 dB steps plus full mute. T he DACs’ ∑∆ noise shapers also  
oversample by 64 and convert the signal to a single bit stream.  
T he DAC outputs are then filtered in the analog domain by a  
combination of switched-capacitor and continuous-time filters.  
T hey remove the very high frequency components of the DAC  
bitstream output. No external components are required. Phase  
linearity at the analog output is achieved by internally compen-  
sating for the group delay variation of the analog output filters.  
T he ∑∆ DACs are preceded by a digital interpolation filter. An  
attenuator provides independent user volume control over each  
DAC channel. Nyquist images and shaped quantization noise  
are removed from the DACs’ analog stereo output by on-chip  
switched-capacitor and continuous-time filters. T wo stereo pairs  
of auxiliary line-level inputs can also be mixed in the analog do-  
main with the DAC output.  
AUD IO FUNCTIO NAL D ESCRIP TIO N  
T his section overviews the functionality of the AD1848K and is  
intended as a general introduction to the capabilities of the de-  
vice. As much as possible, detailed reference information has  
been placed in “Control Registers” and other sections. T he user  
is not expected to refer repeatedly to this section.  
Changes in DAC output attenuation take effect only on zero  
crossings of the digital signal, thereby eliminating “zipper”  
noise. Each channel has its own independent zero-crossing de-  
tector and attenuator change control circuitry. A timer guarantees  
that requested volume changes will occur even in the absence of  
an input signal that changes sign. T he time-out period is 8 milli-  
seconds at a 48 kHz sampling rate and 48 milliseconds at an  
8 kHz sampling rate. (T ime out [ms] ≈ 384/FS [kHz].)  
Analog Inputs  
T he AD1848K SoundPort Stereo Codec accepts stereo  
line-level and mic-level inputs. LINE, MIC, and AUX1 inputs  
and post-mixed DAC output analog stereo signals are multi-  
plexed to the internal programmable gain amplifier stage  
(PGA). Each channel of the mic inputs can be amplified by  
REV. 0  
–9–  
AD1848K  
D igital Mixing  
On input, 8-bit companded data is expanded to an internal lin-  
ear representation, according to whether µ-law or A-law was  
specified in the Codec’s internal registers. Note that when µ-law  
compressed data is expanded to a linear format, it requires 14  
bits. A-law data expanded requires 13 bits.  
Stereo digital output from the ADCs can be mixed digitally with  
the input to the DACs. Digital output from the ADCs going out  
of the data port is unaffected by the digital mix. Along the digi-  
tal mix datapath, the 16-bit linear output from the ADCs is  
attenuated by an amount specified with control bits. Both chan-  
nels of the monitor data are attenuated by the same amount.  
(Note that internally the AD1848K always works with 16-bit  
PCM linear data, digital mixing included; format conversions  
take place at the input and output.)  
15  
0
0
0
8
7
COMPRESSED  
INPUT DATA  
MSB  
LSB  
15  
EXPANSION MSB  
3/2 2/1  
LSB  
Sixty-four steps of –1.5 dB attenuation are supported to  
–94.5 dB. T he digital mix datapath can also be completely  
muted, preventing any mixing of the analog input with the digi-  
tal input. Note that the level of the mixed signal is also a func-  
tion of the input PGA settings, since they affect the ADCs’  
output.  
15  
MSB  
3/2 2/1  
LSB  
DAC INPUT  
0 0 0 / 0 0  
Figure 2. A-Law or µ-Law Expansion  
T he attenuated digital mix data is digitally summed with the  
DAC input data prior to the DACs’ datapath attenuators. T he  
digital sum of digital mix data and DAC input data is clipped at  
plus or minus full scale and does not wrap around. Because both  
stereo signals are mixed before the output attenuators, mix data  
is attenuated a second time by the DACs’ datapath attenuators.  
When 8-bit companding is specified, the ADCs’ linear output is  
compressed to the format specified.  
15  
MSB  
0
ADC OUTPUT  
LSB  
15  
MSB  
3/2 2/1  
LSB  
0
0
In case the AD1848K is capturing data but ADC output data is  
not removed in time (“ADC overrun”), then the last sample  
captured before overrun will be used for the digital mix. In case  
the AD1848K is playing back data but input digital DAC data  
fails to arrive in time (“DAC underrun”), then a midscale zero  
will be added to the digital mix data.  
TRUNCATION  
15  
MSB  
8
7
LSB  
0 0 0 0 0 0 0 0  
COMPRESSION  
Figure 3. A-Law or µ-Law Com pression  
Analog O utputs  
A stereo line level output is available at external pins. Each  
channel of this output can be independently muted. When  
muted, the outputs will settle to a dc value near VREF, the mid-  
scale reference voltage.  
Note that all format conversions take place at input or output.  
Internally, the AD1848K always uses 16-bit linear PCM repre-  
sentations to maintain maximum precision.  
P ower Supplies and Voltage Refer ence  
D igital D ata Types  
T he AD1848K operates from +5 V power supplies. Indepen-  
dent analog and digital supplies are recommended for optimal  
performance though excellent results can be obtained in single  
supply systems. A voltage reference is included on the Codec  
and its 2.25 V buffered output is available on an external pin  
(VREF). T he reference output can be used for biasing op amps  
used in dc coupling. T he internal reference must be externally  
bypassed to analog ground at the VREF_F pin.  
T he AD1848K supports four global data types: 16-bit twos-  
complement linear PCM, eight-bit unsigned linear PCM,  
companded µ-law, and 8-bit companded A-law, as specified by  
control register bits. Data in all four formats is always trans-  
ferred MSB first. Eight-bit data is always left justified in 16-bit  
fields; said in other words, the MSBs of all data types are always  
aligned; in yet other words, full-scale representations in all four  
formats correspond to equivalent full-scale signals. T he eight  
least significant bit positions of 8-bit data in 16-bit fields are  
ignored on input and zeroed on output.  
Clocks and Sam ple Rates  
T he AD1848K operates from external crystals. T wo crystal in-  
puts are provided to generate a wide range of sample rates. T he  
oscillators for these crystals are on the AD1848K, as is a multi-  
plexer for selecting between them. T hey can be overdriven with  
external clocks by the user, if so desired. T he recommended  
crystal frequencies are 16.9344 MHz and 24.576 MHz. From  
them the following sample rates are divided down: 5.5125,  
6.615, 8, 9.6, 11.025, 16, 18.9, 22.05, 27.42857, 32, 33.075,  
37.8, 44.1, 48 kHz.  
T he 16-bit PCM data format is capable of representing 96 dB of  
dynamic range. Eight-bit PCM can represent 48 dB of dynamic  
range. Companded µ-law and A-law data formats use nonlinear  
coding with less precision for large amplitude signals. T he loss  
of precision is compensated for by an increase in dynamic range  
to 64 dB and 72 dB, respectively.  
–10–  
REV. 0  
AD1848K  
CO NTRO L REGISTERS  
Index  
Register Nam e  
Contr ol Register Ar chitectur e  
0
1
2
3
4
5
6
7
Left Input Control  
Right Input Control  
T he AD1848K SoundPort Stereo Codec accepts both data and  
control information through its byte-wide parallel port. Indirect  
addressing minimizes the number of external pins required to  
access all 21 of its byte-wide internal registers. Only two  
external address pins, ADR1:0, are required to accomplish all  
data and control transfers. T hese pins select one of five direct  
registers. (ADR1:0 = 3 addresses two registers, depending on  
whether the transfer is a playback or a capture.)  
Left Aux # 1 Input Control  
Right Aux # 1 Input Control  
Left Aux # 2 Input Control  
Right Aux # 2 Input Control  
Left Output Control  
Right Output Control  
Clock and Data Format  
Interface Configuration  
Pin Control  
T est and Initialization  
Miscellaneous Information  
Digital Mix  
Upper Base Count  
Lower Base Count  
8
9
AD R1:0  
Register Nam e  
10  
11  
12  
13  
14  
15  
0
1
2
3
Index Address Register  
Indexed Data Register  
Status Register  
PIO Data Registers  
Figure 4. AD1848K Direct Register Map  
Figure 5. AD1848K Indirect Register Map  
A write to or a read from the Indexed Data Register will access  
the indirect register which is indexed by the value most recently  
written to the Index Address Register. T he Status Register and  
the PIO Data Register are always accessible directly, without in-  
dexing. T he 16 indirect registers are indexed in Figure 5.  
A detailed map of all direct and indirect register contents is  
summarized for reference as follows:  
Dir ect Register s:  
AD R1:0  
D ata 7  
IN IT  
IXD 7  
C U /L  
C D 7  
D ata 6  
MCE  
IXD 6  
CL/R  
C D 6  
D ata 5  
T RD  
IXD 5  
CRDY  
C D 5  
D ata 4  
res  
IXD 4  
SOUR  
C D 4  
P D 4  
D ata 3  
IXA3  
IXD 3  
PU /L  
C D 3  
D ata 2  
IXA2  
IXD 2  
PL/R  
C D 2  
D ata 1  
IXA1  
IXD 1  
PRDY  
C D 1  
D ata 0  
IXA0  
IXD 0  
IN T  
C D 0  
P D 0  
0
1
2
3
3
P D 7  
P D 6  
P D 5  
P D 3  
P D 2  
P D 1  
Indir ect Register s:  
IXA3:0  
D ata 7  
LSS1  
D ata 6  
D ata 5  
LM GE  
RMGE  
res  
res  
res  
D ata 4  
res  
res  
LX1A4  
RX1A4  
LX2A4  
RX2A4  
LD A4  
RDA4  
S/M  
D ata 3  
LIG 3  
RIG 3  
LX1A3  
RX1A3  
LX2A3  
RX2A3  
LD A3  
RDA3  
C FS2  
ACAL  
res  
D ata 2  
D ata 1  
D ata 0  
LIG 0  
RIG 0  
LX1A0  
RX1A0  
LX2A0  
RX2A0  
LD A0  
RDA0  
CSS  
P EN  
res  
ORL0  
ID 0  
D M E  
U B0  
0
1
2
3
4
5
6
7
8
LSS0  
RSS0  
res  
res  
res  
res  
res  
res  
FM T  
PPIO  
XC T L0  
PU R  
res  
DMA4  
U B6  
LB6  
LIG 2  
RIG 2  
LX1A2  
RX1A2  
LX2A2  
RX2A2  
LD A2  
RDA2  
C FS1  
SD C  
res  
ORR0  
ID 2  
DMA0  
U B2  
LB2  
LIG 1  
RIG 1  
LX1A1  
RX1A1  
LX2A1  
RX2A1  
LD A1  
RDA1  
C FS0  
C EN  
IEN  
ORL1  
ID 1  
res  
U B1  
RSS1  
LM X1  
RMX1  
LM X2  
RMX2  
LD M  
RDM  
res  
CPIO  
XC T L1  
COR  
res  
DMA5  
U B7  
res  
LD A5  
RDA5  
L/C  
res  
res  
ACI  
res  
DMA3  
U B5  
LB5  
9
res  
res  
10  
11  
12  
13  
14  
15  
DRS  
res  
DMA2  
U B4  
LB4  
ORR1  
ID 3  
DMA1  
U B3  
LB7  
LB3  
LB1  
LB0  
Figure 6. AD1848K Register Sum m ary  
Note that the only sticky bit in any of the AD1848K control registers is the interrupt (INT ) bit. All other bits change with every  
sample period.  
REV. 0  
–11–  
AD1848K  
D ir ect Contr ol Register D efinitions  
Index Register (ADR1:0 = 0)  
AD R1:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
0
IN IT  
MCE  
T RD  
res  
IXA3  
IXA2  
IXA1  
IXA0  
IXA3:0  
Index Address. T hese bits define the address of the AD1848K register accessed by the Indexed Data Register. T hese bits  
are read/write.  
res  
Reserved for future expansion. Always write a zero to this bit.  
T RD  
T ransfer Request Disable. T his bit, when set, causes all data transfers to cease when the Interrupt Status (INT ) bit of  
the Status Register is set.  
0
T ransfers Enabled During Interrupt. PDRQ and CDRQ pin outputs are generated uninhibited by interrupts.  
DMA Current Counter Register decrements with every sample period when either PEN or CEN are enabled.  
1
T ransfers Disabled By Interrupt. PDRQ and CDRQ pin outputs are generated only if INT bit is 0 (when either  
PEN or CEN, respectively, are enabled). Any pending playback or capture requests are allowed to complete at the  
time when T RD is set. After pending requests complete, midscale inputs will be internally generated for the  
DACs, and the ADC output buffer will contain the last valid output. Clearing the sticky INT bit (or the T RD bit)  
will cause the resumption of playback and/or capture requests (presuming PEN and/or CEN are enabled). T he  
DMA Current Counter Register will not decrement while both the T RD bit is set and the INT bit is a one.  
MCE  
Mode Change Enable. T his bit must be set whenever the current functional mode of the AD1848K is changed. Specifi-  
cally, the Clock and Data Format and Interface Configuration registers cannot be changed unless this bit is set. T he  
exceptions are CEN and PEN in the Interface Configuration which can be changed “on-the-fly.” MCE should be  
cleared at the completion of the desired register changes. T he DAC outputs are automatically muted when the MCE bit  
is set. After MCE is cleared, the DAC outputs will be restored to the state specified by the LDM and RDM mute bits.  
Both ADCs and DACs are automatically muted for approximately 128 sample cycles after exiting the MCE state to al-  
low the reference and all filters to settle. T he ADCs will produce midscale values; the DACs’ analog output will be  
muted. All converters are internally operating during these ≈128 sample cycles, and the AD1848K will expect playback  
data and will generate (midscale capture data. Note that the autocalibrate-in-process (ACI) bit will be set on exit from  
the MCE state regardless of whether or not ACAL was set. ACI will remain HI for these ≈128 sample cycles; system  
software should poll this bit rather than count cycles.  
Special sequences must be followed if autocalibrate (ACAL) is set or sample rates are changed (CFS2:0 and or CSS)  
during mode change enable. See the “Autocalibration” and “Changing Sample Rates” sections below.  
INIT  
AD1848K Initialization. T his bit is set when the AD1848K is in a state which cannot respond to parallel bus cycles. T his  
bit is read only.  
Immediately after reset and once the AD1848K has left the INIT state, the initial value of this register will be “0100 0000 (40h).”  
During AD1848K initialization, this register cannot be written and is always read “1000 0000 (80h).”  
Indexed Da ta Register (ADR1:0 = 1)  
AD R1:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
1
IXD 7  
IXD 6  
IXD 5  
IXD 4  
IXD 3  
IXD 2  
IXD 1  
IXD 0  
IXD7:0  
Indexed Register Data. T hese bits contain the contents of the AD1848K register referenced by the Indexed  
Data Register.  
During AD1848K initialization. this register cannot be written and is always read as “1000 0000 (80h).”  
–12–  
REV. 0  
AD1848K  
Sta tus Register (ADR1:0 = 2)  
AD R1:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
2
C U /L  
CL/R  
CRDY  
SOUR  
PU /L  
PL/R  
PRDY  
IN T  
INT  
Interrupt Status. T his sticky bit (the only one) indicates the status of the interrupt logic of the AD1848K. T his bit is  
cleared by any host write of any value to this register. T he IEN bit of the Pin Control Register determines whether the  
state of this bit is reflected on the INT pin of the AD1848K. T he only interrupt condition supported by the AD1848K is  
generated by the underflow of the DMA Current Count Register.  
0
1
Interrupt pin inactive  
Interrupt pin active  
PRDY  
PL/R  
Playback Data Register Ready. T he PIO Playback Data Register is ready for more data. T his bit should only be used  
when direct programmed I/O data transfers are desired. T his bit is read only.  
0
1
DAC data is still valid. Do not overwrite.  
DAC data is stale. Ready for next host data write value.  
Playback Left/Right Sample. T his bit indicates whether the PIO playback data needed is for the right channel DAC or  
left channel DAC. T his bit is read only.  
0
1
Right channel needed  
Left channel or mono  
PU/L  
Playback Upper/Lower Byte. T his bit indicates whether the PIO playback data needed is for the upper or lower byte of  
the channel. T his bit is read only.  
0
1
Lower byte needed  
Upper byte needed or any 8-bit mode  
SOUR  
CRDY  
CL/R  
CU/L  
Sample Over/Underrun. T his bit indicates that the most recent sample was not serviced in time and therefore either a  
capture overrun (COR) or playback underrun (PUR) has occurred. T he bit indicates an overrun for ADC capture and  
an underrun for DAC playback. If both capture and playback are enabled, the source which set this bit can be deter-  
mined by reading COR and PUR. T his bit changes on a sample-by-sample basis. T his bit is read only.  
Capture Data Ready. T he PIO Capture Data Register contains data ready for reading by the host. T his bit should only  
be used when direct programmed I/O data transfers are desired. T his bit is read only.  
0
1
ADC data is stale. Do not reread the information.  
ADC data is fresh. Ready for next host data read.  
Capture Left/Right Sample. T his bit indicates whether the PIO capture data waiting is for the right channel ADC or left  
channel ADC. T his bit is read only.  
0
1
Right channel  
Left channel or mono  
Capture Upper/Lower Byte. T his bit indicates whether the PIO capture data ready is for the upper or lower byte of the  
channel. T his bit is read only.  
0
1
Lower byte ready  
Upper byte ready or any 8-bit mode  
T he PRDY, CRDY, and INT bits of this status register can change asynchronously to host accesses. T he host may access this regis-  
ter while the bits are transitioning. T he host read may return a zero value just as these bits are changing, for example. A one value  
would not be read until the next host access.  
T his registers’s initial state after reset is “1100 1100.”  
REV. 0  
–13–  
AD1848K  
PIO Da ta Register s (ADRI :0 = 3)  
AD R1:0  
D ata 7  
C D 7  
P D 7  
D ata 6  
C D 6  
P D 6  
D ata 5  
C D 5  
P D 5  
D ata 4  
C D 4  
P D 4  
D ata 3  
C D 3  
P D 3  
D ata 2  
C D 2  
P D 2  
D ata 1  
C D 1  
P D 1  
D ata 0  
C D 0  
P D 0  
3
3
T he PIO Data Registers are two registers mapped to the same address. Writes send data to the PIO Playback Data Register (PD7:0).  
Reads will receive data from the PIO Capture Data Register (CD7:0).  
During AD1848K initialization, the PIO Playback Data Register cannot be written and the Capture Data Register is always read  
“1000 0000 (80h).”  
CD7:0  
PIO Capture Data Register. This is the control register where capture data is read during programmed I/O data transfers.  
T he reading of this register will increment the state machine so that the following read will be from the next appropriate  
byte in the sample. T he exact byte which is next to be read can be determined by reading the Status Register. Once all  
relevant bytes have been read, the state machine will stay pointed to the last byte of the sample until a new sample is re-  
ceived from the ADCs. Once this has occurred, the state machine and status register will point to the first byte of the  
sample. Until a new sample is received, reads from this register will return the most significant byte of the sample.  
PD7:0  
PIO Playback Data Register. T his is the control register where playback data is written during programmed I/O data  
transfers.  
Writing data to this register will increment the playback byte tracking state machine so that the following write will be  
to the correct byte of the sample. Once all bytes of a sample have been written, subsequent byte writes to this port are  
ignored. T he state machine is reset when the current sample is sent to the DACs.  
Indir ect Contr ol Register D efinitions  
T he following control registers are accessed by writing index values to IXA3:0 in the Index Address Register (ADR1:0 = 0) followed  
by a read/write to the Indexed Data Register (ADR1:0 = 1).  
Left Input Contr ol (IXA3:0 = 0)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
0
LSS1  
LSS0  
LM GE  
res  
LIG 3  
LIG 2  
LIG 1  
LIG 0  
LIG3:0  
Left Input Gain Select. T he least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.  
Reserved for future expansion. Always write a zero to this bit.  
res  
LMGE  
LSS1:0  
Left Input Microphone Gain Enable. Setting this bit will enable the +20 dB gain of the left mic input signal.  
Left Input Source Select. T hese bits select the input source for the left gain stage preceding the left ADC.  
0
1
2
3
Left Line Source Selected  
Left Auxiliary 1 Source Selected  
Left Microphone Source Selected  
Left Line Post-Mixed DAC Output Source Selected  
T his register’s initial state after reset is “0000 0000.”  
–14–  
REV. 0  
AD1848K  
Right Input Contr ol (IXA3:0 = 1)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
1
RSS1  
RSS0  
RMGE  
res  
RIG 3  
RIG 2  
RIG 1  
RIG 0  
RIG3:0  
Right Input Gain Select. T he least significant bit of this gain select represents +1.5 dB. Maximum gain is +22.5 dB.  
Reserved for future expansion. Always write a zero to this bit.  
res  
RMGE  
RSS1:0  
Right Input Mic Gain Enable. Setting this bit will enable the +20 dB gain of the right mic input signal.  
Right Input Source Select. T hese bits select the input source for the right channel gain stage preceding the right ADC.  
0
1
2
3
Right Line Source Selected  
Right Auxiliary 1 Source Selected  
Right Microphone Source Selected  
Right Post-Mixed DAC Output Source Selected  
T his register’s initial state after reset is “0000 0000.”  
Left Auxilia r y # 1 Input Contr ol (IXA3:0 = 2)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
2
LM X1  
res  
res  
LX1A4  
LX1A3  
LX1A2  
LX1A1  
LX1A0  
LX1A4:0 Left Auxiliary Input # 1 Attenuate Select. T he least significant bit of this gain/attenuate select represents –1.5 dB.  
LX1X4:0 = 0 produces a +12 dB gain. LX1A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is  
–34.5 dB.  
res  
Reserved for future expansion. Always write zeros to these bits.  
LMX1  
Left Auxiliary # 1 Mute. T his bit, when set, will mute the left channel of the Auxiliary # 1 input source. T his bit powers  
up set.  
T his register’s initial state after reset is “1000 0000 (80h).”  
Right Auxilia r y # 1 Input Contr ol (IXA3:0 = 3)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
3
RMX1  
res  
res  
RX1A4  
RX1A3  
RX1A2  
RX1A1  
RX1A0  
RX1A4:0 Right Auxiliary Input # 1 Attenuate Select. T he least significant bit of this gain/attenuate select represents –1.5 dB.  
RX1A4:0 = 0 produces a +12 dB gain. RX1A4:0 = “01000” (8 decimal) produces 0 dB gain. Maximum attenuation is  
–34.5 dB.  
res  
Reserved for future expansion. Always write zeros to these bits.  
RMX1  
Right Auxiliary # 1 Mute. T his bit, when set, will mute the right channel of the Auxiliary # 1 input source. T his bit  
powers up set.  
T his register’s initial state after reset is “1000 0000 (80h).”  
REV. 0  
–15–  
AD1848K  
Left Auxilia r y # 2 Input Contr ol (IXA3:0 = 4)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
4
LM X2  
res  
res  
LX2A4  
LX2A3  
LX2A2  
LX2A1  
LX2A0  
LX2A4:0 Left Auxiliary Input # 2 Attenuate Select. T he least significant bit of this gain/attenuate select represents –1.5 dB.  
LX2A4:0 = 0 produces a +12 dB gain. LX2A4:0 = “01000” (8 decimal) produces 0 dB gain.  
Maximum attenuation is –34.5 dB.  
res  
Reserved for future expansion. Always write zeros to these bits.  
LMX2  
Left Auxiliary # 2 Mute. T his bit, when set to 1, will mute the left channel of the Auxiliary # 2 input source.  
T his bit powers up set.  
T his register’s initial state after reset is “1000 0000 (80h).”  
Right Auxilia r y # 2 Input Contr ol (IXA3:0 = 5)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
5
RMX2  
res  
res  
RX2A4  
RX2A3  
RX2A2  
RX2A1  
RX2A0  
RX2A4:0 Right Auxiliary Input # 1 Attenuate Select. T he least significant bit of this gain/attenuate select represents –1.5 dB.  
RX2A4:0 = 0 produces a +12 dB gain. RX2A4:0 = “01000” (8 decimal) produces 0 dB gain.  
Maximum attenuation is –34.5 dB.  
res  
Reserved for future expansion. Always write zeros to these bits.  
RMX2  
Right Auxiliary # 2 Mute. T his bit, when set, will mute the right channel of the Auxiliary # 2 input source.  
T his bit powers up set.  
T his register’s initial state after reset is “1000 0000 (80h).”  
Left DAC Contr ol (IXA3:0 = 6)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
6
LD M  
res  
LD A5  
LD A4  
LD A3  
LD A2  
LD A1  
LD A0  
LDA5:0  
Left DAC Attenuate Select. T he least significant bit of this attenuate select represents –1.5 dB. LDA5:0 = 0 produces a  
0 dB attenuation. Maximum attenuation is –94.5 dB.  
res  
Reserved for future expansion. Always write a zero to this bit.  
LDM  
Left DAC Mute. T his bit, when set to 1, will mute the left DAC output. Auxiliary inputs are muted independently with  
the Left Auxiliary Input Control Registers. T his bit powers up set.  
T his register’s initial state after reset is “1x00 0000.”  
Right DAC Contr ol (IXA3:0 = 7)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
7
RDM  
res  
RDA5  
RDA4  
RDA3  
RDA2  
RDA1  
RDA0  
RDA5:0  
Right DAC Attenuate Select. T he least significant bit of this attenuate select represents –1.5 dB. RDA5:0 = 0 produces  
0 dB attenuation. Maximum attenuation is –94.5 dB.  
res  
Reserved for future expansion. Always write a zero to this bit.  
RDM  
Right DAC Mute. T his bit, when set to 1, will mute the right DAC output. Auxiliary inputs are muted independently  
with the Right Auxiliary Input Control Registers. T his bit powers up set.  
T his register’s initial state after reset is “1x00 0000.”  
–16–  
REV. 0  
AD1848K  
Clock a nd Da ta For m a t Register (IXA3:0 = 8)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
8
res  
FM T  
L/C  
S/M  
C FS2  
C FS1  
C FS0  
CSS  
The contents of the Clock and Data Format Register cannot be changed except when the AD1848K is in Mode Change Enable (MCE) state.  
Write attempts to this register when the AD1848K is not in the MCE state will not be successful.  
CSS  
Clock Source Select. T his bit selects the crystal clock source which will be used for the audio sample rate.  
0
1
XT AL1 (24.576 MHz)  
XT AL2 (16.9344 MHz)  
CFS2:0  
Clock Frequency Divide Select. T hese bits select the audio sample rate frequency. T he actual audio sample rate depends  
on which crystal clock source is selected and the frequency of that source.  
D ivide  
Factor  
XTAL1  
24.576 MH z  
XTAL2  
16.9344 MH z  
CFS  
0
1
2
3
4
5
6
7
3072  
1536  
896  
768  
448  
384  
512  
2560  
8.0 kHz  
16.0 kHz  
5.5125 kHz  
11.025 kHz  
18.9 kHz  
22.05 kHz  
37.8 kHz  
44.1 kHz  
33.075 kHz  
6.615 kHz  
27.42857 kHz  
32.0 kHz  
Not Supported  
Not Supported  
48.0 kHz  
9.6 kHz  
Note that the AD1848K’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an external  
clock source is applied, it will be divided down by the selected Divide Factor. It need not be at the recommended crystal frequencies.  
S/M  
Stereo/Mono Select. T his bit determines how the audio data streams are formatted. Selecting stereo will result with alter-  
nating samples representing left and right audio channels. Mono playback plays the same audio sample on both chan-  
nels. Mono capture only captures data from the left audio channel.  
0
1
Mono  
Stereo  
L/C  
Linear/Companded Select. T his bit selects between a linear digital representation of the audio signal or a nonlinear,  
companded format for all input and output data. T he type of linear PCM or the type of companded format is defined by  
the FMT bits.  
0
1
Linear PCM  
Companded  
FMT  
Format Select. T his bit defines the format for all digital audio input and outputs based on the state of the L/C bit.  
Linear P CM (L/C = 0)  
Com panded (L/C = 1)  
0
1
8-bit Unsigned PCM  
16-bit T wos-Complement PCM  
8-bit µ-law Companded  
8-bit A-law Companded  
res  
Reserved for future expansion. Always write a zero to this bit.  
T his register’s initial state after reset is “x000 0000.”  
REV. 0  
–17–  
AD1848K  
Inter fa ce Configur a tion Register (IXA3:0 = 9)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
9
CPIO  
PPIO  
res  
res  
ACAL  
SD C  
C EN  
P EN  
The contents of the Interface Configuration Register cannot be changed except when the AD1848K is in Mode Change Enable (MCE) state.  
Write attempts to this register when the AD1848K is not in the MCE state will not be successful. PEN and CEN are exceptions; these bits may  
always be written.  
PEN  
CEN  
SDC  
Playback Enable. T his bit will enable the playback of data in the format selected. T he AD1848K will generate PDRQ  
and respond to PDAK signals when this bit is enabled and PPIO = 0. If PPIO = 1, this bit enables Programmed I/O  
(PIO) playback mode. PEN may be set and reset without setting the MCE bit.  
0
1
Playback disabled (PDRQ and PIO Playback Data Register inactive)  
Playback enabled  
Capture Enable. T his bit will enable the capture of data in the format selected. T he AD1848K will generate CDRQ and  
respond to CDAK signals when this bit is enabled and CPIO = 0. If CPIO = 1, this bit enables PIO capture mode. CEN  
may be set and reset without setting the MCE bit.  
0
1
Capture disabled (CDRQ and PIO Capture Data Register inactive)  
Capture enabled  
Single DMA Channel. T his bit will force both capture and playback DMA requests to occur on the Playback DMA  
channel. T he Capture DMA CDRQ pin will be LO. T his bit will allow the AD1848K to be used with only one DMA  
channel. Simultaneous capture and playback cannot occur in this mode. Should both capture and playback be enabled  
(CEN = PEN = 1) in the mode, only playback will occur. See “Data and Control T ransfers” for further explanation.  
0
1
Dual DMA channel mode  
Single DMA channel mode  
ACAL  
Autocalibrate Enable. T his bit determines whether the AD1848K performs an autocalibrate whenever the PWRDWN  
pin is deasserted or from the Mode Change Enable (MCE) bit being reset. ACAL is normally set. See “Autocalibration”  
below for a description of a complete autocalibration sequence.  
0
1
No autocalibration  
Autocalibration after power down/reset or mode change  
res  
Reserved for future expansion. Always write zeros to these bits.  
PPIO  
Playback PIO Enable. T his bit determines whether the playback data is transferred via DMA or PIO.  
0
1
DMA transfers only  
PIO transfers only  
CPIO  
Capture PIO Enable. T his bit determines whether the capture data is transferred via DMA or PIO.  
0
1
DMA transfers only  
PIO transfers only  
T his register’s initial state after reset is “00xx 1000 (x8h).”  
Pin Contr ol Register (IXA3:0 = 10)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
10  
XC T L1  
XC T L0  
res  
res  
res  
res  
IEN  
res  
res  
IEN  
Reserved for future expansion. Always write zeros to these bits.  
Interrupt Enable. T his bit enables the interrupt pin. T he Interrupt Pin will go active HI when the number of samples  
programmed in the Base Count Register is reached.  
0
1
Interrupt disabled  
Interrupt enabled  
XCT L1:0 External Control. T he state of these independent bits is reflected on the respective XCT L1:0 pins of the AD1848K.  
0
1
T T L Logic LO on XCT L1:0 pins  
T T L Logic HI on XCT L1:0 pins  
T his register’s initial state after reset is “00xx xx0x.”  
–18–  
REV. 0  
AD1848K  
Test a nd Initia liza tion Register (IXA3:0 = 11)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
11  
COR  
PU R  
ACI  
DRS  
ORR1  
ORR0  
ORL1  
ORL0  
ORL1:0  
Overrange Left Detect. T hese bits indicate the overrange on the left input channel. T his bit changes on a sample-by  
sample basis. T his bit is read only.  
0
1
2
3
Less than –1 dB underrange  
Between –1 dB and 0 dB underrange  
Between 0 dB and +1 dB overrange  
Greater than +1 dB overrange  
ORR1:0  
Overrange Right Detect. T hese bits indicate the overrange on the right input channel. T his bit changes on a sample-by  
sample basis. T his bit is read only.  
0
1
2
3
Less than –1 dB underrange  
Between –1 dB and 0 dB underrange  
Between 0 dB and +1 dB overrange  
Greater than +1 dB overrange  
DRS  
ACI  
Data Request Status. T his bit indicates the current status of the PDRQ and CDRQ pins of the AD1848K.  
0
1
CDRQ and PDRQ are presently inactive (LO)  
CDRQ or PDRQ are presently active (HI)  
Autocalibrate-In-Progress. T his bit indicates the state of autocalibration or a recent exit from Mode Change Enable  
(MCE). T his bit is read only.  
0
1
Autocalibration is not in progress  
Autocalibration is in progress or MCE was exited within approximately the last 128 sample periods  
PUR  
COR  
Playback Underrun. T his bit is set when playback data has not arrived from the host in time to be played. As a result, a  
midscale value will be sent to the DACs. T his bit changes on a sample by sample basis.  
Capture Overrun. T his bit is set when the capture data has not been read by the host before the next sample arrives. T he  
sample being read will not be overwritten by the new sample. T he new sample will be ignored. T his bit changes on a  
sample by sample basis.  
T he occurrence of a PUR and/or COR is designated in the Status Register’s Sample Overrun/Underrun (SOUR) bit. T he SOUR bit  
is the logical OR of the COR and PUR bits. T his enables a polling host CPU to detect an overrun/underrun condition while checking  
other status bits.  
T his register’s initial state after reset is “0000 0000.”  
Miscella neous Contr ol Register (IXA3:0 = 12)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
12  
res  
res  
res  
res  
ID 3  
ID 2  
ID 1  
ID 0  
res  
ID3:0  
Reserved for future expansion. T he bits are read only. Do not write to these bits.  
AD1848K Revision ID. T hese four bits define the revision level of the AD1848K. Revisions increment by one LSB. T he  
K-Grade revision is ID = “1010.” T hese bits are read only.  
T his register’s initial state after reset is “xxxx RRRR” where RRRR = Revision ID of the silicon in use.  
REV. 0  
–19–  
AD1848K  
Digita l Mix Contr ol Register (IXA3:0 = 13)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
13  
DMA5  
DMA4  
DMA3  
DMA2  
DMA1  
DMA0  
res  
D M E  
DME  
Digital Mix Enable. T his bit will enable the digital mix of the ADCs’ output with the DACs’ input. When enabled, the  
data from the ADCs are digitally mixed with other data being delivered to the DACs (regardless of whether or not play-  
back [PEN] is enabled, i.e., set). If capture is enabled (CEN set) and there is a capture overrun (COR), then the last  
sample captured before overrun will be used for the digital mix. If playback is enabled (PEN set) and there is a playback  
underrun (PUR), then a midscale zero will be added to the digital mix data.  
0
1
Digital mix disabled (muted)  
Digital mix enabled  
res  
Reserved for future expansion. Always write a zero to this bit.  
DMA5:0 Digital Mix Attenuation. T hese bits determine the attenuation of the ADC data in mixing with the DAC input. Each  
attenuate step is –1.5 dB ranging to –94.5 dB.  
T his register’s initial state after reset is “0000 00x0.”  
DMA Ba se Count Register s (IXA3:0 = 14 & 15)  
T he DMA Base Count Registers in the AD1848K simplify integration of the AD1848K in ISA systems. T he ISA DMA controller re-  
quires an external count mechanism to notify the host CPU via interrupt of a full DMA buffer. T he programmable DMA Base  
Count Registers will allow such interrupts to occur.  
T he Base Count Registers contain the number of sample periods which will occur before an interrupt is generated on the interrupt  
(INT ) pin. T o load, first write a value to the Lower Base Count Register. Writing a value to the Upper Base Register will cause both  
Base Count Registers to load into the Current Count Register. Once AD1848K transfers are enabled, each sample period the Cur-  
rent Count Register will decrement until zero count is reached. T he next sample period after zero will generate the interrupt and re-  
load the Current Count Register with the values in the Base Count Registers. T he interrupt is cleared by a write to the Status  
Register.  
T he Host Interrupt Pin (INT ) will go HI during the sample period in which the Current Count Register underflows when Interrupt  
Enable (IEN) is set. It will go LO when the Interrupt Status (INT ) bit is cleared. Note that both the bit and the pin have the same  
name (INT ). T he Current Count Register is decremented every sample period when either the PEN or CEN bit is enabled and also  
either the T ransfer Request Disable (T RD) bit or the Interrupt Status (INT ) bit are zero. Note that the internal INT bit will become  
one on counter underflow even if the external interrupt pin is not enabled, i.e., IEN is zero. T he Current Count Register is  
decremented in both PIO and DMA data transfer modes.  
Upper Ba se Count Register (IXA3:0 = 14)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
14  
U B7  
U B6  
U B5  
U B4  
U B3  
U B2  
U B1  
U B0  
UB7:0  
Upper Base Count. T his byte is the upper byte of the base count register containing the eight most significant bits of the  
16-bit base register. Reads from this register return the same value which was written. T he current count contained in  
the counters can not be read.  
T his register’s initial state after reset is “0000 0000.”  
Lower Upper Ba se Count Register (IXA3:0 = 15)  
IXA3:0  
D ata 7  
D ata 6  
D ata 5  
D ata 4  
D ata 3  
D ata 2  
D ata 1  
D ata 0  
15  
LB7  
LB6  
LB5  
LB4  
LB3  
LB2  
LB1  
LB0  
LB7:0  
Lower Base Count. T his byte is the lower byte of the base count register containing the eight least significant bits of the  
16-bit base register. Reads from this register return the same value which was written. T he current count contained in  
the counters cannot be read.  
T his register’s initial state after reset is “0000 0000.”  
–20–  
REV. 0  
AD1848K  
D ATA AND CO NTRO L TRANSFERS  
Contr ol and P r ogr am m ed I/O (P IO ) Tr ansfer s  
T he AD1848K SoundPort Stereo Codec supports a DMA re-  
quest/grant architecture for transferring data with the host com-  
puter bus. One or two DMA channels can be supported.  
Programmed I/O (PIO) mode is also supported for control reg-  
ister accesses and for applications lacking DMA control. PIO  
transfers can be made on one channel while the other is per-  
forming DMA. T ransfers to and from the AD1848K SoundPort  
Codec are asynchronous relative to the internal data conversion  
clock. T ransfers are buffered, but the AD1848K supports no in-  
ternal FIFOs. T he host is responsible for providing playback  
data before the next digital-to-analog conversion and removing  
capture data before the next analog-to-digital conversion.  
T his simpler mode of transfers is used both for control register  
accesses and programmed I/O. T he 21 control and PIO data  
registers cannot be accessed via DMA transfers. Playback PIO is  
activated when both Playback Enable (PEN) is set and Playback  
PIO (PPIO) is set. Capture PIO is activated when both Capture  
Enable (CEN) is set and Capture PIO (CPIO) is set. See Fig-  
ures 11 and 12 for the detailed timing of the control register/  
PIO transfers. T he RD and WR signals are used to define the  
actual read and write cycles, respectively. T he host holds CS  
LO during these transfers. T he DMA Capture Data Acknowl-  
edge (CDAK) and Playback Data Acknowledge (PDAK) must  
be held inactive, i.e., HI.  
D ata O r der ing  
CDRQ /  
PDRQ  
OUTPUTS  
T he number of byte-wide transfers required depends on the  
data format selected. T he AD1848K is designed for “little  
endian” formats in which the least significant byte (i.e., occupy-  
ing the lowest memory address) gets transferred first. So 16-bit  
data transfers require first transferring the least significant bits  
7:0 and then transferring the most significant bits 15:8, where  
bit 15 is the most significant bit in the word.  
tSUDK1  
tSUDK2  
CDAK  
INPUT  
tCSSU  
tCSHD  
CS INPUT  
In addition, left channel data is always transferred before right  
channel data with the AD1848K. T he following figures should  
make these requirements clear.  
tDBDL  
DBEN &  
DBDIR  
OUTPUTS  
TIME  
tSTW  
SAMPLE 6  
SAMPLE 5  
SAMPLE 4  
SAMPLE 3  
SAMPLE 2  
SAMPLE 1  
RD INPUT  
tDHD1  
tRDDV  
MONO  
MONO  
MONO  
MONO  
DATA7:0  
OUTPUTS  
BYTE 4  
BYTE 3  
BYTE 2  
BYTE 1  
tADSU  
tADHD  
Figure 7. AD1848K 8-Bit Mono Data Stream Sequencing  
ADR1:0  
INPUTS  
TIME  
Figure 11. AD1848K Control Register/PIO Read Cycle  
SAMPLE 3  
SAMPLE 3  
SAMPLE 2  
SAMPLE 2  
SAMPLE 1  
SAMPLE 1  
CDRQ/  
PDRQ  
RIGHT  
LEFT  
RIGHT  
LEFT  
OUTPUTS  
tSUDK2  
tSUDK1  
BYTE 4  
BYTE 3  
BYTE 2  
BYTE 1  
PDAK  
INPUT  
Figure 8. AD1848K 8-Bit Stereo Data Stream Sequencing  
TIME  
tCSHD  
tCSSU  
CS INPUT  
SAMPLE 6  
SAMPLE 5  
SAMPLE 4  
SAMPLE 3  
SAMPLE 2  
SAMPLE 1  
tDBDL  
MONO  
MONO  
DBEN  
OUTPUT  
BYTES 3 & 4  
BYTES 1 & 2  
Figure 9. AD1848K 16-Bit Mono Data Stream Sequencing  
DBDIR  
OUTPUT  
HI  
TIME  
tSTW  
WR INPUT  
SAMPLE 3  
SAMPLE 3  
SAMPLE 2  
SAMPLE 2  
SAMPLE 1  
SAMPLE 1  
tWDSU  
tDHD2  
DATA7:0  
INPUTS  
LEFT  
RIGHT  
BYTES 3 & 4  
BYTES 1 & 2  
tADSU  
tADHD  
ADR1:0  
INPUTS  
Figure 10. AD1848K 16-Bit Stereo Data  
Stream Sequencing  
Figure 12. AD1848K Control Register/PIO Write Cycle  
REV. 0  
–21–  
AD1848K  
For read/capture cycles, the AD1848K will place data on the  
DAT A7:0 lines while the host is asserting the read strobe, RD,  
by holding it LO. For write/playback, the host must place data  
on the DAT A7:0 pins while strobing the WR signal LO. T he  
AD1848K latches the write/playback data on the rising edge of  
the WR strobe.  
DMA transfers may be independently aborted by resetting the  
Capture Enable (CEN) and/or Playback Enable (PEN) bits in  
the Interface Configuration Register. T he current capture  
sample transfer will be completed if a capture DMA is termi-  
nated. T he current playback sample transfer must be completed  
if a playback DMA is terminated. If CDRQ and/or PDRQ are  
asserted HI while the host is resetting CEN and/or PEN, the re-  
quest must be acknowledged. T he host must assert CDAK and/  
or PDAK LO and complete a final sample transfer.  
When using PIO data transfers, the Status Register must be  
polled to determine when data should be transferred. Note that  
the ADC capture data will be ready (CRDY HI) from the previ-  
ous sample period shortly before the DAC playback data is  
ready (PRDY HI) for the next sample period. T he user should  
not wait for both ADCs and DACs to become ready before initi-  
ating data transfers. Instead, as soon as capture data is ready, it  
should be read; as soon as the DACs are ready, playback data  
should be written.  
Single-Channel D MA  
Single-Channel DMA mode allows the AD1848K to be used in  
systems with only a single DMA channel. It is enabled by setting  
the SDC bit in the Interface Configuration Register. All cap-  
tures and playbacks take place on the playback channel. Obvi-  
ously, the AD1848K cannot perform a simultaneous capture  
and playback in Single-Channel DMA mode.  
Values written to the XCT L1:0 bits in the Pin Control Register  
(IXA3:0 = 10) will be reflected in the state of the XCT L1:0 ex-  
ternal output pins. T his feature allows a simple method for sig-  
naling or software control of external logic. Changes in state of  
the external XCT L pins will occur within one sample period.  
Because their change is referenced to the internal sample clock,  
no useful timing diagram can be constructed.  
Playback will occur in single-channel DMA mode exactly as it  
does in T wo-Channel mode. Capture, however, is diverted to  
the playback channel which means that the capture data request  
occurs on the PDRQ pin and the capture data acknowledge  
must be received on the PDAK pin. T he CDRQ pin will remain  
inactive LO. Any inputs to CDAK will be ignored.  
D ir ect Mem or y Access (D MA) Tr ansfer s  
Playback and capture are distinguished in Single-Channel DMA  
mode by the state of the playback enable (PEN) or capture en-  
able (CEN) control bits. If both PEN and CEN are set in  
Single-Channel DMA mode, playback will be presumed.  
T he second type of bus cycle supported by the AD1848K are  
DMA transfers. Both dual channel and single channel DMA op-  
erations are supported. T o enable Playback DMA transfers,  
playback enable (PEN) must be set and PPIO cleared. T o en-  
able Capture DMA transfers, capture enable (CEN) must be set  
and CPIO cleared. During DMA transfers, the AD1848K as-  
serts HI the Capture Data Request (CDRQ) or the Playback  
Data Request (PDRQ) followed by the host’s asserting LO the  
DMA Capture Data Acknowledge (CDAK) or Playback Data  
Acknowledge (PDAK), respectively. T he host’s asserted  
Acknowledge signals cause the AD1848K to perform DMA  
transfers. T he input address lines, ADR1:0, are ignored. Data is  
transferred between the proper internal sample registers.  
T o avoid confusion of the origin of a request when switching be-  
tween playback and capture in Single-Channel DMA mode,  
both CEN and PEN should be disabled and all pending re-  
quests serviced before enabling the alternative enable bit.  
Switching between playback and capture in Single-Channel  
DMA mode no longer requires changing the PPIO and CPIO  
bits or passing through the Mode Change Enable state except  
for initial setup. For setup, assign zeros to both PPIO and  
CPIO. T his configures both playback and capture for DMA.  
T hen, switching between playback and capture can be effected  
entirely by setting and clearing the PEN and CEN control bits,  
a technique which avoids having to enter the Mode Change  
Enable state.  
T he read strobe (RD) and write strobe (WR) delimit valid data  
for DMA transfers. Chip select (CS) is a “don’t care”; its state  
is ignored by the AD1848K.  
T he AD1848K asserts the Data Request Signals, CDRQ and  
PDRQ, at the rate of once per sample period, where PDRQ is  
asserted near the beginning of an internal sample period and  
CDRQ is asserted late in the same period to maximize the avail-  
able processing time. Once asserted, these signals will remain  
active HI until the corresponding DMA cycle occurs with the  
host’s Data Acknowledge signals. T he Data Request signals will  
be deasserted after the falling edge of the final RD or WD strobe  
in the transfer of a sample, which typically consists of multiple  
bytes. See “Data Ordering” above for a definition of “sample.”  
D MA Tim ing  
Below, timing parameters are shown for 8-Bit Mono Sample  
Read/Capture and Write/Playback DMA transfers in Figures 13  
and 14. Note that in single-channel DMA mode, the Read/  
Capture cycle timing shown in Figure 13 applies to the PDRQ  
and PDAK signals, rather than the CDRQ and CDAK signals  
as shown. T he same timing parameters apply to multibyte trans-  
fers. T he relationship between timing signals is shown in Fig-  
ures 15 and 16.  
T he Host Interrupt Pin (INT ) will go HI during the sample  
period in which the Current Count Register underflows. T his  
event is referenced to the internal sample period clock which is  
not available externally.  
–22–  
REV. 0  
AD1848K  
ISA BUS  
BCLK  
ISA BUS  
BCLK  
PDRQ  
OUTPUT  
CDRQ OUTPUT  
CDAK INPUT  
tDRHD  
tDRHD  
tDKSU  
PDAK  
INPUT  
tDKSU  
tDKHDA  
tDKHDB  
tDBDL  
tDBDL  
DBEN  
DBEN & DBDIR  
OUTPUTS  
OUTPUTS  
DBDIR  
OUTPUT  
HI  
tSTW  
RD INPUT  
tSTW  
WR INPUT  
tRDDV  
tDHD1  
DATA7:0  
OUTPUTS  
tDHD2  
tWDSU  
DATA7:0  
INPUTS  
Figure 13. AD1848K 8-Bit Mono DMA Read/Capture Cycle  
Figure 14. AD1848K 8-Bit Mono DMA Write/Playback Cycle  
ISA BUS  
BCLK  
CDRQ/  
PDRQ  
OUTPUTS  
CDAK/  
PDAK  
INPUTS  
tBWDN  
RD OR WR  
INPUTS  
RIGHT/HIGH  
BYTE  
LEFT/LOW  
DATA7:0  
BYTE  
Figure 15. AD1848K 8-Bit Stereo or 16-Bit Mono DMA Cycle  
ISA BUS  
BCLK  
CDRQ/ PDRQ  
OUTPUTS  
CDAK/ PDAK  
INPUTS  
tBWDN  
RD OR WR  
INPUTS  
LOW  
BYTE  
HIGH  
BYTE  
LOW  
BYTE  
HIGH  
BYTE  
DATA7:0  
LEFT SAMPLE  
RIGHT SAMPLE  
Figure 16. AD1848K 16-Bit Stereo DMA Cycle  
REV. 0  
–23–  
AD1848K  
D MA Inter r upt  
T he completion of autocalibration can be determined by polling  
the Autocalibrate-In-Progress (ACI) bit in the T est and Initial-  
ization Register, which will be set during autocalibration. T rans-  
fers enabled during autocalibration do not begin until the  
completion of autocalibration.  
Writing to the internal 16-bit Base Count Register sets up the  
count value for the number of samples to be transferred. Note  
that the number of bytes transferred for a given count will be a  
function of the selected global data format. T he internal Cur-  
rent Count Register is updated with the current contents of the  
Upper and Lower Base Count Registers when a write occurs to  
the Upper Base Count Register.  
T he following summarizes the procedure for autocalibration:  
•
Mute left and right DAC outputs, AUX1 and AUX2 inputs,  
and digital mix. (It is unnecessary to mute the DAC outputs,  
as this will happen automatically.)  
T he Current Count Register cannot be read by the host. Read-  
ing the Base Count Registers will only read back the initializa-  
tion values written to them.  
•
•
•
•
Set the Mode Change Enable (MCE) bit.  
Set the Autocalibration (ACAL) bit.  
The Current Count Register is decremented every sample  
period when either the PEN or CEN bit is enabled and also either  
the T ransfer Request Disable (T RD) bit or the Interrupt Status  
(INT ) bit is zero. An interrupt event is generated after the Cur-  
rent Count Register is zero and an additional playback sample is  
transferred. T he INT bit in the Status Register always reflects  
the current internal interrupt state defined above. T he external  
INT pin will only go active HI if the Interrupt Enable (IEN) bit  
in the Interface Configuration Register is set. If the IEN bit is  
zero, the external INT pin will always stay LO, even though the  
Status Register’s INT bit may be set.  
Clear the Mode Change Enable (MCE) bit.  
T he Autocalibrate-In-Progress (ACI) bit will transition from  
LO to HI within five sample periods. It will remain HI for  
approximately 384 sample periods. Poll the ACI bit until it  
transitions from HI to LO.  
•
Set to desired gain/attenuation values, and unmute DAC  
outputs (if muted), AUX inputs, and digital mix.  
During the autocalibration sequence, data output from the  
ADCs is meaningless. Inputs to the DACs are ignored. Even if  
the user specified the muting of all analog outputs, near the end  
of the autocalibration sequence, dc analog outputs very close to  
VREF will be produced at the line output.  
P O WER UP AND RESET  
T he PWRDWN pin should be held in its active LO state when  
power is first applied to the AD1848K. Analog Devices recom-  
mends waiting one full second after deasserting PWRDWN be-  
fore commencing audio activity with the AD1848K. T his will  
allow the analog outputs to fully settle to the VREF voltage level  
prior to system autocalibration. At any point when powered, the  
AD1848K can be put into a state for minimum power consump-  
tion by asserting PWRDWN LO. All analog and digital sections  
are shut down. T he AD1848K’s parallel interface does not func-  
tion; all bidirectional signal lines are in high impedance three-  
state.  
CH ANGING SAMP LE RATES  
T o change the selection of the current sample rate requires a  
Mode Change Enable sequence since the bits which control that  
selection are in the Clock and Data Format Register. T he fact  
that the clocks change requires a special sequence which is sum-  
marized as follows:  
•
If autocalibration will take place at the end of this sequence,  
mute the AUX1 and AUX2 inputs and the digital mix.  
•
•
Set the Mode Change Enable (MCE) bit.  
Deasserting PWRDWN by bringing it HI begins the AD1848K’s  
initialization. While initializing, the AD1848K ignores all writes  
and all reads will yield “1000 0000 (80h).” At the conclusion of  
reset initialization, all registers will be set to their default values  
as listed in “Control Registers” above. T he conclusion of the  
initialization period can be detected by polling the index register  
for some value other than “1000 0000 (80h).”  
In a single write cycle, change the Clock Frequency Divide  
Select (CFS2:0) and/or the Clock Source Select (CSS).  
•
T he AD1848K now needs to resynchronize its internal  
states to the new clock. Writes to the AD1848K will be  
ignored. Reads will produce “1000 0000 (80h)” until the  
resynchronization is complete. Poll the Index Register until  
something other than this value is returned.  
It is imperative to autocalibrate on power up for proper opera-  
tion. See next section.  
•
•
Clear the Mode Change Enable (MCE) bit.  
If ACAL is set, follow the procedure described in “Auto-  
calibration” above.  
AUTO CALIBRATIO N  
T he AD1848K can calibrate the ADCs and DACs for greater  
accuracy by minimizing DC offsets. Autocalibration occurs  
whenever the AD1848K returns from the Mode Change Enable  
state and the ACAL bit in the Interface Configuration register  
has been set. If the ACAL bit is not set, the RAM normally  
containing ADC and DAC offset compensations will be saved,  
retaining the offsets of the most recent autocalibration. T here-  
fore, it is imperative to autocalibrate on power up for proper  
operation.  
•
•
Poll the ACI hit until it transitions LO (approximately 128  
sample cycles).  
Set to desired gain/attenuation values, and unmute DAC  
outputs (if muted).  
–24–  
REV. 0  
AD1848K  
AP P LICATIO NS CIRCUITS  
Note that if a battery-powered microphone is used, the buffer  
and R2s are not needed. T he values of R1, R2, and C should be  
chosen in light of the mic characteristics and intended gain.  
T ypical values for these might be R1 = 20 kΩ, R2 = 2 kΩ, and  
C = 220 pF.  
T he AD1848K Stereo Codec has been designed to require a  
minimum of external circuitry. T he recommended circuits are  
shown in Figures 17 through 25. Analog Devices estimates that  
the total cost of all the components shown in these figures, in-  
cluding crystals but not including connectors, to be less than  
$10 in the U.S.A. in 10,000 quantities.  
C
See Figure 1 for an illustration of the connection between the  
AD1848K SoundPort Codec and the Industry Standard Archi-  
tecture (ISA) computer bus, also known as the “PC-AT bus.”  
Note that the 74_245 transceiver receives its enable and direc-  
tion signals directly from the Codec. Analog Devices recom-  
mends using the “slowest” 74_245 adequately fast to meet all  
AD1848K and computer bus timing and drive requirements. So  
doing will minimize switching transients of the 74_245. T his in  
turn will minimize the digital feedthrough effects of the trans-  
ceiver when driving the AD1848K, which can cause the audio  
noise floor to rise.  
R
1
1µF  
5.1k  
0.33µF  
L_MIC  
1/2 SSM-2135  
OR AD820  
R
R
1/2 SSM-2135  
OR AD820  
2
V
LEFT ELECTRET  
CONDENSER  
MICROPHONE  
INPUT  
REF  
C
2
R
1
1µF  
5.1k  
0.33µF  
R_MIC  
RIGHT ELECTRET  
CONDENSER  
MICROPHONE  
INPUT  
1/2 SSM-2135  
OR AD820  
Industry-standard compact disc “line-levels” are 2 V rms cen-  
tered around analog ground. (For other audio equipment, “line  
level” is much more loosely defined.) T he AD1848K SoundPort  
is a +5 V only powered device. Line level voltage swings for the  
AD1848K are defined to be 1 V rms for a sine wave ADC input  
and 0.707 V rms for a sine wave DAC output. T hus, 2 V rms  
input analog signals must be attenuated and either centered  
around the reference voltage intermediate between 0 V and  
+5 V or ac-coupled. T he VREF pin will be at this intermediate  
voltage, nominally 2.25 V. It has limited drive but can be used  
as a dc bias to an op amp input. Note, however, that dc-coupled  
inputs are not recommended, as they provide no performance  
benefits with the AD1848K architecture. Furthermore, dc offset  
differences between multiple dc-coupled inputs create the  
potential for “clicks” when changing the input mux selection.  
V
REF  
Figure 18. AD1848K "Phantom -Powered" Microphone  
Input Circuit  
Figure 19 shows ac-coupled line outputs. T he resistors are used  
to center the output signals around analog ground. If  
dc-coupling is desired, VREF could be used with op amps as  
mentioned previously.  
1µF  
L_OUT  
47k  
1µF  
A circuit for 2 V rms line-level inputs and auxiliaries is shown in  
Figure 17. Note that this is a divide-by-two resistive divider.  
T he input resistor and 560 pF capacitor provides the single-pole  
of anti-alias filtering required for the ADCs. If line-level inputs  
are already at the 1 V rms levels expected by the AD1848K, the  
resistors in parallel with the 560 pF capacitors can be omitted.  
R_OUT  
47k  
Figure 19. AD1848K Line Output Connections  
A circuit for headphone drive is illustrated in Figure 20. Drive is  
supplied by +5 V operational amplifiers. T he circuit shown ac  
couples the line output to the headphones.  
0.33µF  
5.1k  
L_LINE  
L_AUX1  
560pF  
5.1k  
L_AUX2  
NPO  
18k  
20k  
470µF  
L_OUT  
HEADPHONE  
LEFT  
0.33µF  
5.1k  
R_LINE  
V
SSM-2135  
REF  
R_AUX1  
560pF  
5.1k  
470µF  
R_AUX2  
NPO  
HEADPHONE  
RIGHT  
20k  
R_OUT  
Figure 17. AD1848K 2 V rm s Line-Level Input Circuit  
18k  
Figure 20. AD1848K Headphone Drive Connections  
T he AD1848K Codec contains an optional +20 dB gain block  
to accommodate condenser microphones. Particular system re-  
quirements will depend upon the characteristics of the intended  
microphone. Figure 18 illustrates one example of how an elec-  
tret condenser mike requiring phantom power could be con-  
nected to the AD1848K. VREF is shown buffered by an op amp;  
a transistor like a 2N4124 will also work fine for this purpose.  
REV. 0  
–25–  
AD1848K  
Figure 21 illustrates reference bypassing. VREF_F should only be  
connected to its bypass capacitors.  
power supply is not available, we recommend the circuit shown  
in Figure 24 for using a single +5 V supply. Ferrite beads suffice  
for the inductors shown. T his circuitry should be as close to the  
supply pins as is practical.  
_
V
F
V
REF  
REF  
FERRITE  
0.1µF  
10µF  
10µF  
+5V SUPPLY  
0.1µF  
1µF  
0.1µF  
0.1µF  
0.1µF  
V
V
V
DD  
Figure 21. AD1848K Voltage Reference Bypassing  
DD  
DD  
Figure 22 illustrates signal-path filtering capacitors, L_FILT  
and R_FILT . Note that AD1848Ks will perform satisfactorily  
with 0.1 µF capacitors; increasing the value to 1.0 µF does im-  
prove performance at very low frequencies, however.  
0.1µF  
0.1µF  
0.1µF  
0.1µF  
V
V
V
DD  
V
DD  
DD  
DD  
FERRITE  
1.6Ω  
1µF  
L_FILT  
R_FILT  
1µF  
0.1µF  
0.1µF  
V
V
CC  
CC  
1.0µF  
1.0µF  
Figure 24. AD1848K Recom m ended Power Supply  
Bypassing  
Figure 22. AD1848K External Filter Capacitor Connections  
Analog Devices recommends a split ground plane as shown in  
Figure 25. T he analog plane and the digital plane are connected  
directly under the AD1848K. Splitting the ground plane directly  
under the SoundPort Codec is optimal because analog pins will  
be located above the analog ground plane and digital pins will  
be located directly above the digital ground plane for the best  
isolation. T he digital ground and analog grounds should be tied  
together in the vicinity of the AD1848K. Other schemes may  
also yield satisfactory results. If the split ground plane recom-  
mended here is not possible, the AD1848K should be entirely  
over the analog ground plane with the 74_245 transceiver over  
the digital plane.  
T he crystals shown in the crystal connection circuitry of Figure  
23 should be fundamental-mode and parallel-tuned. T wo  
sources for the exact crystals specified are Component Market-  
ing Services in Massachusetts, U.S. at 617-762-4339 and Cardi-  
nal Components in New Jersey, U.S. at 201-746-0333. Note  
that using the exact data sheet frequencies is not required and  
that external clock sources can be used to overdrive the  
AD1848K’s internal oscillators. (See the description of the  
CFS2:0 control bits above.) If using an external clock source,  
apply it to the crystal input pins while leaving the crystal output  
pins unconnected. Attention should be paid to providing low jit-  
ter external input clocks.  
ANALOG GROUND PLANE  
DIGITAL GROUND PLANE  
XTAL2I  
XTAL2O  
XTAL1I  
XTAL1O  
GNDD  
R_AUX2  
20–64pF  
20–64pF  
20–64pF  
20–64pF  
16.9344MHz  
24.576MHz  
Figure 23. AD1848K Crystal Connections  
AD1848K  
Analog Devices also recommends a pull-down resistor for  
PWRDWN.  
Good, standard engineering practices should be applied for  
power supply decoupling. Decoupling capacitors should be  
placed as close as possible to package pins. If a separate analog  
GNDD  
R_FILT  
Figure 25. AD1848K Recom m ended Ground Plane  
–26–  
REV. 0  
AD1848K  
FREQ UENCY RESP O NSE P LO TS  
10  
0
10  
0
–10  
–20  
–30  
–40  
–10  
–20  
–30  
–40  
–50  
–60  
–70  
–80  
–90  
–50  
dB  
dB  
–60  
–70  
–80  
–90  
–100  
–110  
–120  
–100  
–110  
–120  
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
0.0  
0.1  
0.2  
0.3  
0.4  
0.5  
0.6  
0.7  
0.8  
0.9  
1.0  
SAMPLE FREQUENCY (F  
)
SAMPLE FREQUENCY (F  
)
S
S
Figure 26. AD1848K Analog-to-Digital Frequency  
Response (Full-Scale Line-Level Inputs, 0 dB Gain)  
Figure 28. AD1848K Digital-to-Analog Frequency  
Response (Full-Scale Inputs, 0 dB Attenuation)  
10  
0
10  
0
–10  
–20  
–30  
–40  
–10  
–20  
–30  
–40  
–50  
dB  
–50  
dB  
–60  
–60  
–70  
–80  
–70  
–80  
–90  
–90  
–100  
–110  
–100  
–110  
–120  
–120  
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60  
0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60  
SAMPLE FREQUENCY (F  
)
SAMPLE FREQUENCY (F  
)
S
S
Figure 27. AD1848K Analog-to-Digital Frequency  
Response—Transition Band (Full-Scale Line-Level  
Inputs, 0 dB Gain)  
Figure 29. AD1848K Digital-to-Analog Frequency  
Response—Transition Band (Full-Scale Inputs, 0 dB  
Attenuation)  
REV. 0  
–27–  
AD1848K  
O UTLINE D IMENSIO NS  
D imensions shown in inches and (mm).  
P -68A  
ST-64  
68-Lead P lastic Leaded Chip Car r ier  
64-Lead Thin Q uad Flatpack  
0.175 (4.45)  
0.063 (1.60) MAX  
0.995 (25.27)  
0.630 ± 0.009  
(16.00 ± 0.25)  
0.169 (4.29)  
SQ  
SQ  
SQ  
0.885 (22.48)  
0.055 ± 0.002  
(1.40 ± 0.05)  
0.551 ± 0.004  
(14.00 ± 0.10)  
9
61  
60  
10  
PIN 1  
IDENTIFIER  
0.050  
(1.27)  
TYP  
0.024  
±
0.006  
(0.60 ± 0.15)  
64  
49  
1
48  
SEATING  
PLANE  
0.925 (23.50)  
0.895 (22.73)  
12  
TYP  
°
TOP VIEW  
0.019 (0.48)  
0.017 (0.43)  
TOP VIEW  
0.029 (0.74)  
0.027 (0.69)  
26  
44  
27  
43  
0.954 (24.23)  
0.950 (24.13)  
SQ  
0.104 (2.64) TYP  
0.004 (0.102)  
MAX  
LEAD  
COPLANARITY  
16  
33  
17  
32  
6
°
± 4  
°
0
°
– 7  
°
0.031 (0.80)  
0.014 (0.35)  
0.007 (0.17) MAX  
IND EX  
P AGE  
PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
ELECT RICAL SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . 2  
ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
PINOUT S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
PIN DESCRIPT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
AUDIO FUNCT IONAL DESCRIPT ION . . . . . . . . . . . . . . 9  
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Analog Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . . . . 9  
Digital-to-Analog Datapath . . . . . . . . . . . . . . . . . . . . . . . . 9  
Digital Mixing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Digital Data T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Power Supplies and Voltage Reference . . . . . . . . . . . . . . . 10  
Clocks and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . . 10  
CONT ROL REGIST ERS . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Control Register Architecture . . . . . . . . . . . . . . . . . . . . . . 11  
Direct Control Register Definitions . . . . . . . . . . . . . . . . . 12  
Indirect Control Register Definitions . . . . . . . . . . . . . . . . 14  
DAT A AND CONT ROL T RANSFERS . . . . . . . . . . . . . . . 21  
Data Ordering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21  
Control and Programmed I/O (PIO) T ransfers . . . . . . . . 21  
Direct Memory Access (DMA) T ransfers . . . . . . . . . . . . . 22  
Single-Channel DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
DMA T iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22  
DMA Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
POWER UP AND RESET . . . . . . . . . . . . . . . . . . . . . . . . . 24  
AUT OCALIBRAT ION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24  
CHANGING SAMPLE RAT ES . . . . . . . . . . . . . . . . . . . . . 24  
APPLICAT IONS CIRCUIT S . . . . . . . . . . . . . . . . . . . . . . . 25  
FREQUENCY RESPONSE PLOT S . . . . . . . . . . . . . . . . . 27  
PACKAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28  
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REV. 0  

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