AD1849KP_技术文档

Serial-Port 16-Bit

SoundPort Stereo Codec

a

AD1849K

FEATURES

speaker and stereo headphone drive circuits that require no

additional external components. Dynamic range exceeds 80 dB

over the 20 kHz audio band. Sample rates from 5.5 kHz to

48 kHz are supported from external crystals, from an external

clock, or from the serial interface bit clock.

Single-Chip Integrated ⌺⌬ Digital Audio Stereo Codec

Multiple Channels of Stereo Input and Output

Digital Signal Mixing

On-Chip Speaker and Headphone Drive Capability

Program m able Gain and Attenuation

On-Chip Signal Filters

T he Codec includes a stereo pair of Σ∆ analog-to-digital

converters and a stereo pair of Σ∆ digital-to-analog converters.

Analog signals can be input at line levels or microphone levels.

A software controlled programmable gain stage allows

independent gain for each channel going into the ADC. T he

ADCs’ output can be digitally mixed with the DACs’ input.

Digital Interpolation and Decim ation

Analog Output Low -Pass

Sam ple Rates from 5.5 kHz to 48 kHz

44-Lead PLCC and TQFP Packages

Operation from +5 V and Mixed +5 V/ +3.3 V Supplies

Serial Interface Com patible w ith ADSP-21xx Fixed-

Point DS␮Ps

T he left and right channel 16-bit outputs from the ADCs are

available over a single bidirectional serial interface that also sup-

ports 16-bit digital input to the DACs and control information.

T he AD1849K can accept and generate 8-bit µ-law or A-law

companded digital data.

Com patible w ith CS4215 (See Text)

P RO D UCT O VERVIEW

T he Serial-Port AD1849K SoundPort® Stereo Codec integrates

the key audio data conversion and control functions into a single

integrated circuit. T he AD1849K is intended to provide a com-

plete, single-chip audio solution for multimedia applications

requiring operation from a single +5 V supply. External signal

path circuit requirements are limited to three low tolerance

capacitors for line level applications; anti-imaging filters are

incorporated on-chip. The AD1849K includes on-chip monaural

T he Σ∆ DACs are preceded by a digital interpolation filter. An

attenuator provides independent user volume control over each

DAC channel. Nyquist images and shaped quantization noise

are removed from the DACs’ analog stereo output by on-chip

switched-capacitor and continuous-time filters. Two independent

stereo pairs of line-level (or one line-level and one headphone)

outputs are generated, as well as drive for a monaural (mono)

speaker.

SoundPort is a registered trademark of Analog Devices, Inc.

(Continued on page 8)

FUNCTIO NAL BLO CK D IAGRAM

DIGITAL

SUPPLY

ANALOG

SUPPLY

CRYSTALS

POWER DOWN

2

DIGITAL

I/O

LINE L

LINE R

OSCILLATORS

L

DATA/CONTROL

MODE

∑∆ A/D

µ/A

ANALOG

OUT

GAIN

CONVERTER

LAW

MIC L

MIC R

20

DATA/CONTROL

TRANSMIT

MUX

dB

R

S

∑∆ A/D

CONVERTER

µ/A

LAW

E

R

I

L

O

P

B

A

C

K

LOOPBACK

A

L

MONITOR MIX

P

O

R

T

L

∑∆ D/A

CONVERTER

ANALOG

FILTER

µ/A

LAW

∑

ATTENUATE

INTERPOL ATTENUATE

LINE 0 L

MUTE

DATA/CONTROL

RECEIVE

R

L

∑∆ D/A

CONVERTER

ANALOG

FILTER

µ/A

LAW

LINE 0 R

LINE 1 L

∑

INTERPOL ATTENUATE

2

PARALLEL I/O

BIT CLOCK

ANALOG

IN

FRAME SYNC

∑

MUTE

HEADPHONE RETURN

LINE 1 R

R

AD1849K

REFERENCE

RESET

OUT

RETURN

MONO SPEAKER

CHAINING CHAINING

OUTPUT INPUT

2.25V

REV. 0

Inform ation furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assum ed by Analog Devices for its

use, nor for any infringem ents of patents or other rights of third parties

which m ay result from its use. No license is granted by im plication or

otherwise under any patent or patent rights of Analog Devices.

One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.

Tel: 617/ 329-4700 Fax: 617/ 326-8703

AD1849K–SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

STAND ARD TEST CO ND ITIO NS UNLESS O TH ERWISE NO TED

T emperature

25

5.0

256

°C

V

DAC Input Conditions

0 dB Attenuation

Full-Scale Digital Inputs

16-Bit Linear Mode

OLB = 1

Digital Supply (V_DD

Analog Supply (V_CC

Clock (SCLK)

Master Mode

)

F_S

256 Bits per Frame

Word Rate (F_S)

Input Signal

48

1

kHz

ADC Input Conditions

0 dB PGA Gain

Analog Output Passband

V_IH

V_IL

External Load Impedance

(Line 0)

20 Hz to 20 kHz

–3.0 dB Relative to Full Scale

Line Input

16-Bit Linear Mode

2.4

0.8

10

V

kΩ

All tests are performed on all ADC and DAC channels.

External Load Impedance

(Line 1)

48

Ω

External Load Capacitance

(Line 0, 1)

100

pF

ANALO G INP UT

Min

Typ

Max

Units

Input Voltage*

(RMS Values Assume Sine Wave Input)

Line and Mic with 0 dB Gain

0 94

2.66

0.094

0.266

0.99

2.80

0.099

0.280

1.04

2.94

0.104

0.294

15

V rms

V p-p

V rms

V p-p

pF

Mic with +20 dB Gain

Input Capacitance

*Accounts for Sum of Worst Case Reference Errors and Worst Case Gain Errors.

P RO GRAMMABLE GAIN AMP LIFIER—AD C

Min

Typ

Max

Units

Step Size (0 dB to 22.5 dB)

(All Steps T ested, –30 dB Input)

PGA Gain Range*

1.3

1.5

1.7

dB

Line and Mic with 0 dB Gain

Mic with +20 dB Gain

–0.2

19.8

22.7

42.7

dB

D IGITAL D ECIMATIO N AND INTERP O LATIO N FILTERS*

Min

Max

Units

Passband

0

0.45 × F_S

±0.1

0.55 × F_S

Hz

dB

Hz

dB

Passband Ripple

T ransition Band

Stopband

Stopband Rejection

Group Delay

0.45 × F_S

≥0.55 × F_S

74

30/F_S

0.0

Group Delay Variation Over Passband

µs

–2–

REV. 0

AD1849K

ANALO G-TO -D IGITAL CO NVERTERS

Min

Typ

16

Max

Units

Resolution*

Bits

dB

ADC Dynamic Range, A-Weighted

Line and Mic with 0 dB Gain (–60 dB Input,

T HD+N Referenced to Full Scale)

Mic with +20 dB Gain (–60 dB Input,

T HD+N Referenced to Full Scale)

78

72

83

74

dB

ADC T HD+N, (Referenced to Full Scale)

Line and Mic with 0 dB Gain

0.013

–78

0.032

–70

0.020

–74

0.056

–65

%

dB

%

Mic with +20 dB Gain

dB

ADC Crosstalk

Line to Line (Input L, Ground R,

Read R; Input R, Ground L, Read L)

Line to Mic (Input LINL & R,

Ground and Select MINL & R,

Read Both Channels)

–80

–60

dB

Gain Error (Full-Scale Span Relative to Nominal)

0.75

0.3

dB

ADC Interchannel Gain Mismatch (Line and Mic)

(Difference of Gain Errors)

D IGITAL-TO -ANALO G CO NVERTERS

Min

Typ

Max

Units

Resolution*

16

Bits

DAC Dynamic Range

(–60 dB Input, T HD+N Referenced

to Full Scale)

80

86

dB

DAC T HD+N (Referenced to Full Scale)

Line 0 and 1 (10 kΩ Load)

0.010

–80

0.022

–73

0.045

–67

0.020

–74

0.100

–60

0.100

–60

%

dB

%

dB

%

dB

Line 1 (48 Ω Load)

Mono Speaker (48 Ω Load)

DAC Crosstalk (Input L, Zero R, Measure

LOUT 0R & 1R; Input R, Zero L,

Measure LOUT 0L & 1L)

–80

dB

Gain Error (Full-Scale Span Relative to Nominal)

0.75

0.3

dB

DAC Interchannel Gain Mismatch (Line 0 and 1)

(Difference of Gain Errors)

T otal Out-of-Band Energy*

(Measured from 0.55 × F_Sto 100 kHz)

–60

–72

dB

Audible Out-of-Band Energy*

(Measured from 0.55 F_Sto 22 kHz,

All Selectable Sampling Frequencies)

*Guaranteed, not tested.

REV. 0

–3–

AD1849K

MO NITO R MIX ATTENUATO R

Min

Typ

Max

Units

Step Size (0.0 dB to –60 dB)*

Step Size (–61.5 dB to –94.5 dB)*

Output Attenuation*

1.3

1.0

–95

1.5

1.7

2.0

0.2

dB

D AC ATTENUATO R

Min

Typ

Max

Units

Step Size (0.0 dB to –60 dB)

(T ested at Steps –1.5 dB, –19.5 dB,

–39 dB and –60 dB)

1.3

1.5

1.7

dB

Step Size (–61.5 dB to –94.5 dB)*

Output Attenuation*

1.0

–95

1.5

2.0

0.2

dB

SYSTEM SP ECIFICATIO NS

Min

Typ

Max

Units

System Frequency Response*

(Line In to Line Out,

–0.5

+0.2

dB

0 to 0.45 × F_S)

Differential Nonlinearity*

Phase Linearity Deviation*

±0.9

5

LSB

Degrees

ANALO G O UTP UT

Min

Typ

Max

Units

Full-Scale Output Voltage (Line 0 & 1)

[OLB = 1]

Full-Scale Output Voltage (Line 0)

[OLB = 0]

Full-Scale Output Voltage (Line 1)

[OLB = 0]

0.707

2.0

1.0

2.8

4.0

V rms

V p-p

V rms

V p-p

1.85

2.1

Full-Scale Output Voltage (Mono Speaker)

[OLB = 1]

Full-Scale Output Voltage (Mono Speaker)

[OLB = 0]

4.0

8.0

V p-p

CMOUT Voltage (No Load)

CMOUT Current Drive*

CMOUT Output Impedance

Mute Attenuation of 0 dB

Fundamental* (LINE 0, 1, & MONO)

1.80

2.25

100

4

2.50

–80

V

µA

kΩ

dB

STATIC D IGITAL SP ECIFICATIO NS

Min

Max

Units

High Level Input Voltage (V_IH

Digital Inputs

XT AL1/2I

)

2.4

–0.3

2.4

(V_DD+) + 0.3

0.8

V

µA

Low Level Input Voltage (V_IL)

High Level Output Voltage (V_OH) at I_OH= –2 mA

Low Level Output Voltage (V_OL) at I_OL= 2 mA

Input Leakage Current

(GO/NOGO T ested)

Output Leakage Current

0.4

10

–10

10

µA

(GO/NOGO T ested)

–4–

REV. 0

AD1849K

D IGITAL TIMING P ARAMETERS (Guar anteed over +4.75 V to +5.25 V, 0؇C to +70؇C)

Min

Typ

Max

Units

SCLK Period (t_CLK

)

Slave Mode, MS = 0

Master Mode, MS = 1*

SCLK HI (t_HI)*

80

ns

s

1/(F_S× Bits per Frame)

Slave Mode, MS = 0

SCLK LO (t_LO)*

Slave Mode, MS = 0

CLKIN Frequency

CLKIN HI

CLKIN LO

Crystals Frequency

Input Setup T ime (t_S)

25

ns

MHz

ns

13.5

27

30

ns

15

10

ns

ms

ns

Input Hold T ime (t_IH

Output Delay (t_D)

)

25

Output Hold T ime (t_OH

Output Hi-Z to Valid (t_ZV

Output Valid to Hi-Z (t_VZ

Power Up RESET LO T ime

Operating RESET LO T ime

)

0

15

)

20

50

100

P O WER SUP P LY

Min

Typ

Max

Units

Power Supply Voltage Range*

4.75

5.25

V

–Digital and Analog

Power Supply Current—Operating

(50% I_VDD, 50% I_VCC, Unloaded Outputs)

Power Supply Current—Power Down

Power Supply Rejection (@ 1 kHz)*

(At Both Analog and Digital

100

20

130

200

mA

µA

dB

40

Supply Pins, Both ADCs and DACs)

CLO CK SP ECIFICATIO NS*

Min

Max

Units

Input Clock Frequency, Crystals

Clock Duty Cycle T olerance

Sample Rate (F_S)

27

±10

50

MHz

%

kHz

5.5125

*Guaranteed, not tested.

Specifications subject to change without notice.

REV. 0

–5–

AD1849K

ABSO LUTE MAXIMUM RATINGS*

44-Lead P lastic Leaded Chip Car r ier P inout

Min

Max

Units

0.180 (4.57)

0.165 (4.19)

0.056 (1.42)

0.042 (1.07)

0.048 (1.21)

0.042 (1.07)

Power Supplies

0.025 (0.63)

0.015 (0.38)

0.020 (0.50)

R

Digital (V_DD

Analog (V_CC

)

–0.3

6.0

V

0.048 (1.21)

0.042 (1.07)

6

40

39

1

7

IDENTIFIER

1

0.021 (0.53)

0.013 (0.33)

Input Current

IDENTIFIER

(Except Supply Pins and MOUT ,

MOUT R, LOUT 1R, LOUT 1L,

LOUT 1C)

±10.0

mA

0.63 (16.00)

0.59 (14.99)

0.032 (0.81)

BOTTOM VIEW

Analog Input Voltage (Signal Pins)

Digital Input Voltage (Signal Pins)

Ambient T emperature (Operating)

Storage T emperature

ESD T olerance (Human Body

Model per Method 3015.2

of MIL-ST D-883B)

–0.3

0

–65

500

(V_CC+) + 0.3

(V_DD+) + 0.3

+70

V

°C

V

TOP VIEW

0.026 (0.66)

0.050

(1.27)

BSC

+150

17

29

28

18

0.040 (1.01)

0.025 (0.64)

0.656 (16.66)

0.650 (16.51)

SQ

0.110 (2.79)

0.085 (2.16)

0.695 (17.65)

0.685 (17.40)

WARNING: CMOS device. May be susceptible to high voltage

transient-induced latchup.

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause

permanent damage to the device. T his is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

44-Lead TQ FP

44 43 42 41 40 39 38 37 36 35 34

O RD ERING GUID E

1

33

GNDD

V_DD

COUT1

V_DD

Tem perature

Range

P ackage

D escription

P ackage

O ption

2

3

32

31

30

29

28

27

26

25

24

23

Model

GNDD

CIN2

PIO1

4

5

PIO0

AD1849KP 0°C to +70°C

44-Lead PLCC

P-44A

AD1849KST

SoundPort®

STEREO CODEC

COUT2

RESET

PDN

D/C

6

7

N/C

LOUT0R

LOUT0L

LOUT1L

8

C0

9

MINR

LINR

10

11

LOUT1C

LOUT1R

MINL

12 13 14 15 16 17 18 19 20 21 22

N/C = NO CONNECT

CAUTIO N

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection.

Although the AD1849K features proprietary ESD protection circuitry, permanent damage may

occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD

precautions are recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–6–

REV. 0

AD1849K

P IN D ESCRIP TIO N

D igital Signals

P in Nam e

P LCC

TQFP

I/O

D escription

SDRX

SDT X

SCLK

FSYNC

T SOUT

T SIN

1

39

38

37

36

35

34

29

44

1

4

5

42

43

7

I

Receive Serial Data Pin

T ransmit Serial Data Pin

Bidirectional Serial Bit Clock

Frame Sync Output Signal

Chaining Word Output

Chaining Word Input

Data/Control Select Input

Crystal 1 Input

Crystal 1 Output

44

43

42

41

40

35

6

O

I/O

O

I

O

I

O

I

O

I

I/O

D/C

CIN1

COUT 1

CIN2

COUT 2

CLKIN

CLKOUT

PDN

RESET

PIO1

PIO0

7

10

11

4

Crystal 2 Input

Crystal 2 Output

External Sample Clock Input (256 × F_S)

External Sample Clock Output (256 × F_S)

Power Down Input (Active HI)

Reset Input (Active LO)

Parallel Input/Output Bit 1

Parallel Input/Output Bit 0

5

13

12

37

36

6

31

30

Analog Signals

P in Nam e

P LCC

TQFP

I/O

D escription

LINL

LINR

MINL

18

16

17

12

10

11

I

Left Channel Line Input

Right Channel Line Input

Left Channel Microphone Input (–20 dB from Line Level if MB = 0 or Line

Level if MB = 1)

MINR

15

9

I

Right Channel Microphone Input (–20 dB from Line Level if MB = 0 or Line

Level if MB = 1)

LOUT 0L

LOUT 0R

LOUT 1L

LOUT 1R

LOUT 1C

MOUT

MOUT R

C0

C1

N/C

V_REF

32

33

31

29

30

27

28

14

20

26

34

21

19

26

27

25

23

24

21

22

8

14

20

28

15

13

O

I

O

I

O

Left Channel Line Output 0

Right Channel Line Output 0

Left Channel Line Output 1

Right Channel Line Output 1

Common Return Path for Large Current from External Headphones

Mono Speaker Output

Mono Speaker Output Return

External 1.0 µF Capacitor (±10%) Connection

No Connect (Do Not Connect)

Voltage Reference (Connect to Bypass Capacitor)

Common Mode Reference Datum Output (Nominally 2.25 V)

O

CMOUT

P ower Supplies

P in Nam e

P LCC

TQFP

I/O

D escription

V_CC

GNDA

V_DD

23 & 24

22 & 25

3, 8, 38

2, 9, 39

17, 18

16, 19

41, 2, 32

40, 3, 33

I

Analog Supply Voltage (+5 V)

Analog Ground

Digital Supply Voltage (+5 V)

Digital Ground

GNDD

REV. 0

–7–

AD1849K

(Continued from page 1)

Monitor Mix

A monitor mix is supported that digitally mixes a portion of the

digitized analog input with the analog output (prior to digitiza-

tion). T he digital output from the ADCs going out of the serial

data port is unaffected by the monitor mix. Along the monitor

mix datapath, the 16-bit linear output from the ADCs is

attenuated by an amount specified with control bits. Both

channels of the monitor data are attenuated by the same

amount. (Note that internally the AD1849K always works with

16-bit PCM linear data, digital mixing included; format

conversions take place at the input and output.)

FUNCTIO NAL D ESCRIP TIO N

T his section overviews the functionality of the AD1849K and is

intended as a general introduction to the capabilities of the

device. As much as possible, detailed reference information has

been placed in “Control Registers” and other sections. T he user

is not expected to refer repeatedly to this section.

Analog Inputs

T he AD1849K SoundPort Stereo Codec accepts stereo

line-level and mic-level inputs. T hese analog stereo signals are

multiplexed to the internal programmable gain amplifier (PGA)

stage. T he mic inputs can be amplified by +20 dB prior to the

PGA to compensate for the voltage swing difference between

line levels and typical condenser microphones. T he mic inputs

can bypass the +20 dB fixed gain block and go straight to the

input multiplexer, which often results in an improved system

signal-to-noise ratio.

Sixteen steps of –6 dB attenuation are supported to –94.5 dB. A

“0” implies no attenuation, while a “14” implies 84 dB of

attenuation. Specifying full scale “15” completely mutes the

monitor datapath, preventing any mixing of the analog input

with the digital input. Note that the level of the mixed output

signal is also a function of the input PGA settings since they

affect the ADCs’ output.

T he PGA following the input multiplexer allows independent

selectable gains for each channel from 0 to 22.5 dB in +1.5 dB

steps. T he Codec can operate either in a global stereo mode or

in a global mono mode with left-channel inputs appearing at

both channel outputs.

T he attenuated monitor data is digitally summed with the DAC

input data prior to the DACs’ datapath attenuators. Because

both stereo signals are mixed before the output attenuators, mix

data is attenuated a second time by the DACs’ datapath

attenuators. T he digital sum of digital mix data and DAC input

data is clipped at plus or minus full scale and does not wrap

around.

Analog-to-D igital D atapath

T he AD1849K ∑∆ ADCs incorporate a proprietary fourth-order

modulator. A single pole of passive filtering is all that is required

for anti-aliasing the analog input because of the ADC’s high 64

times oversampling ratio. T he ADCs include linear-phase digital

decimation filters that low-pass filter the input to 0.45 × F_S

(“F_S” is the word rate or “sampling frequency”). ADC input

overrange conditions will cause a sticky bit to be set that can be

read.

Analog O utputs

One stereo line-level output, one stereo headphone output, and

one monaural (mono) speaker output are available at external

pins. Each of these outputs can be independently muted.

Muting either the line-level stereo output or the headphone

stereo output mutes both left and right channels of that output.

When muted, the outputs will settle to a dc value near

CMOUT , the midscale reference voltage. T he mono speaker

output is differential. T he chip can operate either in a global

stereo mode or in a global mono mode with left channel inputs

appearing at both outputs.

D igital-to-Analog D atapath

T he ∑∆ DACs are preceded by a programmable attenuator and

a low-pass digital interpolation filter. T he attenuator allows

independent control of each DAC channel from 0 dB to –94.5 dB

in 1.5 dB steps plus full digital mute. T he anti-imaging inter-

polation filter oversamples by 64 and digitally filters the higher

frequency images. T he DACs’ ∑∆ noise shapers also oversample

by 64 and convert the signal to a single-bit stream. T he DAC

outputs are then filtered in the analog domain by a combination

of switched-capacitor and continuous-time filters. T hey remove

the very high frequency components of the DAC bitstream

output, including both images at the oversampling rate and

shaped quantization noise. No external components are required.

Phase linearity at the analog output is achieved by internally

compensating for the group delay variation of the analog output

filters.

D igital D ata Types

T he AD1849K supports four global data types: 16-bit twos-

complement linear PCM, 8-bit unsigned linear PCM, 8-bit

companded µ-law, and 8-bit companded A-law, as specified by

control register bits. Data in all four formats is always trans-

ferred MSB first. Sixteen-bit linear data output from the ADCs

and input to the DACs is in twos-complement format. Eight-bit

data is always left-justified in 16-bit fields; in other words, the

MSBs of all data types are always aligned; in yet other words,

full-scale representations in all three formats correspond to

equivalent full-scale signals. T he eight least-significant bit

positions of 8-bit linear and companded data in 16-bit fields are

ignored on input and zeroed on output.

Attenuation settings are specified by control bits in the data

stream. Changes in DAC output level take effect only on zero

crossings of the digital signal, thereby eliminating “zipper”

noise. Each channel has its own independent zero-crossing

detector and attenuator change control circuitry. A timer

guarantees that requested volume changes will occur even in the

absence of an input signal that changes sign. T he time-out

period is 10.7 milliseconds at a 48 kHz sampling rate and 64

milliseconds at an 8 kHz sampling rate (T ime-out [ms] ≈ 512/

Sampling Rate [kHz]).

T he 16-bit PCM data format is capable of representing 96 dB of

dynamic range. Eight-bit PCM can represent 48 dB of dynamic

range. Companded µ-law and A-law data formats use nonlinear

coding with less precision for large-amplitude signals. T he loss

of precision is compensated for by an increase in dynamic range

to 64 dB and 72 dB, respectively.

–8–

REV. 0

AD1849K

On input, 8-bit companded data is expanded to an internal

linear representation, according to whether µ-law or A-law was

specified in the Codec’s internal registers. Note that when µ-law

compressed data is expanded to a linear format, it requires 14

bits. A-law data expanded requires 13 bits, see Figure 1.

Autocalibr ation

The AD1849K supports an autocalibration sequence to eliminate

DAC and ADC offsets. T he autocalibration sequence is

initiated in the transition from Control Mode to Data Mode,

regardless of the state of the AC bit. T he user should specify

that analog outputs be muted to prevent undesired outputs.

Monitor mix will be automatically disabled by the Codec.

15

0

8

7

COMPRESSED

INPUT DATA

MSB

LSB

During the autocalibration sequence, the serial data output from

the ADCs is meaningless and the ADI bit is asserted. Serial data

inputs to the DACs are ignored. Even if the user specified the

muting of all analog outputs, near the end of the autocalibration

sequence, dc analog outputs very close to CMOUT will be

produced at the line outputs and mono speaker output.

15

EXPANSION MSB

3/2 2/1

LSB

15

MSB

3/2 2/1

LSB

DAC INPUT

0 0 0 / 0 0

An autocalibration sequence is also performed when the

AD1849K leaves the reset state (i.e., RESET goes HI). T he

RESET pin should be held LO for 50 ms after power up or after

leaving power-down mode to delay the onset of the autocalibration

sequence until after the voltage reference has settled.

Figure 1. A-Law or µ-Law Expansion

When 8-bit companding is specified, the ADCs’ linear output is

compressed to the format specified prior to output. See Figure 2.

Note that all format conversions take place at input or output.

Internally, the AD1849K always uses 16-bit linear PCM

representations to maintain maximum precision.

Loopback

Digital and analog loopback modes are supported for device and

system testing. T he monitor mix datapath is always available for

loopback test purposes. Additional loopback tests are enabled by

setting the ENL bit (Control Word Bit 33) to a “1.”

15

MSB

0

ADC OUTPUT

LSB

Analog loopback mode D-A-D is enabled by setting the ADL

bit (Control Word Bit 32) to a “1” when ENL is a “1.” In this

mode, the DACs’ analog outputs are re-input to the PGAs prior

to the ADCs, allowing digital inputs to be compared to digital

outputs. T he monitor mix will be automatically disabled by the

Codec during D-A-D loopback. T he analog outputs can be

individually attenuated, and the analog inputs are internally

disconnected. Note that muting the line 0 output mutes the

looped-back signal in this mode.

15

MSB

3/2

2/1

TRUNCATION

LSB

15

MSB

8

7

LSB

0 0 0 0 0 0 0 0

COMPRESSION

Figure 2. A-Law or µ-Law Com pression

P ower Supplies and Voltage Refer ence

The AD1849K operates from +5 V power supplies. Independent

analog and digital supplies are recommended for optimal

performance, though excellent results can be obtained in single

supply systems. A voltage reference is included on the Codec

and its 2.25 V buffered output is available on an external pin

(CMOUT ). T he CMOUT output can be used for biasing op

amps used in dc coupling. T he internal reference is externally

bypassed to analog ground at the V_REFpin. Note that V_REF

should only be connected to its bypass capacitors.

Digital loopback mode D-D is enabled by resetting the ADL bit

(Control Word Bit 32) to a “0” when ENL is a “1.” In this

mode, the control and data bit pattern presented on the SDRX

pin is echoed on the SDT X pin with a two frame delay, allowing

the host controller to verify the integrity of the serial interface

starting on the third frame after D-D loopback is enabled.

During digital loopback mode, the output DACs are

operational.

REV. 0

–9–

AD1849K

T he loopback modes are shown graphically in Figure 3.

Clocks and Sam ple Rates

T he AD1849K can operate from external crystals, from a 256 ×

F_Sinput clock, from an input clock with a programmable divide

factor, or from the serial port’s bit clock (at 256 × F_S), selected

under software control. T wo crystal inputs are provided to

generate a wide range of sample rates. T he oscillators for these

crystals are on the AD1849K, as is a multiplexer for selecting

between them. T hey can be overdriven with external clocks by

the user, if so desired. T he recommended crystal frequencies are

16.9344 MHz and 24.576 MHz. From them the following sample

rates can be internally generated: 5.5125, 6.615, 8, 9.6, 11.025,

16, 18.9, 22.05, 27.42857, 32, 33.075, 37.8, 44.1, 48 kHz.

Regardless of clock input source, a clock output of 256 × F_Sis

generated (with some skew). If an external input clock or the

serial port’s bit clocks are selected to drive the AD1849K’s

internal operation, they should be low jitter clocks. If no

external clock will be used, Analog Devices recommends tying

the clock input pin (CLKIN) to ground. If either external

crystal is not used, Analog Devices recommends tying its input

(CIN1 and/or CIN2) to ground.

µ/A-LAW

ENCODE

SDTX

SDRX

LINE, MIC

INPUT

GAIN

A/D

DISCONNECTED

MONITOR

DISABLE

AD1849K

MUTE

0

1

LINE 0

OUTPUT

LINE 1

µ/A-LAW

DECODE

Σ

D/A

FUNCTIONAL

AD1849K Analog Loopback D-A-D

µ/A-LAW

ENCODE

GAIN

SDTX

SDRX

LINE, MIC

INPUT

A/D

AD1849K

MONITOR

LINE 0,

LINE 1

µ/A-LAW

DECODE

Σ

D/A

MUTE

OUTPUT

FUNCTIONAL

AD1849K Digital Loopback D-D

Figure 3. AD1849K Loopback Modes

–10–

REV. 0

AD1849K

CO NTRO L REGISTERS

T he AD1849K SoundPort Stereo Codec accepts control information through its serial port when in Control Mode. Some control

information is also embedded in the data stream when in Data Mode. (See Figure 8.) Control bits can also be read back for system

verification. Operation of the AD1849K is determined by the state of these control bits. T he 64-bit serial Control Mode and Data

Mode control registers have been arbitrarily broken down into bytes for ease of description. All control bits initialize to default states

after RESET or Power Down. T hose control bits that cannot be changed in Control Mode are initialized to defaults on the transition

from Data Mode to Control Mode. See below for a definition of these defaults.

Contr ol Mode Contr ol Register s

Contr ol Byte 1, Sta tus Register

D ata 7

D ata 6

D ata 5

D ata 4

MB

D ata 3

OLB

59

D ata 2

D CB

58

D ata 1

D ata 0

AC

0

1

0

63

62

61

60

57

56

MB

Mic bypass:

0

1

Mic inputs applied to +20 dB fixed gain block.

Mic inputs bypass +20 dB fixed gain block.

OLB

Output level bit:

0

Full-scale line 0 output is 2.8 V p-p (1 V rms).

Full-scale line 1 output is 4.0 V p-p.

Full-scale mono speaker output is 8.0 V p-p.

Full-scale line 0 output is 2.0 V p-p.

Full-scale line 1 output is 2.0 V p-p.

Full-scale mono speaker output is 4.0 V p-p.

1

DCB

AC

Data/control bit. Used for handshaking in data/control transitions. See “DCB Handshake Protocol.”

Autocalibration.

Autocalibration will always occur on the Control-to-Data mode transition. T he AC bit is ignored. Autocalibration

requires an interval of 194 frames. Offsets for all channels of ADC and DAC are zeroed. T he user should specify that

analog outputs are muted to prevent undesired outputs, i.e., OM0 = “0,” OM1 = “0,” and SM =“0.” Monitor mix will

be automatically disabled by the Codec.

REV. 0

–11–

AD1849K

Contr ol Byte 2, Da ta For m a t Register

D ata 7

D ata 6

D ata 5

D FR2

53

D ata 4

D FR1

52

D ata 3

D FR0

51

D ata 2

ST

D ata 1

D F1

49

D ata 0

D F0

48

0

55

54

50

DFR2:0

Data conversion frequency (F_S) select tin kHz):

D FR

D ivide Factor

XTAL1 (24.576 MH z)

XTAL2 (16.9344 MH z)

0

1

2

3

4

5

6

7

3072

1536

896

768

448

384

512

2560

8

16

5.5125

11.025

18.9

22.05

37.8

44.1

33.075

6.615

27.42857

32

N/A

48

9.6

Note that the AD1849K’s internal oscillators can be overdriven by external clock sources at the crystal input pins. If an

external clock source is used, it should be applied to the crystal input pin (CIN1 or CIN2), and the crystal output pin

(COUT 1 or COUT 2) should be left unconnected. T he external clock source need not be at the recommended crystal

frequencies, and it will be divided down by the selected Divide Factor.

ST

Global stereo mode. Both converters are placed in the same mode.

0

1

Mono mode. The left analog input appears at both ADC outputs. The left digital input appears at both DAC outputs.

Stereo mode

DF1:0

Codec data format selection:

0

1

2

3

16-bit twos-complement PCM linear

8-bit µ-law companded

8-bit A-law companded

8-bit unsigned PCM linear

Contr ol Byte 3, Ser ia l Por t Contr ol Register

D ata 7

D ata 6

MCK2

46

D ata 5

MCK1

45

D ata 4

MCK0

44

D ata 3

FSEL1

43

D ata 2

FSEL0

42

D ata 1

MS

D ata 0

T XD IS

40

IT S

47

41

IT S

Immediate three-state:

0

1

FSYNC, SDT X and SCLK three-state within 3 SCLK cycles after D/C goes LO

FSYNC, SDT X and SCLK three-state immediately after D/C goes LO

MCK2:0 Clock source select for Codec internal operation:

0

1

2

3

4

Serial bit clock (SCLK) is the master clock at 256 × F_S

24.576 MHz crystal (XT AL1) is the clock source

16.9344 MHz crystal (XT AL2) is the clock source

External clock (CLKIN) is the clock source at 256 × F_S

External clock (CLKIN) is the clock source, divided by the factor selected by DFR2:0

(External clock must be stable and valid within 2000 periods after it is selected.)

FSEL1:0 Frame size select:

0

1

2

3

64 bits per frame

128 bits per frame

256 bits per frame

Reserved

Note that FSEL is overridden in Data Mode when SCLK is the clock source (MCK = “0”). When SCLK is

providing the 256 × F_Sclock for internal Codec operation, 256 bits per frame is effectively selected, regardless of

FSEL’s contents.

MS

Master/slave mode for the serial interface:

0

1

Receive serial clock (SCLK) and T SIN from an external device (“slave mode”)

T ransmit serial clock (SCLK) and frame sync (FSYNC) to external devices (“master mode”)

Note that MS is overridden when SCLK is the clock source (MCK = “0”). When SCLK is providing the clock for

internal Codec operation, slave mode is effectively selected, regardless of the contents of MS.

T ransmitter disable:

T XDIS

0

1

Enable serial output

T hree-state serial data output (high impedance)

Note that Control Mode overrides T XDIS. In Control Mode, the serial output is always enabled.

–12–

REV. 0

AD1849K

Contr ol Byte 4, Test Register

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

ENL

33

D ata 0

ADL

32

0

39

38

37

36

35

34

ENL

ADL

Enable loopback testing:

0

1

Disabled

Enabled

Loopback mode:

0

1

Digital loopback from Data/Control receive to Data/Control transmit (D-D)

Analog loopback from DACs to ADCs (D-A-D)

Contr ol Byte 5, Pa r a llel Por t Register

D ata 7

PIO1

31

D ata 6

PIO0

30

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0

29

28

27

26

25

24

PIO1:0 Parallel I/O bits for system signaling. PIO bits do not affect Codec operation.

Contr ol Byte 6, Reser ved Register

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0

23

22

21

20

19

18

17

16

Reserved bits should be written as 0.

Contr ol Byte 7, Revision Register

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

REVID3

11

D ata 2

REVID2

10

D ata 1

REVID1

9

D ata 0

REVID0

8

0

1

0

15

14

13

12

REVID3:0

Silicon revision identification. Reads greater than or equal to 0010 (i.e., 0010, 0011, etc.) for the AD1849K.

Contr ol Byte 8, Reser ved Register

D ata 7

D ata 6

D ata 5

D ata 4

D ata 3

D ata 2

D ata 1

D ata 0

0

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reserved bits should be written as 0.

REV. 0

–13–

AD1849K

D ata Mode D ata and Contr ol Register s

Da ta Byte 1, Left Audio Da ta —Most Significa nt 8 Bits

D ata 7

L15

D ata 6

L14

D ata 5

L13

D ata 4

L12

D ata 3

L11

D ata 2

L10

D ata 1

L9

D ata 0

L8

63

62

61

60

59

58

57

56

In 16-bit linear PCM mode, this byte contains the upper eight bits of the left audio data sample. In the 8-bit companded and linear

modes, this byte contains the left audio data sample. In mono mode, only the left audio data is used. MSB first format is used in all

modes, and twos-complement coding is used in 16-bit linear PCM mode.

Da ta Byte 2, Left Audio Da ta —Lea st Significa nt 8 Bits

D ata 7

L7

D ata 6

L6

D ata 5

L5

D ata 4

L4

D ata 3

L3

D ata 2

L2

D ata 1

L1

D ata 0

L0

55

54

53

52

51`

50

49

48

In 16-bit linear PCM mode, this byte contains the lower eight bits of the left audio data sample. In the 8-bit companded and linear

modes, this byte is ignored on input, zeroed on output. In mono mode, only the left audio data is used. MSB first format is used in

all modes, and twos-complement coding is used in 16-bit linear PCM mode.

Da ta Byte 3, Right Audio Da ta —Most Significa nt 8 Bits

D ata 7

R15

D ata 6

R14

D ata 5

R13

D ata 4

R12

D ata 3

R11

D ata 2

R10

D ata 1

R9

D ata 0

R8

47

46

45

44

43

42

41

40

In 16-bit linear PCM mode, this byte contains the upper eight bits of the right audio data sample. In the 8-bit companded and linear

modes, this byte contains the right audio data sample. In mono mode, this byte is ignored on input, zeroed on output. MSB first

format is used in all modes, and twos complement coding is used in 16-bit linear PCM mode.

Da ta Byte 4, Right Audio Da ta —Lea st Significa nt 8 Bits

D ata 7

R7

D ata 6

R6

D ata 5

R5

D ata 4

R4

D ata 3

R3

D ata 2

R2

D ata 1

R1

D ata 0

R0

39

38

37

36

35

34

33

32

In 16-bit linear PCM mode, this byte contains the lower eight bits of the right audio data sample. In the 8-bit companded and linear

modes, this byte is not used. In mono mode, this byte is ignored on input, zeroed on output. MSB first format is used in all modes,

and twos-complement coding is used in 16-bit linear PCM mode.

Da ta Byte 5, Output Setting Register 1

D ata 7

OM1

31

D ata 6

OM0

30

D ata 5

LO5

29

D ata 4

LO4

28

D ata 3

LO3

27

D ata 2

LO2

26

D ata 1

LO1

25

D ata 0

LO0

24

OM1

OM0

Output Line 1 Analog Mute:

0

1

Mute Line 1

Line 1 on

Output Line 0 Analog Mute:

0

1

Mute Line 0

Line 0 on

LO5:0 Output attenuation setting for the left DAC channel; “0” represents no attenuation. Step size is 1.5 dB; “62” represents

93 dB of attenuation. Attenuation = 1.5 dB × LO, except for LO = “63,” which represents full digital mute.

–14–

REV. 0

AD1849K

Da ta Byte 6, Output Setting Register 2

D ata 7

AD I

23

D ata 6

SM

D ata 5

RO5

21

D ata 4

RO4

20

D ata 3

RO3

19

D ata 2

RO2

18

D ata 1

RO1

17

D ata 0

RO0

16

22

ADI

SM

ADC Invalid. T his bit is set to “1” during the autocalibration sequence, indicating that the serial data output from the

ADCs is meaningless.

Mono Speaker Analog Mute:

0

1

Mute mono speaker

Mono speaker on

RO5:0

Output attenuation setting for the right DAC channel; “0” represents no attenuation. Step size is 1.5 dB; “62”

represents 93 dB of attenuation. Attenuation = 1.5 dB × RO, except for RO = “63,” which represents full digital mute.

Da ta Byte 7, Input Setting Register 1

D ata 7

PIO1

15

D ata 6

PIO0

14

D ata 5

OVR

13

D ata 4

IS

D ata 3

LG3

11

D ata 2

LG2

10

D ata 1

LG1

9

D ata 0

LG0

8

12

PIO1:0

OVR

Parallel I/O bits for system signaling. PIO bits do not affect Codec operation.

ADC input overrange. T his bit is set to “1” if either ADC channel is driven beyond the specified input range. It is

“sticky,” i.e., it remains set until explicitly cleared by writing a “0” to OVR. A “1” written to OVR is ignored,

allowing OVR to remain “0” until an overrange condition occurs.

IS

Input selection:

0

1

Line-level stereo inputs

Microphone (condenser-type) level inputs if MB = 0 (+20 dB gain), or line-level stereo inputs if MB = 1

(0 dB gain).

LG3:0

Input gain for left channel. “0” represents no gain. Step size is 1.5 dB; “15” represents +22.5 dB of input gain.

Gain = 1.5 dB × LG.

Da ta Byte 8, Input Setting Register 2

D ata 7

MA3

7

D ata 6

MA2

6

D ata 5

MA1

5

D ata 4

MA0

4

D ata 3

RG3

3

D ata 2

RG2

2

D ata 1

RG1

1

D ata 0

RG0

0

MA3:0

RG3:0

Monitor mix. “0” represents no attenuation, i.e., the ADCs’ output is fully mixed with the DACs’ input. Step size

is 6 dB; “14” represents an attenuation of both channels of the ADCs’ output along the monitor datapath of

84 dB. Mix attenuation = 6 dB × MA, except for MA = “15,” which disables monitor mix entirely.

Input gain for right channel. “0” represents no gain. Step size is 1.5 dB; “15” represents +22.5 dB of input gain.

Gain = 1.5 dB × RG.

REV. 0

–15–

AD1849K

Contr ol Register D efaults

Upon coming out of RESET or Power Down, internal control registers will be initialized to the following values:

Defaults Calming Out of RESET or Power Down

MB

OLB

0

Mic Input Applied to +20 dB Fixed Gain Block

Full-Scale Line 0 Output 2.8 V p-p, Full-Scale Line 1 Output 4.0 V p-p, Full-Scale Mono Speaker

Output 8.0 V p-p

DCB

AC

DFR2:0

ST

1

0

Data/Control Bit HI

Autocalibration Disabled

8 or 5.5125 kHz

Monophonic Mode

DF1:0

IT S

MCK2:0

FSEL1:0

MS

1

0

2

8-Bit µ-Law Data

FSYNC, SDT X and SCLK T hree-State within 3 SCLK Cycles after D/C Goes LO

Serial Bit Clock [SCLK] is the Master Clock

256 Bits per Frame

0

Slave Mode

T XDIS

ENL

1

0

T hree-State Serial Data Output

Loopback Disabled

ADL

0

Digital Loopback

PIO1:0

OM1:0

LO5:0

ADI

3

0

63

1

0

“1”s, i.e., T hree-State for the Open Collector Outputs

Mute Line 0 and Line 1 Outputs

Mute Left DAC

ADC Data Invalid, Autocalibration in Progress

Mute Mono Speaker

SM

RO5:0

OVR

63

0

Mute Right DAC

No Overrange

IS

0

15

0

Line-Level Stereo Inputs

No Gain on Left Channel

No Mix

LG3:0

MA3:0

RG3:0

No Gain on Right Channel

Also, when making a transition from Control Mode to Data Mode, those control register values that are not changeable in Control

Mode get reset to the defaults above (except PIO). T he control registers that can be changed in Control Mode will have the values

they were just assigned. T he subset of the above list of control registers that are assigned default values on the transition from

Control Mode to Data Mode are:

Defaults at a Control-to-Data Mode Transition

OM1:0

LO5:0

SM

RO5:0

OVR

0

63

0

63

0

Mute Line 0 and Line 1

Mute Left DAC

Mute Mono Speaker

Mute Right DAC

No Overrange

IS

0

15

0

Line-Level Stereo Inputs

No Gain

No Mix

LG3:0

MA3:0

RG3:0

No Gain

Note that all these defaults can be changed with control information in the first Data Word. Note also that the PIO bits in the output

serial streams always reflect the values most recently read from the external PIO pins. (See “Parallel I/O Bits” below for timing

details.) A Control-to-Data Mode transition is no exception.

An important consequence of these defaults is that the AD1849K Codec always comes out of reset or power down in slave mode with an

externally supplied serial bit clock (SCLK) as the clock source. An external device must supply the serial bit clock and the chaining word

input signal (T SIN) initially. (See “Codec Startup, Modes, and T ransitions” below for more details.)

–16–

REV. 0

AD1849K

SERIAL INTERFACE

Recommended modes are indicated above by “yes.” Note that

Codec performance is improved with a clean clock source, and

in many systems the lowest jitter clocks available will be those

generated by the Codec’s internal oscillators. Conversely, SCLK

in many systems will be the noisiest source. T he master/SCLK

clock source combination is impossible because selecting SCLK

as the clock source overrides the MS control bit, forcing slave

mode. (T he SCLK pin cannot be driving out if it is simulta-

neously receiving an external clock.)

A single serial interface on the AD1849K provides for the trans-

fer of both data and control information. T his interface is simi-

lar to AT &T ’s Concentrated Highway Interface (CHI), allowing

simple connection with ISDN and other telecommunication

devices. T he AD1849K’s implementation also allows a no-glue

direct connection to members of Analog Devices’ family of

fixed-point DSP processors, including the ADSP-2101, the

ADSP-2105, the ADSP-2111, and the ADSP-2115.

Fr am es and Wor ds

T he internal oscillators or CLKIN can be the clock source when

the serial interface is in slave mode provided that all clocks

applied to the AD1849K SoundPort Codec are derived from the

same external source. Precise phase alignment of the clocks is

not necessary, rather the requirement is that there is no

frequency drift between the clocks.

T he AD1849K serial interface supports time-division multi-

plexing. Up to four AD1849K Codecs or compatible devices

can be daisy-chained on the same serial lines. A “frame” can

consist of one, two, or four 64-bit “words.” T hus, frames can be

64, 128, or 256 bits in length as specified by the FSEL bits in

Control Byte 3. Only 64 bits of each frame, a “word,” contain

meaningful data and/or control information for a particular

Codec. See Figure 4 below.

In master mode, the SCLK output frequency is determined by

the number of bits per frame selected (FSEL) and the sampling

frequency, F_S. In short, SCLK = FSEL × F_Sin master mode.

ONE WORD/FRAME

TWO WORDS/FRAME

FOUR WORDS/FRAME

WORD #1

63

Tim ing Relationships

0

Input data (except PIO) is clocked by the falling edge of SCLK.

Data outputs (except PIO) begin driving on the rising edge of

SCLK and are always valid well before the falling edge of

SCLK.

WORD #1

WORD #2

127

63 64

WORD #1

63 64

WORD #2

WORD #3

WORD #4

255

Word chaining input, T SIN, indicates to a particular Codec the

beginning of its word within a frame in both slave and master

modes. T he master mode Codec will generate a FSYNC output

which indicates the beginning of a frame. In single Codec

systems, the master’s FSYNC output should be tied to the

master’s T SIN input to indicate that the beginning of the frame

is also the beginning of its word. In multiple Codec daisy-chain

systems, the master’s FSYNC output should be tied to the

T SIN input of the Coded (either the master or one of the

slaves) which is intended to receive the first word in the frame.

FSYNC and T SIN are completely independent, and nothing

about the wiring of FSYNC to T SIN is determined by master or

slave status (i.e., the master can own any one of the words in the

frame). T he master Codec’s FSYNC can also be tied to all of

the slave Codecs’ FSYNC pins. When a slave, a Codec’s

FSYNC output is three-stated. T hus, it can be connected to a

master’s FSYNC without consequence. See “Daisy-Chaining

Multiple Codecs” below for more details.

127 128

191 192

Figure 4. Fram es and Words

T he AD1849K supports two types of words: Data Words and

Control Words. The proper interpretation of a word is deter-

mined by the state of the asynchronous Data/Control (D/C) pin.

T he D/C pin establishes whether the SoundPort Codec is in the

“Data” mode or “Control” mode. T ransitions between these

modes require an adherence to a handshaking protocol to pre-

vent ambiguous bus ownership. T he Data/ Control transition

protocol is described below in a separate section.

Clocks and the Ser ial Inter face

T he primary pins of the AD1849K’s serial interface are the

serial data receive (SDRX) input pin. T he serial data transmit

(SRT X) pin, the serial data bit clock (SCLK) pin, the frame

sync output (FSYNC) pin, the chaining word input (T SIN) pin,

and the chaining word output (T SOUT ) pin. T he AD1849K

can operate in either master mode—in which case SCLK and

FSYNC are outputs and T SIN is an input—or in slave mode—

in which case SCLK and T SIN are inputs and FSYNC is three-

stated. If the AD1849K is in master mode, the internally

selected clock source is used to drive SCLK and FSYNC. Note

that in Control Mode, the Codec always behaves as a slave,

regardless of the current state of the MS (Master/Slave) bit.

T he FSYNC rate is always equal to the data conversion

sampling frequency, F_S. In Data Mode, the key significance of

“frames” are to synchronize the transfer of digital data between

an AD1849K’s internal ADCs and DACs and its serial interface

circuitry. If, for example, a Codec has been programmed for two

words per frame (FSEL = “1”), then it will trigger the data

converters and transfer data between the converters and the

interface every 128 SCLKs. T he T SIN input signals the Codec

where its word begins within the frame. In Control Mode, frame

size is irrelevant to the operation of any particular Codec; T SIN

and T SOUT are sufficient to convey all the information

required.

T he five possible combinations of clock source and master/slave

are summarized in Figure 5.

INTERNAL OSCILLATORS

CLKIN

SCLK

MASTER

SLAVE

YES

IMPOSSIBLE

CONDITIONAL

YES

Figure 5. Clock Source and Master/Slave Com binations

REV. 0

–17–

AD1849K

T SIN is sampled on the falling edge of SCLK. A LO-to-HI

transition of T SIN defines the beginning of the word to occur at

the next rising edge of SCLK (for driving output data). T he

LO-to-HI transition is defined by consecutive LO and HI

samples of T SIN at the falling edges of SCLK. Both input and

output data will be valid at the immediately subsequent falling

edge of SCLK. See Figures 6 and 7.

t_CLK

t_HI

t_LO

SCLK

t_IH

t_S

SDRX AND TSIN

INPUTS

t_OH

t_D

SCLK

SDTX, FSYNC,

AND TSOUT

OUTPUTS

t_ZV

SDTX CONTROL

OR DATA BYTE 1,

BIT 7 OUTPUT

FSYNC, TSIN, &

TSOUT

t_VZ

SDTX CONTROL

OR DATA BYTE 8,

BIT 0 OUTPUT

t_IH

SDRX & SDTX

t_S

FIRST DATA BIT

OF WORD

PIO

INPUTS

t_OH

Figure 6. AD1849K Tim ing Relationships

t_D

PIO

After the beginning of a word has been recognized, T SIN is a

“don’t care”; its state will be ignored until one SCLK period

before the end of the current word.

OUTPUTS

Figure 7. AD1849K Tim ing Param eters

T he AD1849K comes out of reset with the default conditions

specified in “Control Register Defaults.” It will be in the mode

specified by the D/C pin. If in Control Mode, the SoundPort

Codec can be configured by the host for operation. Subsequent

transitions to Control Mode after initialization are expected to

be relatively infrequent. Control information that is likely to

change frequently, e.g., gain levels, is transmitted along with the

data in Data Mode. See Figure 8 for a complete map of the data

and control information into the 64-bit Data Word and the

64-bit Control Word.

16-BIT STEREO DATA WORD

63

48 47

32 31 30 29 24 23 22 21 16 15 14 13

12 11

8

7

4

3

0

Left-Channel Audio Right-Channel Audio

OM LO ADI SM RO PIO OVR IS LG

MA RG

16-BIT MONO DATA WORD

63

48 47

32 31 30 29 24 23 22 21 16 15 14 13

OM LO ADI SM RO

12 11

7

4

3

0

Left-Channel Audio

PIO OVR IS LG MA 0000

8-BIT STEREO DATA WORD

63

56 55

48 47

40 39

32 31 30 29 24 23 22 21 16 15 14 13

12 11

8

7

4

3

0

Left Audio 0000 0000 Right Audio 0000 0000 OM

LO ADI SM RO PIO OVR IS LG MA

RG

8-BIT MONO DATA WORD

63

56 55

32 31 30 29 24 23 22 21 16 15 14 13

LO ADI SM RO

12 11 8 7 4 3

0

Left Audio 0000 0000 Left Audio 0000 0000 OM

PIO OVR IS LG MA 0000

CONTROL WORD

63 61 60 59 58 57 56 55 54 53 51 50 49 48 47 46 44 43 42 41

40 39 34 33 32 31 30 29 24 23

16 15 12 11

8

7

0

001 MB OLB DCB 0 AC 00 DFR ST DF ITS MCK FSEL MS TXDIS 0000 00 ENL ADL PIO 00 0000 0000 0000 0010 REVID 0000 0000

Figure 8. AD1849K Bit Positions for Data and Control

–18–

REV. 0

AD1849K

D aisy-Chaining Multiple Codecs

bits per frame, and SCLK as an input. T he slaves FSYNC out-

puts will be three-stated and thus can be connected to the

master’s FSYNC without contention.

Up to four SoundPort Codecs can be daisy-chained with frame

sizes in multiples of 64 bits. T he serial data is time-division

multiplexed (T DM), allocating each Codec its own 64-bit word

in the frame.

If SCLK is the clock source, it must run at 256 × F_S, and

therefore the frame size must be 256 bits, i.e., four words. By

contrast, if the master Codec’s CLKOUT is used as the clock

source, then it can run at either 256 × F_Sor 128 × F_S.

T he pins that support T DM daisy-chaining of multiple Codecs

are the word chaining input (T SIN) and the word chaining out-

put (T SOUT ). As described above, T SIN is used to indicate

the position of the first bit of a particular Codec’s 64-bit word

within the total frame.

P ar allel I/O Bits

Both Data and Control Words allocate Bit positions for

“parallel I/O,” PIO1:0. T his provides a convenient mechanism

for transferring signaling information between the serial data

and control streams and the external pair of bidirectional pins

also named “PIO1” and “PIO0.” T he states of the parallel I/O

bits and pins do not affect the internal operation of the Codec in

any way; their exclusive use is for system signaling.

T he word chaining output (T SOUT ) is generated by every

Codec during the transmission of the last bit of its 64-bit word.

T he first device in any Codec chain uses an externally generated

or self-generated FSYNC signal as an input to T SIN. T he

T SOUT of the first Codec is wired directly to the T SIN of the

second Codec and so on. T he waveform of T SOUT is a pulse of

one SCLK period in duration. All Codecs share the same

SCLK, FSYNC, SDRX, and SDT X lines since they are select-

ing different words from a common frame.

T he PIO pins are open-drain and should be pulled HI exter-

nally. T hey can be read (through serial output data) in either

Control or Data Mode and can be written (through serial input

data) in Data Mode exclusively. T he values in the PIO field of

the Control Word serial input in Control Mode will be ignored.

An external device may drive either PIO pin LO even when

written HI by the Codec, since the pin outputs are open-drain.

T hus, a PIO value read back as a serial output bit may differ

from the value just written as a serial input bit.

Note that a powered-down Codec immediately echoes T SIN on

T SOUT . T hus, a Codec can be added or removed from the

chain simply by using the PDN pin. See “Reset and Power

Down” below for more details. See Figure 9 for an illustration

of daisy-chained Codecs.

T he PIO pins are read on the rising edge of SCLK five (5)

SCLK periods before the first PIO bit is transmitted out over

the serial interface. In Data Mode, the PIO pins are sampled as

Bit 20 starts to be driven out. In Control Mode, the PIO pins

are sampled as Bit 36 starts being driven out. T iming para-

meters are as shown in Figure 7; PIO pin input data is relative

to the rising edge of SCLK. (Note that only the PIO pins are

read on SCLK rising edges.)

SCLK

SDTX

SDRX

SCLK

SDRX

SDTX

EXTERNAL

DEVICE

AD1849K #1

MASTER

FSYNC

D/C

FSYNC

TSIN

TSOUT

D/C

PDN1

PDN2

CLKOUT

RESET

PDN

RESET

T he PIO pins are driven very shortly after the PIO data bits in

the input Data Word are read (Data Mode only). T hey are

driven on the falling edge of SCLK (unlike any other output).

T he PIO data bits in the input are located at Bits 15 and 14 in

the Data Word and at Bits 31 and 30 in the Control Word

(Figure 8). Due to the five (5) SCLK period delay, the PIO pins

will be driven out with new values for Data Mode on the SCLK

falling edge when Bit 8 is read in, and for Control Mode on the

SCLK falling edge when Bit 24 is read in.

SCLK

SDRX

AD1849K #2

SDTX

SLAVE

FSYNC

TSIN

CLKIN

TSOUT

D/C

PDN

CO D EC STARTUP , MO D ES, AND TRANSITIO NS

Reset and P ower D own

RESET

T he AD1849K Stereo Codec can be reset by either of two

closely related digital input signals, RESET and Power Down

(PDN). RESET is active LO and PDN is active HI. Asserting

PDN is equivalent to asserting RESET with two exceptions.

First, if PDN is asserted (when RESET is HI), then the T SIN

and T SOUT chaining pins remain active. T SOUT will

immediately echo whatever signal is applied to T SIN during

power down. T his feature allows a very simple system test to

detect “life” even in a power-down state. It also allows the user

to selectively shut off Codecs in a daisy chain by powering down

the unwanted Codecs. T he down-stream Codecs will simply

move up a word position in frame. T he second difference is that

power consumption will be lower in power-down mode than in

exclusive reset mode. T he CMOUT and LOUT 1C pins will not

supply current while the AD1849K is in the power-down state

since all outputs collapse to ground.

Figure 9. AD1849K Daisy-Chaining

Note that at most, one Codec in a daisy-chain can be in master

mode without contention. All other Codecs must be in slave

mode, receiving SCLK and T SIN externally.

Each slave can use SCLK as its clock source. However, as an

alternative, it is possible to connect the CLKOUT pin of the

master Codec to the CLKIN pins of the slaves, so that the sam-

ple frequency selected by the master (from one of its two crys-

tals) will be automatically applied to the slaves. T he master

must be programmed for the desired sample frequency and the

correct number of bits per frame. T he slaves must be pro-

grammed for CLKIN as the clock source, the correct number of

REV. 0

–19–

AD1849K

RESET should be asserted when power is first applied to the

AD1849K. RESET should be asserted for a minimum of 50 ms

at power-up or when leaving the power-down mode to allow the

power supplies and the voltage reference to settle. Any time

RESET is asserted during normal operation, it should remain

asserted for a minimum of 100 ns to insure a complete reset.

Note that an autocalibration sequence will always occur when

RESET is deasserted, in addition to on the Control Mode to

Data Mode transition.

protocol to ensure a smooth transition between serial bus

masters (i.e., the external controller and the Codec) and

guarantee unambiguous serial bus ownership. T his software

handshake protocol for Control Mode to Data Mode transitions

makes use of the Data/Control Bit (DCB) in the Control Mode

Control Word (Bit 58). Prior to initiating the change to Control

Mode, the external controller should gradually attenuate the

audio outputs. T he DCB handshake protocol requires the

following steps:

Coming out of either reset or power down, the state of the Data/

Control pin (D/C) will determine whether the Codec is in Data

Mode or Control Mode. In the unlikely event that the control

register defaults are desired for Codec operation, it is possible to

go directly from reset or power down to Data Mode and begin

audio operation.

Enter Control Mode

T he external controller drives the D/C pin LO, forcing the

Codec into Control Mode as a slave. T he DCB transmitted

from the external controller to the Codec may be “0” or “1” at

this point in the handshake.

When IT S = 0 (Control Word Bit 47) and the Codec was oper-

ating as the master in the preceding Data Mode, immediately

after D/C goes LO, the Codec will drive FSYNC and T SOUT

LO for one SCLK period, then three-state FSYNC. SDT X is

three-stated immediately after D/C goes LO. T SOUT is not

three-stated. T he Codec will drive SCLK for three (3) SCLK

periods after D/C goes LO and then three-state SCLK. T he

external controller must wait at least three (3) SCLK periods

after it drives D/C LO, and then start driving SCLK.

Contr ol Mode

More typically, users coming out of reset or power down will

want to change the control register defaults by transmitting a

Control Word in Control Mode. T he user of the AD1849K

SoundPort Codec can also enter Control Mode at any time

during normal Data Mode operation. T he D/C pin is provided

to make this possible. T he Codec enters Control Mode when

the D/C pin is driven LO or held LO when coming out of reset

and/or power down.

When IT S = 1 (Control Word Bit 47) and the Codec was

operating as the master in the preceding Data Mode, the Codec

will three-state FSYNC, SDT X, and SCLK immediately after

D/C goes LO. T SOUT is driven LO immediately after D/C

goes LO and is not three-stated. T he external controller may

start driving SCLK immediately.

In Control Mode, the location of a word within a frame is

determined solely by the behavior of the T SIN and T SOUT

signals. Each Codec by itself does not care where the frame

boundaries fall as defined by the system. T he contents of the

frame size select (FSEL1:0, Control Word Bits 43 and 42) bits

are irrelevant to the operation of each AD1849K in Control

Mode. In Control Mode, a Codec requires 64 SCLK cycles to

be fully programmed. Additional SCLK cycles (more than 64)

that occur before the end of the frame will be ignored.

When IT S = 0 and the external controller was operating as the

master in the preceding Data Mode, the external controller

must continue to supply SCLK to the slave Codec for at least

three (3) SCLK periods after D/C goes LO before a Control

Mode T SIN is issued to the Codec. T SIN must be held LO

externally until the first Control Word in Control Mode is

supplied by the external controller. T his prevents false starts

and can be easily accomplished by using a pull-down resistor on

T SIN as recommended. T he slave Codec drives T SOUT and

SDT X LO, then three-states SDT X, all within 1 1/2 (one and

one half) SCLK periods after D/C goes LO. T SOUT is not

three-stated.

If four Codecs, for example, were daisy-chained, then each

Codec would receive T SIN every 256 bits. In this case, Codec

# 2’s input Control Word will be positioned between Bit 64 and

Bit 127 in the input frame.

Contr ol Wor d Echo

While in Control Mode, the AD1849K Codec will echo the

Control Word received as a serial input on the SDRX pin as a

serial output in the next frame on the SDT X pin. (SDT X will

be enabled regardless of the setting of the T XDIS bit, Control

Word Bit 40.) T his echoing of the control information allows

the external controller to confirm that the Codec has received

the intended Control Word. For the four Codec daisy chain

example above, the Control Word will be echoed bit for bit as

an output between Bit 64 and Bit 127 in the next output frame.

In general, in Control Mode, the location of the echo Control

Word within a frame will be at the same word location as the

input Control Word.

When IT S = 1 and the external controller was operating as the

master in the preceding Data Mode, the external controller

must continue to supply SCLK to the slave Codec. A Control

Mode T SIN should be issued to the Codec three or more

SCLK periods after D/C goes LO. T he slave Codec drives

T SOUT LO and three-states SDT X immediately after D/C

goes LO. T SOUT is not three-stated.

T he Codec initializes its Data Mode Control Registers to the

defaults identified above, which among other actions, mutes all

audio outputs.

In the first frame of Control Mode, the AD1849K will output a

Control Word that reflects the control register values operative

during the most recent Data Mode operation. If Control Mode

was entered prior to any Data Mode operation, this first output

word will simply reflect the standard default settings. DCB will

always be “1” in the first output echoed Control Word.

First DCB Interlock

When the external controller is ready to continue with the DCB

handshake, the Control Word sent by the external controller

should have the DCB reset to “0” along with arbitrary control

information (i.e., the control information does not have to be

valid, although if it is valid, it allows the external controller to

verify that the echoed Control Word is correct). T he external

controller should continue to transmit this bit pattern with

D CB H andshaking P r otocol

T he D/C pin can make transitions completely asynchronously to

internal Codec operation. T his fact necessitates a handshaking

–20–

REV. 0

AD1849K

DCB = “0” until the echoed DCB from the Codec also is reset

to “0” (i.e., it must poll DCB until a “0” is read). T his is the

first interlock of the DCB handshake.

recognize a complete FSYNC LO-to-HI transition. If an

AD1849K Codec enters Data Mode as a slave, it can recognize

a T SIN LO-to-HI transition even if SCLK is simultaneously

making its first LO-to-HI transition. In fact, the AD1849K

serial interface will operate properly even if D/C, SCLK, and

T SIN all go HI at the same time.

T he DCB = “0” is echoed on SDT X in the next frame after it

was received on SDRX if a sample rate has been consistently

selected AND the clock source is generated using the internal

oscillator. Otherwise DCB = “0” will be echoed on SDT X in

the frame after at least 2 ms of consistent sample rate selection

expires. If SCLK or CLKIN is used as the clock source, the user

must guarantee that the source selection and sample rate are

stable for 2 ms before D/C is driven HI.

See Figure 10 for a flow chart representation of a typical startup

sequence, including the DCB handshake.

Apply power while RESET is pulled LO

and wait 50 milliseconds

Note that after sending a Control Word with DCB = “0,” the

external controller must take care not to set (or glitch) DCB =

“1” until after the echoed DCB = “0” has been received from

the Codec.

Provide TSIN and SCLK

signals to Codec. Drive RESET

HI (inactive) while D/C is LO

ENTER CONTROL MODE

Transmit a Control Word

to Codec with DCB LO

Second DCB Interlock

After it sees the DCB = “0” (and has optionally verified that the

echoed Control Word is correct), and when it is ready to

continue with the DCB handshake, the external controller

should transmit the desired and valid control information, but

now with DCB set to “1.” T he external controller can then

transmit arbitrary control information until the echoed DCB

from the Codec is also set to “l” (i.e., it must poll DCB until a

“l” is read). After this Control Word with DCB = “1,” all future

control information received by the Codec during Control

Mode (i.e., while D/C is LO) will be ignored. T his is the second

and final interlock of the DCB handshake.

Wait for Codec to transmit

back a DCB LO

FIRST DCB INTERLOCK

0 – 2ms

Transmit desired Control Word

to Codec with DCB HI

Wait for Codec to transmit

back a DCB HI

SECOND DCB INTERLOCK

0 – 2ms

Bring D/C HI

EXIT CONTROL MODE

AUTOCALIBRATION

T he Codec will echo DCB = “l” in the next frame after it was

received on SDRX if a sample rate has been consistently

selected AND the clock source is generated using the internal

oscillator. Otherwise DCB = “1” will be echoed on SDT X once

one sample rate selection has been held constant for at least

2 ms. If SCLK or CLKIN is used as the clock source, the user

must guarantee that the source selection and sample rate are

stable for 2 ms before D/C is driven HI. T he Codec will

transmit the full 64-bit Control Word with DCB = “1” and then

three-state the SDT X pin. T he external controller must

continue to supply SCLK to the Codec until all 64 bits of the

Control Word with DCB = “1” have been transmitted by the

Codec, plus at least one [1] more SCLK after this 64-bit

Control Word (i.e., at least 65 SCLKs). Note that echoing the

full 64-bit Control Word makes the AD1849K match the

behavior of the CS4215.

Transmit 194 Data Words

to Codec

Begin audio operation

Figure 10. Typical AD1849K Startup Sequence

AP P LICATIO NS CIRCUITS

T he AD1849K Stereo Codec has been designed to require a

minimum of external circuitry. T he recommended circuits are

shown in Figures 11 through 20 and summarized in Figure 21.

Analog Devices estimates that the total cost of all the compo-

nents shown in these Figures, including crystals, to be less than

$5 in 10,000 piece quantities.

Industry-standard compact disc “line-levels” are 2 V rms

centered around analog ground. (For other audio equipment,

“line level” is much more loosely defined.) T he AD1849K

SoundPort is a +5 V only powered device. Line level voltage

swings for the AD1849K are defined to be 1 V rms for ADC

input and 0.707 V rms for DAC output. T hus, 2 V rms input

analog signals must be attenuated and either centered around

the reference voltage intermediate between 0 V and + 5 V or

ac-coupled. T he CMOUT pin will be at this intermediate

voltage, nominally 2.25 V. It has limited drive but can be used

as a voltage datum to an op amp input. Note, however, that

dc-coupled inputs are not recommended, as they provide no

performance benefits with the AD1849K architecture. Further-

more, dc offset differences between multiple dc-coupled inputs

create the potential for “clicks” when changing the input mux

selection.

Exit Control Mode

Control mode DCB handshake is now complete. T he Codec

will remain inactive until D/C goes HI or RESET and or PDN

are asserted.

Note that if a sample rate and a clock source have been

consistently selected throughout the handshake, the AD1849K

and the CS4215 DCB protocols are equivalent.

Contr ol Mode to D ata Mode Tr ansition and Autocalibr ation

T he AD1849K will enter Data Mode when the asynchronous

D/C signal goes HI. T he serial interface will become active

immediately and begin receiving and transmitting Data Words

in accordance with the SCLK, FSYNC, T SIN, and T SOUT

signals as shown in Figure 6. If the Codec enters Data Mode as

a master, it will generate one complete SCLK period before it

drives FSYNC HI; FSYNC will go HI with the second rising

edge of SCLK. T his allows external devices driven by SCLK to

REV. 0

–21–

AD1849K

A circuit for 2 V rms line-level inputs is shown in Figure 11.

Note that this is approximately a divide-by-two resistive divider.

Figure 13 shows ac-coupled line outputs. T he resistors are used

to center the output signals around analog ground. If dc-

coupling is desired, CMOUT could be used with op amps as

mentioned below.

0.33µF

5.1k

LINL

1µF

5.1k

560pF

NPO

LOUT0L

47k

0.33µF

5.1k

LINR

1µF

LOUT0R

5.1k

560pF

NPO

47k

Figure 11. AD1849K 2 V rm s Line-Level Input Circuit

Figure 13. AD1849K Line Output Connections

An external passive antialias filter is required. If line-level inputs

are already at the 1 V rms levels expected by the AD1849K, the

resistors in parallel with the 560 pF capacitors should be

omitted and the series 5.1 kΩ resistor should be decreased to

2.5 kΩ.

A circuit for headphone drive is illustrated in Figure 14. Drive is

supplied by +5 V operational amps. T he circuit shown ac

couples the headphones to the line output.

8.66k

T he AD1849K Codec contains a bypassable +20 dB gain block

to accommodate condenser microphones. Particular system

requirements will depend upon the characteristics of the

intended microphone. Figure 12 illustrates one example of how

an electret condenser mike requiring phantom power could be

connected to the AD1849K. CMOUT is shown buffered by an

op amp; a transistor like a 2N4124 will also work fine for this

purpose. Note that if a battery-powered microphone is used, the

buffer and R2s are not needed. T he values of R1, R2, and C

should be chosen in light of the mic characteristics and intended

gain. T ypical values for these might be R1 = 20 kΩ, R2 = 2 kΩ,

and C = 220 pF.

10k

470µF

LOUT1L

HEADPHONE

LEFT

LOUT1C

LOUT1R

SSM-2135

470µF

HEADPHONE

RIGHT

10k

8.66k

Figure 14. AD1849K Headphone Drive Connections

T he AD1849K has a common return path LOUT 1C which is

biased up to the CMOUT voltage, nominally 2.25 V. T he

AD1849K allows for 6 dB larger output voltage swings by

resetting the OLB bit (Bit 59 of the Control Word) to “0.”

Figure 15 illustrates an alternative headphone connection for

the AD1849K which uses the LOUT 1C pin to eliminate the

need for ac coupling. T he 12 Ω resistors minimize output level

variations caused by different headphone impedances.

LOUT 1L, LOUT 1R and LOUT 1C are short-circuit protected.

Note that driving headphones directly as shown in Figure 15

with OLB = 0 will cause clipping for large input signals and will

only work with very efficient “Walkman-type” headphones. For

high quality headphone listening, Analog Devices recommends

the circuit shown in Figure 14 with OLB = 1.

C

R₁

1µF

5k

0.33µF

MINL

R₂

1/2 SSM-2135

OR AD820

CMOUT

LEFT ELECTRET

CONDENSER

MICROPHONE

INPUT

1/2 SSM-2135

OR AD820

C

R₂

R₁

1µF

5k

0.33µF

MINR

RIGHT ELECTRET

CONDENSER

MICROPHONE

INPUT

1/2 SSM-2135

OR AD820

12Ω 1/2W

CMOUT

LOUT1L

LOUT1R

LOUT1C

HEADPHONE

LEFT

Figure 12. AD1849K “Phantom -Powered” Microphone

Input Circuit

12Ω 1/2W

HEADPHONE

RIGHT

HEADPHONE

RETURN

Figure 15. AD1849K Optional Headphone Drive

Connections

–22–

REV. 0

AD1849K

No external circuitry is required for driving a single speaker

from the AD1849K’s mono outputs as shown in Figure 16.

Note that this output is differential. Analog Devices guarantees

specified distortion performance for speaker impedances of 48 Ω

or greater. Lower impedance speakers can be used, but at the

cost of some distortion. When driving speakers much less than

48 Ω, a power amp should be used. T he AD1849K can drive

speakers of 32 Ω or greater.

clock sources can be used to overdrive the AD1849K’s internal

oscillators. (See the description of the MCK1:0 control bits

above.) If using an external clock source, apply it to the crystal

input pins while leaving the crystal output pins unconnected.

Attention should be paid to providing low jitter external input

clocks.

CIN2

COUT2

CIN1

COUT1

MOUT

20–64pF

16.9344MHz

24.576MHz

Z ≥ 32Ω

Figure 19. AD1849K Crystal Connections

MOUTR

Good, standard engineering practices should be applied for

power-supply decoupling. Decoupling capacitors should be

placed as close as possible to package pins. If a separate analog

power supply is not available, we recommend the circuit shown

in Figure 20 for using a single +5 V supply. Ferrite beads suffice

for the inductors shown. T his circuitry should be as close to the

supply pins as is practical.

Figure 16. AD1849K External Mono Speaker Connector

Figure 17 illustrates reference bypassing. V_REFshould only be

connected to its bypass capacitors, which should be located as

close to Pin 21 as possible (especially the 0.1 µF capacitor).

V

CMOUT

REF

FERRITE

0.1µF

10µF

+5V SUPPLY

0.1µF

1µF

0.1µF

V_DD

Figure 17. AD1849K Voltage Reference Bypassing

Figure 18 illustrates signal-path filtering capacitors, C0 and C1.

T he AD1849K must use 1.0 µF capacitors.

FERRITE

1.6Ω

C0

C1

1µF

0.1µF

V_CC

1µF

Figure 20. AD1849K Recom m ended Power Supply

Bypassing

Figure 18. AD1849K External Filter Capacitor Connections

T he two PIO pins must be pulled HI, as they have open drain

outputs. Analog Devices also recommends pull-down resistors

for SCLK, FSYNC, SDT X, SDRX, and T SIN to provide

margin against system noise. CLKIN, CIN1, and CIN2, if not

used, should be grounded. A typical connection diagram is

shown in Figure 21, which serves to summarize the preceding

application circuits.

The crystals shown in the crystal connection circuitry of Figure 19

should be fundamental-mode and parallel-tuned. Two sources for

the exact crystals specified are Component Marketing Services

in Massachusetts, U.S. at 617-762-4339 and Cardinal Compo-

nents in New Jersey, U.S. at 201-746-0333. Note that using the

exact data sheet frequencies is not required and that external

REV. 0

–23–

AD1849K

Low level ADSP-21xx software drivers for the AD1849K are

supplied with the AD1849K Evaluation Board. Source and

object codes arc available from your Analog Devices Sales

Representative or on the Analog Devices DSP Bulletin Board.

T he DSP Bulletin Board telephone number is (617) 461-4258,

8 data bits, no parity, 1 stop bit, 300 to 2400 baud.

FERRITE

Ω

1.6

FERRITE

+5V

SUPPLY

0.1µF

1µF

0.1µF

1µF

0.1µF

0.33µF

V

DD

5.1k

DD

Note that the interface to the T exas Instruments T MS320C25

must be significantly more complicated than these three

examples because the C25’s serial port cannot be a master,

which is required of the external controller during Control

Mode.

LINL

V

CC

1µF

0.1µF

5.1k

560pF

NPO

V

CC

MOUT

MONO

SPEAKER

LINE IN

MOUTR

LOUT0L

0.33µF

5.1k

LINR

ANALOG GROUND PLANE

DIGITAL GROUND PLANE

1µF

5.1k

560pF

NPO

47k

N/C

LOUT0R

LINE

OUT 0

AD1849K

LOUT0R

AD1849K

PDN

PREFERRED

MICROPHONE

INPUT CIRCUIT

47k

MINL

MINR

LINE OUT 1 OR

PREFERRED

HEADPHONE

CIRCUIT

C0

LOUT1L

LOUT1R

LOUT1C

CMOUT

V

REF

10µF

0.1µF

COUT1

CIN1

Figure 22. AD1849K Recom m ended Ground Plane

C0

24.576MHz

20–64pF

1µF

SCLK0

RFS0

SCLK

FSYNC

TSIN

C1

COUT2

ADSP-2111

1µF

GNDA

AD1849K

DT0

DR0

FL0

SDRX

SDTX

D/C

16.9344MHz

CIN2

TSIN

GNDA

RESET

FSYNC

SCLK

PDN

SCLK0

RFS0

SCLK

FSYNC

TSIN

PIO0

PIO1

SDTX

ADSP-2101

ADSP-2115

AD1849K

GNDD GNDD SDRX

GNDD

47k

DT0

DR0

FO

SDRX

SDTX

D/C

20k

V

DD

UNUSED INPUTS SHOULD BE GROUNDED AND NC'S LEFT UNCONNECTED

10k

Figure 21. Typical Connection Diagram

SCLK

RFS

TFS

SCLK

FSYNC

TSIN

Analog Devices recommends a split ground plane as shown in

Figure 22. T he analog plane and the digital plane are connected

directly under the AD1849K. Splitting the ground plane directly

under the SoundPort Codec is optimal because analog pins will

be located above the analog ground plane and digital pins will

be located directly above the digital ground plane for the best

isolation. T he digital ground and analog grounds should be tied

together in the vicinity of the AD1849K. Other schemes may

also yield satisfactory results.

10k

D

ADSP-2105

AD1849K

DT

DR

D8

SDRX

SDTX

D/C

Q

CLR

WR

DMS

RESET

Figure 23 illustrates the “zero-chip” interfaces of the AD1849K

SoundPort Codec to four of Analog Devices’ Fixed-Point

DSµPs. T he ADSP-2111, ADSP-2101 and ADSP-2115 use

their multichannel serial port for the data interface and flag

outputs for D/C. T he ADSP-2105 has a single serial port which

operates in its frameless mode. Because the ADSP-2105 lacks a

flag output, it alone does require additional circuitry to generate

D/C. Shown is an implementation using a single D-flop, an

OR-gate, and two pull-down resistors.

Figure 23. Interfaces to Analog Devices’ Fixed-Point

DS µPs

–24–

REV. 0

AD1849K

CS4215 CO MP ATIBILITY

• Pin 38 (PLCC) and Pin 32 (T QFP) on the AD1849K is used

as a digital power supply. On the CS4215, this pin is a “no

connect.” We strongly recommend connecting this pin to the

digital supply. Both chips should operate in this configura-

tion. Pin 39 (PLCC) and Pin 33 (T QFP) on the AD1849K is

used as a digital ground. On the CS4215, this pin is a “no

connect.” We strongly recommend connecting this pin to the

digital ground plane. Both chips should operate in this

configuration.

T he Analog Devices AD1849K SoundPort Stereo Codec is pin-

compatible with the CS4215. T hese chips were independently

codeveloped to a common specification provided by Sun

Microsystems, Inc. Because of their independent development,

they will differ in performance and in minor details. A board can

be designed to accommodate either chip by attending to a few

differences in their required support circuitry.

• If consistent control information is transmitted to the Codec

during Control Mode, the AD1849K DCB handshake is

compatible with the CS4215. See text for more details.

• Analog Devices recommends a 10 µF bypass capacitor on the

voltage reference output, CMOUT (Pin 19). Using a 0.47 µF

capacitor may be acceptable in many systems, however DAC

performance at low sample rates will be improved with the

larger capacitor.

• T he Analog Devices AD1849K uses two external capacitors

to complete its internal input filter as shown in Figure 18.

T he CS4215 calls the two pins on the AD1849K for these

capacitor connections, “no connects.” By laying out a board

with these capacitors, either chip will work.

• T he AD1849K requires an external passive antialias filter as

shown in Figure 11. In contrast, the recommended input

circuit for the CS4215 is a single-pole active filter requiring a

dual op amp. T hough overkill for the AD1849K, this input

circuit will work with the AD1849K as well.

• T he AD1849K was designed to require no external low-pass

filters on analog outputs. As shown in Figure 13, the

AD1849K only requires ac coupling capacitors and resistors

for line-level dc bias. In contrast, the CS4215 has a single-

pole passive filter for its recommended line-level output

circuit. T hough overkill for the AD1849K, this output circuit

will work with the AD1849K as well.

REV. 0

–25–

AD1849K

FREQ UENCY RESP O NSE P LO TS

10

0

10

0

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

–60

–70

–80

–90

dB

–60

–70

–80

–90

–100

–110

–120

–100

–110

–120

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

0.0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1.0

SAMPLE FREQUENCY (F

)

SAMPLE FREQUENCY (F

)

S

Figure 24. AD1849K Analog-to-Digital Frequency Response

to F_S(Full-Scale Line-Level Inputs, 0 dB Gain)

Figure 26. AD1849K Digital-to-Analog Frequency Response

(Full-Scale Inputs, 0 dB Attenuation)

10

0

10

0

–10

–20

–30

–40

–50

–10

–20

–30

–40

–50

dB

–60

–70

–80

–70

–80

–90

–100

–110

–100

–110

–120

0.40 0.42 0.44 0.46 0.48 0.50 0.52 0.54 0.56 0.58 0.60

SAMPLE FREQUENCY (F_S

)

SAMPLE FREQUENCY (F_S

)

Figure 25. AD1849K Analog-to-Digital Frequency Response

– Transition Band (Full-Scale Line-Level Inputs, 0 dB Gain)

Figure 27. AD1849K Digital-to-Analog Frequency Response –

Transition Band (Full-Scale Inputs, 0 dB Attenuation)

–26–

REV. 0

AD1849K

IND EX

P AGE

PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

ELECT RICAL SPECIFICAT IONS . . . . . . . . . . . . . . . . . . . 2

ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

PIN OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

AD1849K PIN DESCRIPT ION . . . . . . . . . . . . . . . . . . . . .

FUNCT IONAL DESCRIPT ION . . . . . . . . . . . . . . . . . . . .

Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog-to-Digital Datapath . . . . . . . . . . . . . . . . . . . . . . .

Digital-to-Analog Datapath . . . . . . . . . . . . . . . . . . . . . . .

Monitor Mix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Analog Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Digital Data T ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Power Supplies and Voltage Reference . . . . . . . . . . . . . . .

Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6

7

8

9

Clocks and Sample Rates . . . . . . . . . . . . . . . . . . . . . . . . 10

CONT ROL REGIST ERS . . . . . . . . . . . . . . . . . . . . . . . . . 11

Control Mode Control Registers . . . . . . . . . . . . . . . . . . 11

Data Mode Data and Control Registers . . . . . . . . . . . . . 14

Control Register Defaults . . . . . . . . . . . . . . . . . . . . . . . . 16

SERIAL INT ERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Frames and Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Clocks and the Serial Interface . . . . . . . . . . . . . . . . . . . . 17

T iming Relationships . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Daisy-Chaining Multiple Codecs . . . . . . . . . . . . . . . . . . 19

Parallel I/O Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

CODEC ST ART UP, MODES, AND T RANSIT IONS . . 19

Reset and Power Down . . . . . . . . . . . . . . . . . . . . . . . . . 19

Control Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Control Word Echo . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DCB Handshaking Protocol . . . . . . . . . . . . . . . . . . . . . . 20

Control Mode to Data Mode T ransition

and Autocalibration . . . . . . . . . . . . . . . . . . . . . . . . . . 21

APPLICAT IONS CIRCUIT S . . . . . . . . . . . . . . . . . . . . . . 21

CS4215 COMPAT IBILIT Y . . . . . . . . . . . . . . . . . . . . . . . . 25

FREQUENCY RESPONSE PLOT S . . . . . . . . . . . . . . . . 26

PACKAGE—Outline Dimension Drawings . . . . . . . . . . . . 28

REV. 0

–27–

AD1849K

O UTLINE D IMENSIO NS

D imensions shown in inches and (mm).

44-Lead P lastic Leaded Chip Car r ier (P LCC)

0.180 (4.57)

0.165 (4.19)

0.056 (1.42)

0.048 (1.21)

0.042 (1.07)

0.025 (0.63)

0.042 (1.07)

0.020 (0.50) R

0.015 (0.38)

0.048 (1.21)

0.042 (1.07)

6

40

39

PIN 1

7

IDENTIFIER

PIN 1

IDENTIFIER

0.021 (0.53)

0.013 (0.33)

0.63 (16.00)

0.59 (14.99)

0.032 (0.81)

BOTTOM VIEW

TOP VIEW

0.026 (0.66)

0.050

(1.27)

BSC

17

29

28

18

0.040 (1.01)

0.025 (0.64)

0.656 (16.66)

0.650 (16.51)

SQ

0.110 (2.79)

0.085 (2.16)

0.695 (17.65)

0.685 (17.40)

44-Lead Thin Q uad Flatpack (TQ FP )

0.006 ± 0.002

(0.145 ± 0.055)

0.472 (12.00) SQ

0.024 ± 0.006

(0.6 ± 0.15)

0

MIN

°

33

23

34

22

0.394

(10.0)

SQ

TOP VIEW

SEATING

PLANE

PIN 1

44

12

1

11

0.004 ± 0.002

(0.1 ± 0.05)

0.055 ± 0.002

(1.40 ± 0.05)

0.018 (0.45)

0.012 (0.30)

0.0315 (0.80)

BSC

0.093 (1.6)

MAX

–28–

REV. 0


型号：	AD1849KP
厂家：	ADI
描述：	Serial-Port 16-Bit SoundPort Stereo Codec 串行端口16位SoundPort立体声编解码器解码器编解码器消费电路商用集成电路
文件：	总28页 (文件大小：295K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD1849KP [ADI]

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