MAT02FHZ [ADI]
TRANSISTOR 20 mA, 40 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR, TO-78, METAL CAN-6, BIP General Purpose Small Signal;
| 型号： | MAT02FHZ |
| 厂家： | 
ADI |
| 描述： | TRANSISTOR 20 mA, 40 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR, TO-78, METAL CAN-6, BIP General Purpose Small Signal 开关 晶体管 |
| 文件： | 总12页 (文件大小：648K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, Matched
Dual Monolithic Transistor
a
MAT02
PIN CONNECTION
FEATURES
Low Offset Voltage: 50 V max
Low Noise Voltage at 100 Hz, 1 mA: 1.0 nV/√Hz max
High Gain (hFE):
TO-78
(H Suffix)
500 min at IC = 1 mA
300 min at IC = 1 A
Excellent Log Conformance: rBE Ӎ 0.3 ⍀
Low Offset Voltage Drift: 0.1 V/؇C max
Improved Direct Replacement for LM194/394
NOT
Sbstrate is coned to case on TO-78 package.
ubstrate is normaonnected to the most negative
circuit potential, but cbe floated.
PRODUCT DESCRIPTION
The design of the MAT02 series of NPN dual monolithic tran-
sistors is optimized for very low noise, low drift and low rBE
Precision Monolithics’ exclusive Silicon Nitride “Triple-
Passivation” process stabilizes the critical device parameters
over wide ranges of temperature and elapsed time. Also, the high
current gain (hFE) of the MAT02 is maintained over a
range of collector current. Exceptional characteristics
MAT02 include offset voltage of 50 µV max (A/E gr
150 µV max F grade. Device performance is specified
full military temperature range as well as at .
The MAshould used in any application where low
noise is a prity. he MAT02 can be used as an input
stage to make mplifier with noise voltage of less than
1.0 nV/√Hz at 100 Hz. Other applications, such as log/antilog
cuits, muse the excellent logging conformity of the
M0Typical bulk resistance is only 0.3 Ω to 0.4 Ω. The
MAT2 electrical characteristics approach those of an ideal
ransistor when operated over a collector current range of 1
µA to 10 mA. For applications requiring multiple devices
see MAT04 Quad Matched Transistor data sheet.
.
Input protection diodes are provided acrthe em-base
junctions to prevent degradation of the daractetics
due to reverse-biased emitter current. The substrate is amped
to the most negative emitter by sitic isoiunction
created by the protection dios in complete isola-
tion between the transistors.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
MAT02–SPECIFICATIONS
(@ VCB = 15 V, IC = 10 A, TA = 25؇C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
MAT02E
MAT02F
Parameter
Symbol
Conditions
Min Typ Max Min Typ
Max
Unit
Current Gain
hFE
IC = 1 mA1
500
500
400
300
605
590
550
485
0.5
10
10
10
5
5
400
400
300
200
605
590
550
485
0.5
80
10
10
5
5
IC = 100 µA
IC = 10 µA
IC = 1 µA
Current Gain Match
Offset Voltage
Offset Voltage
∆hFE
VOS
10 µA ≤ IC ≤ 1 mA2
2
4
%
VCB = 0, 1 µA ≤ IC ≤ 1 mA3
50
25
25
25
25
150
50
50
50
50
µV
µV
µV
µV
µV
4
∆VOS/∆VCB 0 ≤ VCB ≤ VMAX
Change vs. VCB
1 µA ≤ IC ≤ 1 mA3
Offset Voltage Change
vs. Collector Current
Offset Current
∆VOS/∆IC
VCB = 0 V
1 µA ≤ IC ≤ 1 mA3
Change vs. VCB
Bulk Resistance
Collector-Base
∆IOS/∆VCB 0 ≤ VCB ≤ VMAX
30
0.3
70
0
0
0.3
0.5
pA/V
Ω
rBE
10 µA ≤ IC ≤ 10 mA5
Leakage Current
Collector-Collector
Leakage Current
Collector-Emitter
Leakage Current
Noise Voltage Density
ICBO
ICC
VCB = VMAX
25
35
3
20
200
200
25
35
35
400
400
400
pA
pA
pA
5, 6
VCC = VMAX
5, 6
VCE = VMAX
ICES
en
VBE = 0
IC = 1 mA, VCB = 07
fO = 10 Hz
0.9
0.85
0.85
1
1
1
1.6
0.9
0.85
0.85
3
2
2
2
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fO = 100 Hz
fO = 1 kHz
fO = 10 kHz
Collector Saturation
Voltage
Input Bias Current
Input Offset Current
Breakdown Voltage
VCE(SAT)
IB
IOS
IC = 1 mA, IB =
IC = 10 µA
IC = 10 µA
0.05 0.1
0.05
0.2
34
1.3
V
25
0.6
nA
nA
V
BVCEO
40
40
Gain-Bandwidth Product fT
IC = 0 mA, V= 10 V
VCB 15 E =
200
23
200
23
MHz
pF
Output Capacitance
Collector-Collector
Capacitance
COB
CCC
C = 0
35
35
pF
NOTES
1Current gain is guaranteed with Collectswept from 0 to VMAX at the indicated collector currents.
2Current gain match (∆hFE) is defined as: ∆
FE min)
C
3Measured at IC = 10 µA and y desige specified range of IC.
4This is the maximum chans swept om 0 V to 40 V.
5Guaranteed by design.
6ICC and ICES are verified bBO
7Sample tested.
.
Specifications subject to change otice.
–2–
REV. E
MAT02
(V = 15 V, –25؇C ≤ T ≤ +85؇C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
CB
A
MAT02E
MAT02F
Min Typ Max
Parameter
Symbol
Conditions
Min Typ Max
Unit
Offset Voltage
VOS
VCB = 0
70
220
µV
1 µA ≤ IC ≤ 1 mA1
Average Offset
Voltage Drift
2
TCVOS
IOS
10 µA ≤ IC ≤ 1 mA, 0 ≤ VCB ≤ VMAX
0.08 0.3
0.03 0.1
8
0.08 1
0.03 0.3
13
µV/°C
V
OS Trimmed to Zero3
Input Offset Current
Input Offset
Current Drift
Input Bias Current
Current Gain
IC = 10 µA
nA
TCIOS
IB
hFE
IC = 10 µA4
IC = 10 µA
IC = 1 mA5
IC = 100 µA
IC = 10 µA
IC = 1 µA
40
90
4
40
150
50
pA/°C
nA
325
275
225
20
00
250
200
1
Collector-Base
ICBO
ICES
ICC
VCB = VMAX
3
3
3
4
4
nA
nA
nA
Leakage Current
Collector-Emitter
Leakage Current
Collector-Collector
Leakage Current
VCE = VMAX, VBE = 0
VCC = VMAX
NOTES
1Measured at IC = 10 µA and guaranteed by design over the specified range of I
VOS
2Guaranteed by VOS test (TCVOS
≅
for VOS ꢀ VBE) T = 298K for TA = 25°C.
T
3The initial zero offset voltage is established by adjusting the ratio o= 25°his ratio must be held to 0.003% over the entire temperature range.
Measurements are taken at the temperature extremes and 25°C.
4Guaranteed by design.
5Current gain is guaranteed with Collector-Base Voltage (VCB) sweX at the indicated collector current.
Specifications subject to change without notice.
ABSOLUTE MAXIMUM RATINGS1
Collector-Base Voltage (BVCBO) . . . . . . . . . . . . . . . . . . 40 V
Collector-Emitter Voltage (BVC. . . . . . . . . . . . 40 V
Collector-Collector Voltage (. . . . . . . . . . . . . . . 40 V
Operating Junction Temperature . . . . . . . . . . –55°C to +150°C
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . . 300°C
Junction Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Emitter-Emitter Voltage (BV
. . . . . . . . . . 40 V
Collector Current (IC) . . . . . . . . . . . . . . . 20 mA
Emitter Current (IE) . . . . . . . . . . . . . . . . 20 mA
Total Power Dissi
NOTES
1Absolute maximum ratings apply to both DICE and packaged devices.
2Rating applies to applications using heat sinking to control case temperature.
Derate linearly at 16.4 mW/°C for case temperature above 40°C.
3Rating applies to applications not using a heat sinking; devices in free air only.
Derate linearly at 6.3 mW/°C for ambient temperature above 70°C.
Case Tempera. . . . . . . . . . . . . . . . . . . 1.8 W
Ambient Temp. . . . . . . . . . . . . . . . 500 mW
Operating Temper
MAT02E, F . . . . . . . . . . . . . . . . . . . .–25°C to +85°C
ORDERING GUIDE
VOS max
(TA = 25؇C)
Temperature
Range
Package
Option
Model
MAT02EH
MAT02FH
50 µV
150 µV
–25°C to +85°C
–25°C to +85°C
TO-78
TO-78
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT02 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. E
–3–
–Typical Performance Characteristics
MAT02
TPC 2. Current Gain
vs. Temperature
TPC 1. Current Gain vs.
Collector Current
T3. in Bandwidth
vs. ctor Cuent
TPC 6. Small-Signal Output
Conductance vs. Collector Current
TPC 4. Base-Emitter-On
Voltage vs. Collector Current
T. all Signal Input
Resistanvs. Collector Current
TPC 9. Noise Voltage Density
vs. Collector Current
TPC 8. Noise Voltage
Density vs. Frequency
TPC 7. Saturation Voltage
vs. Collector Current
REV. E
–4–
MAT02
TPC . Collector-to-Base
age vs. emperature
TPC 10. Noise Current
Density vs. Frequency
TPC 11. Total Noise vs.
Collective Current
TPC 15. Collector-Base
Capacitance vs. Reverse Bias Voltage
TPC 13. Collector-to-Collector
Leakage vs. Temperature
TPC . Collector-to-Collector
Captance vs. Collector-to
Sstrate Voltage
TPC 16. Collector-to-Collector
Capacitance vs. Reverse Bias
Voltage
TPC 17. Emitter-Base Capacitance
vs. Reverse Bias Voltage
REV. E
–5–
MAT02
Figure 1. Lonce TCircuit
LOG CONFORMANCE TESTING
kT
q
IC1
IC2
In
∆VBE
=
+ IC1 rBE1 – IC2 rBE2
(2)
The log conformance of the MAT02 is tested usg the circuit
shown above. The circuit employs a dual transode logmic
converter operating at a fixed ratio of collector rrthat e
swept over a 10:1 range. The output of each transdiode conter
is the VBE of the transistor plus an errwhich is he od-
uct of the collector current and rBter resistance.
The difference of the VBE is ampli100 by the
AMP01 instrumentation amplifier. Temitter-base
voltage (∆VBE) consists of eraturent dc level plus
an ac error voltage, whation m true log confor-
mity as the collector c
A ramp function that sweeps from 1 V to 10 V is converted by
the op amps to a collector current ramp through each transistor.
Because IC1 is made equal to 10 IC2, and assuming TA = 25°C,
the previous equation becomes:
∆VBE = 59 mV + 0.9 IC1 rBE (∆rBE ~ 0)
As viewed on an oscilloscope, the change in ∆VBE for a 10:1
change in IC is then displayed as shown in Figure 2 below:
The output of the tranmic converter comes from
the idealized intrinsic traation (for silicon):
kT
q
IC
IS
VBE
=
In
(1)
Figure 2.
where
k = Boltzmann’s Constant (1.38062 × 10–23 J/K)
q = Unit Electron Charge (1.60219 × 10–19 °C)
T = Absolute Temperature, K (= °C + 273.2)
IS = Extrapolated Current for VBE→0
IC = Collector Current
With the oscilloscope ac coupled, the temperature dependent
term becomes a dc offset and the trace represents the deviation
from true log conformity. The bulk resistance can be calculated
from the voltage deviation ∆VO and the change in collector
current (9 mA):
∆VO
9mA 100
1
×
rBE
=
(3)
An error term must be added to this equation to allow for the
bulk resistance (rBE) of the transistor. Error due to the op amp
input current is limited by use of the OP15 BiFET-input op
amp. The resulting AMP01 input is:
This procedure finds rBE for Side A. Switching R1 and R2 will
provide the rBE for Side B. Differential rBE is found by making
R1 = R2.
REV. E
–6–
MAT02
Figure 3. One-Quadrant Multiplier/Divider
these ects cbe lumped together as a total effective bulk
resistanc. The rC term causes departure from the desired
logarithmic latiohip. The rBE term for the MAT02 is less
than 0.5 Ω anBE between the two sides is negligible.
APPLICATIONS: NONLINEAR FUNCTIONS
MULTIPLIER/DIVIDER CIRCUIT
The excellent log conformity of the MAT02 over a very wide
range of collector current makes it ideal for use in log-antilog
circuits. Such nonlinear functions as multiplying, dividing,
squaring and square-rooting are accurately and easily imple-
mented with a log antilog circuit using two MAT02 pai
Figure 3). The transistor circuit accepts three input c
I2 and I3) and provides an output current IO accordin
IO = I1I2/I3. All four currents must be positive in the l
circuit, but negative input voltages can be eaccomm
by various offsetting techniques. Protectivdiodes across each
base-to-emitter junction would normally nee, bthese
diodes are built into the MAT02. External protection des
are, therefore, not needed.
Returning tthe multiplier/divider circuit of Figure 1 and using
uation 4):
VBA + VBE2A – VBE2B – VBE1B + (I1 + I2 – IO – I3) rBE = 0
f the transistor pairs are held to the same temperature, then:
I1I2
I3IO
IS1AI
IS1B IS2B
kT
q
kT
q
S2A + (I1 + I2 – IO – I3) rBE (6)
In
=
In
If all the terms on the right-hand side were zero, then In
(I1 I2/I3 IO) would equal zero, which would lead directly to
the desired result:
For the circuit shown in Figutional amplifiers
make I1 = VX/R1, I2 = VY/R2, O = VO/RO. The
output voltage for this one-qualog multiplier/
divider is ideally:
I1I2
I3
IO
=
, where I1, I2, I3, IO > 0
(7)
Note that this relationship is temperature independent. The
right-hand side of Equation (6) is near zero and the output
current IO will be approximately I1 I2/I3. To estimate error,
define ø as the right-hand side terms of Equation (6):
VO
=
X, VY, VZ > 0)
(4)
If all the resistors (RR3) are made equal, then
VO = VXVY/VZ
IS1AIS2A
IS1B IS2B kT
q
+
ø = In
(I1 + I2 – IO – I3) rBE
(8)
For the MAT02, In (ISA/ISB) and ICrBE are very small. For small
Resistor values of 50 kΩ to 100 kΩ are recommended assuming
an input range of 0.1 V to +10 V.
ø, εØ ~ 1 + ø and therefore:
I1I2
I3IO
ERROR ANALYSIS
The base-to-emitter voltage of the MAT02 in its forward active
operation is:
= 1 + ø
(9)
kT IC
I1I2
I3
In
VBE
=
+ rBEIC, VCB ~ 0
(5)
(1 – ø)
IO
~
q
IS
The first term comes from the idealized intrinsic transistor
equation previously discussed (see equation (1)).
The In (ISA/ISB) terms in ø cause a fixed gain error of less than
0.6% from each pair when using the MAT02, and this gain
error is easily trimmed out by varying RO. The IOUT terms are
Extrinsic resistive terms and the early effect cause departure
from the ideal logarithmic relationship. For small VCB, all of
REV. E
–7–
MAT02
more troublesome because they vary with signal levels and are
multiplied by absolute temperature. At 25°C, kT/q is
sumption or single-supply operation is needed. The value of
frequency-compensating capacitor (CO) is dependent on the
op amp frequency response and peak collector current. Typi-
cal values for CO range from 30 pF to 300 pF.
approximately 26 mV and the error due to an rBEIC term will be
r
BEIC/26 mV. Using an rBE of 0.4 Ω for the MAT02 and assum-
ing a collector current range of up to 200 µA, then a peak error
of 0.3% could be expected for an rBEIC error term when using
the MAT02. Total error is dependent on the specific application
configuration (multiply, divide, square, etc.) and the required
dynamic range. An obvious way to reduce ICrBE error is to re-
duce the maximum collector current, but then op amp offsets
and leakage currents become a limiting factor at low input lev-
els. A design range of no greater than 10 µA to 1 mA is generally
recommended for most nonlinear function circuits.
A powerful technique for reducing error due to ICrBE is shown in
Figure 4. A small voltage equal to ICrBE is applied to the transis-
tor base. For this circuit:
Figure 4. Compention of k Resance Error
RC
R2
rBE
R1
VB =
V1 and ICrBE
=
V1
(10)
FOUR-QUADRANMUIPLIER
A simplified schematic for a f-quadrant log-antilog multiplier
is shown in Fire 5. Similar to previously discussed one-
quadrant mtiplier, e circuit makes IO = I1 I2/I3. The two
input currs, I1 d I2, are each offset in the positive direction.
This positive t is theubtracted out at the output stage.
Assuming ideal ampthe currents are:
The error from rBEIC is cancelled if RC/R2 is made equal to rOUT R1.
Since the MAT02 bulk resistance is approximately 0.39 Ω, an
RC of 3.9 Ω and R2 of 10 R1 will give good error cancellation.
In more complex circuits, such as the circuit in Figure 3, it may
be inconvenient to apply a compensation voltage to each indi-
vidual base. A better approach is to sum all compensation to the
bases of Q1. The “A” side needs a base voltage of (VO/RO + VZ/
R3) rBE, and the “B” side needs a base voltage of (VX/R1+VY/R)
VX
R
1
V
R2
VY VR
R
I1 =
+
R , I2 =
+
1
R2
r
BE. Linearity of better than 0.1% is readily achievable wit
(11)
(12)
this compensation technique.
VX VY VR VO
VR
R2
IO
=
+
+
1
+
, I3 =
Operational amplifier offsets are another source of erro
Figure 4, the input offset voltage and input bias current
cause an error in collector current of (VOS/R1IB. A low
offset op amp, such as the OP07 with less tn 75 µV VOS
and IB of less than 3 nA, is recommended. 193,
micropower op amp, should be considered if low power n-
R
1
R
R2 RO
From IO = I1 I2/I3, the output voltage will be:
ROR2 VXVY
VO
=
R12
VR
Figure 5. Four-Quadrant Multiplier
REV. E
–8–
MAT02
Figure 6. Multifunction Conver
Collector current range is the key design decision. The inher-
ently low rBE of the MAT02 allows the use of a relative
collector current. For input scaling of 10 V full-scal
a 10 V reference, we have a collector-current range f
of:
LTIFNCTION CONVERTER
Thtifunction converter circuit provides an accurate means
of squaring, square rooting, and raising ratios to arbitrary pow-
ers. The excellent log conformity of the MAT02 allows a wide
range of exponents. The general transfer function is:
VZ m
–10 10
10 1
R1 R
+
≤ I
≤
+
C
(13)
VO = VY
(15)
R
R2
1
V
X
Practical values for R1 and R2 woulrange from 50 kΩ o
VX, VY, and VZ are input voltages and the exponent “m” has a
practical range of approximately 0.2 to 5. Inputs VX and VY are
often taken from a fixed reference voltage. With a REF01 pro-
viding a precision 10 V to both VX and VY, the transfer function
would simplify to:
100 kΩ. Choosing an R1 of 82 k2 of 62 ovides a
collector current range of apA to 283 µA. An
RO of 108 kΩ will then make factor 1/10 and
VO = VXVY/10. The output, as wnputs, are scaled for
10 V full scale.
VZ m
Linear error for tstantially improved by the
small correction o the base of Q1 as shown in
Figure 5. Assumink emitter resistance for each
MAT02 transistor, tror is nulled if:
VO = 10
(16)
10
As with the multiplier/divider circuits, assume that the transistor
pairs have excellent matching and are at the same temperature.
The In ISA/ISB will then be zero. In the circuit of Figure 6, the
voltage drops across the base-emitter junctions of Q1 provide:
(I1 + I2 – I3 – IO) rBE + ρVO = 0
The currents are known from the previous discussion, and the
relationship needed is simply:
RB
RB + KRA
kT
q
IZ
IX
VA
=
In
(17)
rBE
RO
VO
=
VO
(14)
IZ is VZ/R1 and IX is VX/R1. Similarly, the relationship for Q2 is:
The output voltage is attenuated by a factor of rBE/RO and ap-
plied to the base of Q1 to cancel the summation of voltage drops
due to rBEIC terms. This will make In (I1 I2/I3 IO) more nearly
zero which will thereby make IO = I1 I2/I3 a more accurate rela-
tionship. Linearity of better than 0.1% is readily achievable with
this circuit if the MAT02 pairs are carefully kept at the same
temperature.
RB
kT
q
IO
IY
VA
=
In
(18)
R + 1– K R
(
)
B
A
IO is VO/RO and IY is VY/R1. These equations for Q1 and Q2 can
then be combined.
RB + KRA
R + 1– K R
IZ
IO
IY
In
= In
(19)
IX
(
)
B
A
REV. E
–9–
MAT02
Substituting in the voltage relationships and simplifying leads
to:
R
R1
VZ m
O VY
VO
=
, where
V
X
(20)
RB + KRA
m =
R + 1– K R
(
)
B
A
The factor “K” is a potentiometer position and varies from zero
to 1.0, so “m” ranges from RB/(RA + RB) to (RB + RA)/RB.
Practical values are 125 Ω for RB and 500 Ω for RA; these
values will provide an adjustment range of 0.2 to 5.0. A value
of 100 kΩ is recommended for the R1 resistors assuming a full-
scale input range of 10 V. As with the one-quadrant
multiplier/divider circuit previously discussed, the VX, VY, and
VZ inputs must all be positive.
The op amps should have the lowest possible input offsets. The
OP07 is recommended for most applications, although such
programmable micropower op amps as the OP193/OP293 offer
advantages in low-power or single-supply circuits. The micro-
power op amps also have very low input bias-current drift, an
important advantage in log/antilog circuits. External offset
nulling may be needed, particularly for applications requiring a
wide dynamic range. Frequency compensating capacitors, on
the order of 50 pF, may be required for A2 and A3. Amplifier
A1 is likely to need a larger capacitor, typically 0.0047 µF, to
assure stability.
Fige 7. Fast Loithmic Amplifier
LOW-NO
؋
10AMPLIFIER The MAT0oivoltage exceptionally low, only 1 nV/√Hz
at 10 Hz when erated er a collector current range of 1 mA
to 4 mA. A singled ×1000 amplifier that takes advantage of
tlow MAT02 noise level is shown in Figure 8. In addition to
low ise, the aplifier has very low drift and high CMRR. An
OP18usefor the second stage to obtain good speed with
nimal wer consumption. Small-signal bandwidth is 4.0
, slew rate is 2.4 V/µs, and total supply current is approxi-
y 2.25 mA.
Accuracy is limited at the higher input levels by bulk emit
resistance, but this is much lower for the MAT02 than for
transistor pairs. Accuracy at the lower signal levprimarily
depends on the op amp offsets. Accuracies of tter tha%
are readily achievable with this circuit configuiod cae
better than 0.1% over a limited operating range.
FAST LOGARITHMIC AMPLIF
The circuit of Figure 7 is a modifard logarith-
mic amplifier configuration. Runninat 2.5 mA
per side (full-scale) allows responwide dynamic
range. The circuit has rrent ge, a 5 decade
voltage range, and is settling time to 1% with
a 1 V to 10 V step.
The output follows the e
R3 + R2 kT VREF
In
VO
=
(21)
R2
q
VIN
The output is inverted with respect to the input, and is nomi-
nally –1 V/decade using the component values indicated.
Figure 8. Low-Noise, Single-Ended × 1000 Amplifier
REV. E
–10–
MAT02
Transistors Q2 and Q3 form a 2 mA current source (0.65 V/
330 Ω ~ 2 mA). Each collector of Q1 operates at 1 mA. The
OP184 inputs are 3 V below the positive supply voltage (RLIC
~ 3 V). Input stage gain is gmRL, which is approximately 100
when operating at IC of 1 mA with RL of 3 kΩ. Since the
OP184 has a minimum open-loop gain of 500,000, total
open-loop gain for the composite amplifier is over 50 million.
Even at closed-loop gain of 1000, the gain error due to finite
open-loop gain will be negligible. The OP184 features excellent
symmetry of slew-rate and very linear gain. Signal distortion is
minimal.
Input bias current is relatively low due to the high current gain
of the MAT02. The minimum β of 400 at 1 mA for the
MAT02F implies an input bias current of approximately 2.5 µA.
This circuit should be used with signals having relatively low
source impedance. A high source impedance will degrade offset
and noise performance.
This circuit configuration provides exceptionally low input noise
voltage and low drift. Noise can be reduced even further by
raising the collector currents from 1 mA to 3 mA, but power
consumption is then increased.
Dynamic range of this amplifier is excellent; the OP184 has an
output voltage swing of 14.8 V with a 15 V supply.
Input characteristics are outstanding. The MAT02F has offset
voltage of less than 150 µV at 25°C and a maximum offset drift
of 1 µV/°C. Nulling the offset will further reduce offset drift.
This can be accomplished by slightly unbalancing the collector
load resistors. This adjustment will reduce the drift to less than
0.1 µV/°C.
REV. E
–11–
MAT02
OUTLINE DIMENSION
Dimensions shown in inches and (mm).
6-Lead Metal Can
(TO-78)
REFERENCE PLANE
0.750 (19.05)
0.500 (12.70)
0.185 (4.70)
0.165 (4.19)
0.250 (6.35) MIN
0.050 (1.27) MAX
0.100 (2.54) BSC
4
0.160 (4.06)
0.110 (2.79)
5
0.045 (1.14)
0.027 (0.69)
0.200
(5.08)
BSC
3
6
2
1
0.100
(2.54)
BSC
0.019 (0.48)
0.016 (0.41)
0.034 (0.86)
0.027 (0.69)
0.040 (1.02) MAX
0.021 (0.53)
0.016 (0.41)
0.045 (1.14)
0.010 (0.25)
45° B
BASE AND SEATING PLANE
Revision History
Location
Page
4/02—Data Sheet changed from REV. D to REV. E.
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1/02—Data Sheet changed from REV. C to RV. D.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Deleted ELECTRICAL CHARA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted TYPICAL ELCHCTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Deleted DICE CHAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to ABSOLUTE ATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Updated Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
REV. E
–12–
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