MAT03-913L [ADI]
TRANSISTOR SMALL SIGNAL TRANSISTOR, CERAMIC, FLATPAK-2, BIP General Purpose Small Signal;
| 型号： | MAT03-913L |
| 厂家： | 
ADI |
| 描述： | TRANSISTOR SMALL SIGNAL TRANSISTOR, CERAMIC, FLATPAK-2, BIP General Purpose Small Signal CD |
| 文件： | 总5页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Tuesday, Feb 26, 2008 3:48 PM /
Low noise, matched,
dual PNP transistor
MAT03
1.0
SCOPE
This specification documents the detail requirements for space qualified product manufactured on
Analog Devices, Inc.'s QML certified line per MIL-PRF-38535 Level V except as modified herein.
The manufacturing flow described in the STANDARD SPACE LEVEL PRODUCTS PROGRAM
brochure is to be considered a part of this specification. http://www.analog.com/aerospace
This data sheet specifically details the space grade version of this product. A more detailed
operational description and a complete datasheet for commercial product grades can be found at
www.analog.com/MAT03
2.0
Part Number. The complete part number(s) of this specification follow:
Part Number
Description
MAT03-903H
MAT03-903L
MAT03-913H
MAT03-913L
Low noise, matched, dual PNP transistor
Low noise, matched, dual PNP transistor
Radiation Tested, Low noise, matched, dual PNP transistor
Radiation Tested, Low noise, matched, dual PNP transistor
2.1
Case Outline.
Letter Descriptive designator Case Outline (Lead Finish per MIL-PRF-38535)
H
L
MACY1-X6
GDFP1-F10
6-Lead can package (TO)
10-Lead ceramic flatpack (cerpak)
Figure 1 - Terminal connections.
3.0
Absolute Maximum Ratings. (TA = 25°C, unless otherwise noted)
Collector to base voltage (BVCBO)..................................................................................36V
Collector to emitter voltage (BVCEO)..............................................................................36V
Collector to collector voltage (BVCC).............................................................................36V
Emitter to emitter voltage (BVEE)...................................................................................36V
Collector current (IC)....................................................................................................20mA
Emitter current (IE).......................................................................................................20mA
Total power dissipation 1/........................................................................................500mW
Operating ambient temperature range.............................................................-55 to +125°C
Operating junction temperature range ....................................................... -55°C to +125°C
Storage temperature range ......................................................................... -65°C to +150°C
Lead temperature (soldering, 60 sec)........................................................................+300°C
Dice junction temperature range................................................................ -65°C to +150°C
1/ Rating applies to applications not using heat sinking, device is free air only.
ASD0011414
Rev. F
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may
result from its use. Specifications subject to change without notice. No license
is granted by implication or otherwise under any patent or patent rights of
Analog Devices. Trademarks and registered trademarks are the property of
their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106,
U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2008 Analog Devices, Inc. All rights reserved.
MAT03
3.1
Thermal Characteristics:
Thermal Resistance, TO-78 (H) Package
Junction-to-Case (ΘJC) = 45°C/W Max
Junction-to-Ambient (ΘJA) = 150°C/W Max
Derate linearly at 6.67 mW/°C for ambient temperatures above 70°C.
Thermal Resistance, cerpac (L) Package
Junction-to-Case (ΘJC) = 80°C/W Max
Junction-to-Ambient (ΘJA) = 180°C/W Max
Derate linearly at 5.56 mW/°C for ambient temperatures above 70°C.
Terminal Connections 1/
Terminal
6 lead TO 10 lead flatpack
1
2
3
4
5
C1
B1
E1
E2
B2
C2
C1
nc
B1
nc
E1
E2
nc
6
7
8
9
B2
nc
10
11
12
13
14
15
16
17
18
19
20
C2
1/ Substrate is connected to case on TO-78 package. Substrate is normally connected to the most
negative circuit potential, but can be floated.
ASD0011414 Rev. F | Page 2 of 5
MAT03
4.0
Electrical Table:
Table I
Parameter
See notes at end of table
Current gain
Symbol
hFE
Conditions 1/
Sub-
group
1
2, 3
1
2, 3
1
2, 3
1
Limit Limit
Units
Min
100
70
Max
IC = 1mA, VCB = 0V, -36V
90
60
80
50
IC = 100μA, VCB = 0V, -36V
IC = 100μA, VCB =-36V
IC = 10μA, VCB = 0V, -36V
IC = 10μA, VCB = -36V
IC = 100μA, VCB = 0V
VCB = 0V
Current gain match 2/
Offset voltage
3
%
μV
ΔhFE
VOS
1
2,3
100
150
0.5
Change in offset voltage vs
temperature 3/
Offset voltage change vs VCB
TCVOS
VCB = 0V
μV/°C
μV
VCB = 0V, -36V
1
1
150
50
ΔVOS
/ ΔVCB
ΔVOS/
ΔIC
Offset voltage change vs
collector current
IC1 = 10μA, IC2 = 1mA,
VCB=0V
Input offset current
IOS
rBE
ICBO
VCESAT
BVCEO
eN
1
1
1
1
1
7
35
0.75
200
0.1
nA
Ohm
pA
V
V
CB = 0V, IC = 100μA
Bulk emitter resistance
Collector base leakage current
Collector saturation voltage
Breakdown voltage
VCB = -36V
IC = 1mA, IB = 100μA
36
V
Noise voltage density
IC = 1mA
VCB = 0V
fO = 10Hz
2
nV/ Hz
fO = 100Hz
fO = 1000Hz
fO = 10000Hz
1
1
1
TABLE I NOTES:
1/ VCB = -15V, IC = 10μA, unless otherwise specified.
100(ΔIB )hFE min
2/ Current gain match (ΔhFE) is defined as: ΔhFE =
.
IC
3/ Guaranteed by VOS test (TCVOS = VOS/T for VOS << VBE) (T = 298°K for TA = +25°C).
ASD0011414 Rev. F | Page 3 of 5
MAT03
4.1
Electrical Test Requirements:
Table II
Test Requirements
Subgroups (in accordance
with MIL-PRF-38535,
Table III)
Interim Electrical Parameters
Final Electrical Parameters
Group A Test Requirements
1
1, 2, 3, 1/ 2/
1, 2, 3, 7
Group C end-point electrical parameters 1 2/
Group D end-point electrical parameters
Group E end-point electrical parameters
1
1
1/ PDA applies to Subgroup 1. Delta's excluded from PDA.
2/ See Table III for delta parameters. See table I for conditions.
4.2
Table III. Burn-in test delta limits.
Table III
TEST
TITLE
BURN-IN LIFETEST
ENDPOINT ENDPOINT
DELTA
LIMIT
UNITS
hFE @ 1mA
hFE @ 100μA
hFE @ 10μA
IOS
100 min
90 min
80 min
35
60 min
54 min
48 min
55
±40
±36
±32
±20
nA
5.0
Life Test/Burn-In Circuit:
5.1
5.2
5.3
HTRB is not applicable for this drawing.
Burn-in is per MIL-STD-883 Method 1015 test condition B.
Steady state life test is per MIL-STD-883 Method 1005.
ASD0011414 Rev. F | Page 4 of 5
MAT03
Rev
A
B
Description of Change
Date
July 24, 2000
Jan. 22, 2002
Initiate
Page 1: Update web address; correct typo for dice junction
temperature.
Page 2: change RC package theta JC from 18 to 35 °C
Page 3: delete text “note 1” under table I conditions; change delta hFE
condition from mA to μA; delete subgroups for TCVOS; format note
numbers for table I; change note 3 from ” This is the maximum change in
VOS measured at IC = 10mA with VCB = 0V” TO “Guaranteed by VOS test
(TCVOS = VOS/T for VOS << VBE) (T = 298°K for TA = +25°C)”
Page 4, Table II: delete subgroup 7 from final electricals
Page 5: add resistor values to burn-in figure.
Change R3 of BI circuit from 2.5K to 10K ohm.
Update web address. Delete burn-in circuit.
Update package offering
C
D
E
F
Apr. 17, 2002
June 20, 2003
Oct. 10, 2007
Feb. 25,2008
Update header/footer & add to 1.0 scope description
© 2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective
companies.
Printed in the U.S.A.
02/08
ASD0011414 Rev. F | Page 5 of 5
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