MAT03 [ADI]
Low Noise, Matched Dual PNP Transistor; 低噪声，匹配双PNP晶体管
| 型号： | MAT03 |
| 厂家： | 
ADI |
| 描述： | Low Noise, Matched Dual PNP Transistor |
| 文件： | 总12页 (文件大小：255K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, Matched
Dual PNP Transistor
a
MAT03
FEATURES
P IN CO NNECTIO N
Dual Matched PNP Transistor
Low Offset Voltage: 100 V m ax
Low Noise: 1 nV/ √Hz @ 1 kHz m ax
High Gain: 100 m in
TO -78
(H Suffix)
High Gain Bandw idth: 190 MHz typ
Tight Gain Matching: 3% m ax
Excellent Logarithm ic Conform ance: rBE Ӎ 0.3 ⍀ typ
Available in Die Form
Each transistor is individually tested to data sheet specifications.
Device performance is guaranteed at 25°C and over the extended
industrial and military temperature ranges. T o insure the long-
term stability of the matching parameters, internal protection
diodes across the base-emitter junction clamp any reverse base-
emitter junction potential. T his prevents a base-emitter break-
down condition which can result in degradation of gain and
matching performance due to excessive breakdown current.
GENERAL D ESCRIP TIO N
T he MAT 03 dual monolithic PNP transistor offers excellent
parametric matching and high frequency performance. Low
noise characteristics (1 nV/√Hz max @ 1 kHz), high bandwidth
(190 MHz typical), and low offset voltage (100 µV max), makes
the MAT 03 an excellent choice for demanding preamplifier ap-
plications. T ight current gain matching (3% max mismatch) and
high current gain (100 min), over a wide range of collector cur-
rent, makes the MAT 03 an excellent choice for current mirrors.
A low value of bulk resistance (typically 0.3 Ω) also makes the
MAT 03 an ideal component for applications requiring accurate
logarithmic conformance.
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
MAT03–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
(@ T = +25؇C, unless otherwise noted.)
A
MAT03A
Min Typ
MAT03E
MAT03F
P aram eter
Sym bol
Conditions
Max Min Typ Max Min Typ Ma x Units
Current Gain1
hFE
VCB = 0 V, –36 V
IC = 1 mA
IC = 100 µA
IC = 10 µA
IC = 100 µA,VCB = 0 V
VCB = 0 V, IC = 100 µA
100 165
100 165
80
70
60
165
150
120
0.5
40
90
150
120
0.5
40
90
150
120
0.5
40
80
80
Current Gain Matching2 DhFE
3
100
3
100
6
200
%
µV
Offset Voltage3
VOS
Offset Voltage Change
vs. Collector Voltage
DVOS/DVCB IC = 100 µA
VCB1 = 0 V
VCB2 = –36 V
DVOS/DIC VCB = 0 V
11
11
12
12
0.3
0.3
6
150
150
50
11
11
12
12
0.3
0.3
6
150
150
50
11
11
12
12
0.3
0.3
6
200
200
75
µV
µV
µV
µV
Ω
Offset Voltage Change
vs. Collector Current
Bulk Resistance
IC1 = 10 µA, IC2 = 1 mA
VCB = 0 V
10 µA ≤ IC ≤ 1 mA
50
50
75
rBE
IOS
0.75
0.75
35
0.75
0.75
35
0.75
0.75
45
Ω
nA
Offset Current
IC = 100 µA, VCB = 0 V
Collector-Base
Leakage Current
ICB0
eN
VCB = –36 V = VMAX
IC = 1 mA, VCB = 0
fO = 10 Hz
fO = 100 Hz
fO = 1 kHz
50
200
50
200
50
400
pA
Noise Voltage Density4
0.8
0.7
0.7
0.7
2
1
1
1
0.8
0.7
0.7
0.7
0.8
0.7
0.7
0.7
nV/÷Hz
nV/÷Hz
nV/÷Hz
nV/÷Hz
fO = 10 kHz
Collector Saturation
Voltage
VCE(SAT )
IC = 1 mA, IB = 100 µA
0.025 0.1
0.025 0.1
0.025 0.1
V
(at –55؇C ≤ T ≤ +125؇C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
A
MAT03A
Typ
P aram eter
Sym bol
Conditions
Min
Max
Units
Current Gain
hFE
VCB = 0 V, –36 V
IC = 1 mA
70
60
50
110
100
85
IC = 100 µA
IC = 10 µA
Offset Voltage
VOS
T CVOS
IOS
IC = 100 µA, VCB = 0 V
IC = 100 µA, VCB = 0 V
IC = 100 µA, VCB = 0 V
40
0.3
15
150
0.5
85
µV
µV/°C
nA
Offset Voltage Drift5
Offset Current
Breakdown Voltage
BVCEO
36
54
V
(at –40؇C ≤ T ≤ +85؇C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
A
MAT03E
Min Typ Max
MAT03F
Min Typ Max
P aram eter
Sym bol
Conditions
Units
Current Gain
hFE
VCB = 0 V, –36 V
IC = 1 mA
70
60
50
120
105
90
60
50
40
120
105
90
IC = 100 µA
IC = 10 µA
Offset Voltage
VOS
T CVOS
IOS
IC = 100 µA, VCB = 0 V
IC = 100 µA, VCB = 0 V
IC = 100 µA, VCB = 0 V
30
0.3 0.5
10 85
135
30
265
µV
µV/°C
nA
Offset Voltage Drift5
Offset Current
0.3 1.0
10 200
Breakdown Voltage
BVCEO
36
36
V
NOT ES
1Current gain is measured at collector-base voltages (VCB) swept from 0 to VMAX at indicated collector current. T ypicals are measured at VCB = 0 V.
100 ( ∆IB ) hFE (min )
2
Current gain matching (∆hFE) is defined as: ∆hFE =
.
IC
IC1
KT
q
3Offset voltage is defined as: VOS = VBE1 – VBE2, where VOS is the differential voltage for IC1 = IC2: VOS = VBE1 – VBE2
4Sample tested. Noise tested and specified as equivalent input voltage for each transistor.
=
In
.
IC2
5Guaranteed by VOS test (TCVOS = VOS/T for VOS Ӷ VBE
)
where T = 298°K for T A = 25°C.
Specifications subject to change without notice.
REV. B
–2–
MAT03
(at 25؇C, unless otherwise noted.)
WAFER TEST LIMITS
MAT03N
Lim its
P aram eter
Sym bol
Conditions
Units
Breakdown Voltage
Offset Voltage
BVCEO
VOS
36
V min
µV max
µV max
min
IC = 100 µA, VCB = 0 V
10 µA ≤ IC ≤ 1 mA
200
200
80
60
6
200
200
75
75
0.75
0.1
Current Gain
hFE
IC = 1 mA, VCB = 0 V, –36 V
IC = 10 µA, VCB = 0 V, –36 V
IC = 100 µA, VCB = 0 V
VCB1 = 0 V, IC = 100 µA
VCB2 = –36 V
VCB = 0
IC1 = 10 µA, IC2 = 1 mA
10 µA ≤ IC ≤ 1 mA
min
Current Gain Match
Offset Voltage Change vs. VCB
∆hFE
∆VOS/∆VCB
% max
µV max
µV max
µV max
µV max
Ω max
V max
Offset Voltage Change
vs. Collector Current
Bulk Resistance
∆VOS/∆IC
rBE
VCE (SAT )
Collector Saturation Voltage
IC = 1 mA, IB = 100 µA
NOT E:
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
D ICE CH ARACTERISTICS
ABSO LUTE MAXIMUM RATINGS 1
Collector-Base Voltage (BVCBO
Collector-Emitter Voltage (BVCEO
)
. . . . . . . . . . . . . . . . . . . . 36 V
. . . . . . . . . . . . . . . . . . 36 V
1. COLLECTOR (1 )
2. BASE (1 )
)
3. EMITTER (1 )
4. COLLECTOR (2)
5. BASE (2)
Collector-Collector Voltage (BVCC) . . . . . . . . . . . . . . . . . . 36 V
Emitter-Emitter Voltage (BVEE) . . . . . . . . . . . . . . . . . . . . . 36 V
Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Emitter Current (IE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
T otal Power Dissipation
6. EMITTER (2 )
SUBSTRATE CAN BE
CONNECTED TO V– OR
FLOATED
Ambient T emperature ≤ 70°C2 . . . . . . . . . . . . . . . . 500 mW
Operating T emperature Range
MAT 03A . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
MAT 03E/F . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Operating Junction T emperature . . . . . . . . . . –55°C to +150°C
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
Junction T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
O RD ERING GUID E 1
VO S m ax
Tem perature
P ackage
O ption
Model
MAT 03AH2 100 µV
(TA = +25؇C) Range
NOT ES
1Absolute maximum ratings apply to both DICE and packaged devices.
2Rating applies to T O-78 not using a heat sink, and LCC; devices in free air only. For
T O-78, derate linearly at 6.3 mW/°C above 70°C ambient temperature; for LCC,
derate at 7.8 mW/°C.
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
T O-78
T O-78
T O-78
MAT 03EH
MAT 03FH
100 µV
200 µV
NOT ES
1Burn-in is available on industrial temperature range parts.
2For devices processed in total compliance to MIL-ST D-883, add/883 after part
number. Consult factory for 883 data sheet.
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT 03 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
MAT03
Figure 2. Current Gain
vs. Tem perature
Figure 3. Gain Bandwidth vs.
Collector Current
Figure 1. Current Gain vs.
Collector Current
Figure 5. Sm all-Signal Input Resistance
(hie) vs. Collector Current
Figure 6. Sm all Signal Output Con-
ductance (hoe) vs. Collector Current
Figure 4. Base-Em itter Voltage
vs. Collector Current
REV. B
–4–
MAT03
Figure 8. Noise Voltage Density
vs. Frequency
Figure 9. Noise Voltage Density
Figure 7. Saturation Voltage
vs. Collector Current
Figure 11. Collector-Base Capacitance vs. VCB
Figure 10. Total Noise vs. Collector Current
REV. B
–5–
MAT03
Figure 12. SPICE or SABER Model
MAT03 NO ISE MEASUREMENT
AP P LICATIO NS INFO RMATIO N
MAT03 MO D ELS
T he MAT 03 model (Figure 12) includes parasitic diodes D3
through D6. D1 and D2 are internal protection diodes which
prevent zenering of the base-emitter junctions.
2
All resistive components (Johnson noise, en = 4kT BR, or en =
0.13√R nV/√Hz, where R is in kΩ) and semiconductor junctions
(Shot noise, caused by current flowing through a junction, pro-
duces voltage noise in series impedances such as transistor-
collector load resistors, In = 0.566 √I pA/√Hz where I is in µA)
contribute to the system input noise.
T he analysis programs, SPICE and SABER, are primarily used
in evaluating the functional performance of systems. T he mod-
els are provided only as an aid in utilizing these simulation
programs.
Figure 13 illustrates a technique for measuring the equivalent
input noise voltage of the MAT 03. 1 mA of stage current is used
Figure 13. MAT03 Voltage Noise Measurem ent Circuit
REV. B
–6–
MAT03
measurement circuit must be thermally isolated. Effects of extrane-
ous noise sources must also be eliminated by totally shielding
the circuit.
to bias each side of the differential pair. T he 5 kΩ collector re-
sistors noise contribution is insignificant compared to the volt-
age noise of the MAT 03. Since noise in the signal path is
referred back to the input, this voltage noise is attenuated by the
gain of the circuit. Consequently, the noise contribution of the
collector load resistors is only 0.048 nV/√Hz. T his is consider-
ably less than the typical 0.8 nV/√Hz input noise voltage of the
MAT 03 transistor.
SUP ER LO W NO ISE AMP LIFIER
T he circuit in Figure 14a is a super low noise amplifier with
equivalent input voltage noise of 0.32 nV/√Hz. By paralleling
three MAT 03 matched pairs, a further reduction of amplifier
noise is attained by a reduction of the base spreading resistance
by a factor of 3, and consequently the noise by √3. Additionally,
the shot noise contribution is reduced by maintaining a high col-
lector current (2 mA/device) which reduces the dynamic emitter
resistance and decreases voltage noise. T he voltage noise is in-
versely proportional to the square root of the stage current, and
current noise increases proportionally to the square root of the
stage current. Accordingly, this amplifier capitalizes on voltage
noise reduction techniques at the expense of increasing the cur-
rent noise. However, high current noise is not usually important
when dealing with low impedance sources.
T he noise contribution of the OP27 gain stages is also negligible
due to the gain in the signal path. T he op amp stages amplify
the input referred noise of the transistors to increase the signal
strength to allow the noise spectral density (ein × 10000) to be
measured with a spectrum analyzer. And, since we assume
equal noise contributions from each transistor in the MAT 03,
the output is divided by √2 to determine a single transistor’s
input noise.
Air currents cause small temperature changes that can appear
as low frequency noise. T o eliminate this noise source, the
Figure 14a. Super Low Noise Am plifier
REV. B
–7–
MAT03
T his amplifier exhibits excellent full power ac performance,
0.08% T HD into a 600 Ω load, making it suitable for exacting
audio applications (see Figure 14b).
and the VBE of a silicon transistor is predictable and constant (to
a few percent) over a wide temperature range. T he voltage differ-
ence, approximately 1 V, is dropped across the 250 Ω resistor
which produces a temperature stabilized emitter current.
CURRENT SO URCES
A fundamental requirement for accurate current mirrors and ac-
tive load stages is matched transistor components. Due to the
excellent VBE matching (the voltage difference between VBE’s
required to equalize collector current) and gain matching, the
MAT 03 can be used to implement a variety of standard current
mirrors that can source current into a load such as an amplifier
stage. T he advantages of current loads in amplifiers versus resis-
tors is an increase of voltage gain due to higher impedances,
larger signal range, and in many applications a wider signal
bandwidth.
Figure 16 illustrates a cascode current mirror consisting of two
MAT 03 transistor pairs.
T he cascode current source has a common base transistor in se-
ries with the output which causes an increase in output imped-
ance of the current source since VCE stays relatively constant.
High frequency characteristics are improved due to a reduction
of Miller capacitance. T he small-signal output impedance can
be determined by consulting “hOF vs. Collector Current” typical
graph. T ypical output impedance levels approach the perfor-
mance of a perfect current source.
Figure 14b. Super Low Noise Am plifier—Total
Harm onic Distortion
LO W NO ISE MICRO P H O NE P REAMP LIFIER
Figure 15 shows a microphone preamplifier that consists of a
MAT 03 and a low noise op amp. T he input stage operates at a
relatively high quiescent current of 2 mA per side, which reduces
the MAT 03 transistor’s voltage noise. T he 1/ƒ corner is less than
1 Hz. T otal harmonic distortion is under 0.005% for a 10 V p-p
signal from 20 Hz to 20 kHz. T he preamp gain is 100, but can be
modified by varying R5 or R6 (VOUT /VIN = R5/R6 + 1).
Considering a typical collector current of 100 µA, we have:
1
roQ3
=
= 1 MΩ
1. 0 µ MHOS
A total input stage emitter current of 4 mA is provided by Q2.
T he constant current in Q2 is set by using the forward voltage of
a GaAsP LED as a reference. T he difference between this voltage
Figure 15. Low Noise Microphone Pream plifier
REV. B
–8–
MAT03
Since Q2 buffers Q3, both transistors in the MAT 03, Q1 and Q3,
maintain the same collector current. D2 and D3 form a Baker
clamp which prevents Q2 from turning off, thereby improving
the switching speed of the current mirror. T he feedback serves
to increase the output impedance and improves accuracy by re-
ducing the base-width modulation which occurs with varying
collector-emitter voltages. Accuracy and linearity performance
of the current pump is summarized in Figure 19.
Q2 and Q3 are in series and operate at the same current levels so
the total output impedance is:
RO = hFE roQ3 @ (160)(1 MΩ) = 160 MΩ.
Figure 16. Cascode Current Source
Figure 17a. Current Matching Circuit
CURRENT MATCH ING
T he objective of current source or mirror design is generation of
currents that are either matched or must maintain a constant ra-
tio. However, mismatch of base-emitter voltages cause output
current errors. Consider the example of Figure 17a. If the resis-
tors and transistors are equal and the collector voltages are the
same, the collector currents will match precisely. Investigating
the current-matching errors resulting from a nonzero VOS, we
define ∆IC as the current error between the two transistors.
Graph 17b describes the relationship of current matching errors
versus offset voltage for a specified average current IC. Note that
since the relative error between the currents is exponentially pro-
portional to the offset voltage, tight matching is required to de-
sign high accuracy current sources. For example, if the offset
voltage is 5 mV at 100 µA collector current, the current match-
ing error would be 20%. Additionally, temperature effects such
as offset drift (3 µV/°C per mV of VOS) will degrade performance
if Q1 and Q2 are not well matched.
Figure 17b. Current Matching Accuracy %
vs. Offset Voltage
D IGITALLY P RO GRAMMABLE BIP O LAR CURRENT
P UMP
T he circuit of Figure 18 is a digitally programmable current
pump. T he current pump incorporates a DAC08, and a fast
Wilson current source using the MAT 03. Examining Figure 18,
the DAC08 is set for 2 mA full-scale range so that bipolar cur-
rent operation of ±2 mA is achieved. T he Wilson current mirror
maintains linearity within the LSB range of the 8-bit DAC08
(±2 mA/256 = 15.6 µA resolution) as seen in Figure 19. A
negative feedback path established by Q2 regulates the collector
current so that it matches the reference current programmed by
the DAC08.
Collector-emitter voltages across both Q1 and Q3 are matched
by D1, with Q3’s collector-emitter voltage remaining constant,
independent of the voltage across the current source output.
Figure 18. Digitally Program m able Bipolar Current Pum p
REV. B
–9–
MAT03
T he full-scale output of the DAC08, IOUT , is a linear function
of IREF
256
256
256
256
IFR
=
× IREF, and IOUT
+
–
= IREF
IOUT
T he current mirror output is IOUT
= 1, so that if
IOUT
IREF = 2 mA:
I = 2 IOUT – 1.992 mA
Input Code
= 2
(2 mA) – 1.992 mA.
256
D IGITAL CURRENT P UMP CO D ING
D igital Input
Figure 19. Digitally Program m able Current
Pum p—INL Error as Digital Code
B1 . . . B8
O utput Current
FULL RANGE
HALF-RANGE
ZERO-SCALE
1111 1111
1000 0000
0000 0000
I = 1.992 mA
I = 0.008 mA
I = –1.992 mA
REV. B
–10–
MAT03
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
TO -78 Metal Can
REFERENCE PLANE
0.750 (19.05)
0.500 (12.70)
0.185 (4.70)
0.165 (4.19)
0.250 (6.35) MIN
0.050 (1.27) MAX
0.100 (2.54) BSC
4
0.160 (4.06)
0.110 (2.79)
5
0.045 (1.14)
0.027 (0.69)
0.200
(5.08)
BSC
3
6
2
1
0.100
(2.54)
BSC
0.019 (0.48)
0.016 (0.41)
0.034 (0.86)
0.027 (0.69)
0.040 (1.02) MAX
0.021 (0.53)
0.016 (0.41)
0.045 (1.14)
0.010 (0.25)
45° BSC
BASE & SEATING PLANE
REV. B
–11–
–12–
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