MAT02BIEH [ADI]
TRANSISTOR 20 mA, 40 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR, TO-78, BIP General Purpose Small Signal;
| 型号： | MAT02BIEH |
| 厂家： | 
ADI |
| 描述： | TRANSISTOR 20 mA, 40 V, 2 CHANNEL, NPN, Si, SMALL SIGNAL TRANSISTOR, TO-78, BIP General Purpose Small Signal 晶体 晶体管 |
| 文件： | 总12页 (文件大小：265K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Noise, Matched
Dual Monolithic Transistor
a
MAT02
P IN CO NNECTIO N
FEATURES
Low Offset Voltage: 50 V m ax
Low Noise Voltage at 100 Hz, 1 m A: 1.0 nV/ √Hz m ax
High Gain (hFE): 500 m in at IC = 1 m A
300 m in at IC = 1 A
TO -78
(H Suffix)
Excellent Log Conform ance: rBE Ӎ 0.3 ⍀
Low Offset Voltage Drift: 0.1 V/ ؇C m ax
Im proved Direct Replacem ent for LM194/ 394
Available in Die Form
NOTE
Substrate is connected to case on TO-78 package. Sub-
strate is normally connected to the most negative circuit
potential, but can be floated.
P RO D UCT D ESCRIP TIO N
T he design of the MAT 02 series of NPN dual monolithic tran-
ABSO LUTE MAXIMUM RATINGS1
Collector-Base Voltage (BVCBO . . . . . . . . . . . . . . . . . . . . 40 V
Collector-Emitter Voltage (BVCEO . . . . . . . . . . . . . . . . . . 40 V
)
sistors is optimized for very low noise, low drift, and low rBE
Precision Monolithics’ exclusive Silicon Nitride “T riple-
Passivation” process stabilizes the critical device parameters
over wide ranges of temperature and elapsed time. Also, the high
current gain (hFE) of the MAT 02 is maintained over a wide
range of collector current. Exceptional characteristics of the
MAT 02 include offset voltage of 50 µV max (A/E grades) and
150 µV max F grade. Device performance is specified over the
full military temperature range as well as at 25°C.
.
)
Collector-Collector Voltage (BVCC) . . . . . . . . . . . . . . . . . . 40 V
Emitter-Emitter Voltage (BVEE) . . . . . . . . . . . . . . . . . . . . . 40 V
Collector Current (IC) . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
Emitter Current (IE) . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA
T otal Power Dissipation
Case T emperature ≤ 40°C2 . . . . . . . . . . . . . . . . . . . . . 1.8 W
Ambient T emperature ≤ 70°C3 . . . . . . . . . . . . . . . . 500 mW
Operating T emperature Range
MAT 02A . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to +125°C
MAT 02E, F . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
Operating Junction T emperature . . . . . . . . . . –55°C to +150°C
Storage T emperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering, 60 sec) . . . . . . . . . . . . . +300°C
Junction T emperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Input protection diodes are provided across the emitter-base
junctions to prevent degradation of the device characteristics
due to reverse-biased emitter current. T he substrate is clamped
to the most negative emitter by the parasitic isolation junction
created by the protection diodes. T his results in complete isola-
tion between the transistors.
NOT ES
T he MAT 02 should be used in any application where low noise
is a priority. T he MAT 02 can be used as an input stage to make
an amplifier with noise voltage of less than 1.0 nV/√Hz at 100 Hz.
Other applications, such as log/antilog circuits, may use the ex-
cellent logging conformity of the MAT 02. T ypical bulk resis-
tance is only 0.3 Ω to 0.4 Ω. The MAT02 electrical charac-
teristics approach those of an ideal transistor when operated over
a collector current range of 1 µA to 10 mA. For applications re-
quiring multiple devices see MAT 04 Quad Matched T ransistor
data sheet.
1Absolute maximum ratings apply to both DICE and packaged devices.
2Rating applies to applications using heat sinking to control case temperature.
Derate linearly at 16.4 mW/°C for case temperature above 40°C.
3Rating applies to applications not using a heat sinking; devices in free air only.
Derate linearly at 6.3 mW/°C for ambient temperature above 70°C.
O RD ERING GUID E 1
VO S m ax
(TA = +25؇C) Range
Tem perature
P ackage
O ption
Model
MAT 02AH2 50 µV
–55°C to +125°C T O-78
–55°C to +125°C T O-78
–55°C to +125°C T O-78
MAT 02EH
MAT 02FH
50 µV
150 µV
NOT ES
1Burn-in is available on commercial and industrial temperature range parts in
T O-can packages.
2For devices processed in total compliance to MIL-ST D-883, add /883 after part
number. Consult factory for 883 data sheet.
REV. C
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700
Fax: 617/ 326-8703
MAT02–SPECIFICATIONS
(@ V = 15 V, IC = 10 A, T = 25؇C, unless otherwise noted.)
CB
A
ELECTRICAL CHARACTERISTICS
MAT02A/E
MAT02F
Typ
P aram eter
Sym bol
Conditions
Min
Typ
Max Min
Max
Units
Current Gain
hFE
IC = 1 mA1
IC = 100 µA
IC = 10 µA
500
500
400
300
605
590
550
485
0.5
10
10
10
5
5
400
400
300
200
605
590
550
485
0.5
80
10
10
5
5
IC = 1 µA
Current Gain Match
Offset Voltage
Offset Voltage
∆hFE
VOS
10 µA ≤ IC ≤ 1 mA2
2
4
%
VCB = 0, 1 µA ≤ IC ≤ 1 mA3
50
25
25
25
25
150
50
50
50
50
µV
µV
µV
µV
µV
4
∆VOS/∆VCB 0 ≤ VCB ≤ VMAX
,
Change vs. VCB
1 µA ≤ IC ≤ 1 mA3
VCB = 0 V
Offset Voltage Change
vs. Collector Current
Offset Current
∆VOS/∆IC
1 µA ≤ IC ≤ 1 mA3
Change vs. VCB
Bulk Resistance
∆IOS/∆VCB 0 ≤ VCB ≤ VMAX
rBE
30
0.3
70
0.5
30
0.3
70
0.5
pA/V
Ω
10 µA ≤ IC ≤ 10 mA5
Collector-Base
Leakage Current
Collector-Collector
Leakage Current
Collector-Emitter
Leakage Current
Noise Voltage Density
ICBO
ICC
VCB = VMAX
25
35
35
200
200
200
25
35
35
400
400
400
pA
pA
pA
5, 6
VCC = VMAX
VCE = VMAX
5, 6
ICES
en
VBE = 0
IC = 1 mA, VCB = 07
fO = 10 Hz
1.6
0.9
0.85
0.85
2
1
1
1
1.6
0.9
0.85
0.85
3
2
2
2
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
fO = 100 Hz
fO = 1 kHz
fO = 10 kHz
Collector Saturation
Voltage
Input Bias Current
Input Offset Current
Breakdown Voltage
VCE(SAT )
IB
IOS
IC = 1 mA, IB = 100 µA
IC = 10 µA
IC = 10 µA
0.05 0.1
0.05
0.2
34
1.3
V
25
0.6
nA
nA
V
BVCEO
40
40
Gain-Bandwidth Product fT
IC = 10 mA, VCE = 10 V
VCB = 15 V, IE = 0
200
23
200
23
MHz
pF
Output Capacitance
Collector-Collector
Capacitance
COB
CCC
VCC = 0
35
35
pF
NOT ES
1Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to VMAX at the indicated collector currents.
100 (∆IB) (hFE min)
2Current gain match (∆hFE) is defined as: ∆hFE =
IC
3Measured at IC = 10 µA and guaranteed by design over the specified range of I C
4T his is the maximum change in VOS as VCB is swept from 0 V to 40 V.
5Guaranteed by design.
.
6ICC and ICES are verified by measurement of ICBO
7Sample tested.
.
Specifications subject to change without notice.
–2–
REV. C
MAT02
(V = 15 V, –25؇C ≤ T ≤ +85؇C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
CB
A
MAT02E
MAT02F
P aram eter
Sym bol
Conditions
Min Typ Max
Min Typ Max
Units
Offset Voltage
VOS
VCB = 0
70
220
µV
1 µA ≤ IC ≤ 1 mA1
Average Offset
Voltage Drift
2
T CVOS
IOS
10 µA ≤ IC ≤ 1 mA, 0 ≤ VCB ≤ VMAX
VOS T rimmed to Zero3
IC = 10 µA
0.08 0.3
0.03 0.1
8
0.08
0.03 0.3
13
1
µV/°C
Input Offset Current
Input Offset
nA
Current Drift
Input Bias Current
Current Gain
T CIOS
IB
hFE
IC = 10 µA4
IC = 10 µA
IC = 1 mA5
IC = 100 µA
IC = 10 µA
IC = 1 µA
40
90
45
40
150
50
pA/°C
nA
325
275
225
200
300
250
200
150
Collector-Base
ICBO
ICES
ICC
VCB = VMAX
2
3
3
3
4
4
nA
nA
nA
Leakage Current
Collector-Emitter
Leakage Current
Collector-Collector
Leakage Current
VCE = VMAX, VBE = 0
VCC = VMAX
(V = 15 V, –55؇C ≤ T ≤ +125؇C, unless otherwise noted.)
ELECTRICAL CHARACTERISTICS
CB
A
MAT02A
P aram eter
Sym bol
Conditions
Min
Typ
Max
Units
Offset Voltage
VOS
VCB = 0
80
µV
1 µA ≤ IC ≤ 1 mA1
Average Offset
Voltage Drift
2
T CVOS
IOS
10 µA ≤ IC ≤ 1 mA, 0 ≤ VCB ≤ VMAX
VOS T rimmed to Zero3
IC = 10 µA
0.08
0.03
0.3
0.1
9
µV/°C
µV/°C
nA
Input Offset Current
Input Offset
Current Drift
Input Bias Current
Current Gain
T CIOS
IB
hFE
IC = 10 µA4
IC = 10 µA
40
90
60
pA/°C
nA
IC = 1 mA5
275
225
125
150
IC = 100 µA
IC = 10 µA
IC = 1 µA
Collector-Base
ICBO
ICES
ICC
VCB = VMAX
TA = 125°C
VCE = VMAX, VBE = 0
Leakage Current
Collector-Emitter
Leakage Current
Collector-Collector
Leakage Current
15
50
30
nA
nA
nA
T
A = 125°C
VCC = VMAX
TA = 125°C
NOT ES
1Measured at IC = 10 µA and guaranteed by design over the specified range of I C
.
VOS
2Guaranteed by VOS test (TCVOS
for VOS Ӷ VBE) T = 298°K for T A = 25°C.
T
3T he initial zero offset voltage is established by adjusting the ratio of IC1 to IC2 at T A = 25°C. T his ratio must be held to 0.003% over
the entire temperature range. Measurements are taken at the temperature extremes and 25 °C.
4Guaranteed by design.
5Current gain is guaranteed with Collector-Base Voltage (VCB) swept from 0 to VMAX at the indicated collector current.
Specifications subject to change without notice.
REV. C
–3–
MAT02
(@ 25؇C for V = 15 V and I = 10 A, unless otherwise noted.)
WAFER TEST LIMITS
CB
C
MAT02N
Lim its
P aram eter
Sym bol
Conditions
Units
Breakdown Voltage
Offset Voltage
Input Offset Current
Input Bias Current
Current Gain
BVCEO
VOS
IOS
IB
hFE
40
V min
µV max
nA max
nA max
min
10 µA ≤ IC ≤ 1 mA1
150
1.2
34
400
300
4
VCB = 0 V
IC = 1 mA, VCB = 0 V
IC = 10 µA, VCB = 0 V
10 µA ≤ IC ≤ 1 mA, VCB = 0 V
0 V ≤ VCB ≤ 40 V
10 µA ≤ IC ≤ 1 mA1
VCB = 0
Current Gain Match
Offset Voltage
Change vs. VCB
Offset Voltage Change
vs. Collector Current
Bulk Resistance
∆hFE
∆VOS/∆VCB
% max
µV max
50
∆VOS/∆IC
50
µV max
10 µA ≤ IC ≤ 1 mA1
100 µA ≤ IC ≤ 10 mA
IC = 1 mA
rBE
VCE (SAT )
0.5
0.2
Ω max
V max
Collector Saturation Voltage
IB = 100 µA
NOT ES
1Measured at lC = 10 µA and guaranteed by design over the specified range of IC
.
Electrical tests are performed at wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed
for standard product dice. Consult factory to negotiate specifications based on dice lot qualification through sample lot assembly and testing.
(V = 15 V, I = 10 A, T = +25؇C, unless otherwise noted.)
TYPICAL ELECTRICAL CHARACTERISTICS
CB
C
A
MAT02N
Lim its
P aram eter
Sym bol
Conditions
Units
Average Offset
Voltage Drift
Average Offset
Current Drift
Gain-Bandwidth
Product
Offset Current Change vs. VCB
T CVOS
10 µA ≤ IC ≤ 1 mA
0 ≤ VCB ≤ VMAX
IC = 10 µA
0.08
40
µV/°C
T CIOS
fT
pA/°C
MHz
pA/V
VCE = 10 V, IC = 10 mA
200
70
∆IOS/∆VCB
0 ≤ VCB ≤ 40 V
D ICE CH ARACTERISTICS
1. COLLECTOR (1)
2. BASE (1)
3. EMITTER (1)
4. COLLECTOR (2)
5. BASE (2)
6. EMITTER (2)
7. SUBSTRATE
Die Size 0.061 × 0.057 inch, 3,477 sq. m ils
(1.549 × 1.448 m m , 224 sq. m m )
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the MAT 02 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. C
–4–
MAT02
Figure 2. Current Gain
vs. Tem perature
Figure 3. Gain Bandwidth
vs. Collector Current
Figure 1. Current Gain vs.
Collector Current
Figure 4. Base-Em itter-On
Voltage vs. Collector Current
Figure 5. Sm all Signal Input
Resistance vs. Collector Current
Figure 6. Sm all-Signal Output
Conductance vs. Collector Current
Figure 9. Noise Voltage Density
vs. Collector Current
Figure 7. Saturation Voltage
vs. Collector Current
Figure 8. Noise Voltage
Density vs. Frequency
REV. C
–5–
MAT02
Figure 12. Collector-to-Base
Leakage vs. Tem perature
Figure 11. Total Noise vs.
Collective Current
Figure 10. Noise Current
Density vs. Frequency
Figure 15. Collector-Base
Capacitance vs. Reverse Bias Voltage
Figure 13. Collector-to-Collector
Leakage vs. Tem perature
Figure 14. Collector-to-Collector
Capacitance vs. Collector-to
Substrate Voltage
Figure 16. Collector-to-Collector
Capacitance vs. Reverse Bias Voltage
Figure 17. Em itter-Base Capacitance
vs. Reverse Bias Voltage
REV. C
–6–
MAT02
Figure 18. Log Conform ance Test Circuit
LO G CO NFO RMANCE TESTING
An error term must be added to this equation to allow for the
bulk resistance (rBE) of the transistor. Error due to the op amp
input current is limited by use of the OP15 BiFET -input op
amp. T he resulting AMP01 input is:
T he log conformance of the MAT 02 is tested using the circuit
shown above. T he circuit employs a dual transdiode logarith-
mic converter operating at a fixed ratio of collector currents
that are swept over a 10:1 range. The output of each transdiode
converter is the VBE of the transistor plus an error term which
is the product of the collector current and rBE, the bulk emitter
resistance. T he difference of the VBE is amplified at a gain of
×100 by the AMP01 instrumentation amplifier. T he differen-
tial emitter-base voltage (∆VBE) consists of a temperature-
dependent dc level plus an ac error voltage which is the devia-
tion from true log conformity as the collector currents vary.
kT
q
IC1
IC2
In
∆VBE
=
+ IC1 rBE1 – IC2 rBE2
(2)
A ramp function which sweeps from 1 V to 10 V is converted by
the op amps to a collector current ramp through each transistor.
Because IC1 is made equal to 10 IC2, and assuming TA = 25°C,
the previous equation becomes:
T he output of the transdiode logarithmic converter comes
from the idealized intrinsic transistor equation (for silicon):
∆VBE = 59 mV + 0.9 IC1 rBE (∆rBE ~ 0)
As viewed on an oscilloscope, the change in ∆VBE for a 10:1
change in IC is then displayed as shown below:
kT
q
IC
IS
In
VBE
=
where
(1)
k = Boltzmann’s Constant (1.38062 × 10-23 J/°K)
q = Unit Electron Charge (1.60219 × 10-19 °C)
T = Absolute T emperature, °K (= °C + 273.2)
IS = Extrapolated Current for VBE→0
IC = Collector Current
REV. C
–7–
MAT02
With the oscilloscope ac coupled, the temperature dependent
term becomes a dc offset and the trace represents the deviation
from true log conformity. T he bulk resistance can be calculated
from the voltage deviation ∆VO and the change in collector cur-
rent (9 mA):
by various offsetting techniques. Protective diodes across each
base-to-emitter junction would normally be needed, but these
diodes are built into the MAT 02. External protection diodes are
therefore not needed.
For the circuit shown in Figure 19, the operational amplifiers
make I1 = VX/R1, I2 = VY/R2, I3 = VZ/R3, and IO = VO/RO. T he
output voltage for this one-quadrant, log-antilog multiplier/di-
vider is ideally:
∆VO
1
×
rBE
=
(3)
9 mA 100
T his procedure finds rBE for Side A. Switching R1 and R2 will
provide the rBE for Side B. Differential rBE is found by making
R1 = R2.
R3RO VXVY
R1R2 V Z
VO
=
(VX, VY, VZ > 0)
(4)
If all the resistors (RO, R1, R2, R3) are made equal, then VO
VXVY/VZ. Resistor values of 50 kΩ to 100 kΩ are recommended
assuming an input range of 0.1 V to +10 V.
=
AP P LICATIO NS: NO NLINEAR FUNCTIO NS
MULTIP LIER/D IVID ER CIRCUIT
T he excellent log conformity of the MAT 02 over a very wide
range of collector current makes it ideal for use in log-antilog
circuits. Such nonlinear functions as multiplying, dividing,
squaring, and square-rooting are accurately and easily imple-
mented with a log-antilog circuit using two MAT 02 pairs (see
Figure 19). T he transistor circuit accepts three input currents
(I1, I2, and I3) and provides an output current IO according to
IO = I1I2/I3. All four currents must be positive in the log-antilog
circuit, but negative input voltages can be easily accommodated
ERRO R ANALYSIS
T he base-to-emitter voltage of the MAT 02 in its forward active
operation is:
kT
q
IC
IS
In
VBE
=
+ rBEIC, VCB ~ 0
(5)
T he first term comes from the idealized intrinsic transistor
equation previously discussed (see equation (1)).
Figure 19. One-Quadrant Multiplier/Divider
REV. C
–8–
MAT02
approximately 26 mV and the error due to an rBEIC term will be
r
BEIC/26 mV. Using an rBE of 0.4 Ω for the MAT 02 and assum-
ing a collector current range of up to 200 µA, then a peak error
of 0.3% could be expected for an rBEIC error term when using
the MAT 02. T otal error is dependent on the specific application
configuration (multiply, divide, square, etc.) and the required
dynamic range. An obvious way to reduce ICrBE error is to re-
duce the maximum collector current, but then op amp offsets
and leakage currents become a limiting factor at low input lev-
els. A design range of no greater than 10 µA to 1 mA is generally
recommended for most nonlinear function circuits.
Figure 20. Com pensation of Bulk Resistance Error
A powerful technique for reducing error due to ICrBE is shown in
Figure 20. A small voltage equal to ICrBE is applied to the tran-
sistor base. For this circuit:
Extrinsic resistive terms and the early effect cause departure
from the ideal logarithmic relationship. For small VCB, all of
these effects can be lumped together as a total effective bulk re-
sistance rBE. T he rBEIC term causes departure from the desired
logarithmic relationship. T he rBE term for the MAT 02 is less
than 0.5 Ω and ∆rBE between the two sides is negligible.
RC
R2
rBE
R1
VB =
V1 and ICrBE
=
V1
(10)
T he error from rBEIC is cancelled if RC/R2 is made equal to rBE
/
R1. Since the MAT 02 bulk resistance is approximately 0.39 Ω,
an RC of 3.9 Ω and R2 of 10 R1 will give good error cancellation.
Returning to the multiplier/divider circuit of Figure 1 and using
Equation (4):
In more complex circuits, such as the circuit in Figure 19, it
may be inconvenient to apply a compensation voltage to each
individual base. A better approach is to sum all compensation to
VBE1A + VBE2A – VBE2B –VBE1B + (I1 + I2 – IO – I3) rBE = 0
If the transistor pairs are held to the same temperature, then:
the bases of Q1. T he “A” side needs a base voltage of (VO/RO
+
VZ/R3) rBE and the “B” side needs a base voltage of (VX/R1+VY/
R2) rBE. Linearity of better than ±0.1% is readily achievable with
this compensation technique.
kT
q
I1I2 kT
IS1AIS2A
IS1BIS2B
In
=
In
+ (I1 + I2 – IO – I3) rBE
(6)
I3IO
q
If all the terms on the right-hand side were zero, then we would
have In (I1 I2/I3 IO) equal to zero which would lead directly to
the desired result:
Operational amplifier offsets are another source of error. In Fig-
ure 20, the input offset voltage and input bias current will cause
an error in collector current of (VOS/R1) + IB. A low offset op
amp, such as the OP07 with less than 75 µV of VOS and IB of
less than ±3 nA, is recommended. T he OP22/OP32, a program-
mable micropower op amp, should be considered if low power
consumption or single-supply operation is needed. T he value of
frequency-compensating capacitor (CO) is dependent on the op
amp frequency response and peak collector current. T ypical val-
ues for CO range from 30 pF to 300 pF.
I1I2
I3
IO
=
, where I1, I2, I3, IO > 0
(7)
Note that this relationship is temperature independent. T he
right-hand side of Equation (6) is near zero and the output cur-
rent IO will be approximately I1 I2/I3. T o estimate error, define ø
as the right-hand side terms of Equation (6):
.
. .
IS1AIS2A
IS1BIS2B kT
q
FO UR-Q UAD RANT MULTIP LIER
+
ø = In
(I1 + I2 – IO – I3) rBE
(8)
A simplified schematic for a four-quadrant log/antilog multiplier
is shown in Figure 21. As with the previously discussed one-
quadrant multiplier, the circuit makes IO = I1 I2/I3. T he two
input currents, I1 and I2, are each offset in the positive direction.
T his positive offset is then subtracted out at the output stage.
Assuming ideal op amps, the currents are:
For the MAT 02, In (ISA/ISB) and ICrBE are very small. For small
ø, εØ ~ 1 + ø and therefore:
I1I2
I3IO
= 1 + ø
VX
R1 R2
V
VY VR
+
R , I2 =
(9)
I1 =
+
R1 R2
I1I2
(1 – ø)
(11)
(12)
IO
~
I3
VX VY VR
R1 R1 R2 RO
V
VR
R2
IO
=
+
+
+
O , I3 =
T he In (ISA/ISB) terms in ø cause a fixed gain error of less than
±0.6% from each pair when using the MAT 02, and this gain
error is easily trimmed out by varying RO. T he ICrBE terms are
more troublesome because they vary with signal levels and
are multiplied by absolute temperature. At 25°C, kT /q is
From IO = I1 I2/I3, the output voltage will be:
RO R2 VXVY
R12
VO
=
VR
REV. C
–9–
MAT02
Collector-current range is the key design decision. T he inher-
ently low rBE of the MAT 02 allows the use of a relatively high
collector current. For input scaling of ±10 V full-scale and us-
ing a 10 V reference, we have a collector-current range for I1
and I2 of:
MULTIFUNCTIO N CO NVERTER
T he multifunction converter circuit provides an accurate means
of squaring, square rooting, and of raising ratios to arbitrary
powers. T he excellent log conformity of the MAT 02 allows a
wide range of exponents. T he general transfer function is:
–10 10
+
10 10
≤ +
≤ IC
(13)
R1 R2
R1 R2
m
VZ
VX
VO = VY
(15)
Practical values for R1 and R2 would range from 50 kΩ to
100 kΩ. Choosing an R1 of 82 kΩ and R2 of 62 kΩ provides a
collector-current range of approximately 39 µA to 283 µA. An
RO of 108 kΩ will then make the output scale factor 1/10 and
VO = VXVY/10. T he output, as well as both inputs, are scaled
for ±10 V full scale.
VX, VY, and VZ are input voltages and the exponent “m” has a
practical range of approximately 0.2 to 5. Inputs VX and VY are
often taken from a fixed reference voltage. With a REF01 pro-
viding a precision +10 V to both VX and VY, the transfer func-
tion would simplify to:
Linear error for this circuit is substantially improved by the
small correction voltage applied to the base of Q1 as shown in
Figure 21. Assuming an equal bulk emitter resistance for each
MAT 02 transistor, then the error is nulled if:
m
VZ
VO = 10
(16)
10
(I1 + I2 – I3 – IO) rBE + ρVO = 0
As with the multiplier/divider circuits, assume that the transistor
pairs have excellent matching and are at the same temperature.
T he In ISA/ISB will then be zero. In the circuit of Figure 22, the
voltage drops across the base-emitter junctions of Q1 provide:
T he currents are known from the previous discussion, and the
relationship needed is simply:
rBE
VO
=
VO
(14)
RB
RB + KRA
kT
q
IZ
IX
RO
VA
=
In
(17)
T he output voltage is attenuated by a factor of rBE/RO and ap-
plied to the base of Q1 to cancel the summation of voltage
drops due to rBEIC terms. T his will make In (I1 I2/I3 IO) more
nearly zero which will thereby make IO = I1 I2/I3 a more accu-
rate relationship. Linearity of better than 0.1% is readily achiev-
able with this circuit if the MAT 02 pairs are carefully kept at
the same temperature.
IZ is VZ/R1 and IX is VX/R1. Similarly, the relationship for Q2 is:
RB
kT
q
IO
I Y
VA
=
In
(18)
R + 1 – K R
(
)
B
A
IO is VO/RO and IY is VY/R1. T hese equations for Q1 and Q2 can
then be combined.
RB + KRA
IZ
IX
IO
IY
In
= In
(19)
R + 1 – K R
(
)
B
A
Figure 21. Four-Quadrant Multiplier
REV. C
–10–
MAT02
Substituting in the voltage relationships and simplifying leads
to:
Accuracy is limited at the higher input levels by bulk emitter re-
sistance, but this is much lower for the MAT 02 than for other
transistor pairs. Accuracy at the lower signal levels primarily de-
pends on the op amp offsets. Accuracies of better than 1% are
readily achievable with this circuit configuration and can be bet-
ter than ±0.1% over a limited operating range.
m
R
R1
VZ
VX
O VY
VO
=
, where
(20)
FAST LO GARITH MIC AMP LIFIER
RB + KRA
T he circuit of Figure 23 is a modification of a standard logarith-
mic amplifier configuration. Running the MAT 02 at 2.5 mA per
side (full-scale) allows a fast response with wide dynamic range.
T he circuit has a 7 decade current range, a 5 decade voltage
range, and is capable of 2.5 µs settling time to 1% with a 1 V to
10 V step.
m =
R + 1 – K R
(
)
B
A
T he factor “K” is a potentiometer position and varies from zero
to 1.0, so “m” ranges from RB/(RA + RB) to (RB + RA)/RB.
Practical values are 125 Ω for RB and 500 Ω for RA; these val-
ues will provide an adjustment range of 0.2 to 5.0. A value of
100 kΩ is recommended for the R1 resistors assuming a full-
scale input range of 10 V. As with the one-quadrant multiplier/
divider circuit previously discussed, the VX, VY, and VZ inputs
must all be positive.
T he output follows the equation:
R3 + R2 kT VREF
In
VO
=
(21)
R2
q
VIN
T he output is inverted with respect to the input, and is nomi-
nally –1 V/decade using the component values indicated.
T he op amps should have the lowest possible input offsets. T he
OP07 is recommended for most applications, although such
programmable micropower op amps as the OP22 or OP32 offer
advantages in low-power or single-supply circuits. T he micro-
power op amps also have very low input bias-current drift, an
important advantage in log/antilog circuits. External offset null-
ing may be needed, particularly for applications requiring a
wide dynamic range. Frequency compensating capacitors, on
the order of 50 pF, may be required for A2 and A3. Amplifier
A1 is likely to need a larger capacitor, typically 0.0047 µF, to as-
sure stability.
LO W-NO ISE
؋
1000 AMP LIFIER T he MAT 02 noise voltage is exceptionally low, only 1 nV/√Hz
at 10 Hz when operated over a collector-current range of 1 mA
to 4 mA. A single-ended ×1000 amplifier that takes advantage of
this low MAT 02 noise level is shown in Figure 24. In addition
to low noise, the amplifier has very low drift and high CMRR.
An OP32 programmable low-power op amp is used for the sec-
ond stage to obtain good speed with minimal power consump-
tion. Small-signal bandwidth is 1 MHz, slew rate is 2.4 V/µs,
and total supply current is approximately 2.8 mA.
Figure 22. Multifunction Converter
REV. C
–11–
MAT02
current. A set resistor of 549 kΩ was found to provide the best
step response for this circuit. T he resultant supply current is
found from:
T ransistors Q2 and Q3 form a 2 mA current source (0.65 V/
330 Ω ~ 2 mA). Each collector of Q1 operates at 1 mA. T he
OP32 inputs are 3 V below the positive supply voltage (RLIC
~ 3 V). T he OP32’s low input offset current, typically less than
1 nA, and low offset voltage of 1 mV cause negligible error
when referred to the amplifier input. Input stage gain is gmRL,
which is approximately 100 when operating at IC of 1 mA with
RL of 3 kΩ. Since the OP32 has a minimum open-loop gain of
500,000, total open-loop gain for the composite amplifier is
over 50 million. Even at closed-loop gain of 1000, the gain er-
ror due to finite open-loop gain will be negligible. T he OP32
features excellent symmetry of slew-rate and very linear gain.
Signal distortion is minimal.
V + – V – – 2V
(
)
(
)
(
)
, I SY =15 ISET
BE
RSET
=
(22)
ISET
T he ISET , using ±15 V supplies and an RSET of 549 kΩ, is ap-
proximately 52 µA which will result in supply current of 784 µA.
Dynamic range of this amplifier is excellent; the OP32 has an
output voltage swing of ±14 V with a ±15 V supply.
Input characteristics are outstanding. T he MAT 02F has offset
voltage of less than 150 µV at 25°C and a maximum offset drift
of 1 µV/°C. Nulling the offset will further reduce offset drift.
T his can be accomplished by slightly unbalancing the collector
load resistors. T his adjustment will reduce the drift to less than
0.1 µV/°C.
Frequency compensation is very easy with this circuit; just vary
the set-resistor RS for the desired frequency response.
Gain-bandwidth of the OP32 varies directly with the supply
Input bias current is relatively low due to the high current gain
of the MAT 02. T he minimum β of 400 at 1 mA for the
MAT 02F implies an input bias current of approximately 2.5 µA.
T his circuit should be used with signals having relatively low
source impedance. A high source impedance will degrade offset
and noise performance.
T his circuit configuration provides exceptionally low input noise
voltage and low drift. Noise can be reduced even further by rais-
ing the collector currents from 1 mA to 3 mA, but power con-
sumption is then increased.
O UTLINE D IMENSIO N
D imensions shown in inches and (mm).
6-Lead Metal Can
(TO -78)
REFERENCE PLANE
0.750 (19.05)
0.500 (12.70)
0.185 (4.70)
Figure 23. Fast Logarithm ic Am plifier
0.250 (6.35) MIN
0.050 (1.27) MAX
0.165 (4.19)
0.100 (2.54) BSC
4
0.160 (4.06)
0.110 (2.79)
5
0.045 (1.14)
0.027 (0.69)
0.200
(5.08)
BSC
3
6
2
1
0.100
(2.54)
BSC
0.019 (0.48)
0.016 (0.41)
0.034 (0.86)
0.027 (0.69)
0.040 (1.02) MAX
0.021 (0.53)
0.016 (0.41)
0.045 (1.14)
0.010 (0.25)
45° BSC
BASE & SEATING PLANE
Figure 24. Low-Noise, Single-Ended X1000 Am plifier
REV. C
–12–
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