ADV7630KSVZ_技术文档

2.25 GHz XpressView

HDMI 1:2 Splitter with 4:1 Input Mux

ADV7630

Data Sheet

General

FEATURES

Interrupt controller with interrupt output

On-chip 5 V regulator for 5 V HDMI cable power support

Software libraries, driver, and application available

Internal EDID RAM

2.25 GHz TMDS HDMI 1:2 splitter with 4:1 input mux

High-Definition Multimedia Interface (HDMI) supported

All mandatory and additional 3D video formats supported

CEC 1.4-compatible

225 MHz maximum TMDS clock frequency

XpressView fast switching on all HDMI input ports

36-/30-bit per pixel Deep Color and 24-bit per pixel color

support

High-bandwidth Digital Content Protection (HDCP) 1.4

support with internal HDCP keys

HDCP repeater support

Up to 127 KSVs supported

Integrated CEC controller

128-lead 14 mm × 14 mm TQFP_EP package

APPLICATIONS

Video conferencing

HDTV

AVR, HTiB

Soundbar

Video switch

HDMI splitter

5 V detect and hot plug assert for each HDMI port

EDID data extraction on HDMI outputs

Hot plug detection (HPD) input on HDMI outputs

FUNCTIONAL BLOCK DIAGRAM

ADV7630

TMDS

DDC

HDMI 1

HDMI 2

HDMI 3

HDMI 4

TMDS

DDC

TMDS

DDC

HDMI TXA

HDMI TXB

1:2

SPLITTER

4:1

MUX

DEEP

COLOR

HDMIRX

TMDS

DDC

TMDS

DDC

TMDS

DDC

HDCP

KEYS

FAST

SWITCH

CEC

TX EDID/HDCP

BUFFER

2

I C

INT

2

INT

I C

Figure 1.

Rev. 0

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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADV7630

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Pin Configuration and Function Descriptions..............................9

Power Supply Recommendation .................................................. 14

Power-Up Sequence ................................................................... 14

Power-Down Sequence.............................................................. 14

Functional Overview...................................................................... 15

HDMI Receiver........................................................................... 15

HDMI Transmitter..................................................................... 15

I²C Interface ................................................................................ 15

Other Features ............................................................................ 15

Outline Dimensions....................................................................... 16

Ordering Guide .......................................................................... 16

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Detailed Functional Block Diagram .......................................... 3

Specifications..................................................................................... 4

Electrical Characteristics............................................................. 4

Timing Characteristics ................................................................ 6

Absolute Maximum Ratings............................................................ 8

Package Thermal Performance................................................... 8

ESD Caution.................................................................................. 8

REVISION HISTORY

9/12—Revision 0: Initial Version

Rev. 0 | Page 2 of 16

Data Sheet

ADV7630

GENERAL DESCRIPTION

The ADV7630 is a high quality 1:2 HDMI® splitter with 4:1

input multiplexer. It incorporates a four-input HDMI receiver

and dual transmitter functions onto a single chip. The

ADV7630 supports all mandatory HDMI 3D TV formats,

HDTV formats up to 1080p 36-bits per pixel Deep Color,

and display resolutions up to 1080p60. The reception of

HDCP encrypted video is also supported by the HDMI

receiver with TMDS The HDMI video transmitted to the

downstream device by the transmitter. HDMI output features

dedicated DDC lines with an HDCP encryption engine.

Each HDMI input port has dedicated 5 V detect and hot plug

assert pins. The HDMI receiver also includes an integrated

equalizer that ensures robust operation of the interface even

with long and low quality cables.

Each HDMI has a dedicated hot plug detect port and DDC lines

along with an internal HDCP encryption engine.

The ADV7630 features an EDID replicator and internal EDID

RAM. On the transmitter side, DDC control allows reading

back EDID data from sink. As the part incorporates an internal

regulator, the EDID functionality on the receiver’s side can be

powered from the HDMI cable when ac power is removed from

the system.

The ADV7630 integrates an HDMI CEC controller that

supports the capability discovery and control (CDC) feature.

The ADV7630 incorporates XpressView™ fast switching on all

input HDMI ports. Using an Analog Devices, Inc., hardware-

based HDCP engine that minimizes software overhead,

XpressView technology allows fast switching between all

HDMI input ports in less than 1 second.

Fabricated in an advanced CMOS process, the ADV7630

is provided in a 14 mm × 14 mm, 128-lead surface-mount

TQF P _ E P, R o H S -compliant package and is specified over

the 0°C to 70°C temperature range.

DETAILED FUNCTIONAL BLOCK DIAGRAM

DDCA_SCL

DDCB_SCL

DDCC_SCL

DDCD_SCL

DDCA_SDA

DDCB_SDA

DDCC_SDA

DDCD_SDA

5V DETECT

VOLTAGE REG.

HPD CONTROLLER

TX EDID

BUFFER

CEC

CONTROLLER

INTERRUPT

CONTROLLER

EDID

REPEATER

CONTROLLER

TXA_DDC_SCL

TXA_DDC_SDA

TXB_DDC_SCL

TXB_DDC_SDA

HDCP

EEPROM

HDCP

ENGINE

EP_SCK

EP_MISO

EP_MOSI

EP_CS

HDCP

ENGINE

TX DDC

CONTROL

TXA_0±

TXA_1±

TXA_2±

TXA_C±

HDMI TX

RXA_0±

RXA_1±

RXA_2±

EQUALIZER

SAMPLER

1:2

SPLITTER

RXB_0±

RXB_1±

RXB_2±

XpressView

FAST

SWITCHING

4:1

MUX

TXB_0±

TXB_1±

TXB_2±

TXB_C±

RXC_0±

RXC_1±

RXC_2±

HDMI TX

RXD_0±

RXD_1±

RXD_2±

TXA_HPD

TXB_HPD

HOT PLUG

DETECT

RXA_C±

RXB_C±

RXC_C±

RXD_C±

CONTROL

PLLs

INTERNAL

CLOCK

INTERFACE

2

I C

ADV7630

Figure 2.

Rev. 0 | Page 3 of 16

ADV7630

Data Sheet

SPECIFICATIONS

DVDD, TXA_PVDD, TXB_PVDD, CVDD, TX_AVDD at 1.71 V to 1.89 V; DVDDIO, TVDD, SYS_3P3V at 3.14 V to 3.46 V; T_MINto

T

_MAX= 0^oC to 70^oC, unless otherwise noted.

ELECTRICAL CHARACTERISTICS

Table 1.

Parameter

Symbol

Test Conditions/Comments

Min Typ

Max

0.8

20

Unit

DIGITAL INPUTS

Input High Voltage

Input Low Voltage

Input Current

V_IH

V_IL

I_IN

Digital inputs

RESET, CS, EP_MISO

Other digital inputs

Excluding differential HDMI inputs

2

V

µA

pF

40

10

Input Capacitance¹

DIGITAL INPUTS (5 V TOLERANT)²

C_IN

Input High Voltage

Input Low Voltage

V_IH

V_IL

2.6

V

0.8

High Impedance Leakage Current

I_LEAK

DDCA_SCL, DDCB_SCL, DDCC_SCL, DDCD_SCL,

DDCA_SDA, DDCB_SDA, DDCC_SDA, DDCD_SDA,

TXA_DDC_SDA, TXB_DDC_SDA³

30

µA

TXA_HPD, TXB_HPD

10

µA

DIGITAL OUTPUTS

Output High Voltage

Output Low Voltage

High Impedance Leakage Current

V_OH

V_OL

I_LEAK

2.4

V

µA

0.4

20

DDCA_SDA, DDCB_SDA, DDCC_SDA, DDCD_SDA,

TXA_DDC_SDA, TXB_DDC_SDA, TXA_DDC_SCL,

TXB_DDC_SCL³

30

All other digital pins

10

µA

pF

Excluding non-tristable outputs⁴

Output Capacitance¹

POWER REQUIREMENTS¹

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply TXA

PLL Power Supply TXB

Terminator Power Supply

Comparator Power Supply

System Power Supply

TX Analog Power Supply

Power-Up Time

C_OUT

DVDD

1.71 1.8

3.14 3.3

1.71 1.8

3.14 3.3

1.71 1.8

3.14 3.3

1.71 1.8

25

1.89

3.46

1.89

3.46

1.89

3.46

1.89

V

DVDDIO

TXA_PVDD

TXB_PVDD

TVDD

CVDD

SYS_3P3V

TX_AVDD

t_PWRUP

ms

Test Condition 1

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

Terminator Power Supply

Comparator Power Supply

System Power Supply

TX Analog Power Supply

I_DVDD

I_DVDDIO

I_{TX_PVDD}

I_TVDD

I_CVDD

I_{SYS_3P3V}

I_{TX_AVDD}

Test Condition 1

277

0.13

85.9

226

307

2.21

33.0

303

0.13

97.6

227

328

3.23

34.9

mA

5

Rev. 0 | Page 4 of 16

Data Sheet

ADV7630

Parameter

Symbol

Test Conditions/Comments

Min Typ

Max

Unit

Test Condition 2

Power-Down Currents¹

I_{DVDD_PD}

I_{DVDDIO_PD}

I_{TX_PVDD_PD}

I_{TVDD_PD}

I_{CVDD_PD}

I_{SYS_3P3V_PD}

I_{TX_AVDD_PD}

Test Condition 2

0.38

0

1.974 mA

0.128 mA

6

0.057 0.157 mA

0.031 0.082 mA

0.027 0.101 mA

0.050 0.217 mA

3.160 3.450 mA

¹Data recorded during lab characterization.

²The following pins are 5 V tolerant: TXA_DDC_SCL, TXA_DDC_SDA, TXB_DDC_SCL, TXB_DDC_SDA, DDCA_SCL, DDCA_SDA, DDCB_SCL, DDCB_SDA, DDCC_SCL,

DDCC_SDA, DDCD_SCL, DDCD_SDA.

³SDA pins are bidirectional.

⁴Non-tristatable pins are all differential HDMI TX outputs.

⁵Sum of currents I_{TXA_PVDD}and I_{TXB_PVDD}

.

⁶Sum of currents I_{TXA_PVDD_PD}and I_{TXB_PVDD_PD}

.

Table 2. Test Conditions for Power Requirements

Parameter

Value Used for Typical Case

Value Used For Maximum Case

TEST CONDITION 1

Number of HDMI Inputs (XpressView Mode)

Video Format (Each HDMI Input)

HDCP Encryption

Four inputs

1080p60, 12 bits

Transmitter only

Off

Four inputs

1080p60, 12 bits

Transmitter only

Off

HDCP Decryption

Audio

192 kHz PCM

Pseudo random

Two outputs

25^oC

192 kHz PCM

Pseudo random

Two outputs

70^oC

Video Pattern (Each HDMI Input)

Number of HDMI Outputs Used

Temperature

Power Supply Voltages

Nominal

Maximum

TEST CONDITION 2 (POWER-DOWN)

Number of HDMI Inputs (XpressView Mode)

Video Format (Each HDMI Input)

HDCP Decryption

Video Pattern (Each HDMI Input)

Number of HDMI Outputs Used

Audio

Not applicable

25^oC

Not applicable

70^oC

Temperature

Power Supply Voltages

Nominal

Maximum

Rev. 0 | Page 5 of 16

ADV7630

Data Sheet

TIMING CHARACTERISTICS

Data and I²C Timing Characteristics

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

CLOCK

Clock Frequency, CLK_IN

Frequency Stability

TMDS Frequency Range

I²C PORTS¹

27.000

MHz

ppm

MHz

200

225

25

SCL Frequency

400

kHz

ns

µs

ns

µs

SCL Minimum Pulse Width High

SCL Minimum Pulse Width Low

Start Condition Hold Time

Start Condition Setup Time

SDA Setup Time

SCL and SDA Rise Time

SCL and SDA Fall Time

Stop Condition Setup Time

RESET FEATURE

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

600

1.3

600

100

300

0.6

5

RESET Pulse Width

ms

SPI PORT¹

EP_CS Falling Edge Before First EP_SCK Edge

EP_CS Rising Edge After Last Rising EP_SCK Edge

SCLK Low Pulse Width

t_CSL

t_CSH

t_SL

191.4

217.5

27.2

ns

SCLK High Pulse Width

t_SH

Data Output Valid After EP_SCK Edge

Data Output Setup Before EP_SCK Edge

Data Input Setup Time Before EP_SCK Edge

Data Input Hold Time After EP_SCK Edge

t_DAV

t_DOSU

t_DSU

t_DHD

217.5

21.3

¹Data guaranteed by design.

Timing Diagrams

t₃

t₅

t₃

SDA

t₆

t₁

SCL

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

Rev. 0 | Page 6 of 16

Data Sheet

ADV7630

t_CSL

t_CSH

EP_CS

EP_SCK

t_SH

t_SL

t_DAV

t_DOSU

EP_MOSI

EP_MISO

t_DSU

t_DHD

Figure 4. SPI Timing

Rev. 0 | Page 7 of 16

ADV7630

Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 4.

PACKAGE THERMAL PERFORMANCE

To reduce power consumption when using the ADV7630, the

user is advised to turn off the unused sections of the part.

Parameter

Rating

CVDD to GND

2.2 V

DVDD to GND

2.2 V

Due to PCB metal variation and, therefore, variation in PCB

heat conductivity, the value of θ_JAmay differ for various PCBs.

TVDD to GND

3.9 V

TX_AVDD to GND

2.2 V

The most efficient measurement solution is obtained using

the package surface temperature to estimate the die tempera-

ture because this eliminates the variance associated with the

θ_JAvalue.

TXA_PVDD to GND

TXB_PVDD to GND

SYS_3P3V to GND

2.2 V

3.9 V

DVDDIO to GND

3.9 V

Digital Inputs Voltage to GND

Analog Inputs Voltage to GND

HDMI Digital Inputs Voltage to GND

GND – 0.3 V to DVDDIO + 0.3 V

GND – 0.3 V to TXA_PVDD + 0.3 V

GND – 0.3 V to TVDD + 0.3 V

GND – 0.3 V to 5.5 V

The maximum junction temperature (T_{J MAX}) of 125°C must not

be exceeded. The following equation calculates the junction

temperature using the measured package surface temperature

and applies only when no heat sink is used on the device under

test (DUT):

5 V Tolerant Digital Inputs to

GND^{1, 3, 6}

5 V Digital Inputs²

5 V Tolerant Digital Outputs to GND^{3, 6}GND – 0.3 V to 5.5 V

T_JT_S



Ψ_JTW_TOTAL



Digital Outputs Voltage to GND^{4, 5}

Analog Outputs Voltage to GND

HDMI Digital Outputs to GND

Maximum Junction Temperature

GND – 0.3 V to DVDDIO + 0.3 V

GND – 0.3 V to CVDD + 0.3 V

GND – 0.3 V to TVDD + 0.3 V

125°C

where:

T_Sis the package surface temperature (°C).

Ψ_JTis 0.22°C/W for the 128-lead TQFP_EP.

(T_{J MAX}

)

W

_TOTAL= ((CVDD × I_CVDD) + (0.2 × TVDD × I_TVDD) + (DVDD ×

Storage Temperature Range

−60°C to +150°C

260°C

I_DVDD) + (TX_AVDD × I_{TX_AVDD}) + (TXA_PVDD × I_{TXA_PVDD}) +

Infrared Reflow Soldering (20 sec)

(TXB_PVDD × I_{TXA_PVDD}) + (DVDDIO × I_DVDDIO)) + N_TX× P_TX

¹The following pins are 3.3 V inputs, 5 V tolerant: TXB_HPD, TXB_DDC_SDA, ,

TXA_HPD, TXA_DDC_SDA, DDCA_SCL, DDCB_SCL, DDCC_SCL, DDCD_SCL.

²The following pins are 5 V inputs: RXA_5V, RXB_5V, RXC_5V, RXD_5V.

³The following pins are 3.3 V outputs, 5 V tolerant: TXB_DDC_SCL,

TXA_DDC_SCL, HPA_D, HPA_C, HPA_B, HPA_A.

where:

0.2 is 20% of the TVDD power that is dissipated on the part

itself.

⁴Except the DDCA_SDA, DDCB_SDA, DDCC_SDA, DDCD_SDA, EP_MOSI,

N_TXis the number of connected and active TX ports.

EP_CS

EP_SCK, and

pins, which are kept to GND – 0.3 V to REG_3P3V.

P

_TX= 28 mW minus average power dissipated on-chip of each

⁵Except the REG_3P3V output, which is kept to GND – 0.3 V to SYS_3P3 +

0.3 V and REG_1P8V output, which is kept to GND – 0.3 V to DVDD + 0.3 V.

⁶The following pins are 3.3 V bidirectional input/outputs, 5 V tolerant:

TXA_DDC_SDA, TXB_DDC_SDA, DDCA_SDA, DDCB_SDA, DDCC_SDA, and

DDCD_SDA.

HDMI transmitters.

ESD CAUTION

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

Rev. 0 | Page 8 of 16

Data Sheet

ADV7630

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

1

2

3

4

96

95

94

93

92

91

90

89

88

87

RESET

DNC

PIN 1

IDENTIFIER

DNC

DVDD

CVDD

RXD_2+

RXD_2–

RXD_1+

RXD_1–

5

DNC

6

DNC

7

DNC

8

INT1

9

CLK_IN

CEC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

86 TVDD

DVDDIO

SDA

85 RXD_0+

84 RXD_0–

83 RXD_C+

SCL

CS

82

81 CVDD

80

79 SYS_3P3V

RXD_C–

DVDD

ADV7630

TOP VIEW

(Not to Scale)

TXB_PVDD

NC

DVDD

78

77

76

75

74

73

72

71

70

69

68

67

66

65

HPA_A

TXB_PVDD

TXB_HPD

TX_AVDD

TXB_C–

TXB_C+

TX_AVDD

TXB_0–

TXB_0+

TX_AVDD

TXB_1–

TXB_1+

TXB_2–

TXB_2+

TX_AVDD

RXA_5V

HPA_B

RXB_5V

HPA_C

RXC_5V

HPA_D

EXPOSED PADDLE—PIN 0 GND (BOTTOM)

RXD_5V

REG_1P8V

EP_CS

EP_SCK

EP_MISO

EP_MOSI

REG_3P3V

NOTES

1. PINS LABELED NC CAN BE ALLOWED TO FLOAT, BUT IT IS BETTER TO CONNECT THESE PINS TO GROUND.

AVOID ROUTING HIGH SPEED SIGNALS THROUGH THESE PINS BECAUSE NOISE COUPLING MAY RESULT.

2. EXPOSED PAD SHOULD BE CONNECTED TO GND.

3. DNC = DO NOT CONNECT TO THIS PIN.

Figure 5. Pin Configuration

Rev. 0 | Page 9 of 16

ADV7630

Data Sheet

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Type

Description

0

1

GND

RESET

Ground

Miscellaneous

digital

The Exposed Pad Should be Connected to GND.

System Reset Input. Active low. A minimum low reset pulse width of 5 ms is required

to reset the ADV7630 circuitry.

2 to 7, 55,

93 to 96

DNC

Do not connect Do not connect to this pin.

8

INT1

Miscellaneous

digital

Interrupt Output Pin.

9

CLK_IN

CEC

Digital input

Input Pin for a 3.3 V 27.000 MHz Clock Oscillator. The following frequencies are also

supported: 24 MHz, 24.576 MHz, and 28.63636 MHz.

Consumer Electronic Control Channel.

10

Digital

input/output

11

12

DVDDIO

SDA

Power

Digital

Digital I/O Supply Voltage (3.3 V).

I²C Port Serial Data Input/Output Pin. SDA is the data line for the control port.

input/output

Digital input

13

14

SCL

CS

I²C Port Serial Clock Input. SCL is the clock line for the control port.

Chip Select Pin. Pulling this pin up causes the I²C state machine to ignore I²C

transmission. This pin has internal pull-down.

15

16

DVDD

TXB_PVDD

Power

Digital Core Supply Voltage (1.8 V).

1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It

should be kept separately from TXA_PVDD to avoid possible crosstalk. This power

supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with

10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the

package.

17

TXB_PVDD

Power

1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It

should be kept separately from TXA_PVDD to avoid possible crosstalk. This power

supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with

10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the

package.

18, 40

19

NC

TXB_PVDD

Not connected

Power

This pin is not connected internally (see Figure 5).

1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It

should be kept separately from TXA_PVDD to avoid possible crosstalk. This power

supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with

10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the

package.

20

TXB_HPD

Digital input

Hot Plug Detect Signal of HDMI Output Port B. This pin indicates to the interface whether

the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels.

21

22

23

24

25

26

27

28

29

30

31

32

33

TX_AVDD

TXB_C−

TXB_C+

TX_AVDD

TXB_0−

TXB_0+

TX_AVDD

TXB_1−

TXB_1+

TXB_2−

TXB_2+

TX_AVDD

Power

1.8 V Power Supply for TMDS Outputs.

HDMI output

Power

HDMI output

Power

HDMI output

Power

TMDS Clock Output Complement of HDMI Output Port B.

TMDS Clock Output True of HDMI Output Port B.

1.8 V Power Supply for TMDS Outputs.

TMDS Output Channel 0 Complement of HDMI Output Port B.

TMDS Output Channel 0 True of HDMI Output Port B.

1.8 V Power Supply for TMDS Outputs.

TMDS Output Channel 1 Complement of HDMI Output Port B.

TMDS Output Channel 1 True of HDMI Output Port B.

TMDS Output Channel 2 Complement of HDMI Output Port B.

TMDS Output Channel 2 True of HDMI Output Port B.

1.8 V Power Supply for TMDS Outputs.

TXB_DDC_SDA Digital

input/output

TXB_DDC_SCL Digital output

HDCP Master Serial Data of HDMI Output Port B. TXB_DDC_SDA is a 3.3 V open-drain

input/output that is 5 V tolerant.

HDCP Master Serial Clock of HDMI Output Port B. TXB_DDC_SCL is a 3.3 V open-drain

output that is 5 V tolerant.

34

Rev. 0 | Page 10 of 16

Data Sheet

ADV7630

Pin No.

Mnemonic

Type

Description

35

TXA_DDC_SDA Digital

HDCP Master Serial Data of HDMI Output Port A. TXA_DDC_SDA is a 3.3 V open-drain

input/output that is 5 V tolerant.

input/output

36

TXA_DDC_SCL Digital output

HDCP Master Serial Clock of HDMI Output Port A. TXA_DDC_SCL is a 3.3 V open-drain

output that is 5 V tolerant.

37

38

DVDD

TXA_PVDD

Power

Digital Core Supply Voltage (1.8 V).

1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It

should be kept separately from TXB_PVDD to avoid possible crosstalk. This power

supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with

10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the

package.

39

41

42

TXA_PVDD

R_EXT

Power

Input

1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It

should be kept separately from TXB_PVDD to avoid possible crosstalk. This power

supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with

10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the

package.

1.8 V Power Supply for PLL. This supply should be filtered and as quiet as possible. It

should be kept separately from TXB_PVDD to avoid possible crosstalk. This power

supply must be filtered with a ferrite bead and decoupled with 100 nF in parallel with

10 nF capacitors. The 100 nF and 10 nF capacitors must be placed close to the

package.

Sets internal reference currents. Place a 470 Ω resistor (1% tolerance) between this pin

and ground.

43

44

45

46

47

48

49

50

51

52

53

54

56

TX_AVDD

TXA_C−

TXA_C+

TX_AVDD

TXA_0−

TXA_0+

TX_AVDD

TXA_1−

TXA_1+

TXA_2−

TXA_2+

TX_AVDD

TXA_HPD

Power

1.8 V Power Supply for TMDS Outputs.

HDMI output

Power

HDMI output

Power

HDMI output

Power

TMDS Clock Output Complement of HDMI Output Port A.

TMDS Clock Output True of HDMI Output Port A.

1.8 V Power Supply for TMDS Outputs.

TMDS Output Channel 0 Complement of HDMI Output Port A.

TMDS Output Channel 0 True of HDMI Output Port A.

1.8 V Power Supply for TMDS Outputs.

TMDS Output Channel 1 Complement of HDMI Output Port A.

TMDS Output Channel 1 True of HDMI Output Port A.

TMDS Output Channel 2 Complement of HDMI Output Port A.

TMDS Output Channel 2 True of HDMI Output Port A.

1.8 V Power Supply for TMDS Outputs.

Digital input

Hot Plug Detect Signal of HDMI Output Port A. This pin indicates to the interface

whether the receiver is connected. It supports 1.8 V to 5 V CMOS logic levels.

57

58

DDCD_SCL

DDCD_SDA

Digital input

Digital

input/output

HDCP Slave Serial Clock Port D. DDCD_SCL is a 3.3 V input that is 5 V tolerant.

HDCP Slave Serial Data Port D. DDCD_SDA is a 5 V tolerant 3.3 V input and open-drain

output.

59

60

DDCC_SCL

DDCC_SDA

Digital input

Digital

input/output

HDCP Slave Serial Clock Port C. DDCC_SCL is a 3.3 V input that is 5 V tolerant.

HDCP Slave Serial Data Port C. DDCC_SDA is a 5 V tolerant 3.3 V input and open-drain

output.

61

62

DDCB_SCL

DDCB_SDA

Digital input

Digital

input/output

HDCP Slave Serial Clock Port B. DDCB_SCL is a 3.3 V input that is 5 V tolerant.

HDCP Slave Serial Data Port B. DDCB_SDA is a 5 V tolerant 3.3 V input and open-drain

output.

63

64

DDCA_SCL

DDCA_SDA

Digital input

Digital

input/output

HDCP Slave Serial Clock Port A. DDCA_SCL is a 3.3 V input that is 5 V tolerant.

HDCP Slave Serial Data Port A. DDCA_SDA is a 5 V tolerant 3.3 V input and open-drain

output.

65

REG_3P3V

Power output

Output of Internal 3.3 V LDO. Must be connected to ground via decoupling capacitors

(10 nF in parallel with 100 nF capacitor). This pin can be used to power up external

EDID SPI EEPROM when part is in power-down mode and 5 V is connected to the part

from an HDMI cable.

66

67

68

69

EP_MOSI

EP_MISO

EP_SCK

EP_CS

Digital output

Digital input

Digital output

SPI Master Output/Slave Input for External EDID Interface.

SPI Master Input/Slave Output for External EDID Interface.

SPI Clock for External EDID Interface.

SPI Chip Select for External EDID Interface.

Rev. 0 | Page 11 of 16

ADV7630

Data Sheet

Pin No.

Mnemonic

Type

Description

70

REG_1P8V

Power output

Output of Internal 1.8 V LDO. This pin must be connected only to decoupling

capacitors (100 nF in parallel with 10 nF).

71

RXD_5V

HDMI input

5 V Detect Pin for Port D in the HDMI Interface. This pin is used to power the EDID

replicator.

72

73

HPA_D

RXC_5V

HDMI output

HDMI input

Hot Plug Assert Signal Output for HDMI Port D.

5 V Detect Pin for Port C in the HDMI Interface. This pin is used to power the EDID

replicator.

74

75

HPA_C

RXB_5V

HDMI output

HDMI input

Hot Plug Assert Signal Output for HDMI Port C.

5 V Detect Pin for Port B in the HDMI Interface. This pin is used to power the EDID

replicator.

76

77

HPA_B

RXA_5V

HDMI output

HDMI input

Hot Plug Assert Signal Output for HDMI Port B.

5 V Detect Pin for Port A in the HDMI Interface. This pin is used to power the EDID

replicator.

78

79

HPA_A

SYS_3P3V

HDMI output

Miscellaneous

power

Hot Plug Assert Signal Output for HDMI Port A.

3.3 V Power Supply.

80

DVDD

Power

Digital Core Supply Voltage (1.8 V).

81

CVDD

Power

HDMI Analog Block Supply Voltage (1.8 V).

82

83

84

85

RXD_C−

RXD_C+

RXD_0−

RXD_0+

TVDD

HDMI input

Power

Digital Input Clock Complement of Port D in the HDMI Interface.

Digital Input Clock True of Port D in the HDMI Interface.

Digital Input Channel 0 Complement of Port D in the HDMI Interface.

Digital Input Channel 0 True of Port D in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

86

87

88

89

90

RXD_1−

RXD_1+

RXD_2−

RXD_2+

CVDD

HDMI input

Power

Digital Input Channel 1 Complement of Port D in the HDMI Interface.

Digital Input Channel 1 True of Port D in the HDMI Interface.

Digital Input Channel 2 Complement of Port D in the HDMI Interface.

Digital Input Channel 2 True of Port D in the HDMI Interface.

HDMI Analog Block Supply Voltage (1.8 V).

91

92

DVDD

Power

Digital Core Supply Voltage (1.8 V).

97

CVDD

Power

HDMI Analog Block Supply Voltage (1.8 V).

98

99

RXC_C−

RXC_C+

RXC_0−

RXC_0+

TVDD

RXC_1−

RXC_1+

RXC_2−

RXC_2+

CVDD

RXB_C−

RXB_C+

RXB_0−

RXB_0+

TVDD

RXB_1−

RXB_1+

RXB_2−

RXB_2+

DVDD

HDMI input

Power

HDMI input

Power

HDMI input

Power

HDMI input

Power

Digital Input Clock Complement of Port C in the HDMI Interface.

Digital Input Clock True of Port C in the HDMI Interface.

Digital Input Channel 0 Complement of Port C in the HDMI Interface.

Digital Input Channel 0 True of Port C in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 1 Complement of Port C in the HDMI Interface.

Digital Input Channel 1 True of Port C in the HDMI Interface.

Digital Input Channel 2 Complement of Port C in the HDMI Interface.

Digital Input Channel 2 True of Port C in the HDMI Interface.

HDMI Analog Block Supply Voltage (1.8 V).

Digital Input Clock Complement of Port B in the HDMI Interface.

Digital Input Clock True of Port B in the HDMI Interface.

Digital Input Channel 0 Complement of Port B in the HDMI Interface.

Digital Input Channel 0 True of Port B in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

Digital Input Channel 1 Complement of Port B in the HDMI Interface.

Digital Input Channel 1 True of Port B in the HDMI Interface.

Digital Input Channel 2 Complement of Port B in the HDMI Interface.

Digital Input Channel 2 True of Port B in the HDMI Interface.

Digital Core Supply Voltage (1.8 V).

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

CVDD

RXA_C−

RXA_C+

Power

HDMI input

HDMI Analog Block Supply Voltage (1.8 V).

Digital Input Clock Complement of Port A in the HDMI Interface.

Digital Input Clock True of Port A in the HDMI Interface.

Rev. 0 | Page 12 of 16

Data Sheet

ADV7630

Pin No.

121

122

Mnemonic

Type

Description

RXA_0−

RXA_0+

TVDD

HDMI input

Power

Digital Input Channel 0 Complement of Port A in the HDMI Interface.

Digital Input Channel 0 True of Port A in the HDMI Interface.

Terminator Supply Voltage (3.3 V).

123

124

125

126

127

RXA_1−

RXA_1+

RXA_2−

RXA_2+

CVDD

HDMI input

Power

Digital Input Channel 1 Complement of Port A in the HDMI Interface.

Digital Input Channel 1 True of Port A in the HDMI Interface.

Digital Input Channel 2 Complement of Port A in the HDMI Interface.

Digital Input Channel 2 True of Port A in the HDMI Interface.

HDMI Analog Block Supply Voltage (1.8 V).

128

Rev. 0 | Page 13 of 16

ADV7630

Data Sheet

POWER SUPPLY RECOMMENDATION

POWER-UP SEQUENCE

POWER-DOWN SEQUENCE

The ADV7630 supplies can be de-asserted simultaneously

as long as a higher rated supply does not go below a lower

rated supply.

The power-up sequence of the ADV7630 is as follows:

RESET

1. Hold

low.

2. Bring up the 3.3 V supplies (DVDDIO, TVDD,

SYS_3P3V).

3. A minimum delay of 20 ms is required from the point

at which the 3.3 V supplies reaches the minimum recom-

mended value (3.14 V) before powering up the 1.8 V

supplies.

3.3V

RESET

0V

1.8V

4. Bring up the 1.8 V supplies (DVDD, TXA_PVDD,

TXB_PVDD, CVDD, TX_AVDD). These should

be powered up together, that is, there should be a

difference of less than 0.3 V between them.

1.8V

SUPPLY

0V

3.3V

3.14V

RESET

powered up.

5.

can be pulled high after supplies have been

3.3V

SUPPLY

RESET > 5ms

TPSS ≥ 20ms

6. A complete reset is recommended after power-up. This

can be performed by the system microcontroller.

0V

Figure 6. Supply Power-Up Sequence

Rev. 0 | Page 14 of 16

Data Sheet

ADV7630

FUNCTIONAL OVERVIEW

HDMI RECEIVER

HDMI TRANSMITTER

The ADV7630 incorporates a 1:2 HDMI splitter with 4:1

multiplexed input receiver that supports all mandatory and

many optional 3D formats, HDTV formats up to 1080p, and all

display resolutions up to UXGA (1600 × 1200 at 60 Hz).

The ADV7630 features two HDMI transmitters: TXA and TXB.

Both transmitters support 3D TV formats as well as all HDTV

formats up to 1080p 36-bit Deep Color. The TXA and TXB

transmitters have separate DDC lines to allow reading EDID

data and performing HDCP operations authentication with

two independent HDMI sinks.

The inclusion of HDCP allows the ADV7630 to receive

encrypted video content. The HDMI interface of the ADV7630

allows for the reception of two parallel and independent video

streams including authentication of a video receiver, decryption

of encoded data at the receiver, and the maintenance of that

authentication during transmission, as specified by the HDCP

1.4 protocol.

Both transmitters feature an on-chip microprocessor unit

(MPU) with an I²C master to perform HDCP operations and

EDID reading operations.

I²C INTERFACE

The ADV7630 supports a 2-wire serial (I²C-compatible)

microprocessor bus driving multiple peripherals. The

ADV7630 is controlled by an external I²C master device,

such as a microcontroller.

The HDMI-compatible receiver on the ADV7630 incorporates

an equalizer that compensates for the high frequency losses

inherent in HDMI and DVI cabling, especially at longer lengths

and higher frequencies. It is capable of equalizing for cable

lengths up to 30 meters to achieve robust receiver performance.

OTHER FEATURES

Other features include the following:

XpressView fast switching can be implemented with full HDCP

authentication available on the background port.

•

Fully qualified software libraries, driver, and application

Programmable interrupt request output pin (INT1)

Chip select

HDMI receiver features include:

•

1:2 HDMI splitter

4:1 HDMI input mux

3D format support

Temperature range: 0^oC to 70^oC

14 mm × 14 mm, Pb-free 128-lead TQFP with exposed pad

225 MHz HDMI receiver

Integrated equalizer for cable lengths up to 30 meters

HDCP 1.4 also on background ports

Internal HDCP keys

36-/30-bit Deep Color support

Repeater support

Internal EDID RAM

Hot plug assert output pin for each HDMI port

CEC controller

Rev. 0 | Page 15 of 16

ADV7630

Data Sheet

OUTLINE DIMENSIONS

16.20

16.00 SQ

15.80

1.20

MAX

14.20

14.00 SQ

13.80

0.75

0.60

0.45

12.40 REF

128

97

96

97

96

128

1

1.00 REF

PIN 1

SEATING

PLANE

EXPOSED

PAD

6.35

REF

TOP VIEW

BOTTOM VIEW

(PINS UP)

1.05

1.00

0.95

(PINS DOWN)

0.20

0.15

0.09

32

65

64

65

64

32

33

0.23

0.18

0.13

VIEW A

FOR PROPER CONNECTION OF

THE EXPOSED PAD, REFER TO

THE PIN CONFIGURATION AND

FUNCTION DESCRIPTIONS

0.15

0.10

0.05

0.40

BSC

LEAD PITCH

7°

0°

0.08

COPLANARITY

SECTION OF THIS DATA SHEET.

VIEW A

COMPLIANT TO JEDEC STANDARDS MS-026-AEE-HD

ROTATED 90° CCW

Figure 7. 128-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-128-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model¹

Temperature Range

Package Description

Package Option

ADV7630KSVZ

0°C to 70°C

128-Lead TQFP_EP

SV-128-1

¹Z = ROHS Compliant.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other

countries.

registered trademarks are the property of their respective owners.

D10635-0-9/12(0)

Rev. 0 | Page 16 of 16


型号：	ADV7630KSVZ
厂家：	ADI
描述：	2.25 GHz XpressView HDMI 1:2 Splitter with 4:1 Input Mux
文件：	总16页 (文件大小：298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ADV7630KSVZ [ADI]

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