ADV7627 [ADI]
3 GHz HDMI 5:1 Transceiver with On-Screen Display;
| 型号： | ADV7627 |
| 厂家： | 
ADI |
| 描述： | 3 GHz HDMI 5:1 Transceiver with On-Screen Display |
| 文件： | 总24页 (文件大小：383K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
3 GHz HDMI 5:1 Transceiver
with On-Screen Display
ADV7627
Data Sheet
HDMI transmitter
FEATURES
3 GHz support on transmitter outputs
EDID data extraction
Hot Plug detect (HPD) inputs
Audio return channel (ARC) receiver
3 GHz color space converter (CSC)
5-input, 1-output HDMI transceiver
HDMI support
3 GHz video support (up to 4k × 2k)
Audio return channel (ARC)
3D TV support
Content type bits
Audio
HDMI-compatible audio interface
8-channel audio extraction port
8-channel audio insertion port
S/PDIF (IEC 60958-compatible) digital audio input/output
Super Audio CD® (SACD) with DSD input/output interface
High bit rate (HBR) audio
Dolby® TrueHD
DTS-HD Master Audio™
Full audio input and output support
General
CEC 1.4-compatible
Extended colorimetry
Character- and icon-based on-screen display (OSD)
3D OSD overlay on all mandatory 3D formats
Support for OSD overlay on 3 GHz video formats
High-bandwidth Digital Content Protection (HDCP 1.4)
HDCP repeater support: up to 127 KSVs supported
300 MHz maximum TMDS clock frequency (up to 4k × 2k)
48-/36-/30-bit Deep Color input modes supported
Ultralow jitter digital PLL (100% deskew)
TTL pixel port input
Interrupt controller
Standard identification (STDI) circuit
Software libraries, driver, and application available
Allows digital video input to facilitate analog video support
Interlaced-to-progressive converter
HDMI receiver for 5 input ports
APPLICATIONS
3 GHz support on all inputs
AVR
HTiB
Adaptive equalizer for cable lengths up to 30 meters
Flexible internal EDID RAM supports dual EDIDs
Replication of either dual EDID on any input port
5 V detect inputs
Soundbar with HDMI repeater support
Other repeater applications
Hot Plug assert control outputs
FUNCTIONAL BLOCK DIAGRAM
ADV7627
TMDS
DDC
HDCP
HDMI_RX_A
HDMI_RX_B
HDMI_RX_C
HDMI_RX_D
HDMI_RX_E
TMDS
DDC
HDCP
5:1
MUX
TMDS
DDC
TMDS
DDC
HDMI_TX
CP-LITE
OSD
HDMI TX
HDMI RX
ARC
TMDS
DDC
TMDS
DDC
CEC
RX EDID WITH
REPLICATOR
DIGITAL AUDIO
OUTPUT PORT
DIGITAL AUDIO
INPUT PORT
PIXEL PORT
INPUT
TX EDID/HDCP
CONTROLLER
2
INTERRUPTS
I C
SPI
Figure 1.
Rev. 0
Document Feedback
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rightsof third parties that may result fromits use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks andregisteredtrademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADV7627
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Power Supply Recommendations................................................. 21
Power-Up Sequence ................................................................... 21
Power-Down Sequence.............................................................. 21
Theory of Operation ...................................................................... 22
HDMI Receiver........................................................................... 22
HDCP Repeater Functionality ................................................. 22
Digital Audio Ports .................................................................... 22
On-Screen Display ..................................................................... 22
Pixel Port Input........................................................................... 22
HDMI Transmitter..................................................................... 22
I2C Interface ................................................................................ 22
Other Features ............................................................................ 22
Outline Dimensions ....................................................................... 23
Ordering Guide .......................................................................... 23
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Detailed Functional Block Diagram .............................................. 4
Specifications..................................................................................... 5
Digital, HDMI, and AC Specifications...................................... 5
Data and I2C Timing Characteristics......................................... 6
Power Specifications .................................................................. 12
Absolute Maximum Ratings.......................................................... 14
Package Thermal Performance................................................. 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
REVISION HISTORY
12/13—Revision 0: Initial Version
Rev. 0 | Page 2 of 24
Data Sheet
ADV7627
GENERAL DESCRIPTION
The ADV7627 is a high performance, five-input, one-output,
High-Definition Multimedia Interface (HDMI®) transceiver.
The ADV7627 supports 3 GHz video and features one HDMI
receiver, one HDMI transmitter, an audio output port, an audio
input port, and a pixel port input. The ADV7627 supports all
HDCP repeater functions through fully tested Analog Devices,
Inc., repeater software libraries and drivers.
The ADV7627 offers an audio output port and an audio input
port. Each audio port supports the extraction and insertion of up
to eight channels of audio data out of or into the HDMI streams.
HDMI audio formats, including I2S, S/PDIF, direct stream digital
(DSD), and high bit rate (HBR) audio are supported.
The ADV7627 features a TTL pixel port input that facilitates the
reception of digital video data from an analog front-end decoder
(for example, the ADV7180, ADV7181D, or ADV7842).
The HDMI receiver and transmitter in the ADV7627 support
the reception and transmission of 3 GHz video formats up to 4k ×
2k at 24 Hz/25 Hz/30 Hz, in addition to all mandatory HDMI 3D
TV formats. The receiver and transmitter also provide support
for THX® Media Director™.
The ADV7627 has an integrated on-screen display (OSD)
generator that enables the creation and control of high quality
character- and icon-based system status and control displays.
The OSD can be overlaid on 3 GHz video formats and 3D video.
Customers who are interested in using OSD are provided with
Blimp, the Analog Devices OSD development tool.
The HDMI receiver features an integrated equalizer that ensures
robust operation of the interface with cable lengths up to 30 meters.
The HDMI receiver has a 768-byte volatile extended display
identification data (EDID) memory, which can facilitate one or two
EDIDs. Each HDMI port features dedicated 5 V detect and Hot
Plug™ assert pins.
The ADV7627 is provided in a space-saving, 260-ball, 15 mm ×
15 mm CSP_BGA surface-mount, RoHS-compliant package and
is specified over the 0°C to 70°C temperature range.
The HDMI transmitter supports audio return channel (ARC)
and features an integrated HDMI CEC controller that supports
capability discovery and control (CDC).
Rev. 0 | Page 3 of 24
ADV7627
Data Sheet
DETAILED FUNCTIONAL BLOCK DIAGRAM
0 0 2 1 1 8
P
H D C
D C M
C S
C
INT1
INT2
AP_IN_MCLK*
AP_IN_SCLK*/AUD_IN_SCLK
AP_IN5*/AUD_IN_LRCLK
AP_IN0*/AUD_IN
EP_MOSI
EP_MISO
EP_SCLK
EP_CS
AP_OUT_MCLK
AP_OUT_SCLK
AP_OUT5
AP_OUT0
TX_ARC+
PCLK
DE
VS
HS
TX_HPD_ARC–
P0*
P15*
P
H D C
CS
ALSB
SDA
SCL
Figure 2. Detailed Functional Block Diagram
Rev. 0 | Page 4 of 24
Data Sheet
ADV7627
SPECIFICATIONS
AVDD_TX = 1.8 V 5%, CVDD = 1.8 V 5%, DVDD = 1.8 V 5%, DVDDIO = 3.3 V 5%, PVDD = 1.8 V 5%,
PVDD_TX = 1.8 V 5%, TVDD = 3.3 V 5%, TMIN to TMAX = 0°C to 70°C.
DIGITAL, HDMI, AND AC SPECIFICATIONS
Table 1.
Parameter
Test Conditions/Comments
Min
2
Typ
Max
Unit
DIGITAL INPUTS
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Leakage Current (IIN)
Input Capacitance (CIN)
DIGITAL INPUTS (5 V TOLERANT)1
Input High Voltage (VIH)
Input Low Voltage (VIL)
Input Leakage Current (IIN)
V
V
µA
pF
0.8
+60
20
−60
2.85
V
V
µA
µA
0.8
+450
+60
RXA_5V, RXB_5V, RXC_5V, RXD_5V, RXE_5V
All other 5 V tolerant digital inputs
−450
−60
DIGITAL OUTPUTS
Output High Voltage (VOH)
Output Low Voltage (VOL)
High Impedance Leakage Current (ILEAK
2.4
V
V
µA
pF
0.4
20
)
10
Output Capacitance (COUT
)
DIGITAL OUTPUTS (5 V TOLERANT)2
Output High Voltage (VOH)
Output Low Voltage (VOL)
AC SPECIFICATIONS
4.85
V
V
0.4
TMDS Input Clock Range
TMDS Output Clock Frequency
25
25
300
300
MHz
MHz
1 The following pins are 5 V tolerant inputs: DDC_SCL_RXA, DDC_SDA_RXA, DDC_SCL_RXB, DDC_SDA_RXB, DDC_SCL_RXC, DDC_SDA_RXC, DDC_SCL_RXD,
DDC_SDA_RXD, DDC_SCL_RXE, DDC_SDA_RXE, RXA_5V, RXB_5V, RXC_5V, RXD_5V, RXE_5V, CEC, DDC_SCL_TX, DDC_SDA_TX, TX_HPD_ARC−, and TX_ARC+.
2 The following pins are 5 V tolerant outputs: RXA_HPA, RXB_HPA, RXC_HPA, RXD_HPA, and RXE_HPA.
Rev. 0 | Page 5 of 24
ADV7627
Data Sheet
DATA AND I2C TIMING CHARACTERISTICS
Table 2.
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
VIDEO SYSTEM CLOCK AND XTAL
Crystal Nominal Frequency
Crystal Frequency Stability
External Clock Source
27.0
MHz
ppm
50
External crystal must operate
at 1.8 V
Input High Voltage
Input Low Voltage
VIH
VIL
XTAL driven with external
clock source
XTAL driven with external
clock source
1.2
V
0.4
V
Pixel Port Input Clock Frequency
Range
Interlaced-to-progressive
converter not enabled
Interlaced-to-progressive
13.5
148.5
13.5
MHz
MHz
converter enabled (480i, 576i)
Serial Port EP_SCLK Frequency
Audio SCLK Frequency
Audio MCLK Frequency
Audio DSD Clock Frequency
RESET FEATURE
27
MHz
MHz
MHz
MHz
49.152
98.304
5.6448
Reset Pulse Width
5
ms
I2C PORTS (FAST MODE)
xCL Frequency1
xCL Minimum Pulse Width High1
xCL Minimum Pulse Width Low1
Start Condition Hold Time
Start Condition Setup Time
xDA Setup Time2
xCL and xDA Rise Time1, 2
xCL and xDA Fall Time1, 2
Setup Time (Stop Condition)
SERIAL PORT, MASTER MODE3, 4
400
kHz
ns
µs
ns
ns
ns
ns
ns
µs
t1
t2
t3
t4
t5
t6
t7
t8
600
1.3
600
600
100
300
300
0.6
SPI Mode 0
t9, t10
1 × EP_SCLK
periods
1.5 × EP_SCLK ns
periods
EP_CS Falling Edge to EP_SCLK
Rising/Falling Edge
EP_SCLK Rising/Falling Edge
to EP_CS Rising Edge
t11, t12
1 × EP_SCLK
periods
1.5 × EP_SCLK ns
periods
EP_CS Pulse Width5
t13
t14
1000
40
ns
EP_SCLK High Time
60
60
0
% duty
cycle
% duty
cycle
EP_SCLK Low Time
40
EP_MOSI Start of Data Invalid
to EP_SCLK Falling Edge
EP_CS Start of Data Invalid to
EP_SCLK Falling Edge
EP_SCLK Falling Edge to EP_MOSI
End of Data Invalid
EP_SCLK Falling Edge to EP_CS
End of Data Invalid
t15
t15
t16
t16
t17
t18
ns
ns
ns
ns
ns
ns
0
2.15
2.15
EP_MISO Setup Time
Valid regardless of the
EP_SCLK active edge used
Valid regardless of the
7.5
0
EP_MISO Hold Time
EP_SCLK active edge used
Rev. 0 | Page 6 of 24
Data Sheet
ADV7627
Parameter
SERIAL PORT, SLAVE MODE3, 4
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
SPI Mode 0
t20
t22
t23
t24
10
10
ns
ns
ns
EP_CS Falling Edge to EP_SCLK
Rising Edge
Final EP_SCLK Rising Edge to EP_CS
Rising Edge
EP_CS Pulse Width5
EP_SCLK High Time
EP_SCLK Low Time
20 × EP_SCLK
periods
45
45
55
55
% duty
cycle
% duty
cycle
EP_MOSI Setup Time
EP_MOSI Hold Time
EP_SCLK Falling Edge to EP_MISO
Start of Data Invalid
t25
t26
t27
0.5
1.4
5.5
ns
ns
ns
EP_SCLK Falling Edge to EP_MISO
End of Data Invalid
t28
9
ns
VIDEO DATA AND CONTROL INPUTS
PCLK High Time5
t29
0.45 to 0.55 ×
PCLK period
0.45 to 0.55 ×
PCLK period
% duty
cycle
% duty
cycle
PCLK Low Time5
Pixel Port Input, Setup Time,
SDR and DDR Modes
Pixel Port Input, Hold Time,
SDR and DDR Modes
Pixel Port Input, Setup Time,
DDR Mode
Pixel Port Input, Hold Time,
DDR Mode
t30
t31
t32
t33
Data latched on rising edge
Data latched on rising edge
Data latched on falling edge
Data latched on falling edge
1.0
1.4
1.0
1.4
ns
ns
ns
ns
AUDIO INPUT PORT, I2S INPUT
AP_IN_SCLK High Time
t37
45
45
55
55
% duty
cycle
% duty
cycle
AP_IN_SCLK Low Time
AP_IN Data Setup Time
AP_IN Data Hold Time
AUD_IN_SCLK High Time
t38
t39
t37
2.3
1.6
45
ns
ns
% duty
cycle
% duty
cycle
55
55
AUD_IN_SCLK Low Time
45
AUD_IN Data Setup Time
AUD_IN Data Hold Time
t38
t39
1.0
3.5
ns
ns
AUDIO INPUT PORT, DSD INPUT
AP_IN_SCLK High Time
t40
45
45
55
55
% duty
cycle
% duty
cycle
AP_IN_SCLK Low Time
AP_IN DSD Data Setup Time
AP_IN DSD Data Hold Time
AUDIO OUTPUT PORT, I2S OUTPUT
AP_OUT_SCLK High Time
t41
t42
2.3
1.6
ns
ns
t46
45
45
55
55
10
10
% duty
cycle
% duty
cycle
AP_OUT_SCLK Low Time
AP_OUT LRCLK Transition Time
AP_OUT LRCLK Transition Time
t47
t48
Start of invalid LRCLK to falling
AP_OUT_SCLK edge
Falling AP_OUT_SCLK edge to
end of invalid LRCLK
ns
ns
Rev. 0 | Page 7 of 24
ADV7627
Data Sheet
Parameter
Symbol
Test Conditions/Comments
Min
Typ
Max
Unit
AP_OUT Data Transition Time
t49
Start of invalid data to falling
AP_OUT_SCLK edge
10
ns
AP_OUT Data Transition Time
t50
Falling AP_OUT_SCLK edge to
end of invalid data
10
ns
AUDIO OUTPUT PORT, DSD OUTPUT
AP_OUT_SCLK High Time
t51
45
45
55
55
10
10
% duty
cycle
% duty
cycle
AP_OUT_SCLK Low Time
AP_OUT DSD Data Transition Time
AP_OUT DSD Data Transition Time
t52
t53
Start of invalid data to falling
AP_OUT_SCLK edge
Falling AP_OUT_SCLK edge to
end of invalid data
ns
ns
1 xCL refers to SCL, DDC_SCL_RXA, DDC_SCL_RXB, DDC_SCL_RXC, DDC_SCL_RXD, and DDC_SCL_RXE.
2 xDA refers to SDA, DDC_SDA_RXA, DDC_SDA_RXB, DDC_SDA_RXC, DDC_SDA_RXD, and DDC_SDA_RXE.
3 SPI Mode 0 only.
4 All serial port measurements are for CPHA = 0, CPOL = 0 (clock is low in idle state; negative edge of clock is used to transmit data and positive edge is used to sample data).
5 Measurements guaranteed by design only.
Timing Diagrams
t3
t5
t3
xDA
xCL
t6
t1
t2
t7
t4
t8
Figure 3. I2C Timing
t13
t9
t11
t12
t10
EP_CS
EP_SCLK
INSTRUCTION
(0x0B)
24-BIT
ADDRESS
DUMMY BYTE
EP_MOSI
23 22 21 ...
3
2
1
0
7
6
5
4
3
2
1
0
DATA OUT 2
DATA OUT 1
EP_MISO
7
6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Figure 4. Detailed SPI Master Timing Diagram (SPI Mode 0, CPOL = CPHA = 0)
t14
t17
t17
t15
t18
t18
t16
EP_SCLK
EP_MOSI
EP_CS
EP_MISO
(FALLING EDGE CAPTURE)
EP_MISO
(RISING EDGE CAPTURE)
Figure 5. SPI Master Mode Timing (SPI Mode 0)
Rev. 0 | Page 8 of 24
Data Sheet
ADV7627
t23
t22
t20
EP_CS
EP_SCLK
W/R
0
DEVICE ADDRESS
SUBADDRESS
DATA IN 0
DATA IN 1
7
6
5
4
3
2
1
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
7
7
6
6
6
5
4
3
2
1
1
1
0
0
0
EP_MOSI
DUMMY BYTE
DATA OUT 0
DELAY MODE 1
EP_MISO
5
4
3
2
DATA OUT 0
DATA OUT 1
DELAY MODE 0
EP_MISO
7
6
5
4
3
2
1
0
5
4
3
2
Figure 6. Detailed SPI Slave Timing Diagram (SPI Mode 0, CPOL = CPHA = 0)
t28
t24
t25
t26
t27
EP_SCLK
EP_MOSI
EP_MISO
Figure 7. SPI Slave Mode Timing (SPI Mode 0)
t29
t30
t31
PCLK
P[15:0]
HS
VS
DE
Figure 8. Pixel Port Input, Noninterleaved SDR Video Data and Control Timing
t29
PCLK
t32
t31
t33
t30
P[15:0]
HS
VS
DE
Figure 9. Pixel Port Input, Noninterleaved DDR Video Data and Control Timing
Rev. 0 | Page 9 of 24
ADV7627
Data Sheet
t37
SCLK
t38
t39
I2S[3:0]
LRCLK
2
AUDIO INPUT PORTS I S SIGNAL ASSIGNMENT
INPUT PORT
SCLK
LRCLK
I2S[3:0]
AUD_IN
AP_IN
AUD_IN_SCLK
AP_IN_SCLK
AUD_IN_LRCLK
AP_IN5
AUD_IN (I2S0 ONLY)
AP_IN[4:1]
NOTES
1. AUD_IN PORT NOT AVAILABLE WHEN AP_IN PORT USED.
2. AP_IN PORT NOT AVAILABLE WHEN PIXEL PORT INPUT USED.
Figure 10. I2S Input Timing
LRCLK
SCLK
LEFT
RIGHT
MSB
MSB
LSB
LSB
RIGHT
LEFT
I2S[3:0]
32 CLOCK SLOTS
32 CLOCK SLOTS
2
I S STANDARD
2
I S FORMAT = 00
Figure 11. I2S Standard Audio, Data Width 16 to 24 Bits per Channel
LEFT
RIGHT
LRCLK
SCLK
LSB
MSB
LSB
MSB
RIGHT
LSB
RIGHT
LEFT
LEFT
I2S[3:0]
16 CLOCK SLOTS
16 CLOCK SLOTS
Figure 12. I2S Standard Audio, 16-Bit Samples Only
Rev. 0 | Page 10 of 24
Data Sheet
ADV7627
LRCLK
LEFT
RIGHT
SCLK
I2S[3:0]
MSB
MSB
MSB
MSB
MSB – 1
LSB
MSB
MSB
MSB
MSB
MSB – 1
LSB
MSB
EXTENDED
MSB
EXTENDED
32 CLOCK SLOTS
32 CLOCK SLOTS
SERIAL AUDIO
RIGHT JUSTIFIED
2
I S FORMAT = 01
Figure 13. Serial Audio, Right-Justified
LRCLK
SCLK
LEFT
RIGHT
MSB
LSB
MSB
LSB
I2S[3:0]
32 CLOCK SLOTS
32 CLOCK SLOTS
SERIAL AUDIO
LEFT JUSTIFIED
2
I S FORMAT = 10
Figure 14. Serial Audio, Left-Justified
LRCLK
SCLK
CHANNEL A
CHANNEL B
I2S[3:0]
LSB
MSB
V
U
C
P
LSB
MSB
V
U
C
P
32 CLOCK SLOTS
32 CLOCK SLOTS
FRAME n
FRAME n + 1
AES3 DIRECT AUDIO
2
I S FORMAT = 11
Figure 15. AES3 Direct Audio
t40
AP_IN_SCLK
t41
t42
AP_IN[5:0]
Figure 16. DSD Input Timing
Rev. 0 | Page 11 of 24
ADV7627
Data Sheet
t46
AP_OUT_SCLK
t47
LRCLK
t48
t49
I2Sx
LEFT-JUSTIFIED
MODE
MSB
MSB – 1
MSB
t50
t49
I2Sx
2
I S MODE
MSB – 1
t50
t49
I2Sx
RIGHT-JUSTIFIED
MODE
MSB
LSB
t50
NOTES
1. LRCLK IS A SIGNAL ACCESSIBLE VIA AP_OUT5.
2. I2Sx ARE SIGNALS ACCESSIBLE VIA AP_OUT1 TO AP_OUT4.
Figure 17. I2S Output Timing
t53
t51
AP_OUT_SCLK
AP_OUT[5:0]
t52
Figure 18. DSD Output Timing
POWER SPECIFICATIONS
Table 3.
Parameter
Symbol
Min
Typ
Max
Unit
POWER SUPPLIES
HDMI Tx Analog Power Supply
Comparator Power Supply
Digital Power Supply
Digital I/O Power Supply
PLL Power Supply
AVDD_TX
CVDD
DVDD
DVDDIO
PVDD
PVDD_TX
TVDD
1.71
1.71
1.71
3.14
1.71
1.71
3.14
1.8
1.8
1.8
3.3
1.8
1.8
3.3
1.89
1.89
1.89
3.46
1.89
1.89
3.46
V
V
V
V
V
V
V
HDMI Tx PLL Power Supply
Termination Power Supply
CURRENT CONSUMPTION—MUX MODE1, 2
HDMI Tx Analog Power Supply
Comparator Power Supply
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
HDMI Tx PLL Power Supply
Termination Power Supply
IAVDD_TX
ICVDD
IDVDD
IDVDDIO
IPVDD
IPVDD_TX
ITVDD
24
mA
mA
mA
mA
mA
mA
mA
96.5
173
1.5
34
70
113
Rev. 0 | Page 12 of 24
Data Sheet
ADV7627
Parameter
Symbol
Min
Typ
Max
Unit
CURRENT CONSUMPTION—AUDIO INSERT MODE1, 3
HDMI Tx Analog Power Supply
Comparator Power Supply
Digital Core Power Supply
Digital I/O Power Supply
IAVDD_TX
ICVDD
IDVDD
IDVDDIO
IPVDD
IPVDD_TX
ITVDD
26
mA
mA
mA
mA
mA
mA
mA
184
216
0.05
64.1
71
PLL Power Supply
HDMI Tx PLL Power Supply
Termination Power Supply
CURRENT CONSUMPTION—POWER-DOWN MODE 01, 4
HDMI Tx Analog Power Supply
Comparator Power Supply
Digital Core Power Supply
Digital I/O Power Supply
116
IAVDD_TX
ICVDD
IDVDD
IDVDDIO
IPVDD
IPVDD_TX
ITVDD
1.30
0.84
0.25
0.21
0.02
0.10
0.14
mA
mA
mA
mA
mA
mA
mA
PLL Power Supply
HDMI Tx PLL Power Supply
Termination Power Supply
CURRENT CONSUMPTION—POWER-DOWN MODE 11, 5
HDMI Tx Analog Power Supply
Comparator Power Supply
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
HDMI Tx PLL Power Supply
Termination Power Supply
IAVDD_TX
ICVDD
IDVDD
IDVDDIO
IPVDD
IPVDD_TX
ITVDD
1.90
0.84
0.95
0.21
0.02
0.10
0.14
mA
mA
mA
mA
mA
mA
mA
CURRENT CONSUMPTION—EXAMPLE MAXIMUM
OPERATING MODE1, 6
HDMI Tx Analog Power Supply
Comparator Power Supply
Digital Core Power Supply
Digital I/O Power Supply
PLL Power Supply
IAVDD_TX
ICVDD
IDVDD
IDVDDIO
IPVDD
IPVDD_TX
ITVDD
31.00
213.00
255.00
0.20
75.00
82.00
127.00
mA
mA
mA
mA
mA
mA
mA
HDMI Tx PLL Power Supply
Termination Power Supply
1 Data recorded during lab characterization. Typical current consumption values are recorded with nominal voltage supply levels and at room temperature.
2 ADV7627 configured in mux mode with one active HDMI Rx input and the HDMI Tx output in use. 4k × 2k at 30 Hz video format with pseudo random test pattern
applied to the active HDMI Rx input port. HDMI Rx termination closed on the active HDMI Rx input port and open on the unused HDMI Rx input ports. HDMI Tx source
termination enabled.
3 ADV7627 configured in audio insert mode with one active HDMI Rx input and the HDMI Tx output in use. Audio inserted on HDMI Tx output from the AP_IN input
port. HBR audio used. No audio extraction. 4k × 2k at 30 Hz video format with pseudo random test pattern applied to the active HDMI Rx input port. HDMI Rx port
termination closed on the active HDMI Rx input port and open on the unused HDMI Rx input ports. HDMI Tx source termination enabled. OSD not enabled.
4 ADV7627 configured in Power-Down Mode 0. In Power-Down Mode 0, all blocks are powered down except for the I2C slave.
5 ADV7627 configured in Power-Down Mode 1. In Power-Down Mode 1, all blocks are powered down except for the I2C slave and the CEC (to monitor wake-up
interrupts).
6 ADV7627 configured in an example maximum operating mode with one active HDMI Rx input and the HDMI Tx output in use. HBR audio from the active HDMI Rx
input inserted on the HDMI Tx output. No audio extraction. 4k × 2k at 30 Hz video format with pseudo random test pattern applied to the active HDMI Rx input port.
HDMI Rx port termination closed on the active HDMI Rx input port and open on the unused HDMI Rx input ports. HDMI Tx source termination enabled. OSD not
enabled. Maximum current consumption values recorded with maximum power supply levels at device maximum operating temperature.
Rev. 0 | Page 13 of 24
ADV7627
Data Sheet
ABSOLUTE MAXIMUM RATINGS
PACKAGE THERMAL PERFORMANCE
Table 4.
To reduce power consumption when using the ADV7627,
the user is advised to turn off unused sections of the device.
Parameter
Rating
2.2 V
2.2 V
2.2 V
2.2 V
2.2 V
4.0 V
4.0 V
AVDD_TX to GND
CVDD to GND
DVDD to GND
Due to printed circuit board (PCB) metal variation and,
therefore, variation in PCB heat conductivity, the value of θJA
may differ for various PCBs. The most efficient measurement
solution is obtained using the package surface temperature to
estimate the die temperature because this solution eliminates
the variance associated with the θJA value.
PVDD to GND
PVDD_TX to GND
DVDDIO to GND
TVDD to GND
Digital Inputs Voltage to GND
GND − 0.3 V to DVDDIO + 0.3 V
up to a maximum of 4.0 V
5.5 V
The maximum junction temperature (TJ MAX) of 125°C must
not be exceeded. The following equation calculates the junction
temperature using the measured package surface temperature
and applies only when no heat sink is used on the device under
test (DUT):
5 V Tolerant Digital Inputs
to GND1
Digital Outputs Voltage to GND GND − 0.3 V to DVDDIO + 0.3 V
up to a maximum of 4.0 V
XTAL+, XTAL− Pins
Maximum Junction Temperature 125°C
(TJ MAX
−0.3 V to PVDD + 0.3 V
TJ = TS + (ΨJT × WTOTAL
)
where:
)
TS is the package surface temperature (°C).
ΨJT = 0.41°C/W for the 260-ball CSP_BGA (based on 2s2p
test board defined in the JEDEC specification).
Storage Temperature Range
Infrared Reflow, Soldering
(20 sec)
−65°C to +150°C
260°C
1 The following inputs are 5 V tolerant: DDC_SCL_RXA, DDC_SDA_RXA, DDC_
SCL_RXB, DDC_SDA_RXB, DDC_SCL_RXC, DDC_SDA_RXC, DDC_SCL_RXD,
DDC_SDA_RXD, DDC_SCL_RXE, DDC_SDA_RXE, RXA_5V, RXB_5V, RXC_5V,
RXD_5V, RXE_5V, CEC, DDC_SCL_TX, DDC_SDA_TX, TX_HPD_ARC−, and
TX_ARC+.
W
TOTAL = ((PVDD × IPVDD) + (PVDD_TX × IPVDD_TX) +
(TVDD × ITVDD) + (CVDD × ICVDD) + (AVDD _T X ×
AVDD_TX) + (DVDD × IDVDD) + (DVDDIO × IDVDDIO))
I
Note that this calculation assumes a configuration of one active
HDMI Rx input and one active HDMI Tx output, where termi-
nation is open on the unused Rx input ports.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Rev. 0 | Page 14 of 24
Data Sheet
ADV7627
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
A
B
C
D
E
F
GND
GND
GND
INT1
NC
RXA_2+
RXA_2–
CVDD
INT2
NC
RXA_1+
RXA_1–
CVDD
SCL
RXA_0+ RXA_C+
CVDD
CVDD
GND
RXB_2+
RXB_2–
GND
RXB_1+
RXB_0+
RXB_C+
CVDD
RXC_2+
RXC_2–
TVDD
RXC_1+
RXC_1–
TVDD
RXC_0+
RXC_0–
RXC_C+
RXC_C–
CVDD
CVDD
CVDD
TVDD
TVDD
GND
GND
GND
TVDD
TVDD
GND
GND
GND
VS
RXC_5V
GND
GND
RXA_0– RXA_C–
RXB_1–
RXB_0–
RXB_C–
CVDD
RXC_HPA
GND
TVDD
SDA
TVDD
CS
TVDD
DDC_
TVDD
DDC_
GND
GND
GND
GND
GND
DDC_
DDC_
DDC_
SDA_RXC SCL_RXC
DDC_
RXA_5V RXA_HPA
RXB_HPA RXB_5V
RXD_2–
RXD_1–
RXD_0–
RXD_2+
RXD_1+
RXD_0+
SCL_RXA SDA_RXA SCL_RXB SDA_RXB
ALSB
RESET
RXD_5V
NC
NC
AP_OUT0 AP_OUT1
AP_OUT2 AP_OUT3
AP_OUT4 AP_OUT5
RXD_HPA
DDC_
SCL_RXD
NC
NC
DVDD
DVDDIO
DVDDIO
GND
DVDD
GND
GND
GND
GND
GND
DVDD
GND
GND
GND
GND
GND
DVDD
GND
GND
GND
GND
GND
DVDD
GND
GND
GND
GND
GND
TEST5
GND
GND
GND
GND
GND
RXD_C– RXD_C+
G
H
J
DDC_
SDA_RXD
NC
NC
CVDD
RXE_2–
RXE_1–
RXE_0–
RXE_C–
CVDD
CVDD
RXE_2+
RXE_1+
RXE_0+
RXE_C+
CVDD
TEST1
PCLK
AP_OUT_ AP_OUT_
MCLK
DDC_
SCL_RXE
TEST6
TEST8
TEST7
SCLK
DDC_
SDA_RXE
GND
GND
AUD_IN
K
L
AUD_IN_ AUD_IN_
SCLK
XTAL+
PVDD
GND
NC
XTAL–
PVDD
GND
NC
GND
RXE_HPA
RXE_5V
GND
LRCLK
TEST3
TEST2
GND
M
N
P
R
T
PVDD_TX PVDD_TX
GND
GND
GND
GND
TEST14
AVDD_TX
AVDD_TX
TEST10
HS
TEST4
TX_HPD_
ARC–
DDC_
SDA_TX
DDC_
SCL_TX
P9/AP_
IN_SCLK
P11/AP_ P13/AP_ P15/AP_
IN4 IN2 IN0
NC
NC
R_TX
GND
GND
GND
GND
TX_ARC+
GND
CEC
DVDDIO
EP_CS
P8/AP_
IN_MCLK
P10/AP_ P12/AP_ P14/AP_
IN5
NC
NC
TEST9
GND
AVDD_TX AVDD_TX DVDDIO EP_SCLK
DE
IN3
IN1
NC
NC
TEST11 PVDD_TX
TEST13 PVDD_TX
TX_C+
TX_0+
TX_1+
TX_2+
GND
EP_MOSI
P1
P3
P5
P7
GND
U
V
GND
1
GND
2
GND
3
TEST12
4
GND
7
TX_C–
8
TX_0–
9
TX_1–
10
TX_2–
11
GND
12
EP_MISO
13
P0
14
P2
15
P4
16
P6
17
GND
18
5
6
Figure 19. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Function
Description
A1
GND
Ground
Ground.
A2
A3
A4
A5
A6
A7
A8
A9
RXA_2+
RXA_1+
RXA_0+
RXA_C+
CVDD
RXB_2+
RXB_1+
RXB_0+
RXB_C+
CVDD
HDMI Rx input
HDMI Rx input
HDMI Rx input
HDMI Rx input
Power
HDMI Rx input
HDMI Rx input
HDMI Rx input
HDMI Rx input
Power
HDMI RxA Channel 2 True Input.
HDMI RxA Channel 1 True Input.
HDMI RxA Channel 0 True Input.
HDMI RxA Clock True Input.
Comparator Power Supply (1.8 V).
HDMI RxB Channel 2 True Input.
HDMI RxB Channel 1 True Input.
HDMI RxB Channel 0 True Input.
HDMI RxB Clock True Input.
A10
A11
A12
Comparator Power Supply (1.8 V).
HDMI RxC Channel 2 True Input.
RXC_2+
HDMI Rx input
Rev. 0 | Page 15 of 24
ADV7627
Data Sheet
Pin No.
A13
A14
A15
A16
A17
A18
B1
Mnemonic
RXC_1+
RXC_0+
RXC_C+
CVDD
RXC_5V
GND
Function
HDMI Rx input
HDMI Rx input
HDMI Rx input
Power
HDMI Rx input
Ground
Ground
Description
HDMI RxC Channel 1 True Input.
HDMI RxC Channel 0 True Input.
HDMI RxC Clock True Input.
Comparator Power Supply (1.8 V).
HDMI RxC 5 V Detect Pin.
Ground.
Ground.
GND
B2
B3
B4
B5
B6
B7
B8
B9
B10
B11
B12
B13
B14
B15
B16
B17
B18
C1
RXA_2−
RXA_1−
RXA_0−
RXA_C−
CVDD
RXB_2−
RXB_1−
RXB_0−
RXB_C−
CVDD
RXC_2−
RXC_1−
RXC_0−
RXC_C−
CVDD
RXC_HPA
GND
HDMI Rx input
HDMI Rx input
HDMI Rx input
HDMI Rx input
Power
HDMI Rx input
HDMI Rx input
HDMI Rx input
HDMI Rx input
Power
HDMI Rx input
HDMI Rx input
HDMI Rx input
HDMI Rx input
Power
HDMI RxA Channel 2 Complement Input.
HDMI RxA Channel 1 Complement Input.
HDMI RxA Channel 0 Complement Input.
HDMI RxA Clock Complement Input.
Comparator Power Supply (1.8 V).
HDMI RxB Channel 2 Complement Input.
HDMI RxB Channel 1 Complement Input.
HDMI RxB Channel 0 Complement Input.
HDMI RxB Clock Complement Input.
Comparator Power Supply (1.8 V).
HDMI RxC Channel 2 Complement Input.
HDMI RxC Channel 1 Complement Input.
HDMI RxC Channel 0 Complement Input.
HDMI RxC Clock Complement Input.
Comparator Power Supply (1.8 V).
HDMI RxC Hot Plug Assert.
Ground.
HDMI Rx output
Ground
Ground
GND
Ground.
C2
C3
C4
C5
CVDD
CVDD
TVDD
TVDD
GND
Power
Power
Power
Power
Comparator Power Supply (1.8 V).
Comparator Power Supply (1.8 V).
HDMI Rx Terminator Supply Voltage (3.3 V).
HDMI Rx Terminator Supply Voltage (3.3 V).
Ground.
C6
Ground
C7
GND
Ground
Ground.
C8
C9
TVDD
TVDD
GND
GND
TVDD
TVDD
GND
GND
Power
Power
Ground
Ground
Power
Power
Ground
Ground
Power
Ground
Ground
Control
HDMI Rx Terminator Supply Voltage (3.3 V).
HDMI Rx Terminator Supply Voltage (3.3 V).
Ground.
C10
C11
C12
C13
C14
C15
C16
C17
C18
D1
Ground.
HDMI Rx Terminator Supply Voltage (3.3 V).
HDMI Rx Terminator Supply Voltage (3.3 V).
Ground.
Ground.
CVDD
GND
GND
Comparator Power Supply (1.8 V).
Ground.
Ground.
Interrupt Output. This pin can be active low or high. When an
unmasked status bit changes, an interrupt is generated on this pin.
INT1
D2
D3
D4
D5
INT2
SCL
SDA
CS
Control
Interrupt Output. This pin can be active low or high. When an
unmasked status bit changes, an interrupt is generated on this pin.
I2C Clock Input. This pin is open drain; connect this pin to a 3.3 V supply
using a 4.7 kΩ resistor.
I2C Data Input. This pin is open drain; connect this pin to a 3.3 V supply
using a 4.7 kΩ resistor.
Chip Select Pin. This pin must be set low or left floating for the chip to
process I2C messages that are destined for the ADV7627. The ADV7627
ignores I2C messages when this pin is high.
I2C control
I2C control
Digital input
D6
RXA_5V
HDMI Rx input
HDMI RxA 5 V Detect Pin.
Rev. 0 | Page 16 of 24
Data Sheet
ADV7627
Pin No.
D7
D8
Mnemonic
Function
Description
RXA_HPA
DDC_SCL_RXA
DDC_SDA_RXA
DDC_SCL_RXB
DDC_SDA_RXB
RXB_HPA
RXB_5V
DDC_SDA_RXC
DDC_SCL_RXC
TVDD
HDMI Rx output
HDMI Rx DDC
HDMI Rx DDC
HDMI Rx DDC
HDMI Rx DDC
HDMI Rx output
HDMI Rx input
HDMI Rx DDC
HDMI Rx DDC
Power
HDMI Rx input
HDMI Rx input
Do not connect
Do not connect
I2C control
HDMI RxA Hot Plug Assert.
HDCP Slave Serial Clock for HDMI RxA.
HDCP Slave Serial Data for HDMI RxA.
HDCP Slave Serial Clock for HDMI RxB.
HDCP Slave Serial Data for HDMI RxB.
HDMI RxB Hot Plug Assert.
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
E1
HDMI RxB 5 V Detect Pin.
HDCP Slave Serial Data for HDMI RxC.
HDCP Slave Serial Clock for HDMI RxC.
HDMI Rx Terminator Supply Voltage (3.3 V).
HDMI RxD Channel 2 Complement Input.
HDMI RxD Channel 2 True Input.
Leave this pin floating.
RXD_2−
RXD_2+
NC
NC
E2
E3
Leave this pin floating.
ALSB
Pin to set the I2C address of the I/O register map for the device. When
the ALSB pin is tied low, the I/O register map I2C address is 0xB0. When
the ALSB pin is tied high, the I/O register map I2C address is 0xB2.
E4
RESET
Miscellaneous digital
HDMI Rx input
Power
Reset Pin.
E15
E16
E17
E18
F1
F2
F3
F4
F15
F16
F17
F18
G1
G2
G3
G4
G7
RXD_5V
TVDD
RXD_1−
RXD_1+
NC
HDMI RxD 5 V Detect Pin.
HDMI Rx Terminator Supply Voltage (3.3 V).
HDMI RxD Channel 1 Complement Input.
HDMI RxD Channel 1 True Input.
Leave this pin floating.
HDMI Rx input
HDMI Rx input
Do not connect
Do not connect
Audio output
Audio output
HDMI Rx output
Ground
HDMI Rx input
HDMI Rx input
Do not connect
Do not connect
Audio output
Audio output
Power
NC
Leave this pin floating.
AP_OUT0
AP_OUT1
RXD_HPA
GND
RXD_0−
RXD_0+
NC
Audio Output Port, Output 0.
Audio Output Port, Output 1.
HDMI RxD Hot Plug Assert.
Ground.
HDMI RxD Channel 0 Complement Input.
HDMI RxD Channel 0 True Input.
Leave this pin floating.
NC
Leave this pin floating.
AP_OUT2
AP_OUT3
DVDD
DVDD
DVDD
DVDD
DVDD
TEST5
DDC_SCL_RXD
GND
RXD_C−
RXD_C+
NC
Audio Output Port, Output 2.
Audio Output Port, Output 3.
Digital Power Supply (1.8 V).
Digital Power Supply (1.8 V).
Digital Power Supply (1.8 V).
Digital Power Supply (1.8 V).
Digital Power Supply (1.8 V).
Test Pin 5. Leave this pin floating.
HDCP Slave Serial Clock for HDMI RxD.
Ground.
G8
G9
Power
Power
Power
Power
G10
G11
G12
G15
G16
G17
G18
H1
H2
H3
H4
H7
Test pin
HDMI Rx DDC
Ground
HDMI Rx input
HDMI Rx input
Do not connect
Do not connect
Audio output
Audio output
Power
HDMI RxD Clock Complement Input.
HDMI RxD Clock True Input.
Leave this pin floating.
NC
Leave this pin floating.
AP_OUT4
AP_OUT5
DVDDIO
GND
Audio Output Port, Output 4.
Audio Output Port, Output 5.
Digital Interface Supply (3.3 V).
Ground.
H8
Ground
H9
GND
Ground
Ground.
H10
H11
GND
GND
Ground
Ground
Ground.
Ground.
Rev. 0 | Page 17 of 24
ADV7627
Data Sheet
Pin No.
H12
H15
H16
H17
H18
J1
J2
J3
J4
J7
Mnemonic
GND
DDC_SDA_RXD
GND
CVDD
CVDD
AP_OUT_MCLK
AP_OUT_SCLK
TEST6
TEST7
DVDDIO
GND
Function
Ground
HDMI Rx DDC
Ground
Power
Power
Audio output
Audio output
Test pin
Test pin
Power
Description
Ground.
HDCP Slave Serial Data for HDMI RxD.
Ground.
Comparator Power Supply (1.8 V).
Comparator Power Supply (1.8 V).
Audio Output Port, MCLK.
Audio Output Port, SCLK.
Connect this pin to ground using a 4.7 kΩ resistor.
Connect this pin to ground using a 4.7 kΩ resistor.
Digital Interface Supply (3.3 V).
Ground.
J8
Ground
J9
GND
Ground
Ground.
J10
J11
J12
J15
J16
J17
J18
K1
GND
GND
GND
DDC_SCL_RXE
TVDD
RXE_2−
RXE_2+
GND
Ground
Ground
Ground
HDMI Rx DDC
Power
HDMI Rx input
HDMI Rx input
Ground
Ground.
Ground.
Ground.
HDCP Slave Serial Clock for HDMI RxE.
HDMI Rx Terminator Supply Voltage (3.3 V).
HDMI RxE Channel 2 Complement Input.
HDMI RxE Channel 2 True Input.
Ground.
K2
GND
Ground
Ground.
K3
K4
K7
TEST8
AUD_IN
GND
Test pin
Audio input
Ground
Connect this pin to ground using a 4.7 kΩ resistor.
Audio Input Port, I2S or S/PDIF Input.
Ground.
K8
GND
Ground
Ground.
K9
GND
Ground
Ground.
K10
K11
K12
K15
K16
K17
K18
L1
L2
L3
L4
L7
GND
GND
GND
DDC_SDA_RXE
TVDD
RXE_1−
RXE_1+
XTAL+
XTAL−
AUD_IN_SCLK
AUD_IN_LRCLK
GND
Ground
Ground
Ground
HDMI Rx DDC
Power
HDMI Rx input
HDMI Rx input
Miscellaneous digital
Miscellaneous digital
Audio input
Audio input
Ground
Ground.
Ground.
Ground.
HDCP Slave Serial Data for HDMI RxE.
HDMI Rx Terminator Supply Voltage (3.3 V).
HDMI RxE Channel 1 Complement Input.
HDMI RxE Channel 1 True Input.
ADV7627 Crystal Input.
ADV7627 Crystal Output.
Audio Input Port, SCLK.
Audio Input Port, LRCLK.
Ground.
L8
GND
Ground
Ground.
L9
GND
Ground
Ground.
L10
L11
L12
L15
L16
L17
L18
M1
M2
M3
M4
M7
M8
GND
GND
GND
RXE_HPA
GND
RXE_0−
RXE_0+
PVDD
PVDD
TEST3
Ground
Ground
Ground
HDMI Rx output
Ground
HDMI Rx input
HDMI Rx input
Power
Power
Test pin
Ground.
Ground.
Ground.
HDMI RxE Hot Plug Assert.
Ground.
HDMI RxE Channel 0 Complement Input.
HDMI RxE Channel 0 True Input.
PLL Digital Supply (1.8 V).
PLL Digital Supply (1.8 V).
Test Pin 3. Leave this pin floating.
Test Pin 2. Leave this pin floating.
Ground.
TEST2
GND
GND
Test pin
Ground
Ground
Ground.
Rev. 0 | Page 18 of 24
Data Sheet
ADV7627
Pin No.
M9
Mnemonic
Function
Ground
Description
GND
Ground.
M10
M11
M12
M15
M16
M17
M18
N1
GND
GND
GND
RXE_5V
GND
RXE_C−
RXE_C+
GND
Ground
Ground
Ground
HDMI Rx input
Ground
HDMI Rx input
HDMI Rx input
Ground
Ground.
Ground.
Ground.
HDMI RxE 5 V Detect Pin.
Ground.
HDMI RxE Clock Complement Input.
HDMI RxE Clock True Input.
Ground.
N2
GND
Ground
Ground.
N3
N4
PVDD_TX
PVDD_TX
GND
Power
Power
Ground
Ground
Power
Power
Do not connect
Do not connect
Ground
HDMI Tx PLL Power Supply (1.8 V).
HDMI Tx PLL Power Supply (1.8 V).
Ground.
N15
N16
N17
N18
P1
GND
Ground.
CVDD
CVDD
NC
NC
GND
Comparator Power Supply (1.8 V).
Comparator Power Supply (1.8 V).
Leave this pin floating.
Leave this pin floating.
Ground.
P2
P3
P4
TEST14
HS
VS
TEST4
TEST1
NC
Test pin
Connect this pin to ground using a 4.7 kΩ resistor.
Horizontal Synchronization for Pixel Port Input Video.
Vertical Synchronization for Pixel Port Input Video.
Test Pin 4. Leave this pin floating.
Test Pin 1. Leave this pin floating.
Leave this pin floating.
Leave this pin floating.
Ground.
P15
P16
P17
P18
R1
Pixel port input sync
Pixel port input sync
Test pin
Test pin
Do not connect
Do not connect
Ground
R2
R3
NC
GND
R4
R5
AVDD_TX
TX_HPD_ARC−
Power
HDMI Tx input
HDMI Tx Analog Supply (1.8 V).
HDMI Tx Hot Plug Detect (HPD) Signal and Audio Return Channel
Complement Input.
R6
R_TX
HDMI Tx input
This pin sets the internal reference currents for HDMI Tx. Place a 470 Ω
resistor (1% tolerance) between this pin and GND. Place the external
resistor as close as possible to the ADV7627.
R7
GND
Ground
Ground.
R8
R9
TX_ARC+
DDC_SDA_TX
DDC_SCL_TX
CEC
DVDDIO
EP_CS
HDMI Tx input
HDMI Tx DDC
HDMI Tx DDC
HDMI Tx CEC
HDMI Tx Audio Return Channel True Input.
HDCP Slave Serial Data for HDMI Tx.
HDCP Slave Serial Clock for HDMI Tx.
HDMI Tx Consumer Electronics Control (CEC).
Digital Interface Supply (3.3 V).
SPI Chip Select Interface for the OSD.
Pixel Port Input P9/Audio Input Port, SCLK.
Pixel Port Input P11/Audio Input Port, Input 4.
Pixel Port Input P13/Audio Input Port, Input 2.
Pixel Port Input P15/Audio Input Port, Input 0.
Pixel Clock for Pixel Port Input Video.
Leave this pin floating.
R10
R11
R12
R13
R14
R15
R16
R17
R18
T1
Power
Serial port control
Pixel port input/audio input
Pixel port input/audio input
Pixel port input/audio input
Pixel port input/audio input
Pixel port input clock
Do not connect
Do not connect
Ground
P9/AP_IN_SCLK
P11/AP_IN4
P13/AP_IN2
P15/AP_IN0
PCLK
NC
NC
GND
T2
T3
Leave this pin floating.
Ground.
T4
T5
T6
AVDD_TX
TEST9
GND
Power
Test pin
Ground
HDMI Tx Analog Supply (1.8 V).
Connect this pin to ground using a 4.7 kΩ resistor.
Ground.
T7
GND
Ground
Ground.
T8
GND
Ground
Ground.
T9
GND
Ground
Ground.
Rev. 0 | Page 19 of 24
ADV7627
Data Sheet
Pin No.
T10
T11
T12
T13
T14
T15
T16
T17
T18
U1
Mnemonic
AVDD_TX
AVDD_TX
DVDDIO
EP_SCLK
P8/AP_IN_MCLK
P10/AP_IN5
P12/AP_IN3
P14/AP_IN1
DE
Function
Description
Power
Power
Power
HDMI Tx Analog Supply (1.8 V).
HDMI Tx Analog Supply (1.8 V).
Digital Interface Supply (3.3 V).
SPI Clock Interface for the OSD.
Pixel Port Input P8/Audio Input Port, MCLK.
Pixel Port Input P10/Audio Input Port, Input 5.
Pixel Port Input P12/Audio Input Port, Input 3.
Pixel Port Input P14/Audio Input Port, Input 1.
Data Enable for Pixel Port Input Video.
Leave this pin floating.
Serial port control
Pixel port input/audio input
Pixel port input/audio input
Pixel port input/audio input
Pixel port input/audio input
Pixel port input sync
Do not connect
Do not connect
Ground
NC
NC
GND
U2
U3
Leave this pin floating.
Ground.
U4
U5
U6
U7
TEST10
TEST11
PVDD_TX
GND
Test pin
Test pin
Power
Ground
Connect this pin to ground using a 4.7 kΩ resistor.
Connect this pin to ground using a 4.7 kΩ resistor.
HDMI Tx PLL Power Supply (1.8 V).
Ground.
U8
U9
TX_C+
TX_0+
TX_1+
TX_2+
GND
EP_MOSI
P1
P3
P5
P7
GND
GND
HDMI Tx output
HDMI Tx output
HDMI Tx output
HDMI Tx output
Ground
Serial port control
Pixel port input
Pixel port input
Pixel port input
Pixel port input
Ground
HDMI Tx Clock True Output.
HDMI Tx Channel 0 True Output.
HDMI Tx Channel 1 True Output.
HDMI Tx Channel 2 True Output.
Ground.
SPI Master Output/Slave Input for OSD.
Pixel Port Input P1.
Pixel Port Input P3.
Pixel Port Input P5.
Pixel Port Input P7.
Ground.
Ground.
U10
U11
U12
U13
U14
U15
U16
U17
U18
V1
Ground
V2
GND
Ground
Ground.
V3
GND
Ground
Ground.
V4
V5
V6
V7
TEST12
TEST13
PVDD_TX
GND
Test pin
Test pin
Power
Ground
Connect this pin to ground using a 4.7 kΩ resistor.
Connect this pin to ground using a 4.7 kΩ resistor.
HDMI Tx PLL Power Supply (1.8 V).
Ground.
V8
V9
TX_C−
TX_0−
TX_1−
TX_2−
GND
EP_MISO
P0
P2
HDMI Tx output
HDMI Tx output
HDMI Tx output
HDMI Tx output
Ground
Serial port control
Pixel port input
Pixel port input
Pixel port input
Pixel port input
Ground
HDMI Tx Clock Complement Output.
HDMI Tx Channel 0 Complement Output.
HDMI Tx Channel 1 Complement Output.
HDMI Tx Channel 2 Complement Output.
Ground.
SPI Master Input/Slave Output for OSD.
Pixel Port Input P0.
Pixel Port Input P2.
V10
V11
V12
V13
V14
V15
V16
V17
V18
P4
P6
GND
Pixel Port Input P4.
Pixel Port Input P6.
Ground.
Rev. 0 | Page 20 of 24
Data Sheet
ADV7627
POWER SUPPLY RECOMMENDATIONS
POWER-UP SEQUENCE
3.3V
The power-up sequence for the ADV7627 is as follows:
RESET
0V
RESET
1. Hold the
pin low.
1.8V
2. Power up the 3.3 V supplies (DVDDIO and TVDD).
3. After the 3.3 V supplies reach their minimum recommended
value of 3.14 V, wait at least 20 ms before powering up the
1.8 V supplies.
1.8V
SUPPLY
0V
3.3V
3.14V
4. Power up the 1.8 V supplies (AVDD_TX, CVDD, DVDD,
PVDD, and PVDD_TX). These supplies should be powered
up at the same time; that is, there should be a difference of
less than 0.3 V between them.
3.3V
SUPPLY
tPSS ≥ 20ms
RESET > 5ms
0V
Figure 20. ADV7627 Supply Power-Up Sequence
RESET
5. Release the
pin after all supplies are established.
POWER-DOWN SEQUENCE
After power-up, a complete reset is recommended. This reset
can be performed by the system microcontroller.
The ADV7627 supplies can be deasserted simultaneously as
long as DVDDIO or TVDD does not fall below a lower rated
supply.
Rev. 0 | Page 21 of 24
ADV7627
Data Sheet
THEORY OF OPERATION
HDMI RECEIVER
ON-SCREEN DISPLAY
The ADV7627 front end incorporates a 5:1 multiplexed HDMI
receiver capable of receiving all HDTV formats up to 3 GHz
(4k × 2k at 24 Hz/25 Hz/30 Hz). The HDMI receiver also sup-
ports HDMI features including 3D TV and content type bits.
A key feature of the ADV7627 is the on-chip character- and
icon-based OSD generator. The generated OSD can be converted
to match the 4:2:2 or 4:4:4 input format in either the RGB or
YCrCb color spaces. After the OSD is generated, it is overlaid
at the output resolution (any video resolution up to 4k × 2k at
24 Hz/25 Hz/30 Hz) for best performance. The OSD portion of
the image is optionally semitransparent using a 5-bit alpha blend
between the input video and the OSD. The OSD font characters
and icons can be stored in external SPI flash memory, read directly
into RAM, or they can be loaded into the on-chip RAM via the
SPI or I2C interface.
The HDMI receiver in the ADV7627 incorporates an adaptive
equalizer, which compensates for the high frequency losses
inherent in HDMI and DVI cabling, especially at longer lengths
and higher frequencies.
The ADV7627 features a 768-byte internal EDID memory space,
which can be used to store two independent EDIDs. The memory
can be partitioned to provide two 256-byte EDIDs or one 512-
byte extended EDID and one 256-byte EDID. Either EDID can
be replicated on any input port.
PIXEL PORT INPUT
The ADV7627 features a 16-bit pixel input port that facilitates
the reception of digital video data from an analog front-end video
decoder such as the ADV7180, ADV7181D, or ADV7842. Both
embedded timing and external synchronization signals are
supported on the pixel port. The pixel port input also features
an interlaced-to-progressive converter for 480i or 576i inputs.
The HDMI receiver offers advanced audio functionality. The
receiver supports multichannel I2S audio for up to eight channels.
The receiver also supports a six-DSD channel interface, with each
channel carrying an oversampled 1-bit representation of the audio
signal as delivered on SACD. The ADV7627 can also receive
HBR audio packet streams and output them through the HBR
interface in an S/PDIF format that conforms to the IEC 60958
standard. S/PDIF is supported via the HPD back channel. The
receiver also contains an audio mute controller that can detect a
variety of conditions that can result in audible extraneous noise
in the audio output. On detection of these conditions, the audio
data can be ramped to prevent audio clicks or pops.
HDMI TRANSMITTER
The ADV7627 incorporates an HDMI transmitter, which supports
all HDTV formats up to 3 GHz (4k × 2k at 24 Hz/25 Hz/30 Hz),
ARC, and all mandatory 3D TV formats. The HDMI transmitter
can output any audio mode received from the HDMI receiver,
including audio sample packets, HBR, or DSD.
The ARC receiver supports both single-ended and differential
modes and simplifies cabling by combining an upstream audio
capability in a conventional HDMI cable. The transmitter features
an on-chip MPU with an I2C master to perform HDCP opera-
tions and EDID read operations.
HDCP REPEATER FUNCTIONALITY
With the inclusion of HDCP 1.4, displays can receive encrypted
video content. The HDMI interface of the ADV7627 allows
authentication of a video receiver, decryption of encoded data at
the receiver, and renewability of that authentication during trans-
mission, as specified by the HDCP 1.4 protocol. Repeater support
is also offered by the ADV7627.
I2C INTERFACE
The ADV7627 supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. The ADV7627
is controlled by an external I2C master device, such as a micro-
controller.
DIGITAL AUDIO PORTS
The ADV7627 features an audio input port and an audio output
port. The audio input and output ports provide comprehensive
muxing support for the destination of the audio (for example, to
the HDMI transmitter or audio output port) and support for the
source of the audio (for example, from the HDMI receiver or from
the audio input port). The extracted audio can be processed by
a SHARC® processor and can be reinserted back into the HDMI
output stream or output via the hardware connected to the system.
OTHER FEATURES
Other features of the ADV7627 include the following:
•
Fully qualified software low level libraries, driver, and
application
•
•
Complete input and output audio support
Programmable interrupt request output pins: INT1
and INT2
The pins for the pixel port input signals (P15 to P8) are shared
with the AP_IN audio input port. When the pixel port input is in
use, the AUD_IN port can be used to provide stereo audio input.
•
•
Chip select and ALSB
Low power consumption: 1.8 V digital core, 1.8 V analog,
and 3.3 V digital input/output
•
•
Temperature range: 0°C to 70°C
15 mm × 15 mm, Pb-free, 260-ball CSP_BGA
Rev. 0 | Page 22 of 24
Data Sheet
ADV7627
OUTLINE DIMENSIONS
15.10
15.00 SQ
14.90
A1 BALL
CORNER
A1 BALL
CORNER
18 16 14 12 10
17 15 13 11
8
6
4
2
9
7
5
3
1
A
B
C
D
F
E
13.60
BSC SQ
G
H
J
L
0.80
BSC
K
M
P
T
N
R
U
V
TOP VIEW
DETAIL A
BOTTOM VIEW
DETAIL A
1.11
1.01
0.91
1.50
1.36
1.21
0.35 NOM
0.30 MIN
0.50
0.45
0.40
COPLANARITY
0.20
SEATING
PLANE
BALL DIAMETER
COMPLIANT TO JEDEC STANDARDS MO-275-KKAB-1.
Figure 21. 260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
(BC-260-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1, 2
Temperature Range
Package Description
Package Option
ADV7627KBCZ-8
ADV7627KBCZ-8-RL
EVAL-ADV7625-SMZ
0°C to 70°C
0°C to 70°C
260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Evaluation Board
BC-260-1
BC-260-1
1 Z = RoHS Compliant Part.
2 This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to
purchase any components with internal HDCP keys.
Rev. 0 | Page 23 of 24
ADV7627
NOTES
Data Sheet
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries.
©2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11833-0-12/13(0)
Rev. 0 | Page 24 of 24
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