ADV7625KBCZ-8-RL_技术文档

3 GHz HDMI 5:2 Crosspoint Transceiver

with On-Screen Display

ADV7625

Data Sheet

2 independent HDMI transmitters

FEATURES

3 GHz support on all outputs

EDID data extraction

Hot Plug detect (HPD) inputs

Audio return channel (ARC) receiver per transmitter

3 GHz color space converter (CSC) per transmitter

Audio

5-input, 2-output crosspoint HDMI transceiver

HDMI support

3 GHz video support (up to 4k × 2k)

Audio return channel (ARC)

3D TV support

Content type bits

HDMI-compatible audio interface

CEC 1.4-compatible

2 independent 8-channel audio extraction ports

2 independent 8-channel audio insertion ports

S/PDIF (IEC 60958-compatible) digital audio input/output

Super Audio CD® (SACD) with DSD input/output interface

High bit rate (HBR) audio

Dolby® TrueHD

DTS-HD Master Audio™

Full audio input and output support

General

Interrupt controller

Standard identification (STDI) circuit

Software libraries, driver, and application available

Extended colorimetry

Character- and icon-based on-screen display (OSD)

3D OSD overlay on all mandatory 3D formats

Support for OSD overlay on 3 GHz video formats

High-bandwidth Digital Content Protection (HDCP 1.4)

HDCP repeater support: up to 127 KSVs supported

300 MHz maximum TMDS clock frequency (up to 4k × 2k)

48-/36-/30-bit Deep Color input modes supported

Ultralow jitter digital PLL (100% deskew)

TTL pixel port input

Allows digital video input to facilitate analog video support

Interlaced-to-progressive converter

2 independent HDMI receivers for 5 input ports

3 GHz support on all inputs

Adaptive equalizer for cable lengths up to 30 meters

Flexible internal EDID RAM supports dual EDIDs

Replication of either dual EDID on any input port

5 V detect inputs

APPLICATIONS

AVR

Soundbar with HDMI repeater support

Matrix switch

Other repeater applications

Hot Plug assert control outputs

FUNCTIONAL BLOCK DIAGRAM

ADV7625

CEC A

HDCP

TMDS

DDC

HDCP

HDMI_RX_A

HDMI_RX_B

HDMI_RX_C

HDMI_RX_D

HDMI_RX_E

TMDS

DDC

TMDS

DDC

HDMI_TX_A

HDMI_TX_B

ARC

5:2

CROSSPOINT

MUX

TMDS

DDC

CP-LITEs

OSD

HDMI TXs

HDMI RXs

HDCP

TMDS

DDC

TMDS

DDC

ARC

TMDS

DDC

CEC B

RX EDID WITH

REPLICATOR

DIGITAL AUDIO

OUTPUT PORTS

DIGITAL AUDIO

INPUT PORTS

PIXEL PORT

INPUT

TX EDID/HDCP

CONTROLLER

2

INTERRUPTS

I C

SPI

Figure 1.

Rev. 0

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rightsof third parties that may result fromits use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks andregisteredtrademarks are the property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

ADV7625

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Power Supply Recommendations................................................. 22

Power-Up Sequence ................................................................... 22

Power-Down Sequence.............................................................. 22

Theory of Operation ...................................................................... 23

HDMI Receivers......................................................................... 23

HDCP Repeater Functionality ................................................. 23

Digital Audio Ports .................................................................... 23

On-Screen Display ..................................................................... 23

Pixel Port Input........................................................................... 23

HDMI Transmitters ................................................................... 23

I²C Interface ................................................................................ 23

Other Features ............................................................................ 23

Outline Dimensions....................................................................... 24

Ordering Guide .......................................................................... 24

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 2

General Description ......................................................................... 3

Detailed Functional Block Diagram .............................................. 4

Specifications..................................................................................... 5

Digital, HDMI, and AC Specifications...................................... 5

Data and I²C Timing Characteristics......................................... 6

Power Specifications .................................................................. 13

Absolute Maximum Ratings.......................................................... 15

Package Thermal Performance................................................. 15

ESD Caution................................................................................ 15

Pin Configuration and Function Descriptions........................... 16

REVISION HISTORY

12/13—Revision 0: Initial Version

Rev. 0 | Page 2 of 24

Data Sheet

ADV7625

GENERAL DESCRIPTION

The ADV7625 is a high performance, five-input, dual-output,

High-Definition Multimedia Interface (HDMI®) transceiver

with crosspoint and splitter capabilities. The ADV7625 supports

3 GHz video and features two independent HDMI receivers, two

independent HDMI transmitters, two audio output ports, two

audio input ports, and a pixel port input. The ADV7625 supports

all HDCP repeater functions through fully tested Analog Devices,

Inc., repeater software libraries and drivers.

The ADV7625 offers two audio output ports and two audio input

ports. Each audio port supports the extraction and insertion of up

to eight channels of audio data out of or into the HDMI streams.

HDMI audio formats, including I²S, S/PDIF, direct stream digital

(DSD), and high bit rate (HBR) audio are supported.

The ADV7625 features a TTL pixel port input that facilitates the

reception of digital video data from an analog front-end decoder

(for example, the ADV7180, ADV7181D, or ADV7842).

The HDMI receivers and transmitters in the ADV7625 support

the reception and transmission of 3 GHz video formats up to 4k ×

2k at 24 Hz/25 Hz/30 Hz, in addition to all mandatory HDMI 3D

TV formats. The receivers and transmitters also provide support

for THX® Media Director™.

The ADV7625 has an integrated on-screen display (OSD)

generator that enables the creation and control of high quality

character- and icon-based system status and control displays.

The OSD can be overlaid on 3 GHz video formats and 3D video.

Customers who are interested in using OSD are provided with

Blimp, the Analog Devices OSD development tool.

Each HDMI receiver features an integrated equalizer that ensures

robust operation of the interface with cable lengths up to 30 meters.

The HDMI receivers share a 768-byte volatile extended display

identification data (EDID) memory, which can facilitate one or two

EDIDs, one for each receiver. Each HDMI port features dedicated

5 V detect and Hot Plug™ assert pins.

The ADV7625 is provided in a space-saving, 260-ball, 15 mm ×

15 mm CSP_BGA surface-mount, RoHS-compliant package and

is specified over the 0°C to 70°C temperature range.

Each HDMI transmitter supports audio return channel (ARC)

and features an integrated HDMI CEC controller that supports

capability discovery and control (CDC).

Rev. 0 | Page 3 of 24

ADV7625

Data Sheet

DETAILED FUNCTIONAL BLOCK DIAGRAM

0 0 2 1 1 8

P

H D C

D C M

C S

P

H D C

D C M

C S

C

INT1

INT2

AP2_IN_MCLK*

AP2_IN_SCLK*/AUD2_IN_SCLK

AP2_IN5*/AUD2_IN_LRCLK

AP2_IN0*/AUD2_IN

K*

AP1_IN_MCL

N_SCLK

N_LRCLK

K*/AUD1_I

AP1_IN_SCL

AP1_IN5*/AUD1_I

EP_MOSI

EP_MISO

EP_SCLK

EP_CS

N

AP1_IN0*/AUD1_I

AP2_OUT_MCLK

AP2_OUT_SCLK

AP2_OUT5

AP2_OUT0

TXB_ARC+

TXB_HPD_ARC–

TXA_ARC+

PCLK

DE

VS

TXA_HPD_ARC–

HS

P0*

AP1_OUT_MCLK

AP1_OUT_SCLK

AP1_OUT5

P15*

AP1_OUT0

P

H D C

P

H D C

CS

ALSB

SDA

SCL

Figure 2. Detailed Functional Block Diagram

Rev. 0 | Page 4 of 24

Data Sheet

ADV7625

SPECIFICATIONS

AVDD_TXA = 1.8 V 5%, AVDD_TXB = 1.8 V 5%, CVDD = 1.8 V 5%, DVDD = 1.8 V 5%, DVDDIO = 3.3 V 5%,

PVDD = 1.8 V 5%, PVDD_TXA = 1.8 V 5%, PVDD_TXB = 1.8 V 5%, TVDD = 3.3 V 5%, T_MINto T_MAX= 0°C to 70°C.

DIGITAL, HDMI, AND AC SPECIFICATIONS

Table 1.

Parameter

Test Conditions/Comments

Min

2

Typ

Max

Unit

DIGITAL INPUTS

Input High Voltage (V_IH)

Input Low Voltage (V_IL)

Input Leakage Current (I_IN)

Input Capacitance (C_IN)

DIGITAL INPUTS (5 V TOLERANT)¹

Input High Voltage (V_IH)

Input Low Voltage (V_IL)

Input Leakage Current (I_IN)

V

µA

pF

0.8

+60

20

−60

2.85

V

µA

0.8

+450

+60

RXA_5V, RXB_5V, RXC_5V, RXD_5V, RXE_5V

All other 5 V tolerant digital inputs

−450

−60

DIGITAL OUTPUTS

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

High Impedance Leakage Current (I_LEAK

2.4

V

µA

pF

0.4

20

)

10

Output Capacitance (C_OUT

)

DIGITAL OUTPUTS (5 V TOLERANT)²

Output High Voltage (V_OH)

Output Low Voltage (V_OL)

AC SPECIFICATIONS

4.85

V

0.4

TMDS Input Clock Range

TMDS Output Clock Frequency

25

300

MHz

¹The following pins are 5 V tolerant inputs: DDC_SCL_RXA, DDC_SDA_RXA, DDC_SCL_RXB, DDC_SDA_RXB, DDC_SCL_RXC, DDC_SDA_RXC, DDC_SCL_RXD,

DDC_SDA_RXD, DDC_SCL_RXE, DDC_SDA_RXE, RXA_5V, RXB_5V, RXC_5V, RXD_5V, RXE_5V, CEC_A, DDC_SCL_TXA, DDC_SDA_TXA, TXA_HPD_ARC−, TXA_ARC+,

CEC_B, DDC_SCL_TXB, DDC_SDA_TXB, TXB_HPD_ARC−, and TXB_ARC+.

²The following pins are 5 V tolerant outputs: RXA_HPA, RXB_HPA, RXC_HPA, RXD_HPA, and RXE_HPA.

Rev. 0 | Page 5 of 24

ADV7625

Data Sheet

DATA AND I²C TIMING CHARACTERISTICS

Table 2.

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

VIDEO SYSTEM CLOCK AND XTAL

Crystal Nominal Frequency

Crystal Frequency Stability

External Clock Source

27.0

MHz

ppm

50

External crystal must operate

at 1.8 V

Input High Voltage

Input Low Voltage

V_IH

V_IL

XTAL driven with external

clock source

XTAL driven with external

clock source

1.2

V

0.4

V

Pixel Port Input Clock Frequency

Range

Interlaced-to-progressive

converter not enabled

Interlaced-to-progressive

13.5

148.5

13.5

MHz

converter enabled (480i, 576i)

Serial Port EP_SCLK Frequency

Audio SCLK Frequency

Audio MCLK Frequency

Audio DSD Clock Frequency

RESET FEATURE

27

MHz

49.152

98.304

5.6448

Reset Pulse Width

5

ms

I²C PORTS (FAST MODE)

xCL Frequency¹

400

kHz

ns

µs

ns

µs

xCL Minimum Pulse Width High¹

xCL Minimum Pulse Width Low¹

Start Condition Hold Time

Start Condition Setup Time

xDA Setup Time²

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

600

1.3

600

100

xCL and xDA Rise Time^{1, 2}

xCL and xDA Fall Time^{1, 2}

Setup Time (Stop Condition)

SERIAL PORT, MASTER MODE^{3, 4}

300

0.6

SPI Mode 0

t₉, t₁₀

1 × EP_SCLK

periods

1.5 × EP_SCLK ns

periods

EP_CS Falling Edge to EP_SCLK

Rising/Falling Edge

EP_SCLK Rising/Falling Edge

to EP_CS Rising Edge

t₁₁, t₁₂

1 × EP_SCLK

periods

1.5 × EP_SCLK ns

periods

EP_CS Pulse Width⁵

t₁₃

t₁₄

1000

40

ns

EP_SCLK High Time

60

0

% duty

cycle

% duty

cycle

EP_SCLK Low Time

40

EP_MOSI Start of Data Invalid

to EP_SCLK Falling Edge

EP_CS Start of Data Invalid to

EP_SCLK Falling Edge

EP_SCLK Falling Edge to EP_MOSI

End of Data Invalid

EP_SCLK Falling Edge to EP_CS

End of Data Invalid

t₁₅

t₁₆

t₁₇

t₁₈

ns

0

2.15

EP_MISO Setup Time

Valid regardless of the

EP_SCLK active edge used

Valid regardless of the

7.5

0

EP_MISO Hold Time

EP_SCLK active edge used

Rev. 0 | Page 6 of 24

Data Sheet

ADV7625

Parameter

SERIAL PORT, SLAVE MODE^{3, 4}

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

SPI Mode 0

t₂₀

t₂₂

t₂₃

t₂₄

10

ns

EP_CS Falling Edge to EP_SCLK

Rising Edge

Final EP_SCLK Rising Edge to EP_CS

Rising Edge

EP_CS Pulse Width⁵

EP_SCLK High Time

EP_SCLK Low Time

20 × EP_SCLK

periods

45

55

% duty

cycle

% duty

cycle

EP_MOSI Setup Time

EP_MOSI Hold Time

EP_SCLK Falling Edge to EP_MISO

Start of Data Invalid

t₂₅

t₂₆

t₂₇

0.5

1.4

5.5

ns

EP_SCLK Falling Edge to EP_MISO

End of Data Invalid

t₂₈

9

ns

VIDEO DATA AND CONTROL INPUTS

PCLK High Time⁵

t₂₉

0.45 to 0.55 ×

PCLK period

0.45 to 0.55 ×

PCLK period

% duty

cycle

% duty

cycle

PCLK Low Time⁵

Pixel Port Input, Setup Time,

SDR and DDR Modes

Pixel Port Input, Hold Time,

SDR and DDR Modes

Pixel Port Input, Setup Time,

DDR Mode

Pixel Port Input, Hold Time,

DDR Mode

t₃₀

t₃₁

t₃₂

t₃₃

Data latched on rising edge

Data latched on falling edge

1.0

1.4

1.0

1.4

ns

AUDIO INPUT PORTS, I²S INPUT

APx_IN_SCLK High Time

t₃₇

45

55

% duty

cycle

% duty

cycle

APx_IN_SCLK Low Time

APx_IN Data Setup Time

APx_IN Data Hold Time

AUDx_IN_SCLK High Time

t₃₈

t₃₉

t₃₇

2.3

1.6

45

ns

% duty

cycle

% duty

cycle

55

AUDx_IN_SCLK Low Time

45

AUDx_IN Data Setup Time

AUDx_IN Data Hold Time

t₃₈

t₃₉

1.0

3.5

ns

AUDIO INPUT PORTS, DSD INPUT

APx_IN_SCLK High Time

t₄₀

45

55

% duty

cycle

% duty

cycle

APx_IN_SCLK Low Time

APx_IN DSD Data Setup Time

APx_IN DSD Data Hold Time

AUDIO OUTPUT PORTS, I²S OUTPUT

APx_OUT_SCLK High Time

t₄₁

t₄₂

2.3

1.6

ns

t₄₆

45

55

10

% duty

cycle

% duty

cycle

APx_OUT_SCLK Low Time

APx_OUT LRCLK Transition Time

t₄₇

t₄₈

Start of invalid LRCLK to falling

APx_OUT_SCLK edge

Falling APx_OUT_SCLK edge

to end of invalid LRCLK

ns

Rev. 0 | Page 7 of 24

ADV7625

Data Sheet

Parameter

Symbol

Test Conditions/Comments

Min

Typ

Max

Unit

APx_OUT Data Transition Time

t₄₉

Start of invalid data to falling

APx_OUT_SCLK edge

10

ns

APx_OUT Data Transition Time

t₅₀

Falling APx_OUT_SCLK edge

to end of invalid data

10

ns

AUDIO OUTPUT PORTS, DSD OUTPUT

APx_OUT_SCLK High Time

t₅₁

45

55

10

% duty

cycle

% duty

cycle

APx_OUT_SCLK Low Time

APx_OUT DSD Data Transition Time

t₅₂

t₅₃

Start of invalid data to falling

APx_OUT_SCLK edge

Falling APx_OUT_SCLK edge

to end of invalid data

ns

¹xCL refers to SCL, DDC_SCL_RXA, DDC_SCL_RXB, DDC_SCL_RXC, DDC_SCL_RXD, and DDC_SCL_RXE.

²xDA refers to SDA, DDC_SDA_RXA, DDC_SDA_RXB, DDC_SDA_RXC, DDC_SDA_RXD, and DDC_SDA_RXE.

³SPI Mode 0 only.

⁴All serial port measurements are for CPHA = 0, CPOL = 0 (clock is low in idle state; negative edge of clock is used to transmit data and positive edge is used to sample data).

⁵Measurements guaranteed by design only.

Timing Diagrams

t₃

t₅

t₃

xDA

xCL

t₆

t₁

t₂

t₇

t₄

t₈

Figure 3. I²C Timing

t₁₃

t₉

t₁₁

t₁₂

t₁₀

EP_CS

EP_SCLK

INSTRUCTION

(0x0B)

24-BIT

ADDRESS

DUMMY BYTE

EP_MOSI

23 22 21 ...

3

2

1

0

7

6

5

4

3

2

1

0

DATA OUT 2

DATA OUT 1

EP_MISO

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

Figure 4. Detailed SPI Master Timing Diagram (SPI Mode 0, CPOL = CPHA = 0)

t₁₄

t₁₇

t₁₅

t₁₈

t₁₆

EP_SCLK

EP_MOSI

EP_CS

EP_MISO

(FALLING EDGE CAPTURE)

EP_MISO

(RISING EDGE CAPTURE)

Figure 5. SPI Master Mode Timing (SPI Mode 0)

Rev. 0 | Page 8 of 24

Data Sheet

ADV7625

t₂₃

t₂₂

t₂₀

EP_CS

EP_SCLK

W/R

0

DEVICE ADDRESS

SUBADDRESS

DATA IN 0

DATA IN 1

7

6

5

4

3

2

1

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

7

6

5

4

3

2

1

0

EP_MOSI

DUMMY BYTE

DATA OUT 0

DELAY MODE 1

EP_MISO

5

4

3

2

DATA OUT 0

DATA OUT 1

DELAY MODE 0

EP_MISO

7

6

5

4

3

2

1

0

5

4

3

2

Figure 6. Detailed SPI Slave Timing Diagram (SPI Mode 0, CPOL = CPHA = 0)

t₂₈

t₂₄

t₂₅

t₂₆

t₂₇

EP_SCLK

EP_MOSI

EP_MISO

Figure 7. SPI Slave Mode Timing (SPI Mode 0)

t₂₉

t₃₀

t₃₁

PCLK

P[15:0]

HS

VS

DE

Figure 8. Pixel Port Input, Noninterleaved SDR Video Data and Control Timing

t₂₉

PCLK

t₃₂

t₃₁

t₃₃

t₃₀

P[15:0]

HS

VS

DE

Figure 9. Pixel Port Input, Noninterleaved DDR Video Data and Control Timing

Rev. 0 | Page 9 of 24

ADV7625

Data Sheet

t₃₇

SCLK

t₃₈

t₃₉

I2S[3:0]

LRCLK

2

AUDIO INPUT PORTS I S SIGNAL ASSIGNMENT

INPUT PORT

SCLK

LRCLK

I2S[3:0]

AUD1_IN

AUD2_IN

AP1_IN

AUD1_IN_SCLK

AUD2_IN_SCLK

AP1_IN_SCLK

AP2_IN_SCLK

AUD1_IN_LRCLK

AUD2_IN_LRCLK

AP1_IN5

AUD1_IN (I2S0 ONLY)

AUD2_IN (I2S0 ONLY)

AP1_IN[4:1]

AP2_IN

AP2_IN5

AP2_IN[4:1]

NOTES

1. AUD1_IN AND AUD2_IN PORTS NOT AVAILABLE WHEN AP1_IN AND AP2_IN PORTS USED.

2. AP1_IN AND AP2_IN PORTS NOT AVAILABLE WHEN PIXEL PORT INPUT USED.

Figure 10. I²S Input Timing

LRCLK

SCLK

LEFT

RIGHT

MSB

LSB

RIGHT

LEFT

I2S[3:0]

32 CLOCK SLOTS

2

I S STANDARD

2

I S FORMAT = 00

Figure 11. I²S Standard Audio, Data Width 16 to 24 Bits per Channel

LEFT

RIGHT

LRCLK

SCLK

LSB_RIGHT

MSB_LEFT

LSB_LEFT

MSB_RIGHT

LSB

I2S[3:0]

16 CLOCK SLOTS

Figure 12. I²S Standard Audio, 16-Bit Samples Only

Rev. 0 | Page 10 of 24

Data Sheet

ADV7625

LRCLK

LEFT

RIGHT

SCLK

I2S[3:0]

MSB

MSB – 1

LSB

MSB

MSB – 1

LSB

MSB

EXTENDED

MSB

EXTENDED

32 CLOCK SLOTS

SERIAL AUDIO

RIGHT JUSTIFIED

2

I S FORMAT = 01

Figure 13. Serial Audio, Right-Justified

LRCLK

SCLK

LEFT

RIGHT

MSB

LSB

MSB

LSB

I2S[3:0]

32 CLOCK SLOTS

SERIAL AUDIO

LEFT JUSTIFIED

2

I S FORMAT = 10

Figure 14. Serial Audio, Left-Justified

LRCLK

SCLK

CHANNEL A

CHANNEL B

I2S[3:0]

LSB

MSB

V

U

C

P

LSB

MSB

V

U

C

P

32 CLOCK SLOTS

FRAME n

FRAME n + 1

AES3 DIRECT AUDIO

2

I S FORMAT = 11

Figure 15. AES3 Direct Audio

t₄₀

APx_IN_SCLK

t₄₁

t₄₂

APx_IN[5:0]

NOTES

1. APx REFERS TO THE AUDIO INPUT PORTS AP1_IN AND AP2_IN.

Figure 16. DSD Input Timing

Rev. 0 | Page 11 of 24

ADV7625

Data Sheet

t₄₆

APx_OUT_SCLK

t₄₇

LRCLK

t₄₈

t₄₉

I2Sx

LEFT-JUSTIFIED

MODE

MSB

MSB – 1

MSB

t₅₀

t₄₉

I2Sx

2

I S MODE

MSB – 1

t₅₀

t₄₉

I2Sx

RIGHT-JUSTIFIED

MODE

MSB

LSB

t₅₀

NOTES

1. APx REFERS TO THE AUDIO OUTPUT PORTS AP1_OUT AND AP2_OUT.

2. LRCLK IS A SIGNAL ACCESSIBLE VIA APx_OUT5.

3. I2Sx ARE SIGNALS ACCESSIBLE VIA APx_OUT1 TO APx_OUT4.

Figure 17. I²S Output Timing

t₅₃

t₅₁

APx_OUT_SCLK

t₅₂

APx_OUT[5:0]

NOTES

1. APx REFERS TO THE AUDIO OUTPUT PORTS AP1_OUT AND AP2_OUT.

Figure 18. DSD Output Timing

Rev. 0 | Page 12 of 24

Data Sheet

ADV7625

POWER SPECIFICATIONS

Table 3.

Parameter

Symbol

Min

Typ

Max

Unit

POWER SUPPLIES

HDMI TxA Analog Power Supply

HDMI TxB Analog Power Supply

Comparator Power Supply

Digital Power Supply

Digital I/O Power Supply

PLL Power Supply

HDMI TxA PLL Power Supply

HDMI TxB PLL Power Supply

Termination Power Supply

CURRENT CONSUMPTION—MUX MODE^{1, 2}

HDMI TxA Analog Power Supply

HDMI TxB Analog Power Supply

Comparator Power Supply

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

AVDD_TXA

AVDD_TXB

CVDD

DVDD

DVDDIO

PVDD

PVDD_TXA

PVDD_TXB

TVDD

1.71

3.14

1.71

3.14

1.8

3.3

1.8

3.3

1.89

3.46

1.89

3.46

V

I_{AVDD_TXA}

I_{AVDD_TXB}

I_CVDD

I_DVDD

I_DVDDIO

I_PVDD

I_{PVDD_TXA}

I_{PVDD_TXB}

I_TVDD

23.2

196

326.1

0.1

69.7

71.5

116

mA

HDMI TxA PLL Power Supply

HDMI TxB PLL Power Supply

Termination Power Supply

CURRENT CONSUMPTION—AUDIO EXTRACT/

AUDIO INSERT MODE^{1, 3}

HDMI TxA Analog Power Supply

HDMI TxB Analog Power Supply

Comparator Power Supply

Digital Core Power Supply

Digital I/O Power Supply

I_{AVDD_TXA}

I_{AVDD_TXB}

I_CVDD

I_DVDD

I_DVDDIO

I_PVDD

I_{PVDD_TXA}

I_{PVDD_TXB}

I_TVDD

26.2

184

436.0

0.05

64

71.1

115

mA

PLL Power Supply

HDMI TxA PLL Power Supply

HDMI TxB PLL Power Supply

Termination Power Supply

CURRENT CONSUMPTION—PIXEL PORT INPUT MODE^{1, 4}

HDMI TxA Analog Power Supply

HDMI TxB Analog Power Supply

Comparator Power Supply

Digital Core Power Supply

Digital I/O Power Supply

I_{AVDD_TXA}

I_{AVDD_TXB}

I_CVDD

I_DVDD

I_DVDDIO

I_PVDD

I_{PVDD_TXA}

I_{PVDD_TXB}

I_TVDD

16.0

25.5

184

mA

164

0.05

64.1

55.2

69.5

115.2

PLL Power Supply

HDMI TxA PLL Power Supply

HDMI TxB PLL Power Supply

Termination Power Supply

CURRENT CONSUMPTION—SPLITTER MODE^{1, 5}

HDMI TxA Analog Power Supply

HDMI TxB Analog Power Supply

Comparator Power Supply

Digital Core Power Supply

Digital I/O Power Supply

I_{AVDD_TXA}

I_{AVDD_TXB}

I_CVDD

I_DVDD

I_DVDDIO

I_PVDD

I_{PVDD_TXA}

I_{PVDD_TXB}

I_TVDD

26.2

93

243.5

0.05

33.5

71.1

115

mA

PLL Power Supply

HDMI TxA PLL Power Supply

HDMI TxB PLL Power Supply

Termination Power Supply

Rev. 0 | Page 13 of 24

ADV7625

Data Sheet

Parameter

Symbol

Min

Typ

Max

Unit

CURRENT CONSUMPTION—POWER-DOWN MODE 0^{1, 6}

HDMI TxA Analog Power Supply

HDMI TxB Analog Power Supply

Comparator Power Supply

Digital Core Power Supply

Digital I/O Power Supply

I_{AVDD_TXA}

I_{AVDD_TXB}

I_CVDD

I_DVDD

I_DVDDIO

I_PVDD

I_{PVDD_TXA}

I_{PVDD_TXB}

I_TVDD

0.65

0.84

0.25

0.21

0.02

0.05

0.14

mA

PLL Power Supply

HDMI TxA PLL Power Supply

HDMI TxB PLL Power Supply

Termination Power Supply

CURRENT CONSUMPTION—POWER-DOWN MODE 1^{1, 7}

HDMI TxA Analog Power Supply

HDMI TxB Analog Power Supply

Comparator Power Supply

Digital Core Power Supply

Digital I/O Power Supply

I_{AVDD_TXA}

I_{AVDD_TXB}

I_CVDD

I_DVDD

I_DVDDIO

I_PVDD

I_{PVDD_TXA}

I_{PVDD_TXB}

I_TVDD

0.95

0.84

0.95

0.21

0.02

0.05

0.14

mA

PLL Power Supply

HDMI TxA PLL Power Supply

HDMI TxB PLL Power Supply

Termination Power Supply

CURRENT CONSUMPTION—EXAMPLE MAXIMUM

OPERATING MODE^{1, 8}

HDMI TxA Analog Power Supply

HDMI TxB Analog Power Supply

Comparator Power Supply

Digital Core Power Supply

Digital I/O Power Supply

PLL Power Supply

HDMI TxA PLL Power Supply

HDMI TxB PLL Power Supply

Termination Power Supply

I_{AVDD_TXA}

I_{AVDD_TXB}

I_CVDD

I_DVDD

I_DVDDIO

I_PVDD

I_{PVDD_TXA}

I_{PVDD_TXB}

I_TVDD

30.00

213.00

530.00

0.25

79.00

80.00

127.00

mA

¹Data recorded during lab characterization. Typical current consumption values are recorded with nominal voltage supply levels and at room temperature.

²ADV7625 configured in mux mode with two active HDMI Rx inputs and two HDMI Tx outputs in use. 4k × 2k at 30 Hz video format with pseudo random test pattern

applied to each active HDMI Rx input port. HDMI Rx termination closed on the two active HDMI Rx input ports and open on the three unused HDMI Rx input ports.

HDMI Tx source termination enabled.

³ADV7625 configured in audio extract/audio insert mode with two active HDMI Rx inputs and two HDMI Tx outputs in use. Audio extracted from both active HDMI Rx

inputs and output on AP1_OUT and AP2_OUT. Audio inserted on HDMI Tx outputs from AP1_IN and AP2_IN input ports, respectively. HBR audio used. 4k × 2k at 30 Hz

video format with pseudo random test pattern applied to both active HDMI Rx input ports. HDMI Rx port termination closed on the two active HDMI Rx input ports

and open on the three unused HDMI Rx input ports. HDMI Tx source termination enabled. OSD not enabled.

⁴ADV7625 configured in pixel port input mode with pixel port input, one HDMI Rx input, and two HDMI Tx outputs in use. 1080p video format applied to pixel port

input and output on one HDMI Tx output. Stereo I²S audio inserted on this HDMI Tx output from one AUDx_IN input. No audio extraction. 4k × 2k at 30 Hz video

format with pseudo random test pattern applied to HDMI Rx input and output on second HDMI Tx output. HBR audio inserted on this HDMI Tx output from the

connected HDMI Rx input. HDMI Rx port termination closed on the active HDMI Rx input port and open on the four unused HDMI Rx input ports. HDMI Tx source

termination enabled. OSD not enabled.

⁵ADV7625 configured in splitter mode with one HDMI Rx input and two HDMI Tx outputs in use. 4k × 2k at 30 Hz video format with pseudo random test pattern applied

to one HDMI Rx input and output on both HDMI Tx outputs using splitter mode. HBR audio from HDMI Rx input inserted on the HDMI Tx outputs. No audio extraction.

HDMI Rx port termination closed on the active HDMI Rx input port and open on the four unused HDMI Rx input ports. HDMI Tx source termination enabled. OSD

enabled and blended on both HDMI Tx outputs using splitter mode.

⁶ADV7625 configured in Power-Down Mode 0 with two HDMI Rx inputs and two HDMI Tx outputs connected. In Power-Down Mode 0, all blocks are powered down

except for the I²C slave.

⁷ADV7625 configured in Power-Down Mode 1 with two HDMI Rx inputs and two HDMI Tx outputs connected. In Power-Down Mode 1, all blocks are powered down

except for the I²C slave and the CEC (to monitor wake-up interrupts).

⁸ADV7625 configured in an example maximum operating mode with two active HDMI Rx inputs and two HDMI Tx outputs in use. HBR audio from the two active HDMI

Rx inputs inserted on the corresponding HDMI Tx outputs. No audio extraction. 4k × 2k at 30 Hz video format with pseudo random test pattern applied to each of the

five HDMI Rx input ports. HDMI Rx port termination closed on all five HDMI Rx input ports (not recommended). HDMI Tx source termination enabled. OSD enabled.

Maximum current consumption values recorded with maximum power supply levels at device maximum operating temperature.

Rev. 0 | Page 14 of 24

Data Sheet

ADV7625

ABSOLUTE MAXIMUM RATINGS

PACKAGE THERMAL PERFORMANCE

Table 4.

To reduce power consumption when using the ADV7625, the

user is advised to turn off unused sections of the device.

Parameter

Rating

2.2 V

4.0 V

AVDD_TXA to GND

AVDD_TXB to GND

CVDD to GND

DVDD to GND

PVDD to GND

PVDD_TXA to GND

PVDD_TXB to GND

DVDDIO to GND

TVDD to GND

Due to printed circuit board (PCB) metal variation and,

therefore, variation in PCB heat conductivity, the value of θ_JA

may differ for various PCBs. The most efficient measurement

solution is obtained using the package surface temperature to

estimate the die temperature because this solution eliminates

the variance associated with the θ_JAvalue.

The maximum junction temperature (T_{J MAX}) of 125°C must

not be exceeded. The following equation calculates the junction

temperature using the measured package surface temperature

and applies only when no heat sink is used on the device under

test (DUT):

Digital Inputs Voltage to GND

GND − 0.3 V to DVDDIO + 0.3 V

up to a maximum of 4.0 V

5.5 V

5 V Tolerant Digital Inputs

to GND¹

Digital Outputs Voltage to GND GND − 0.3 V to DVDDIO + 0.3 V

up to a maximum of 4.0 V

T_J= T_S+ (Ψ_JT× W_TOTAL

where:

T_Sis the package surface temperature (°C).

_JT= 0.41°C/W for the 260-ball CSP_BGA (based on 2s2p test

board defined in the JEDEC specification).

_TOTAL= ((PVDD × I_PVDD) + (PVDD_TXA × I_{PVDD_TXA}) +

)

XTAL+, XTAL− Pins

Maximum Junction Temperature 125°C

(T_{J MAX}

−0.3 V to PVDD + 0.3 V

Ψ

)

Storage Temperature Range

Infrared Reflow, Soldering

(20 sec)

−65°C to +150°C

260°C

W

(PVDD_TXB × I_{PVDD_TXB}) + (TVDD × I_TVDD) + (CVDD × I_CVDD) +

(AVDD_T XA × I_{AVDD_TXA}) + (AVDD_TXB × I_{AVDD_TXB}) + (DVDD ×

¹The following inputs are 5 V tolerant: DDC_SCL_RXA, DDC_SDA_RXA, DDC_

SCL_RXB, DDC_SDA_RXB, DDC_SCL_RXC, DDC_SDA_RXC, DDC_SCL_RXD,

DDC_SDA_RXD, DDC_SCL_RXE, DDC_SDA_RXE, RXA_5V, RXB_5V, RXC_5V,

RXD_5V, RXE_5V, CEC_A, DDC_SCL_TXA, DDC_SDA_TXA, TXA_HPD_ARC−,

TXA_ARC+, CEC_B, DDC_SCL_TXB, DDC_SDA_TXB, TXB_HPD_ARC−, and

TXB_ARC+.

I_DVDD) + (DVDDIO × I_DVDDIO))

Note that this calculation assumes a configuration of two active

HDMI Rx inputs and two active HDMI Tx outputs, where termi-

nation is open on the unused Rx input ports.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

A configuration of one active HDMI Rx input and two active

HDMI Tx outputs (splitter mode) results in approximately

112 mW extra power dissipation on chip.

ESD CAUTION

Rev. 0 | Page 15 of 24

ADV7625

Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

A

B

C

D

E

F

GND

INT1

RXA_2+

RXA_2–

CVDD

RXA_1+

RXA_1–

CVDD

SCL

RXA_0+ RXA_C+

CVDD

GND

RXB_2+

RXB_2–

GND

RXB_1+

RXB_0+

RXB_C+

CVDD

RXC_2+

RXC_2–

TVDD

RXC_1+

RXC_1–

TVDD

RXC_0+

RXC_0–

RXC_C+

RXC_C–

CVDD

TVDD

GND

TVDD

GND

VS

RXC_5V

RXC_HPA

GND

RXA_0– RXA_C–

RXB_1–

RXB_0–

RXB_C–

CVDD

TVDD

SDA

TVDD

CS

TVDD

DDC_

TVDD

DDC_

GND

DDC_

SDA_RXC SCL_RXC

DDC_

INT2

RXA_5V RXA_HPA

RXB_HPA RXB_5V

RXD_2–

RXD_1–

RXD_0–

RXD_2+

RXD_1+

RXD_0+

SCL_RXA SDA_RXA SCL_RXB SDA_RXB

AP1_

OUT0

AP1_

OUT1

ALSB

RESET

RXD_5V

AP1_

OUT2

AP1_

OUT3

AP2_

OUT0

AP2_

OUT1

RXD_HPA

AP1_

OUT4

AP1_

OUT5

AP2_

OUT2

AP2_

OUT3

DDC_SCL

_RXD

DVDD

DVDDIO

GND

DVDD

GND

DVDD

GND

DVDD

GND

DVDD

GND

TEST5

GND

RXD_C– RXD_C+

G

H

J

AP1_

OUT_

MCLK

AP1_

OUT_

SCLK

DDC_

SDA_RXD

AP2_

OUT4

AP2_

OUT5

CVDD

RXE_2–

RXE_1–

RXE_0–

RXE_C–

CVDD

RXE_2+

RXE_1+

RXE_0+

RXE_C+

CVDD

TEST1

PCLK

AP2_

OUT_

MCLK

AP2_

OUT_

SCLK

AUD1_IN_

SCLK

DDC_

SCL_RXE

AUD1_IN

DDC_

SDA_RXE

AUD1_IN_

LRCLK

GND

XTAL+

PVDD

GND

XTAL–

PVDD

K

L

AUD2_IN

AUD2_IN_ AUD2_IN_

SCLK

GND

RXE_HPA

RXE_5V

GND

LRCLK

TEST3

TEST2

GND

M

N

P

R

T

PVDD_

TXA

PVDD_

TXA

GND

TXA_C–

TXA_0–

TXA_1–

TXA_2–

TXA_C+

TXA_0+

TXA_1+

TXA_2+

GND

R_TXA

HS

TEST4

TXB_

HPD_

ARC–

AVDD_

TXA

TXB_

ARC+

DDC_

SDA_TXB SCL_TXB

DDC_

P9/AP2_ P11/AP2_ P13/AP2_ P15/AP2_

IN_SCLK IN4 IN2 IN0

R_TXB

GND

CEC_B

DVDDIO

EP_CS

AVDD_

TXA

AVDD_

TXB

P8/AP2_ P10/AP2_ P12/AP2_ P14/AP2_

IN_MCLK IN5 IN3 IN1

CEC_A

GND

TXB

DVDDIO EP_SCLK

DE

DDC_

SCL_TXA

PVDD_

TXB

TXA_

ARC+

TXB_C+

TXB_0+

TXB_1+

TXB_2+

GND

EP_MOSI P1/AP1_ P3/AP1_ P5/AP1_ P7/AP1_

IN_SCLK IN4 IN2 IN0

GND

U

V

TXA_

HPD_

ARC–

DDC_

SDA_TXA

PVDD_

TXB

P0/AP1_ P2/AP1_ P4/AP1_ P6/AP1_

IN_MCLK

GND

1

GND

2

GND

3

GND

7

TXB_C–

8

TXB_0–

9

TXB_1–

10

TXB_2–

11

GND

12

EP_MISO

13

GND

18

IN5

IN3

IN1

4

5

6

14

15

16

17

Figure 19. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Function

Description

A1

GND

Ground

Ground.

A2

A3

A4

A5

A6

A7

A8

A9

RXA_2+

RXA_1+

RXA_0+

RXA_C+

CVDD

RXB_2+

RXB_1+

RXB_0+

RXB_C+

CVDD

HDMI Rx input

Power

HDMI Rx input

Power

HDMI RxA Channel 2 True Input.

HDMI RxA Channel 1 True Input.

HDMI RxA Channel 0 True Input.

HDMI RxA Clock True Input.

Comparator Power Supply (1.8 V).

HDMI RxB Channel 2 True Input.

HDMI RxB Channel 1 True Input.

HDMI RxB Channel 0 True Input.

HDMI RxB Clock True Input.

A10

A11

A12

Comparator Power Supply (1.8 V).

HDMI RxC Channel 2 True Input.

RXC_2+

HDMI Rx input

Rev. 0 | Page 16 of 24

Data Sheet

ADV7625

Pin No.

A13

A14

A15

A16

A17

A18

B1

Mnemonic

Function

HDMI Rx input

Power

HDMI Rx input

Ground

Description

RXC_1+

RXC_0+

RXC_C+

CVDD

RXC_5V

GND

HDMI RxC Channel 1 True Input.

HDMI RxC Channel 0 True Input.

HDMI RxC Clock True Input.

Comparator Power Supply (1.8 V).

HDMI RxC 5 V Detect Pin.

Ground.

GND

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

C1

RXA_2−

RXA_1−

RXA_0−

RXA_C−

CVDD

RXB_2−

RXB_1−

RXB_0−

RXB_C−

CVDD

RXC_2−

RXC_1−

RXC_0−

RXC_C−

CVDD

RXC_HPA

GND

HDMI Rx input

Power

HDMI Rx input

Power

HDMI Rx input

Power

HDMI RxA Channel 2 Complement Input.

HDMI RxA Channel 1 Complement Input.

HDMI RxA Channel 0 Complement Input.

HDMI RxA Clock Complement Input.

Comparator Power Supply (1.8 V).

HDMI RxB Channel 2 Complement Input.

HDMI RxB Channel 1 Complement Input.

HDMI RxB Channel 0 Complement Input.

HDMI RxB Clock Complement Input.

Comparator Power Supply (1.8 V).

HDMI RxC Channel 2 Complement Input.

HDMI RxC Channel 1 Complement Input.

HDMI RxC Channel 0 Complement Input.

HDMI RxC Clock Complement Input.

Comparator Power Supply (1.8 V).

HDMI RxC Hot Plug Assert.

Ground.

HDMI Rx output

Ground

GND

Ground.

C2

C3

C4

C5

CVDD

TVDD

GND

Power

Comparator Power Supply (1.8 V).

HDMI Rx Terminator Supply Voltage (3.3 V).

Ground.

C6

Ground

C7

GND

Ground

Ground.

C8

C9

TVDD

GND

Power

Ground

Power

Ground

Power

Ground

Control

HDMI Rx Terminator Supply Voltage (3.3 V).

Ground.

C10

C11

C12

C13

C14

C15

C16

C17

C18

D1

GND

Ground.

TVDD

GND

CVDD

GND

HDMI Rx Terminator Supply Voltage (3.3 V).

Ground.

Comparator Power Supply (1.8 V).

Ground.

Interrupt Output. This pin can be active low or high. When an

unmasked status bit changes, an interrupt is generated on this pin.

GND

INT1

D2

D3

D4

D5

INT2

SCL

SDA

CS

Control

Interrupt Output. This pin can be active low or high. When an

unmasked status bit changes, an interrupt is generated on this pin.

I²C Clock Input. This pin is open drain; connect this pin to a 3.3 V supply

using a 4.7 kΩ resistor.

I²C Data Input. This pin is open drain; connect this pin to a 3.3 V supply

using a 4.7 kΩ resistor.

Chip Select Pin. This pin must be set low or left floating for the chip to

process I²C messages that are destined for the ADV7625. The ADV7625

ignores I²C messages when this pin is high.

I²C control

Digital input

D6

RXA_5V

HDMI Rx input

HDMI RxA 5 V Detect Pin.

Rev. 0 | Page 17 of 24

ADV7625

Data Sheet

Pin No.

D7

D8

Mnemonic

RXA_HPA

Function

Description

HDMI Rx output

HDMI Rx DDC

HDMI Rx output

HDMI Rx input

HDMI Rx DDC

Power

HDMI Rx input

Audio output

I²C control

HDMI RxA Hot Plug Assert.

DDC_SCL_RXA

DDC_SDA_RXA

DDC_SCL_RXB

DDC_SDA_RXB

RXB_HPA

HDCP Slave Serial Clock for HDMI RxA.

HDCP Slave Serial Data for HDMI RxA.

HDCP Slave Serial Clock for HDMI RxB.

HDCP Slave Serial Data for HDMI RxB.

HDMI RxB Hot Plug Assert.

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

E1

RXB_5V

HDMI RxB 5 V Detect Pin.

DDC_SDA_RXC

DDC_SCL_RXC

TVDD

RXD_2−

RXD_2+

AP1_OUT0

AP1_OUT1

ALSB

HDCP Slave Serial Data for HDMI RxC.

HDCP Slave Serial Clock for HDMI RxC.

HDMI Rx Terminator Supply Voltage (3.3 V).

HDMI RxD Channel 2 Complement Input.

HDMI RxD Channel 2 True Input.

Audio Output Port 1, Output 0.

Audio Output Port 1, Output 1.

Pin to set the I²C address of the I/O register map for the device. When

the ALSB pin is tied low, the I/O register map I²C address is 0xB0. When

the ALSB pin is tied high, the I/O register map I²C address is 0xB2.

E2

E3

E4

RESET

Miscellaneous digital

HDMI Rx input

Power

Reset Pin.

E15

E16

E17

E18

F1

F2

F3

F4

F15

F16

F17

F18

G1

G2

G3

G4

G7

RXD_5V

TVDD

HDMI RxD 5 V Detect Pin.

HDMI Rx Terminator Supply Voltage (3.3 V).

HDMI RxD Channel 1 Complement Input.

HDMI RxD Channel 1 True Input.

Audio Output Port 1, Output 2.

Audio Output Port 1, Output 3.

Audio Output Port 2, Output 0.

Audio Output Port 2, Output 1.

HDMI RxD Hot Plug Assert.

Ground.

HDMI RxD Channel 0 Complement Input.

HDMI RxD Channel 0 True Input.

Audio Output Port 1, Output 4.

Audio Output Port 1, Output 5.

Audio Output Port 2, Output 2.

Audio Output Port 2, Output 3.

Digital Power Supply (1.8 V).

Test Pin 5. Leave this pin floating.

HDCP Slave Serial Clock for HDMI RxD.

Ground.

RXD_1−

RXD_1+

AP1_OUT2

AP1_OUT3

AP2_OUT0

AP2_OUT1

RXD_HPA

GND

RXD_0−

RXD_0+

AP1_OUT4

AP1_OUT5

AP2_OUT2

AP2_OUT3

DVDD

TEST5

DDC_SCL_RXD

GND

HDMI Rx input

Audio output

HDMI Rx output

Ground

HDMI Rx input

Audio output

Power

G8

G9

Power

G10

G11

G12

G15

G16

G17

G18

H1

H2

H3

H4

H7

Test pin

HDMI Rx DDC

Ground

HDMI Rx input

Audio output

Power

RXD_C−

RXD_C+

AP1_OUT_MCLK

AP1_OUT_SCLK

AP2_OUT4

AP2_OUT5

DVDDIO

GND

HDMI RxD Clock Complement Input.

HDMI RxD Clock True Input.

Audio Output Port 1, MCLK.

Audio Output Port 1, SCLK.

Audio Output Port 2, Output 4.

Audio Output Port 2, Output 5.

Digital Interface Supply (3.3 V).

Ground.

H8

Ground

H9

GND

Ground

Ground.

H10

H11

GND

Ground

Ground.

Rev. 0 | Page 18 of 24

Data Sheet

ADV7625

Pin No.

H12

H15

H16

H17

H18

J1

J2

J3

J4

J7

Mnemonic

Function

Ground

HDMI Rx DDC

Ground

Power

Audio output

Audio input

Power

Description

GND

DDC_SDA_RXD

GND

CVDD

AP2_OUT_MCLK

AP2_OUT_SCLK

AUD1_IN

AUD1_IN_SCLK

DVDDIO

GND

Ground.

HDCP Slave Serial Data for HDMI RxD.

Ground.

Comparator Power Supply (1.8 V).

Audio Output Port 2, MCLK.

Audio Output Port 2, SCLK.

Audio Input Port 1, I²S or S/PDIF Input.

Audio Input Port 1, SCLK.

Digital Interface Supply (3.3 V).

Ground.

J8

Ground

J9

GND

Ground

Ground.

J10

J11

J12

J15

J16

J17

J18

K1

GND

DDC_SCL_RXE

TVDD

RXE_2−

RXE_2+

GND

Ground

HDMI Rx DDC

Power

HDMI Rx input

Ground

Ground.

HDCP Slave Serial Clock for HDMI RxE.

HDMI Rx Terminator Supply Voltage (3.3 V).

HDMI RxE Channel 2 Complement Input.

HDMI RxE Channel 2 True Input.

Ground.

K2

GND

Ground

Ground.

K3

K4

K7

AUD1_IN_LRCLK

AUD2_IN

GND

Audio input

Ground

Audio Input Port 1, LRCLK.

Audio Input Port 2, I²S or S/PDIF Input.

Ground.

K8

GND

Ground

Ground.

K9

GND

Ground

Ground.

K10

K11

K12

K15

K16

K17

K18

L1

L2

L3

L4

L7

GND

DDC_SDA_RXE

TVDD

RXE_1−

RXE_1+

XTAL+

Ground

HDMI Rx DDC

Power

HDMI Rx input

Miscellaneous digital

Audio input

Ground

Ground.

HDCP Slave Serial Data for HDMI RxE.

HDMI Rx Terminator Supply Voltage (3.3 V).

HDMI RxE Channel 1 Complement Input.

HDMI RxE Channel 1 True Input.

ADV7625 Crystal Input.

ADV7625 Crystal Output.

Audio Input Port 2, SCLK.

Audio Input Port 2, LRCLK.

Ground.

XTAL−

AUD2_IN_SCLK

AUD2_IN_LRCLK

GND

L8

GND

Ground

Ground.

L9

GND

Ground

Ground.

L10

L11

L12

L15

L16

L17

L18

M1

M2

M3

M4

M7

M8

GND

RXE_HPA

GND

RXE_0−

RXE_0+

PVDD

TEST3

Ground

HDMI Rx output

Ground

HDMI Rx input

Power

Test pin

Ground.

HDMI RxE Hot Plug Assert.

Ground.

HDMI RxE Channel 0 Complement Input.

HDMI RxE Channel 0 True Input.

PLL Digital Supply (1.8 V).

Test Pin 3. Leave this pin floating.

Test Pin 2. Leave this pin floating.

Ground.

TEST2

GND

Test pin

Ground

Ground.

Rev. 0 | Page 19 of 24

ADV7625

Data Sheet

Pin No.

M9

Mnemonic

GND

Function

Ground

Description

Ground.

M10

M11

M12

M15

M16

M17

M18

N1

GND

RXE_5V

GND

RXE_C−

RXE_C+

GND

Ground

HDMI Rx input

Ground

HDMI Rx input

Ground

Ground.

HDMI RxE 5 V Detect Pin.

Ground.

HDMI RxE Clock Complement Input.

HDMI RxE Clock True Input.

Ground.

N2

GND

Ground

Ground.

N3

N4

PVDD_TXA

GND

CVDD

Power

Ground

Power

HDMI Tx output

Ground

HDMI TxA PLL Power Supply (1.8 V).

Ground.

N15

N16

N17

N18

P1

Ground.

Comparator Power Supply (1.8 V).

HDMI TxA Clock Complement Output.

HDMI TxA Clock True Output.

Ground.

CVDD

TXA_C−

TXA_C+

GND

P2

P3

P4

R_TXA

HDMI Tx input

This pin sets the internal reference currents for HDMI TxA. Place a 470 Ω

resistor (1% tolerance) between this pin and GND. Place the external

resistor as close as possible to the ADV7625.

P15

P16

P17

P18

R1

HS

VS

TEST4

TEST1

TXA_0−

TXA_0+

GND

Pixel port input sync

Test pin

Horizontal Synchronization for Pixel Port Input Video.

Vertical Synchronization for Pixel Port Input Video.

Test Pin 4. Leave this pin floating.

Test Pin 1. Leave this pin floating.

HDMI TxA Channel 0 Complement Output.

HDMI TxA Channel 0 True Output.

Ground.

Test pin

HDMI Tx output

Ground

R2

R3

R4

R5

AVDD_TXA

TXB_HPD_ARC−

Power

HDMI Tx input

HDMI TxA Analog Supply (1.8 V).

HDMI TxB Hot Plug Detect (HPD) Signal and Audio Return Channel

Complement Input.

R6

R_TXB

HDMI Tx input

This pin sets the internal reference currents for HDMI TxB. Place a 470 Ω

resistor (1% tolerance) between this pin and GND. Place the external

resistor as close as possible to the ADV7625.

R7

GND

Ground

Ground.

R8

R9

TXB_ARC+

DDC_SDA_TXB

DDC_SCL_TXB

CEC_B

DVDDIO

EP_CS

HDMI Tx input

HDMI Tx DDC

HDMI Tx CEC

Power

Serial port control

Pixel port input/audio input

Pixel port input clock

HDMI Tx output

Ground

HDMI TxB Audio Return Channel True Input.

HDCP Slave Serial Data for HDMI TxB.

HDCP Slave Serial Clock for HDMI TxB.

HDMI TxB Consumer Electronics Control (CEC).

Digital Interface Supply (3.3 V).

SPI Chip Select Interface for the OSD.

Pixel Port Input P9/Audio Input Port 2, SCLK.

Pixel Port Input P11/Audio Input Port 2, Input 4.

Pixel Port Input P13/Audio Input Port 2, Input 2.

Pixel Port Input P15/Audio Input Port 2, Input 0.

Pixel Clock for Pixel Port Input Video.

HDMI TxA Channel 1 Complement Output.

HDMI TxA Channel 1 True Output.

Ground.

R10

R11

R12

R13

R14

R15

R16

R17

R18

T1

P9/AP2_IN_SCLK

P11/AP2_IN4

P13/AP2_IN2

P15/AP2_IN0

PCLK

TXA_1−

TXA_1+

GND

T2

T3

T4

T5

T6

AVDD_TXA

CEC_A

GND

Power

HDMI Tx CEC

Ground

HDMI TxA Analog Supply (1.8 V).

HDMI TxA Consumer Electronics Control (CEC).

Ground.

T7

GND

Ground

Ground.

Rev. 0 | Page 20 of 24

Data Sheet

ADV7625

Pin No.

T8

Mnemonic

Function

Description

GND

Ground

Ground.

T9

GND

Ground

Ground.

T10

T11

T12

T13

T14

T15

T16

T17

T18

U1

AVDD_TXB

DVDDIO

EP_SCLK

P8/AP2_IN_MCLK

P10/AP2_IN5

P12/AP2_IN3

P14/AP2_IN1

DE

Power

HDMI TxB Analog Supply (1.8 V).

Digital Interface Supply (3.3 V).

SPI Clock Interface for the OSD.

Pixel Port Input P8/Audio Input Port 2, MCLK.

Pixel Port Input P10/Audio Input Port 2, Input 5.

Pixel Port Input P12/Audio Input Port 2, Input 3.

Pixel Port Input P14/Audio Input Port 2, Input 1.

Data Enable for Pixel Port Input Video.

HDMI TxA Channel 2 Complement Output.

HDMI TxA Channel 2 True Output.

Ground.

Serial port control

Pixel port input/audio input

Pixel port input sync

HDMI Tx output

Ground

TXA_2−

TXA_2+

GND

U2

U3

U4

U5

U6

U7

DDC_SCL_TXA

TXA_ARC+

PVDD_TXB

GND

HDMI Tx DDC

HDMI Tx input

Power

HDCP Slave Serial Clock for HDMI TxA.

HDMI TxA Audio Return Channel True Input.

HDMI TxB PLL Power Supply (1.8 V).

Ground.

Ground

U8

U9

TXB_C+

TXB_0+

TXB_1+

TXB_2+

HDMI Tx output

Ground

Serial port control

Pixel port input/audio input

Ground

HDMI TxB Clock True Output.

HDMI TxB Channel 0 True Output.

HDMI TxB Channel 1 True Output.

HDMI TxB Channel 2 True Output.

Ground.

SPI Master Output/Slave Input for OSD.

Pixel Port Input P1/Audio Input Port 1, SCLK.

Pixel Port Input P3/Audio Input Port 1, Input 4.

Pixel Port Input P5/Audio Input Port 1, Input 2.

Pixel Port Input P7/Audio Input Port 1, Input 0.

Ground.

U10

U11

U12

U13

U14

U15

U16

U17

U18

V1

GND

EP_MOSI

P1/AP1_IN_SCLK

P3/AP1_IN4

P5/AP1_IN2

P7/AP1_IN0

GND

Ground

Ground.

V2

GND

Ground

Ground.

V3

GND

Ground

Ground.

V4

V5

DDC_SDA_TXA

TXA_HPD_ARC−

HDMI Tx DDC

HDMI Tx input

HDCP Slave Serial Data for HDMI TxA.

HDMI TxA Hot Plug Detect (HPD) Signal and Audio Return Channel

Complement Input.

V6

V7

PVDD_TXB

GND

Power

Ground

HDMI TxB PLL Power Supply (1.8 V).

Ground.

V8

V9

TXB_C−

TXB_0−

TXB_1−

TXB_2−

HDMI Tx output

Ground

Serial port control

Pixel port input/audio input

Ground

HDMI TxB Clock Complement Output.

HDMI TxB Channel 0 Complement Output.

HDMI TxB Channel 1 Complement Output.

HDMI TxB Channel 2 Complement Output.

Ground.

SPI Master Input/Slave Output for OSD.

Pixel Port Input P0/Audio Input Port 1, MCLK.

Pixel Port Input P2/Audio Input Port 1, Input 5.

Pixel Port Input P4/Audio Input Port 1, Input 3.

Pixel Port Input P6/Audio Input Port 1, Input 1.

Ground.

V10

V11

V12

V13

V14

V15

V16

V17

V18

GND

EP_MISO

P0/AP1_IN_MCLK

P2/AP1_IN5

P4/AP1_IN3

P6/AP1_IN1

GND

Rev. 0 | Page 21 of 24

ADV7625

Data Sheet

POWER SUPPLY RECOMMENDATIONS

POWER-UP SEQUENCE

3.3V

The power-up sequence for the ADV7625 is as follows.

RESET

0V

RESET

1. Hold the

pin low.

1.8V

2. Power up the 3.3 V supplies (DVDDIO and TVDD).

3. After the 3.3 V supplies reach their minimum recom-

mended value of 3.14 V, wait at least 20 ms before

powering up the 1.8 V supplies.

1.8V

SUPPLY

0V

3.3V

3.14V

4. Power up the 1.8 V supplies (AVDD_TXA, AVDD_TXB,

CVDD, DVDD, PVDD, PVDD_TXA, and PVDD_TXB).

These supplies should be powered up at the same time;

that is, there should be a difference of less than 0.3 V

between them.

3.3V

SUPPLY

t_PSS≥ 20ms

RESET > 5ms

0V

Figure 20. ADV7625 Supply Power-Up Sequence

POWER-DOWN SEQUENCE

RESET

5. Release the

pin after all supplies are established.

The ADV7625 supplies can be deasserted simultaneously as

long as DVDDIO or TVDD does not fall below a lower rated

supply.

After power-up, a complete reset is recommended. This reset

can be performed by the system microcontroller.

Rev. 0 | Page 22 of 24

Data Sheet

ADV7625

THEORY OF OPERATION

HDMI RECEIVERS

ON-SCREEN DISPLAY

The ADV7625 front end incorporates two HDMI receivers

capable of receiving all HDTV formats up to 3 GHz (4k × 2k at

24 Hz/25 Hz/30 Hz). The HDMI receivers also support HDMI

features including 3D TV and content type bits.

A key feature of the ADV7625 is the on-chip character-

and icon-based OSD generator. The generated OSD can be

converted to match the 4:2:2 or 4:4:4 input format in either the

RGB or YCrCb color spaces. After the OSD is generated, it is

overlaid at the output resolution (any video resolution up to

4k × 2k at 24 Hz/25 Hz/30 Hz) for best performance. The OSD

portion of the image is optionally semitransparent using a 5-bit

alpha blend between the input video and the OSD. The OSD font

characters and icons can be stored in external SPI flash memory,

read directly into RAM, or they can be loaded into the on-chip

RAM via the SPI or I²C interface.

Each HDMI receiver in the ADV7625 incorporates an adaptive

equalizer, which compensates for the high frequency losses

inherent in HDMI and DVI cabling, especially at longer lengths

and higher frequencies.

The ADV7625 features a 768-byte internal EDID memory space,

which can be used to store two independent EDIDs, one for each

receiver. The memory can be partitioned to provide two 256-byte

EDIDs or one 512-byte extended EDID and one 256-byte

EDID. Either EDID can be replicated on any input port.

PIXEL PORT INPUT

The ADV7625 features a 16-bit pixel input port that facilitates

the reception of digital video data from an analog front-end video

decoder such as the ADV7180, ADV7181D, or ADV7842. Both

embedded timing and external synchronization signals are

supported on the pixel port. The pixel port input also features

an interlaced-to-progressive converter for 480i or 576i inputs.

The two HDMI receivers offer advanced audio functionality.

Each receiver supports multichannel I²S audio for up to eight

channels. The receivers also support a six-DSD channel interface,

with each channel carrying an oversampled 1-bit representation

of the audio signal as delivered on SACD. The ADV7625 can also

receive HBR audio packet streams and output them through the

HBR interface in an S/PDIF format that conforms to the IEC 60958

standard. S/PDIF is supported via the HPD back channel. The

receivers also contain an audio mute controller that can detect a

variety of conditions that can result in audible extraneous noise

in the audio output. On detection of these conditions, the audio

data can be ramped to prevent audio clicks or pops.

HDMI TRANSMITTERS

The ADV7625 incorporates two HDMI transmitters, each of

which supports all HDTV formats up to 3 GHz (4k × 2k at

24 Hz/25 Hz/30 Hz), ARC, and all mandatory 3D TV formats.

Each HDMI transmitter can output any audio mode received

from the corresponding HDMI receiver, including audio sample

packets, HBR, or DSD.

HDCP REPEATER FUNCTIONALITY

Each ARC receiver supports both single-ended and differential

modes and simplifies cabling by combining an upstream audio

capability in a conventional HDMI cable. Each transmitter

features an on-chip MPU with an I²C master to perform HDCP

operations and EDID read operations.

With the inclusion of HDCP 1.4, displays can receive encrypted

video content. The HDMI interface of the ADV7625 allows

authentication of a video receiver, decryption of encoded data at

the receiver, and renewability of that authentication during trans-

mission, as specified by the HDCP 1.4 protocol. Repeater support

is also offered by the ADV7625.

I²C INTERFACE

The ADV7625 supports a 2-wire serial (I²C-compatible)

microprocessor bus driving multiple peripherals. The ADV7625

is controlled by an external I²C master device, such as a micro-

controller.

DIGITAL AUDIO PORTS

The ADV7625 features two independent audio input ports and

two independent audio output ports. The audio input and output

ports provide comprehensive muxing support for the destination

of the audio (for example, to either HDMI transmitter or either

audio output port) and support for the source of the audio (for

example, from either HDMI receiver or from either audio input

port). The extracted audio can be processed by a SHARC® pro-

cessor and can be reinserted back into the HDMI output stream

or output via the hardware connected to the system.

OTHER FEATURES

Other features of the ADV7625 include the following:

•

Fully qualified software low level libraries, driver, and

application

•

Complete input and output audio support

Programmable interrupt request output pins: INT1

and INT2

The pins for the pixel port input signals (P15 to P0) are shared

with the AP1_IN and AP2_IN audio input ports. When the pixel

port input is in use, the AUD1_IN and AUD2_IN ports can be

used to provide stereo audio inputs.

•

Chip select and ALSB

Low power consumption: 1.8 V digital core, 1.8 V analog,

and 3.3 V digital input/output

•

Temperature range: 0°C to 70°C

15 mm × 15 mm, Pb-free, 260-ball CSP_BGA

Rev. 0 | Page 23 of 24

ADV7625

Data Sheet

OUTLINE DIMENSIONS

15.10

15.00 SQ

14.90

A1 BALL

CORNER

A1 BALL

CORNER

18 16 14 12 10

17 15 13 11

8

6

4

2

9

7

5

3

1

A

B

C

D

F

E

13.60

BSC SQ

G

H

J

L

0.80

BSC

K

M

P

T

N

R

U

V

TOP VIEW

DETAIL A

BOTTOM VIEW

DETAIL A

1.11

1.01

0.91

1.50

1.36

1.21

0.35 NOM

0.30 MIN

0.50

0.45

0.40

COPLANARITY

0.20

SEATING

PLANE

BALL DIAMETER

COMPLIANT TO JEDEC STANDARDS MO-275-KKAB-1.

Figure 21. 260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

(BC-260-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model^{1, 2}

Temperature Range

Package Description

Package Option

ADV7625KBCZ-8

ADV7625KBCZ-8-RL

EVAL-ADV7625-SMZ

0°C to 70°C

260-Ball Chip Scale Package Ball Grid Array [CSP_BGA]

Evaluation Board

BC-260-1

¹Z = RoHS Compliant Part.

²This part is programmed with internal HDCP keys. Customers must have HDCP adopter status (consult Digital Content Protection, LLC, for licensing requirements) to

purchase any components with internal HDCP keys.

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

HDMI, the HDMI Logo, and High-Definition Multimedia Interface are trademarks or registered trademarks of HDMI Licensing LLC in the United States and other countries.

registered trademarks are the property of their respective owners.

D11831-0-12/13(0)

Rev. 0 | Page 24 of 24


型号：	ADV7625KBCZ-8-RL
厂家：	ADI
描述：	3 GHz HDMI 5:2 Crosspoint Transceiver
文件：	总24页 (文件大小：412K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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