ADUCRF101BCPZ128R7 [ADI]
IC RF TXRX+MCU - 64-VFQFN;
| 型号： | ADUCRF101BCPZ128R7 |
| 厂家： | 
ADI |
| 描述： | IC RF TXRX+MCU - 64-VFQFN |
| 文件： | 总19页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Precision Analog Microcontroller with
RF Transceiver, ARM Cortex-M3
ADuCRF101
Data Sheet
External watch crystal for wake-up timer
16 MHz internal oscillator with 8-way, programmable
divider
FEATURES
Analog input/output (I/O)
6-channel, 12-bit SAR ADC
Memory
Single-ended and differential inputs
Programmable data rate of up to 167 kSPS
On-chip voltage reference
Supply range: 2.2 V to 3.6 V
Power consumption
128 kB Flash/EE memory, 16 kB SRAM
10,000-cycle Flash/EE endurance
10-year Flash/EE retention
In-circuit download via serial wire and UART
On-chip peripherals
UART, I2C, and SPI serial I/O
28-pin GPIO port
280 nA in shutdown mode, nonretained state
1.9 µA in hibernate mode, processor memory and
transceiver memory retained, RF transceiver in sleep
mode
2 general-purpose, 16-bit timers
32-bit wake-up timer
210 µA/MHz Cortex-M3 dynamic current
12.8 mA transceiver in receive mode, Cortex-M3 in
hibernate mode
16-bit watchdog timer
8-channel pulse-width modulation (PWM)
Package
64-lead, 9 mm × 9 mm LFCSP
9 mA to 32 mA transceiver in transmit mode, Cortex-M3
in hibernate mode
Temperature range: −40°C to +85°C
RF transceiver
Frequency bands
Tools
Low cost development system
Third-party compiler and emulator tool support
862 MHz to 928 MHz
431 MHz to 464 MHz
Multiple configurations supported
Receiver sensitivity, bit error rate (BER)
−107.5 dBm at 38.4 kbps, 2FSK
Single-ended and differential power amplifier (PA)
Low external bill of materials (BOM)
Microcontroller
APPLICATIONS
Battery-powered wireless sensors
Medical telemetry systems
Industrial and home automation
Asset tracking
Security systems (access systems)
Health and fitness applications
32-bit ARM Cortex-M3 processor
Serial wire download and debug
FUNCTIONAL BLOCK DIAGRAM
COMMUNICATIONS
6-INPUT
MUX
12-BIT
SAR ADC
LOW POWER
RF TRANSCEIVER
WIRELESS
WIRED
TEMPERATURE
SENSOR
SERIAL
WIRE
2
SPI
UART
PWM GPIOs
I C
BAND GAP
REFERENCE
PRECISION DATA
ACQUISITION
LOW POWER PROCESSING
CORTEX-M3
PROCESSOR
OSC
POR
128kB
FLASH/EE
WATCHDOG
TIMER
2× GENERAL-
PURPOSE TIMERS
16kB
SRAM
INTERRUPT
CONTROLLER
WAKE-UP
TIMER
ADuCRF101
ON-CHIP PERIPHERALS
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2013–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADuCRF101
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Absolute Maximum Ratings ......................................................... 12
Thermal Resistance.................................................................... 12
ESD Caution................................................................................ 12
Pin Configuration and Function Descriptions........................... 13
Typical Performance Characteristics ........................................... 17
Outline Dimensions....................................................................... 19
Ordering Guide .......................................................................... 19
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description......................................................................... 3
Specifications..................................................................................... 4
Electrical Specifications............................................................... 4
RF Link Specifications ................................................................. 6
Timing Specifications .................................................................. 8
REVISION HISTORY
11/14—Revision A: Initial Version
Rev. A | Page 2 of 19
Data Sheet
ADuCRF101
GENERAL DESCRIPTION
The ADuCRF101 is a fully integrated, data acquisition solution
that is designed for low power, wireless applications. It features
a 12-bit analog-to-digital converter (ADC), a low power ARM®
Cortex®-M3 processor, a 862 MHz to 928 MHz and 431 MHz
to 464 MHz RF transceiver, and Flash®/EE memory. The
ADuCRF101 is packaged in a 9 mm × 9 mm LFCSP.
A 16 MHz on-chip oscillator generates the system clock. This
clock can be internally divided for the processor to operate at
a lower frequency, thus saving power. A low power, internal
32 kHz oscillator is available and can be used to clock the four
timers, as follows: two general-purpose timers, a wake-up timer,
and a system watchdog timer.
The data acquisition section consists of a 12-bit SAR ADC.
The six inputs can be configured in single-ended or differential
mode. When configured in single-ended mode, they can be
used for ratiometric measurements on sensors that are powered,
when required, from the internal low dropout regulator (LDO).
An internal battery monitor channel and an on-chip tempera-
ture sensor are also available.
A range of communication peripherals can be configured, as
required, in a specific application. These peripherals include
UART, I2C, SPI, GPIO ports, PWM, and RF transceivers.
The RF transceiver communicates in the 862 MHz to 928 MHz
and 431 MHz to 464 MHz frequency bands using multiple
configurations.
On-chip factory firmware supports in-circuit serial download
via the UART, and nonintrusive emulation and program download
are also supported via the serial wire interface. These features
are incorporated into a low cost development system supporting
this precision analog microcontroller family.
This wireless data acquisition system is designed to operate in
battery-powered applications where low power is critical. The
device can be configured in normal operating mode or different
low power modes under direct program control. In flexi mode,
any peripheral can wake up the device and operate it. In hibernate
mode, the internal wake-up timer remains active. In shutdown
mode, only an external interrupt can wake up the device.
The ADuCRF101 operates from 2.2 V to 3.6 V and is specified
over an industrial temperature range of −40°C to +85°C. It is
available in a 64-lead LFCSP package.
The ADuCRF101 integrates a low power ARM Cortex-M3
processor. It is a 32-bit RISC machine, offering up to 1.25 DMIPS
peak performance. The ARM Cortex-M3 processor also has a
flexible 14-channel direct memory access (DMA) controller that
supports communication peripherals, serial peripheral interface
(SPI), UART, and I2C. Also provided on chip are 128 kB of
nonvolatile Flash/EE memory and 16 kB of SRAM.
Rev. A | Page 3 of 19
ADuCRF101
Data Sheet
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD = IOVDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, VREF = 1.25 V internal reference, fCORE = 16 MHz, TA = −40°C to +85°C,
unless otherwise noted. Default ADC sampling frequency of 167 kSPS (eight acquisition clocks and ADC clock frequency of 4 MHz).
Table 1.
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
DC ACCURACY
Single-ended input mode; applies to all ADC
input channels
Resolution
Integral Nonlinearity
12
−2.5 to
+1
−2.5 to
+0.5
1
Bits
LSB
VREF = 1.25 V from internal reference
VREF = 1.8 V from LDO
LSB
LSB
Differential Nonlinearity
DC Code Distribution
Guaranteed no missing code at 167 kSPS
Differential
Ratiometric Measurement
CALIBRATED ENDPOINT ERRORS
ADC input shorted, VCM = 0.4 V
Using two 10 kΩ resistors
1
5
LSB
LSB
Measured using the factory-set default values of
the ADCOF and ADCGN registers1
Offset Error
Gain Error
1.6
1
LSB
LSB
DYNAMIC PERFORMANCE
Signal-to-Noise Ratio (SNR)
Signal-to-Noise + Distortion Ratio
(SINAD)
fIN = 1 kHz sine wave
68
66
dB
dB
Total Harmonic Distortion (THD)
Spurious-Free Dynamic Range
(SFDR)
−69
70
dB
dB
ANALOG INPUT
Input Voltage Ranges2
Single-Ended Input
Differential Input
0
0
VREF
VCM VREF/2
V
V
Leakage Current
Excluding VREF pin
During ADC acquisition
100
20
nA
pF
Input Capacitance
ON-CHIP VOLTAGE REFERENCE
Output Voltage
1.25
5
V
mV
Accuracy
Measured at TA = 25°C
Reference Temperature Coefficient
Power Supply Rejection Ratio
(PSRR)
40
60
ppm/°C
dB
Output Impedance
2
5
Ω
ms
Internal VREF Power-On Time
TEMPERATURE SENSOR2
Voltage Output at 25°C
Voltage Temperature Coefficient
Thermal Impedance
0.47 µF external capacitor
Indicates die temperature
435
1.14
35
mV
mV/°C
°C/W
CURRENT CONSUMPTION
Cortex-M3 in Shutdown Mode
Cortex-M3 in Hibernate Mode
RF transceiver in sleep mode, memory not retained
Wake-up timer running from external 32 kHz
crystal, 8 kB of SRAM retained (8 kB not retained)
280
nA
RF Transceiver in Sleep Mode
Memory Retained
Memory Not Retained
1.9
1.75
µA
µA
Rev. A | Page 4 of 19
Data Sheet
ADuCRF101
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
mA
RF Transceiver in Receive Mode
12.8
RF Transceiver in Transmit Mode
Cortex-M3 in Active Mode
9 to 32
mA
RF transceiver idle (PHY_ON state or PHY_OFF
state)1
Static Current
Dynamic Current
START-UP TIME2
From Flexi Mode
2.0
210
mA
µA/MHz
FCLK is the Cortex-M3 clock or divided version of
the 16 MHz oscillator
3 to 5
FCLK
From Hibernate Mode
From Power-On and Shutdown
Mode
From wake-up event to user code execution
From applying power/asserting active external
interrupt to user code execution
13.4
55
µs
ms
RF Link, Waking Up from Sleep
Mode
Includes 310 µs for 26 MHz crystal startup
(7 pF load capacitor at TA = 25°C)
562.8
µs
POWER SUPPLY REQUIREMENTS
Power Supply Voltage Range2
POWER SUPPLY MONITOR
Trip Point Voltage
WATCHDOG TIMER2
Timeout Period
2.2
0
3.6
V
2
V
Programmable
512
sec
FLASH/EE MEMORY2
Endurance3
Data Retention4
10,000
10
Cycles
Years
TJ = 85°C
DIGITAL INPUTS
All digital inputs, excluding LFXTAL1 and XOSC26P
Input Current (Leakage Current)
VINH = IOVDD or VINH = 2.2 V, pull-up disabled;
VINL = 0 V, pull-up disabled
Excluding P2.4
10
10
nA
pF
Input Capacitance
LOGIC INPUTS
All logic inputs, including LFXTAL1 but excluding
XOSC26P
Input Low Voltage, VINL
Input High Voltage, VINH
LOGIC OUTPUTS
Output High Voltage, VOH
Output Low Voltage, VOL
32.768 kHz CRYSTAL
Input Current (Leakage Current)
LFXTAL1 Input Capacitance
LFXTAL2 Output Capacitance
26 MHz CRYSTAL
0.2 × IOVDD
0.36
V
V
0.7 × IOVDD
IOVDD − 0.4
ISOURCE = 1 mA
ISINK = 1 mA
V
V
32.768 kHz crystal, for use with timers
VINH = IOVDD or VINH = 2.2 V, VINL = 0 V
50
5
5
nA
pF
pF
XOSC26P Input Capacitance
XOSC26N Output Capacitance
10
10
16
pF
pF
INTERNAL HIGH FREQUENCY (HF)
OSCILLATOR
Processor clock by default
MHz
Tolerance
3
%
INTERNAL LOW FREQUENCY (LF)
OSCILLATOR
32.768
kHz
Tolerance
20
%
MCU CLOCK DIVIDER2
EXTERNAL CLOCK INPUT2
Range
Eight programmable core clock dividers
External MCU clock range allowed
1
128
32.768
16,000
kHz
1 For detailed information, see the UG-231 User Guide.
2 These values are not production tested; they are guaranteed by design and/or characterization data at production release.
3 Endurance is qualified to 10,000 cycles as per JEDEC Standard No. 22-A117 and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 170,000 cycles.
4 Retention lifetime equivalent at a junction temperature (TJ) of 85°C as per JEDEC Standard No. 22-A117. Retention lifetime derates with junction temperature.
Rev. A | Page 5 of 19
ADuCRF101
Data Sheet
RF LINK SPECIFICATIONS
Table 2.
Parameter
Test Conditions/Comments
Min
862
431
Typ
Max
928
464
Unit
MHz
MHz
FREQUENCY BANDS RANGE
PHASE-LOCKED LOOP
Channel Frequency Resolution
Phase Noise (In Band)
DATA RATE
396.7
−88
Hz
dBc/Hz
10 kHz offset, power amplifier (PA) output power = 10 dBm
2FSK/GFSK
1
300
kbps
DIFFERENTIAL POWER AMPLIFIER
(PA)
Transmit Power1
Transmit Power Variation vs.
Temperature
Programmable
From −40°C to +85°C, RF frequency = 868 MHz
−17 to +10
1
dBm
dB
Transmit Power Flatness
From 902 MHz to 928 MHz and 863 MHz to 870 MHZ
1
dB
SINGLE-ENDED PA
Transmit Power1
Transmit Power Variation vs.
Temperature
Programmable
From −40°C to +85°C, RF frequency = 868 MHz
−21 to 13
0.5
dBm
dB
Transmit Power Flatness
HARMONICS
From 431 MHz to 464 MHz and 862 MHz to 928 MHZ
1
dB
868 MHz, unfiltered conductive, PA output power =
10 dBm
Single-Ended PA
Second Harmonic
Third Harmonic
Fourth Harmonic
Differential PA
−29.8
−15.9
−24
dBc
dBc
dBc
Second Harmonic
Third Harmonic
Fourth Harmonic
OPTIMUM PA LOAD IMPEDANCE
−33.6
−15.6
−36.7
dBc
dBc
dBc
Single-Ended PA, Transmit
Mode
fRF = 915 MHz
fRF = 868 MHz
fRF = 433 MHz
31.2 + j10.4
23.5 + j9.7
35.4 + j3.4
Ω
Ω
Ω
Single-Ended PA, Receive Mode
fRF = 915 MHz
fRF = 868 MHz
7.3 − j126.3
6.9 − j134.2
Ω
Ω
Differential PA, Transmit Mode
Load impedance between RFIO_1P and RFIO_1N to ensure
maximum output power
fRF = 915 MHz
fRF = 868 MHz
fRF = 433 MHz
38.7 + j20.6
42.2 + j20.1
55.6 + j54.9
Ω
Ω
Ω
2FSK/GFSK INPUT SENSITIVITY,
BER
At BER = 10−3
1.0 kbps
38.4 kbps
300 kbps
Frequency deviation = 10 kHz, IF filter bandwidth = 100 kHz
Frequency deviation = 20.0 kHz, IF filter bandwidth = 100 kHz
Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz
At PER = 1%, packet length = 20 bytes, packet mode
−116
−107.5
−100.0
dBm
dBm
dBm
2FSK/GFSK INPUT SENSITIVITY,
PACKET ERROR RATE (PER)
1.0 kbps
38.4 kbps
300 kbps
Frequency deviation = 10 kHz, IF filter bandwidth = 100 kHz
Frequency deviation = 20.0 kHz, IF filter bandwidth = 100 kHz
Frequency deviation = 75 kHz, IF filter bandwidth = 300 kHz
Rev. A | Page 6 of 18
−114
−105.5
−96
dBm
dBm
dBm
Data Sheet
ADuCRF101
Parameter
Test Conditions/Comments
Min
Typ
Max
Unit
ADJACENT CHANNEL REJECTION
Continuous Wave (CW) Interferer Wanted signal 3 dB above the input sensitivity level
(BER = 10−3), CW interferer power level increased until
BER = 10−3, image calibrated
±±00 ꢀHz Channel Spacing
IF bandwidth (BW) = 100 ꢀHz, wanted signal:
fDEV = 1±.5 ꢀHz, DR = 50 ꢀbps
+±00 ꢀHz channel spacing/−±00 ꢀHz channel spacing
IF BW = 100 ꢀHz, wanted signal: fDEV = ±5 ꢀHz, DR = 100 ꢀbps
+300 ꢀHz channel spacing/−300 ꢀHz channel spacing
IF BW = 300 ꢀHz, wanted signal: fDEV = 75 ꢀHz, DR = 300 ꢀbps
+600 ꢀHz channel spacing/−600 ꢀHz channel spacing
Wanted signal 3 dB above the input sensitivity level
(BER = 10−3), modulated interferer with the same modulation
as the wanted signal; interferer power level increased until
BER = 10−3, image calibrated
36/36
39/39
38/30
dB
dB
dB
±300 ꢀHz Channel Spacing
±600 ꢀHz Channel Spacing
Modulated Interferer
±±00 ꢀHz Channel Spacing
±300 ꢀHz Channel Spacing
±600 ꢀHz Channel Spacing
CO-CHANNEL REJECTION
IF BW = 100 ꢀHz, wanted signal: fDEV = 1±.5 ꢀHz, DR = 50 ꢀbps
+±00 ꢀHz channel spacing/−±00 ꢀHz channel spacing
IF BW = 100 ꢀHz, wanted signal: fDEV = ±5 ꢀHz, DR = 100 ꢀbps
+300 ꢀHz channel spacing/−300 ꢀHz channel spacing
IF BW = 300 ꢀHz, wanted signal: fDEV = 75 ꢀHz, DR = 300 ꢀbps
+600 ꢀHz channel spacing/−600 ꢀHz channel spacing
34/34
39/35
dB
dB
35/16
−4
dB
dB
Wanted signal 10 dB above the input sensitivity level
(BER = 10−3), data rate = 38.4 ꢀbps, frequency deviation =
±0 ꢀHz
BLOCKING, ETSI EN 300 ±±0
Measurement procedure as per ETSI EN 300 ±±0-1 V±.3.1;
wanted signal 3 dB above the ETSI EN 300 ±±0 reference
sensitivity level of −99 dBm, IF bandwidth = 100 ꢀHz, data
rate = 38.4 ꢀbps, unmodulated interferer
±± MHz
±10 MHz
−±9
−±0.5
75
dBm
dBm
dB
WIDEBAND INTERFERENCE
REJECTION
Swept from 10 MHz to 100 MHz either side of the RF
frequency
IMAGE CHANNEL ATTENUATION
Measured as image attenuation at the IF filter output,
carrier wave interferer at 400 ꢀHz below the channel
frequency, 100 ꢀHz IF filter bandwidth
Uncalibrated±/calibrated
868 MHz
36/4±
dB
RSSI
Range at Input
Linearity
Absolute Accuracy
LNA INPUT IMPEDANCE
Receive Mode
fRF = 915 MHz
−97 to −±6
±±
±3
dBm
dB
dB
68.9 − j36.1
71.6 − j36.4
99.± − j31.3
Ω
Ω
Ω
fRF = 868 MHz
fRF = 433 MHz
Transmit Mode
fRF = 915 MHz
fRF = 868 MHz
8.6 + j±1.1
8.6 + j±0.4
8.± + j11.4
Ω
Ω
Ω
fRF = 433 MHz
RX SPURIOUS EMISSIONS3
Maximum < 1 GHz
Maximum > 1 GHz
At antenna input, unfiltered conductive
At antenna input, unfiltered conductive
−66
−51
dBm
dBm
1 Measured as the maximum unmodulated power.
± Measured with Bits IMAGE_REJECT_CAL_AMPLITUDE = 0x7 and Bits IMAGE_REJECT_CAL_PHASE = 0x16. For more detailed information, see the UG-±31 User Guide.
3 To achieve the relevant FCC/ETSI specifications, follow the matching and layout guideline information provided in the UG-±31 User Guide.
Rev. A | Page 7 of 18
ADuCRF101
Data Sheet
TIMING SPECIFICATIONS
I2C Timing
Capacitive load for each of the I2C bus lines, Cb = 400 pF maximum as per the I2C bus specifications. I2C timing is guaranteed by design
and not production tested.
I2C Timing in Fast Mode (400 kHz)
Table 3.
Parameter
Description
Min
Max
Unit
ns
ns
ns
ns
ns
ns
ns
μs
ns
ns
ns
tL
tH
Clock (I2CSCL) low pulse width
Clock (I2CSCL) high pulse width
Start condition hold time
Data (I2CSDA) setup time
Data (I2CSDA) hold time
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both clock and data
Fall time for both clock and data
Pulse width of spike suppressed
1300
600
600
100
0
600
600
1.3
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
20 + 0.1 Cb
20 + 0.1 Cb
0
300
300
50
tF
tSUP
I2C Timing in Standard Mode (100 kHz)
Table 4.
Parameter
Description
Min
4.7
4.0
4.7
250
0
4.0
4.0
4.7
Max
Unit
ꢀs
ꢀs
ꢀs
ns
ꢀs
ꢀs
ꢀs
ꢀs
ꢀs
ns
tL
tH
Clock (I2CSCL) low pulse width
Clock (I2CSCL) high pulse width
Start condition hold time
Data (I2CSDA) setup time
Data (I2CSDA) hold time
Setup time for repeated start
Stop condition setup time
Bus free time between a stop condition and a start condition
Rise time for both clock and data
Fall time for both clock and data
tSHD
tDSU
tDHD
tRSU
tPSU
tBUF
tR
1
300
tF
tBUF
tSUP
tR
I2CSDA (I/O)
MSB
LSB
ACK
MSB
tF
tDSU
tDSU
tDHD
tDHD
tPSU
tR
tSHD
tRSU
tH
1
2 TO
7
8
9
1
I2CSCL (I)
tL
tSUP
P
S
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 2. I2C Compatible Interface Timing
Rev. A | Page 8 of 18
Data Sheet
ADuCRF101
tBUF
tSUP
tR
I2CSDA (I/O)
MSB
LSB
ACK
MSB
tF
tDSU
tDSU
tDHD
tDHD
tPSU
tR
tSHD
tRSU
tH
1
2 TO
7
8
9
1
I2CSCL (I)
tL
tSUP
P
S
S(R)
tF
STOP
START
REPEATED
START
CONDITION CONDITION
Figure 2. I2C Compatible Interface Timing
Rev. A | Page 9 of 19
ADuCRF101
Data Sheet
SPI Timing
SPI timing is guaranteed by design and not production tested.
SPI Master Mode Timing
Table 5.
Parameter
Description
Min
Typ
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tSL
tSH
SCLK low pulse width1
(SPIDIV2 + 1) × tUCLK
(SPIDIV2 + 1) × tUCLK
0
SCLK high pulse width1
Data output valid after SCLK edge
Data output setup before SCLK edge1
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
tDAV
tDOSU
tDSU
tDHD
tDF
tDR
tSR
tSF
32.0
(SPIDIV2 + 1) × tUCLK
59.8
16.0
10.6
10.6
10.6
10.6
32.0
32.0
32.0
32.0
1 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
2 For more information about SPIDIV, see the UG-231 User Guide.
1/2 SCLK
CYCLE
3/4 SCLK
CYCLE
CS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
tDR
BIT 6 TO BIT 1
MOSI
MISO
MSB
LSB
MSB IN
tDSU
BIT 6 TO BIT 1
LSB IN
tDHD
Figure 3. SPI Master Mode Timing (Phase Mode = 1)
1 SCLK
CYCLE
3/4 SCLK
CYCLE
CS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDOSU
tDF
tDR
BIT 6 TO BIT 1
MOSI
MISO
MSB
LSB
MSB IN
tDSU
BIT 6 TO BIT 1
LSB IN
tDHD
Figure 4. SPI Master Mode Timing (Phase Mode = 0)
Rev. A | Page 10 of 19
Data Sheet
ADuCRF101
SPI Slave Mode Timing
Table 6.
Parameter
Description
Min
Typ
Max
Unit
tCS
CS to SCLK edge
12.9
ns
tSL
tSH
tDAV
tDSU
tDHD
tDF
tDR
tSR
tSF
tDOCS
tSFS
SCLK low pulse width1
(SPIDIV2 + 1) × tUCLK
(SPIDIV2 + 1) × tUCLK
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SCLK high pulse width1
62.5
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
Data output valid after CS edge
CS high after SCLK edge
47.4
25.8
12.9
10.6
10.6
10.6
10.6
32.0
32.0
32.0
32.0
59.8
12.9
1 tUCLK = 62.5 ns. It corresponds to the internal 16 MHz clock before the clock divider.
2 For more information about SPIDIV, see the UG-231 User Guide.
CS
tSFS
tCS
SCLK
(POLARITY = 0)
tSH
tSL
tSR
tSF
SCLK
(POLARITY = 1)
tDAV
tDF
tDR
MISO
MOSI
MSB
BIT 6 TO BIT 1
LSB
MSB IN
BIT 6 TO BIT 1
LSB IN
tDSU
tDHD
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
CS
tCS
tSFS
SCLK
(POLARITY = 0)
tSH
tSL
tSF
tSR
SCLK
(POLARITY = 1)
tDAV
tDOCS
tDF
tDR
MISO
MOSI
MSB
BIT 6 TO BIT 1
LSB
MSB IN
tDSU
BIT 6 TO BIT 1
LSB IN
tDHD
Figure 6. SPI Slave Mode Timing (Phase Mode = 0)
Rev. A | Page 11 of 19
ADuCRF101
Data Sheet
ABSOLUTE MAXIMUM RATINGS
.
TA = 25°C, unless otherwise noted
The exposed package paddle must be soldered to a metal pad
on the printed circuit board (PCB) and connected to ground.
Table 7.
THERMAL RESISTANCE
Parameter
Rating
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
AVDD, IOVDD, VDDBAT1, and VDDBAT2 to GND −0.3 V to +3.96 V
Digital Input Voltage to GND
Digital Output Voltage to GND
VREF to GND
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +3.96 V
−0.3 V to +2.1 V
2.5 kV
Table 8. Thermal Resistance
Package Type
θJA
Unit
Analog Inputs to GND
64-Lead LFCSP_VQ
35
°C/W
ESD (Human Body Model)
Temperature
ESD CAUTION
Operating Temperature Range
Storage Temperature Range
Junction Temperature
−40°C to +85°C
−65°C to +150°C
105°C
Peak Solder Reflow Temperature
Pb-Free Assemblies (30 sec)
260°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 12 of 19
Data Sheet
ADuCRF101
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
VDDRF1
RBIAS
1
2
3
4
5
6
7
8
9
48 P4.0/PWM0
47 RESET
VDDRF2
RFIO_1P
RFIO_1N
RFO2
46 BM/P0.6/IRQ2/CS3/RTS/PWM0
45 P0.7/IRQ3/CS4/CTS
44 IOVDD
43 P0.0/MISO
VDDBAT2
AVDD
ADuCRF101
42 P0.1/SCLK
41 P0.2/MOSI/PWM0
40 P2.4/IRQ8
TOP VIEW
(Not to Scale)
VREF
ADC0 10
ADC1 11
ADC2 12
ADC3 13
ADC4 14
ADC5 15
LVDD1 16
39 P0.3/IRQ1/CS0/ADCCONVST/PWM1
38 P2.6
37 P0.4/CS1/ECLKOUT
36 P0.5/CS2/ECLKIN
35 P1.0/RXD/IRQ4/MOSI/PWM2
34 P1.1/POR/TXD/PWM3
33 P1.2/PWM4
NOTES
1. THE EXPOSED PACKAGE PADDLE MUST BE SOLDERED TO A METAL PAD ON
THE PCB AND CONNECTED TO GROUND.
Figure 7. Pin Configuration
Table 9. Pin Function Descriptions
Pin
No.
Mnemonic
Description
1
VDDRF1
Voltage Regulator Output for RF Block. For regulator stability and noise rejection, place a
220 nF capacitor between this pin and ground.
2
3
RBIAS
VDDRF2
External Bias Resistor. Use a 36 kΩ resistor with 2% tolerance.
Voltage Regulator Output for RF Block. For regulator stability and noise rejection, place a
220 nF capacitor between this pin and ground.
4
5
6
7
8
RFIO_1P
RFIO_1N
RFO2
VDDBAT2
AVDD
LNA Positive Input in Receive Mode; Differential PA Positive Output in Transmit Mode.
LNA Negative Input in Receive Mode; Differential PA Negative Output in Transmit Mode.
Single-Ended PA Output.
Battery Terminal1. Supply for the LDOs used in the RF section of the transceiver.
Battery Terminal1. Supply for the analog circuits such as the ADC and ADC internal
reference, POR, PSM, and LDOs.
9
VREF
Internal 1.25 V ADC Reference. Place a 0.47 µF capacitor between this pin and ground.
ADC Input Channel 0. Input of DIFF0 pair in differential mode.2
ADC Input Channel 1. Input of DIFF0 pair in differential mode.2
ADC Input Channel 2. Input of DIFF1 pair in differential mode.2
ADC Input Channel 3. Input of DIFF1 pair in differential mode.2
ADC Input Channel 4. Input of DIFF2 pair in differential mode.2
ADC Input Channel 5. Input of DIFF2 pair in differential mode.2
10
11
12
13
14
15
16
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
LVDD1
On-Chip LDO Decoupling Output. Connect a 0.47 µF capacitor to the 1.8 V output to
ensure that the core operating voltage is stable. For correct operation, connect a 1 µF
capacitor between this pin and LVDD2 (Pin 18).
Rev. A | Page 13 of 19
ADuCRF101
Data Sheet
Pin
No.
Mnemonic
Description
17
VDDVCO
Voltage Regulator Output for Voltage Controlled Oscillator (VCO). For regulator stability
and noise rejection, place a 220 nF capacitor between this pin and ground.
18
LVDD2
On-Chip LDO Decoupling Output. Connect a 0.47 µF capacitor to the 1.32 V output to
ensure that the core operating voltage is stable. For correct operation, connect a 1 µF
capacitor between this pin and LVDD1( Pin 16).
19
20
21
22
23
24
SWDIO
GND
IOVDD
SWCLK
VCOGUARD
VDDSYNTH
Serial Wire Bidirectional Data.
Ground. Connect this pin to the exposed pad.
General-Purpose I/O Supply1. Connect this pin to the battery terminal.
Serial Wire Debug Clock.
Guard, Screen for VCO. Connect this pin to VDDVCO.
Voltage Regulator Output for Synthesizer. For regulator stability and noise rejection,
place a 220 nF capacitor between this pin and ground.
25
CWAKE
External Capacitor for Wake-Up Control. Place a 150 nF capacitor between this pin and
ground.
26
27
28
29
XOSC26P
XOSC26N
DGUARD
VDD_DIG1
Connect the 26 MHz reference crystal between this pin and XOSC26N (HFXTAL).3
Connect the 26 MHz reference crystal between this pin and XOSC26P (HFXTAL).
Internal Guard, Screen for Digital Cells. Connect this pin to VDD_DIG1.
Voltage Regulator Output for the Digital Section of the Transceiver. For regulator stability
and noise rejection, place a 220 nF capacitor between this pin and ground.
30
P1.5/IRQ6/I2CSDA/PWM7
General-Purpose Input and Output Port 1.5 (P1.5).
External Interrupt 6 (IRQ6).
I2C Serial Data (I2CSDA).
PWM Channel 7 (PWM7).
31
P1.4/IRQ5/I2CSCL/PWM6
General-Purpose Input and Output Port 1.4 (P1.4).
External Interrupt 5 (IRQ5).
I2C Serial Clock (I2CSCL).
PWM Channel 6 (PWM6).
32
33
34
P1.3/PWM5
General-Purpose Input and Output Port 1.3 (P1.3).
PWM Channel 5 (PWM5).
General-Purpose Input and Output Port 1.2 (P1.2).
PWM Channel 4 (PWM4).
General-Purpose Input and Output Port 1.1 (P1.1).
Power-On Reset Output (POR).
UART TXD (TXD).
P1.2/PWM4
P1.1/POR/TXD/PWM3
PWM Channel 3 (PWM3).
35
P1.0/RXD/IRQ4/MOSI/PWM2
General-Purpose Input and Output Port 1.0 (P1.0).
UART RXD (RXD).
External Interrupt 4 (IRQ4).
SPI1 Master Out, Slave In (MOSI).
PWM Channel 2 (PWM2).
36
37
P0.5/CS2/ECLKIN
General-Purpose Input and Output Port 0.5 (P0.5).
SPI1 Chip Select 2 (CS2).
External Clock Input (ECLKIN).
General-Purpose Input and Output Port 0.4 (P0.4).
SPI1 Chip Select 1 (CS1).
P0.4/CS1/ECLKOUT
External Clock Output (ECLKOUT).
38
39
P2.6
General-Purpose Input and Output Port 2.6. Do not connect this pin. This pin is
connected internally to the RF transceiver. It can be used for BER measurements.
General-Purpose Input and Output Port 0.3 (P0.3).
External Interrupt 1 (IRQ1).
P0.3/IRQ1/CS0/ADCCONVST/PWM1
SPI1 Chip Select 0 (CS0).
ADC Convert Start (ADCCONVST).
PWM Channel 1 (PWM1).
Rev. A | Page 14 of 19
Data Sheet
ADuCRF101
Pin
No.
Mnemonic
Description
40
P2.4/IRQ8
General-Purpose Input and Output Port 2.4 (P2.4). Do not connect this pin. This pin is
connected internally to the RF transceiver and can be used for debug purposes to
monitor RF transceiver interrupts.
External Interrupt 8 (IRQ8).
41
P0.2/MOSI/PWM0
General-Purpose Input and Output Port 0.2 (P0.2).
SPI1 Master Out, Slave In (MOSI).
PWM Channel 0 (PWM0).
42
43
P0.1/SCLK
P0.0/MISO
General-Purpose Input and Output Port 0.1 (P0.1).
SPI1 Serial Clock (SCLK).
General-Purpose Input and Output Port 0.0 (P0.0).
SPI1 Master In, Slave Out (MISO).
44
45
IOVDD
P0.7/IRQ3/CS4/CTS
General-Purpose I/O Supply1. Connect this pin to the battery terminal.
General-Purpose Input and Output Port 0.7 (P0.7).
External Interrupt 3 (IRQ3).
SPI1 Chip Select 4 (CS4).
UART Handshake (CTS).
46
BM/P0.6/IRQ2/CS3/RTS/PWM0
Boot Mode (BM). The ADuCRF101 enters serial download mode if P0.6 is low during, and
for a short time after, an external reset event. It executes user code after any reset event or
if P0.6 is high during an external reset event.
General-Purpose Input and Output Port 0.6 (P0.6).
External Interrupt 2 (IRQ2).
SPI1 Chip Select 3 (CS3).
UART Handshake (RTS).
PWM Channel 0 (PWM0).
47
48
RESET
Reset, Active Low. A low signal on this pin for 24 system clocks causes the device to reset.
General-Purpose Input and Output Port 4.0 (P4.0).
PWM Channel 0 (PWM0).
P4.0/PWM0
49
50
51
52
53
P4.1/PWM1
P4.2/PWM2
P4.3/PWM3
P4.4/PWM4
P4.5/PWM5
General-Purpose Input and Output Port 4.1 (P4.1).
PWM Channel 1 (PWM1).
General-Purpose Input and Output Port 4.2 (P4.2).
PWM Channel 2 (PWM2).
General-Purpose Input and Output Port 4.3 (P4.3).
PWM Channel 3 (PWM3).
General-Purpose Input and Output Port 4.4 (P4.4).l
PWM Channel 4 (PWM4).
General-Purpose Input and Output Port 4.5 (P4.5).
PWM Channel 5 (PWM5).
54
55
56
LFXTAL2
LFXTAL1
VDD_DIG2
32.768 kHz Watch Crystal Input for Wake-Up Timers.
32.768 kHz Watch Crystal Output for Wake-Up Timers.
Voltage Regulator Output for the Digital Section of the Transceiver. For regulator stability
and noise rejection, place a 220 nF capacitor between this pin and ground.
57
58
VDDBAT1
P4.6/PWM6
Battery Terminal1. Supply for the digital section of the transceiver and GPIOs.
General-Purpose Input and Output Port 4.6 (P4.6).
PWM Channel 6 (PWM6).
59
P4.7/PWM7
General-Purpose Input and Output Port 4.7 (P4.7).
PWM Channel 7 (PWM7).
60
61
ADCVREF
Transceiver ADC Reference Output. For adequate noise rejection, place a 220 nF
capacitor between this pin and ground
General-Purpose Input and Output Port 3.2 (P3.2).
PWM Synchronization (PWMSYNC).
P3.2/PWMSYNC
62
P3.3/PWMTRIP
General-Purpose Input and Output Port 3.3 (P3.3).
PWM Safety Cutoff (PWMTRIP).
Rev. A | Page 15 of 19
ADuCRF101
Data Sheet
Pin
No.
Mnemonic
P3.4
P3.5
Description
63
64
General-Purpose Input and Output Port 3.4.
General-Purpose Input and Output Port 3.5.
65
EP
Exposed Pad. The exposed package paddle must be soldered to a metal pad on the PCB
and connected to ground.
1 VDDBAT1, VDDBAT2, AVDD, and IOVDD must all be connected together.
2 For detailed information about the DIFF0 to DIFF2 differential input pairs, see theUG-231 User Guide.
3 For detailed information about HFXTAL, a 26 MHz external crystal used to set the RF transceiver communication frequency, see the UG-231 User Guide.
Rev. A | Page 16 of 19
Data Sheet
ADuCRF101
TYPICAL PERFORMANCE CHARACTERISTICS
15
35
30
25
20
15
10
5
10
5
0
–5
–10
2.2V
3.3V
3.6V
–15
–20
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
PA LEVEL MCR
–20
–15
–10
–5
0
5
10
15
TRANSCEIVER OUTPUT POWER (dBm)
Figure 8. Single-Ended PA at 868 MHz, Output Power vs. PA Level
MCR Setting and VDD
Figure 11. Differential PA at 868 MHz, Transceiver Supply Current vs.
Transceiver Output Power; VDD = 3.3 V
15
10
5
90
80
70
60
50
40
30
20
10
0
0
–40°C, 2.2V
–40°C, 3.3V
–40°C, 3.6V
+25°C, 2.2V
+25°C, 3.3V
+25°C, 3.6V
+85°C, 2.2V
+85°C, 3.3V
+85°C, 3.6V
–5
–10
–15
–20
–10
0
4
8
12 16 20 24 28 32 36 40 44 48 52 56 60 64
PA LEVEL MCR
768 788 808 828 848 868 888 908 928 948 968
INTERFERER FREQUENCY (MHz)
Figure 9. Differential PA at 868 MHz; Output Power vs. PA Level MCR Setting,
Temperature, and VDD
Figure 12. Typical Receiver Wideband Blocking at 868 MHz, VDD = 3.3 V,
Data Rate = 38.4 kbps, Frequency Deviation = 20 kHz,
Measured as per ETSI EN 300 220
10
–10
–30
–50
–70
–90
35
30
25
20
15
10
5
–110
858 860 862 864 866 868 870 872 874 876 878
–20
–15
–10
–5
0
5
10
15
INTERFERER FREQUENCY (MHz)
TRANSCEIVER OUTPUT POWER (dBm)
Figure 13. Typical Receiver Blocking at 868 MHz, VDD = 3.3 V,
Data Rate = 38.4 kbps, Frequency Deviation = 20 kHz,
Measured as per ETSI EN 300 220
Figure 10. Single-Ended PA at 868 MHz, Transceiver Supply Current vs.
Transceiver Output Power, VDD = 3.3 V
Rev. A | Page 17 of 19
ADuCRF101
Data Sheet
–20
10
8
1.0
0.8
MEAN RSSI
IDEAL RSSI
RSSI ERROR
SINGLE-ENDED PA
DIFFERENTIAL
–30
–40
–50
–60
–70
–80
–90
–100
6
0.6
4
0.4
2
0.2
0
0
–2
–4
–6
–8
–10
–0.2
–0.4
–0.6
–0.8
–1.0
–100
–90
–80
–70
–60
–50
–40
–30
–20
–60
–40
–20
0
20
40
60
80
100
ACTUAL RECEIVED POWER (dBm)
TEMPERATURE (°C)
Figure 14. RSSI vs. Actual Received Power, 868 MHz, FSK,
Data Rate = 38.4 kbps, Frequency Deviation = 20 kHz,
IF Bandwidth = 100 kHz
Figure 15. Single-Ended and Differential PA Output Power (POUT) Deviation vs.
Temperature; 868 MHz, VDD = 3.3 V
Rev. A | Page 18 of 19
Data Sheet
ADuCRF101
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.30
0.23
0.18
0.60 MAX
0.60
MAX
PIN 1
INDICATOR
1
49
48
64
PIN 1
INDICATOR
8.85
8.75 SQ
8.65
0.50
BSC
EXPOSED
PAD
5.25
5.10 SQ
4.95
0.50
0.40
0.30
33
32
16
17
0.25 MIN
BOTTOM VIEW
7.50 REF
TOP VIEW
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
0.05 MAX
0.02 NOM
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SEATING
PLANE
0.20 REF
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4
Figure 16. 64-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Description
Package Option
CP-64-5
CP-64-5
ADuCRF101BCPZ128
ADuCRF101BCPZ128R7
ADuCRF101BCPZ128RL
EV-ADuCRF101MK3Z
EV-ADuCRF101MK1Z
EV-ADuCRF101QSP1Z
EV-ADuCRF101QSP3Z
EV-ADuCRF101QS1Z
EV-ADuCRF101QS3Z
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
64-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Evaluation Board for 433 MHz Operation
Evaluation Board for 868 MHz/915 MHz Operation
QuickStart Plus for 868 MHz/915 MHz Operation
QuickStart Plus for 433 MHz Operation
CP-64-5
QuickStart for 868 MHz/915 MHz Operation
QuickStart for 433 MHz Operation
1 Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2013–2014 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11045-0-11/14(A)
Rev. A | Page 19 of 19
相关型号：
©2020 ICPDF网 联系我们和版权申明