ADUCRF101CCPZ128 [ADI]

IC RISC MICROCONTROLLER, Microcontroller;


型号：	ADUCRF101CCPZ128
厂家：	ADI
描述：	IC RISC MICROCONTROLLER, Microcontroller 微控制器外围集成电路
文件：	总13页 (文件大小：231K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Precision Analog Microcontroller with RF

Transceiver, ARM Cortex™-M3

ADuCRF101

Preliminary Technical Data

FEATURES

External Watch crystal for wakeup timer

16 MHz internal Oscillator with 8-way Programmable

Divider

Analog I/O

6-Channel 14-bit or 12-bit ADC

Single ended and differential inputs

Programmable data rate up to 842 kSPS

On-Chip Voltage Reference and Temperature Sensor

Power

Memory

128 k Bytes /64 k Bytes Flash/EE Memory, 16 k Bytes /8 k

Bytes SRAM

20000 cycle Flash/EE endurance

10 year Flash/EE retention

In-circuit download via Serial Wire and UART

On-Chip Peripherals

UART, I²C and SPI Serial I/O

28-Pin GPIO Port

2 General Purpose Timers

Wake-up Timer

Watchdog Timer

Supply Range: 2.2 V to 3.6 V

Power Consumption

680 nA, in power down mode, non-retained state

1.6 µA, in power down mode, processor memory and

transceiver memory retained

190 µA / MHz, Cortex in Active mode

12.8 mA transceiver in receive mode, Cortex in power

down mode

8-Channel PWM

9 mA to 32 mA transceiver in transmit mode, Cortex in

power down mode

RF Transceiver

Frequency bands

862 MHz to 928 MHz

Packages and Temperature Range

64 lead LFCSP (9mm x 9mm) package –40°C to 85°C

Tools

Low-Cost Development System

Third-Party Compiler and emulator tool Support

431 MHz to 464 MHz

Multiple Configurations supported

Receiver sensitivity (BER)

-107.5 dBm at 38.4 kbps, 2FSK

Single ended and differential PA

Low External BOM

Microcontroller

ARM Cortex™-M3 32-bit processor

Serial Wire download and debug

APPLICATIONS

Battery powered wireless sensor

Medical telemetry systems

Industrial and home automation

Asset tracking

Security systems (access systems)

Health and fitness applications

FUNCTIONAL BLOCK DIAGRAM

COMMUNICATIONS

6 I/P

MUX

12/14-BIT

SAR ADC

LOW POWER

RF TRANSCEIVER

WIRELESS

TEMP

SENSOR

SERIAL

WIRE

GPIOS

SPI

I2C

UART

PWM

WIRED

BAND GAP

REFERENCE

LOW POWER PROCESSING

PRECISION DATA

ACQUISITION

POR

OSC

CORTEX M3

Processor

64/128K BYTES

FLASH/EE

8/16K BYTES

SRAM

WATCHDOG

TIMER

2xGEN PURPOSE

TIMERS

INTERRUPT

CONTROLLER

WAKE-UP

TIMER

ADuCRF101

ON-CHIP PERIPHERALS

Figure 1. ADuCF101 Block Diagram

Rev. PrG

Information furnished by Analog Devices is believed to be accurate and reliable.

However, no responsibility is assumed by Analog Devices for its use, nor for any

infringements of patents or other rights of third parties that may result from its use.

Specifications subject to change without notice. No license is granted by implication

or otherwise under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

www.analog.com

Fax: 781.326.8703

ADuCRF101

Preliminary Technical Data

TABLE OF CONTENTS

Features .............................................................................................. 1

ESD Caution...................................................................................9

Pin Configuration and Function Descriptions........................... 10

Outline Dimensions....................................................................... 13

Ordering Guide .......................................................................... 13

Functional block diagram................................................................ 1

General Description ......................................................................... 3

Specifications..................................................................................... 4

Absolute Maximum Ratings............................................................ 9

Rev. PrG | Page 2 of 13

Preliminary Technical Data

GENERAL DESCRIPTION

ADuCRF101

A 16 MHz on-chip oscillator generates the system clock. This

clock can be internally divided for the processor to operate at

lower frequency for power saving reasons. A low power internal

32 kHz oscillator is available and can used to clock the timers.

There are two general-purpose timers, a wake-up timer and a

system watchdog timer.

The ADuCRF101 is a fully integrated data acquisition solution

designed for low power wireless applications. It features a 12-bit

or 14-bit ADC, a low power Cortex™-M3 processor from ARM®,

a 431 MHz to 464 MHz and 862 MHz to 928 MHz RF

transceiver, and Flash/EE memory packaged in a 9 mm × 9 mm

LFCSP.

A range of communication peripherals can be configured as

required in a specific application. These peripherals include

UART, I²C, SPI, GPIO ports, PWM and RF transceiver.

The acquisition section consists of a 12-bit / 14-bit ADC SAR

ADC. The six inputs can be configured as single ended or

differential modes. When configured in single ended mode,

they can be used for ratiometric measurements on sensors,

powered when required from the internal LDO. An internal

battery monitor channel and an on-chip temperature sensor are

also available.

The RF transceiver communicates in the 431 MHz to 464 MHz

and 862 MHz to 928 MHz frequency bands using multiple

configurations.

On-chip factory firmware supports in-circuit serial download

via the UART while nonintrusive emulation and program

download is also supported via the serial wire interface. These

features are incorporated into a low cost development system

supporting this precision analog microcontroller family.

This wireless data acquisition system is designed to operate in

battery-powered applications where low power is critical. The

device can be configured in normal operating mode or different

low power modes under direct program control. In flexi mode

any peripheral can operate and wake-up the device. In

hibernate mode the internal wake-up timer remains active. In

shutdown mode only an external interrupt can wake-up the

device.

The parts operate from 2.2 V to 3.6 V and are specified over an

industrial temperature range of −40°C to +85°C.

Three versions of the ADuCRF101 are available:

•

14-bit ADC, 128 k Byte Flash and 16 k Byte SRAM

12-bit ADC, 128 k Byte Flash and 16 k Byte SRAM

12-bit ADC, 64 k Byte Flash and 8 k Byte SRAM

The ADuCRF101 integrates a low power Cortex-M3 processor

from ARM. It is a 32-bit RISC machine, offering up to 1.25

DMIPS peak performance. The Cortex-M3 processor also has a

flexible 14-channel DMA controller supporting communication

peripherals SPI, UART and I²C. 64 kB / 128 kB of nonvolatile

Flash/EE memory and 8 kB / 16 kB of SRAM are also provided

on-chip.

Rev. PrG| Page 3 of 13

ADuCRF101

Preliminary Technical Data

SPECIFICATIONS

ELECTRICAL SPECIFICATIONS

AVDD = IOVDD = VDDBAT1 = VDDBAT2 = 2.2 V to 3.6 V, V_REF= 1.25 V internal reference, f_CORE= 16 MHz, T_A= −40°C to +85°C

unless otherwise noted. Default ADC sampling frequency: eight acquisition clocks and ADC clock frequency of 4 MHz.

Table 1. 12 Bit ADC channel specification

Parameter

Test Conditions / Comments

Min

Typ

Max

Unit

DC ACCURACY

Single ended input mode. Applies to all

ADC input channels.

Resolution

Integral Nonlinearity

Bits

LSB

V_REF= 1.25 V from internal reference

V_REF= 1.8 V from LDO

Guaranteed no missing code

ADC input is a DC voltage

Differential Nonlinearity

DC Code Distribution

CALIBRATED ENDPOINT ERRORS

Measured using the factory-set default

values ADCOF and ADCGN.

Offset Error

Offset Error Match

Gain Error

0.6

0.25

1.25

0.25

LSB

Gain Error Match

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion

Peak Harmonic or Spurious Noise

(PHSN)

f_IN= 10 kHz sine wave.

TBD

Channel-to-Channel Crosstalk

Measured on adjacent channels

TBD

Table 2. 14 Bit ADC channel specification

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ADC SPECIFICATIONS

DC ACCURACY

Single ended input mode. Applies to all

ADC input channels.

Resolution

Integral Nonlinearity

Bits

LSB

V_REF= 1.25 V from internal reference

V_REF= 1.8 V from LDO

Guaranteed no missing code

ADC input is a DC voltage

Differential Nonlinearity

DC Code Distribution

CALIBRATED ENDPOINT ERRORS

Measured using the factory-set default

values ADCOF and ADCGN.

Offset Error

Offset Error Match

Gain Error

2.5

LSB

Gain Error Match

DYNAMIC PERFORMANCE

Signal-to-Noise Ratio (SNR)

Total Harmonic Distortion

Peak Harmonic or Spurious Noise

(PHSN)

f_IN= 10 kHz sine wave.

TBD

Channel-to-Channel Crosstalk

Measured on adjacent channels

Rev. PrG | Page 4 of 13

TBD

Preliminary Technical Data

ADuCRF101

Table 3. ADuCRF101 Specification

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

ADC SPECIFICATIONS

ANALOG INPUT

Input Voltage Ranges¹

Single ended input

Differential input

V_REF

V_CMV_REF/2

Leakage Current

100

µs

Input Capacitance

ADC Power-up Time

ON-CHIP VOLTAGE REFERENCE

Output Voltage

During ADC Acquisition

Excludes reference power up time

1.25

Accuracy

Measured at T_A= 25°C

Reference Temperature Co

Power Supply Rejection Ratio

Output Impedance

Internal V_REFPower-On Time

TEMPERATURE SENSOR¹

Voltage Output at 25°C

Voltage TC

Accuracy

Thermal impedance

CURRENT CONSUMPTION

ppm/°C

Ω

0.47µF external capacitor

Indicates die temperature

TBD

mV/°C

°C

MCU in low power mode

RF transceiver in sleep mode, memory

not retained

Cortex in SHUTDOWN mode

Wake up timer running from external

32 kHz crystal, 8 kB of SRAM retained

(8 kB non-retained)

680

Cortex in HIBERNATE mode

RF transceiver in sleep mode,

memory retained

RF transceiver in sleep mode,

memory not retained

1.6

µA

1.38

RF transceiver in receive mode

RF transceiver in transmit mode

Cortex in ACTIVE mode

12.8

9 to 32

RF transceiver idle (PHY_ON or

PHY_OFF)

Static current

Dynamic current

STARTUP TIME¹

1.8

190

µA/MHz

From applying power/asserting active

external interrupt to user code

execution

From Power On and SHUTDOWN

mode

From FLEXI mode

FCLK is the Cortex-M3 clock or divided

version of the 16 MHz oscillator.

From wake up event to user code

execution

Includes 310 µs for 26 MHz crystal start

up (7 pF load capacitor at T_A= 25 ⁰C)

FCLK

µs

3 to 5

12.5

562.8

From HIBERNATE mode

RF link waking up from sleep mode

POWER SUPPLY REQUIREMENTS

Power Supply Voltage Range¹

POWER SUPPLY MONITOR

Trip Point voltage

µs

2.2

3.6

POWER-ON-RESET

1.67

Watchdog Timer¹

Timeout Period

Programmable

512

Rev. PrG| Page 5 of 13

ADuCRF101

Preliminary Technical Data

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Flash/EE MEMORY ¹

Endurance²

Data Retention³

20,000

Cycles

Years

T_J= 85°C

Digital Inputs

All digital inputs, excluding LFXTAL1

and XOSC26P

Input Current (leakage current)

V_INH= IOVDD or V_INH= 2.2V, pull up

disabled.

_INL= 0V, pull up disabled.

Input Capacitance

Logic Inputs

All Logic inputs, including LFXTAL1,

excluding XOSC26P

VINL, Input Low Voltage

VINH, Input High Voltage

Logic Outputs

VOH, Output High Voltage

VOL, Output Low Voltage

32.768 kHz CRYSTAL

0.2 x IOVDD

0.36

0.7 x IOVDD

IOVDD – 0.4

I_source= 1 mA

I_sink= 1 mA

32.768 kHz crystal, for use with timers

and/or RF transceiver wake up

controller.

Input Current (leakage current)

V_INH= IOVDD or V_INH= 2.2 V

_INL= 0 V.

LFXTAL1 Input Capacitance

LFXTAL2 Output Capacitance

26 MHz CRYSTAL

XOSC26P Input Capacitance

XOSC26N Output Capacitance

INTERNAL HF OSCILLATOR

Tolerance

Processor clock by default

MHz

INTERNAL LF OSCILLATOR

Tolerance

32.768

kHz

MCU CLOCK DIVIDER¹

EXTERNAL CLOCK INPUT1

Range

8 programmable core clock dividers.

External MCU clock range allowed

128

32.768

16000

kHz

RF LINK SPECIFICATIONS

FREQUENCY RANGE

862

431

928

464

MHz

PHASE-LOCKED LOOP

Channel Frequency Resolution

Phase Noise (In-Band)

396.7

-88

dBc/Hz

10 kHz offset, PA output power = 10

dBm

DATA RATE

2FSK

OOK

2.4

300

19.2

kbps

Manchester Encoding enabled

(Manchester chip rate = 2 x datarate)

Data rate resolution

100

bps

DIFFERENTIAL PA

Transmit Power⁴

Transmit Power variation V’s

Temperature

Programmable.

From -40 °C to +85 °C, RF Frequency =

868 MHz

-17 to 10

dBm

Transmit Power Flatness

From 902 MHz to 928 MHz and 863

MHz to 870 MHZ

SINGLE ENDED PA

Transmit Power⁴

Programmable.

-21 to 13

dBm

Rev. PrG | Page 6 of 13

Preliminary Technical Data

ADuCRF101

Parameter

Test Conditions/Comments

Min

Typ

Max

Unit

Transmit Power variation V’s

Temperature

From -40°C to +85°C, RF Frequency =

868 MHz

0.5

Transmit Power Flatness

From 431 MHz to 464 MHz and 862

MHz to 928 MHZ

HARMONICS

868 MHz, unfiltered conductive, PA

output power = 10 dBm

Differential PA

Second Harmonic

Third Harmonic

All Other Harmonics

OPTIMUM PA LOAD IMPEDANCE

Single-Ended PA, in Transmit Mode

f_RF= 915 MHz

TBD

dBc

31.2+j10.4

23.5+j9.7

35.4+j3.4

Ω

f_RF= 868 MHz

f_RF= 433 MHz

Differential PA, in Transmit Mode

Load impedance between RFIO_1P and

RFIO_1N to ensure maximum output

power

f_RF= 915 MHz

f_RF= 868 MHz

f_RF= 433 MHz

38.7+j20.6

42.2+j20.1

55.6+j54.9

Ω

MODULATION

Deviation Frequency Resolution

100

2FSK/GFSK INPUT SENSITIVITY, BIT

ERROR RATE (BER)

At BER = 10⁻³

1.0 kbps

38.4 kbps

300 kbps

Frequency deviation = 10 kHz, IF filter

bandwidth = 100 kHz

Frequency deviation = 19.2 kHz, IF filter

bandwidth = 100 kHz

Frequency deviation = 75 kHz, IF filter

bandwidth = 300 kHz

-116

dBm

-107.5

-100.5

2FSK/GFSK INPUT SENSITIVITY, PACKET

ERROR RATE (PER)

At PER = 1%, packet length =20 bytes,

packet mode

1.0 kbps

38.4 kbps

300 kbps

Frequency deviation = 10 kHz, IF filter

bandwidth = 100 kHz

Frequency deviation = 19.2 kHz, IF filter

bandwidth = 100 kHz

Frequency deviation = 75 kHz, IF filter

bandwidth = 300 kHz

-115.5

-106

-98

dBm

ADJACENT CHANNEL REJECTION

CW Interferer

Wanted signal 3 dB above the input

sensitivity level (BER = 10⁻³), CW

interferer power level increased until

BER = 10⁻³, image calibrated

200 kHz Channel Spacing

300 kHz Channel Spacing

600 kHz Channel Spacing

Modulated Interferer

IF BW = 100 kHz, wanted signal: F_DEV

12.5 kHz, DR = 50 kbps

IF BW = 100 kHz, wanted signal: F_DEV

25 kHz, DR = 100 kbps

IF BW = 300 kHz, wanted signal: F_DEV

75 kHz, DR = 300 kbps

Wanted signal 3 dB above the input

sensitivity level (BER = 10⁻³), modulated

interferer with the same modulation as

the wanted signal; interferer power

level increased until BER = 10⁻³, image

calibrated

200 kHz Channel Spacing

IF BW = 100 kHz, wanted signal: F_DEV

Rev. PrG| Page 7 of 13

ADuCRF101

Preliminary Technical Data

Parameter

Test Conditions/Comments

12.5 kHz, DR = 50 kbps

IF BW = 100 kHz, wanted signal: F_DEV

25 kHz, DR = 100 kbps

IF BW = 300 kHz, wanted signal: F_DEV

75 kHz, DR = 300 kbps

Desired signal 10 dB above the input

sensitivity level (BER = 10⁻³), data rate =

38.4 kbps, frequency deviation = 20

kHz.

Min

Typ

-4

Max

Unit

300 kHz Channel Spacing

600 kHz Channel Spacing

CO-CHANNEL REJECTION

BLOCKING, ETSI EN 300 220

Measurement procedure as per ETSI EN

300 220-1 V2.3.1; desired signal 3 dB

above the ETSI EN 300 220 reference

sensitivity level of −99 dBm, IF

bandwidth =100 kHz, data rate = 38.4

kbps, unmodulated interferer.

2 MHz

10 MHz

-28

-20.5

dBm

WIDEBAND INTERFERENCE REJECTION

Swept from 10 MHz to 100 MHz either

side of the RF frequency

IMAGE CHANNEL ATTENUATION

Measured as image attenuation at the

IF filter output, carrier wave interferer at

400 kHz below the channel frequency,

100 kHz IF filter bandwidth

868 MHz

RSSI

Uncalibrated⁵/calibrated

36/45

Range at Input

−97 to

−26

dBm

Linearity

Absolute Accuracy

LNA INPUT IMPEDANCE

Receive Mode

f_RF= 915 MHz

f_RF= 868 MHz

f_RF= 433 MHz

68.9-j36.1

71.6-j36.4

99.2-j31.3

Ω

Transmit Mode

f_RF= 915 MHz

f_RF= 868 MHz

8.6+j21.1

8.6+j20.4

8.2+j11.4

Ω

f_RF= 433 MHz

RX SPURIOUS EMISSIONS

Maximum <1 GHz

Maximum >1 GHz

At antenna input, unfiltered conductive

TBD

dBm

¹These numbers are not production tested, but are guaranteed by design and/or characterization data at production release.

²Endurance is qualified to 20,000 cycles as per JEDEC Std. 22 Method A117 and measured at −40°C, +25°C, and +85°C. Typical endurance at 25°C is 170,000 cycles.

³Retention lifetime equivalent at a junction temperature (T_J) of 85°C as per JEDEC Std. 22 Method A117. Retention lifetime derates with junction temperature.

⁴Measured as the maximum unmodulated power.

⁵Measured with IMAGE_REJECT_CAL_AMPLITUDE = 0x7 and IMAGE_REJECT_CAL_PHASE = 0x16.

Rev. PrG | Page 8 of 13

Preliminary Technical Data

ADuCRF101

ABSOLUTE MAXIMUM RATINGS

T_A= 25°C unless otherwise noted

ESD CAUTION

Table 4.

Parameter

Rating

AVDD, IOVDD, VDDBAT1 and

VDDBAT2 to GND

−0.3 V to 3.96 V

Digital Input Voltage to GND

Digital Output Voltage to GND

V_REFto GROUND

−0.3 V to 3.96 V

−0.3 V to 2.1 V

–40°C to +85°C

–65°C to +150°C

105°C

Analog Inputs to GND

Operating Temperature Range

Storage Temperature Range

Junction Temperature

The exposed paddle of the LFCSP package should be connected

to ground.

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

θ_JAThermal Impedance

64-Pin LFCSP _VQ

ESD (Human Body Model)

Peak Solder Reflow Temperature

Pb-Free Assemblies (30 s)

25°C/W

1.5 kV

260°C

Rev. PrG| Page 9 of 13

ADuCRF101

Preliminary Technical Data

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

PIN 1

IDENTIFIER

VDDRF1

RBIAS

48 P4.0

47 RESET

46 P0.6

45 P0.7

VDDRF2

RFIO_1P

RFIO_1N

RF02

IOVDD

43 P0.0

42 P0.1

41 P0.2

40 P2.4

39 P0.3

38 P2.6

37 P0.4

36 P0.5

VDDBAT2

ADuCRF101

TOP VIEW

(Not to Scale)

AVDD

VREF

ADC0 10

ADC1 11

ADC2 12

ADC3 13

ADC4 14

ADC5 15

35 P1.0

34 P1.1

LVDD1

P1.2

Figure 8. 64-Lead LFCSP_VQ Pin Configuration

Table 5. Pin Function Descriptions

No.

Mnemonic

Description

VDDRF1

Voltage Regulator output for RF block. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

RBIAS

VDDRF2

External bias resistor. A 36 kΩ resistor with 2% tolerance should be used.

Voltage Regulator output for RF block. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

RFIO_1P

RFIO_1N

RF02

LNA Positive Input in Receive Mode. Differential PA Positive Output in Transmit Mode.

LNA Negative Input in Receive Mode. Differential PA Negative Output in Transmit Mode.

Single ended PA output.

VDDBAT2 ⁶

AVDD⁶

VREF

ADC0

ADC1

ADC2

ADC3

ADC4

ADC5

Battery Terminal, supply for the LDOs used in the RF section of the transceiver.

Battery terminal, Supply for analog circuits such as ADC and ADC internal reference, POR, PSM and LDOs.

Internal 1.25 V ADC reference. A 0.47 µF capacitor between this pin and ground is required.

ADC input channel 0. Input of DIFF0 pair in differential mode.

ADC input channel 1. Input of DIFF0 pair in differential mode.

ADC input channel 2. Input of DIFF1 pair in differential mode.

ADC input channel 3. Input of DIFF1 pair in differential mode.

ADC input channel 4. Input of DIFF2 pair in differential mode.

ADC input channel 5. Input of DIFF2 pair in differential mode.

On chip LDO decoupling output. Connect a 0.47 µF capacitor to the 1.8V output to ensure core operating

LVDD1

voltage is stable. For correct operation a 1 µF capacitor needs to be connected between this pin and LVDD2 (pin

18).

VDDVCO

LVDD2

Voltage Regulator output for VCO. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

On chip LDO decoupling output. Connect a 0.47 µF capacitor to the 1.32V output to ensure core operating

voltage is stable. For correct operation a 1 µF capacitor needs to be connected between this pin and LVDD1 (pin

16).

SWDIO

Serial Wire bi-directional data

Rev. PrG | Page 10 of 13

No.

Mnemonic

Description

GND

Ground pin, should be connected to the PADDLE.

Battery terminal, General Purpose IO supply.

Serial Wire debug clock

Guard, screen for VCO, should be connected to VDDVCO.

Voltage Regulator output for Synthesizer. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

IOVDD⁶

SWCLK

VCOGUARD

VDDSYNTH

CWAKE

External capacitor for wake up control. A 150 nF capacitor should be placed between this pin and ground.

The 26MHz reference crystal should be connected between this pin and XOSC26N. (HFXTAL)

The 26MHz reference crystal should be connected between this pin and XOSC26P. (HFXTAL)

Internal Guard, Screen for Digital Cells, should be connected to VDD_DIG1.

Voltage Regulator output for Digital. A 220 nF capacitor should be placed between this pin and ground for

regulator stability and noise rejection.

XOSC26P

XOSC26N

DGUARD

VDD_DIG 1

P1.5/IRQ6/I2CSD General Purpose Input and Output Port 1.5/External Interrupt 6/I2C Serial Data/PWM channel 7.

A/PWM7

P1.4/IRQ5/I2CSC

L/PWM6

General Purpose Input and Output Port 1.4/External Interrupt 5/I2C Serial Clock/PWM channel 6.

P1.3/PWM5

P1.2/PWM4

P1.1/PORB/ TXD

/PWM3

General Purpose Input and Output Port 1.3/PWM channel 5.

General Purpose Input and Output Port 1.2/PWM channel 4.

General Purpose Input and Output Port 1.1/POR output/ UART TXD/ PWM channel 3.

P1.0/RXD/IRQ4/

MOSI /PWM2

General Purpose Input and Output Port 1.0/UART RXD/ External Interrupt 4/ SPI1 Master Out Slave In Pin

(MOSI)/PWM channel 2.

General Purpose Input and Output Port 0.5/SPI1 Chip Select 2/External Clock Input

CS2

P0.5/

/ECLKIN

CS1

General Purpose Input and Output Port 0.4/SPI1 Chip Select 1/External Clock Output.

P0.4/

/ECLKOUT

P2.6

General Purpose Input and Output Port 2.6. This pin should not be connected. This pin is connected internally to

the RF transceiver. It can be used for BER measurements.

General Purpose Input and Output Port 0.3/External Interrupt 1/SPI1 Chip Select 0/ADC convert start/PWM

channel 1.

CS0

P0.3/IRQ1/

/ADCCONVST/P

WM1

P2.4/IRQ8

General Purpose Input and Output Port 2.4. This pin should not be connected. This pin is connected internally to

the RF transceiver. It can be used for debug purposes to monitor RF transceiver interrupt/ External Interrupt 8

General Purpose Input and Output Port 0.2/SPI1 Master Out Slave In Pin (MOSI)/PWM channel 0.

P0.2/MOSI/

PWM0

P0.1/SCLK

P0.0/MISO

IOVDD

General Purpose Input and Output Port 0.1/SPI1 Serial Clock

General Purpose Input and Output Port 0.0/SPI1 Master In Slave Out Pin (MISO)

General Purpose I/O supply. Connect to the battery terminal

CS4

General Purpose Input and Output Port 0.7/ External Interrupt 3 / SPI1 Chip Select 4/ UART hand shake.

P0.7/IRQ3/

/CTS

BM/P0.6/

BM (Boot Mode). The ADuCRF101 enters serial download mode if P0.6 is low during an external Reset event. It

executes user code after any reset event or if P0.6 is high during an external Reset event. / General Purpose

Input and Output Port 0.6/External Interrupt 2/ SPI1 Chip Select 3 / UART hand shake/PWM channel 0.

CS3

IRQ2/

RTS/PWM0

RESET

Active Low. A low signal on this pin for 24 system clocks will cause the part to reset.

General Purpose Input and Output Port 4.0/PWM channel 0.

General Purpose Input and Output Port 4.1/PWM channel 1.

General Purpose Input and Output Port 4.2/PWM channel 2.

General Purpose Input and Output Port 4.3/PWM channel 3.

General Purpose Input and Output Port 4.4/PWM channel 4.

General Purpose Input and Output Port 4.5/PWM channel 5.

32.768 kHz watch crystal output for WU timers.

P4.0/PWM0

P4.1/PWM1

P4.2/PWM2

P4.3/PWM3

P4.4/PWM4

P4.5/PWM5

LFXTAL1

LFXTAL2

VDD_DIG2

32.768 kHz watch crystal input for WU timers.

Voltage Regulator output for Digital section of the transceiver. A 220 nF capacitor should be placed between

this pin and ground for regulator stability and noise rejection.

VDDBAT1⁶

P4.6/PWM6

P4.7/PWM7

Battery Terminal, supply for the digital section of the transceiver and GPIOs.

General Purpose Input and Output Port 4.6/PWM channel 6.

General Purpose Input and Output Port 4.7/PWM channel 7.

Rev. PrG | Page 11 of 13

ADuCRF101

Preliminary Technical Data

No.

Mnemonic

Description

ADCVREF

Transceiver’s ADC Reference Output. A 220 nF capacitor should be placed between this pin and ground for

adequate noise rejection.

P3.2/PWMSYNC

P3.3/PWMTRIP

P3.4

P3.5

PADDLE

General Purpose Input and Output Port 3.2/PWM synchronisation.

General Purpose Input and Output Port 3.3/PWM safety cut off.

General Purpose Input and Output Port 3.4.

General Purpose Input and Output Port 3.5.

The exposed package paddle should be soldered to a metal pad on the PCB, and connected to ground.

⁶VDDBAT1, VDDBAT2, AVDD and IOVDD should all be connected together.

Rev. PrG | Page 12 of 13

OUTLINE DIMENSIONS

9.10

9.00 SQ

8.90

0.30

0.25

0.18

0.60 MAX

0.60

MAX

PIN 1

INDICATOR

PIN 1

INDICATOR

8.85

8.75 SQ

8.65

0.50

BSC

EXPOSED

PAD

5.25

5.10 SQ

4.95

0.50

0.40

0.30

0.25 MIN

BOTTOM VIEW

7.50 REF

TOP VIEW

0.80 MAX

0.65 TYP

12° MAX

1.00

0.85

0.80

0.05 MAX

0.02 NOM

SEATING

PLANE

0.20 REF

COMPLIANT TO JEDEC STANDARDS MO-220-VMMD-4

Figure 2. 64-Lead Frame Chip Scale Package [LFCSP_VQ]

9 mm x 9 mm Body, Very Thin Quad

(CP-64-5)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range Description

Package Option

64-lead LFCSP

N/A

ADUCRF101BCPZ64

ADUCRF101BCPZ128

ADUCRF101CCPZ128

EV-ADuCRF101MK3Z

EV-ADuCRF101MK1Z

EV- ADuCRF101QSP1Z

EV-ADuCRF101QSP3Z

-40⁰C to 85⁰C

12-bit ADC, 164k Byte Flash and 8k Byte SRAM

12-bit ADC, 128k Byte Flash and 16k Byte SRAM

14-bit ADC, 128k Byte Flash and 16k Byte SRAM

Evaluation board for 433 MHz operation

Evaluation board for 915 MHz operation

Quick start Plus for 915 MHz operation

Quick start Plus for 433 MHz operation

N/A

I²C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).

registered trademarks are the property of their respective owners.

PR09464-0-11/12(PrG).

Rev. PrG | Page 13 of 13

ADUCRF101CCPZ128 [ADI]

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SI9130DB

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SI9135_11

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SI9130LG-T1-E3

SI9130_11

SI9137

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SI9137LG

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