ADUM1100AR-REEL [ADI]
SPECIALTY TELECOM CIRCUIT, PDSO8, MS-012AA, SOIC-8;
| 型号： | ADUM1100AR-REEL |
| 厂家： | 
ADI |
| 描述： | SPECIALTY TELECOM CIRCUIT, PDSO8, MS-012AA, SOIC-8 |
| 文件： | 总16页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
iCoupler® Digital Isolator
a
ADuM1100
GENERAL DESCRIPTION
FEATURES
The ADuM1100 is a digital isolator based on Analog Devices’
iCoupler technology. Combining high speed CMOS and mono-
lithic air core transformer technology, this isolation component
provides outstanding performance characteristics superior to
alternatives such as optocoupler devices.
High Data Rate: DC to 100 Mbps (NRZ)
Compatible with 3.3 V and 5.0 V Operation/
Level Translation
125؇C Max Operating Temperature
Low Power Operation
5 V Operation
1.0 mA Max @ 1 Mbps
4.5 mA Max @ 25 Mbps
16.8 mA Max @ 100 Mbps
Configured as a pin compatible replacement for existing high speed
optocouplers, the ADuM1100 supports data rates as high as
25 Mbps and 100 Mbps.
The ADuM1100 operates with either voltage supply ranging from
3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge
asymmetry of <2 ns, and is compatible with temperatures up to
125°C. It operates at very low power, less than 0.9 mA of quiescent
current (sum of both sides), and a dynamic current of less than
160 µA per Mbps of data rate. Unlike other optocoupler alter-
natives, the ADuM1100 provides dc correctness with a patented
refresh feature that continuously updates the output signal.
3.3 V Operation
0.4 mA Max @ 1 Mbps
3.5 mA Max @ 25 Mbps
7.1 mA Max @ 50 Mbps
8-Lead SOIC Package (lead-free version available)
High Common-Mode Transient Immunity: >25 kV/s
Safety and Regulatory Information
UL Recognized
2500 V rms for 1 Minute per UL 1577
CSA Component Acceptance Notice No. 5A
VDE Certificate of Conformity
DIN EN 60747-5-2 (VDE 0884 Part 2): 2003–01
DIN EN 60950 (VDE 0805): 2001–12; EN 60950: 2000
VIORM = 560 VPEAK
The ADuM1100 is offered in three grades. The ADuM1100AR
and ADuM1100BR can operate up to a maximum temperature
of 105°C and support data rates up to 25 Mbps and 100 Mbps,
respectively. The ADuM1100UR can operate up to a maximum
temperature of 125°C and supports data rates up to 100 Mbps.
APPLICATIONS
Digital Fieldbus Isolation
Opto-Isolator Replacement
Computer-Peripheral Interface
Microprocessor System Interface
General Instrumentation and Data Acquisition
Applications
FUNCTIONAL BLOCK DIAGRAM
V
V
DD1
DD2
D
E
N
C
O
D
E
E
C
O
D
E
V
GND
I
2
(DATA IN)
V
O
V
DD1
(DATA OUT)
UPDATE
WATCHDOG
GND
2
GND
1
ADuM1100
FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION,
DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY SECTION.
REV. E
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© 2003 Analog Devices, Inc. All rights reserved.
ADuM1100–SPECIFICATIONS
(4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max
ELECTRICAL SPECIFICATIONS, 5 V OPERATION1
specifications apply over the entire recommended operation
range, unless otherwise noted. All typical specifications are at TA = 25؇C, VDD1 = VDD2 = 5 V.)
Parameter
Symbol Min
Typ Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current
Output Supply Current
Input Supply Current (25 Mbps)
(See TPC 1)
IDD1(Q)
IDD2(Q)
IDD1(25)
0.3
0.01 0.06
0.8
mA
mA
mA
VI = 0 V or VDD1
VI = 0 V or VDD1
12.5 MHz Logic Signal Frequency
2.2
0.5
9.0
2.0
3.5
1.0
14
Output Supply Current2 (25 Mbps)
(See TPC 2)
IDD2(25)
IDD1(100)
IDD2(100)
mA
mA
mA
12.5 MHz Logic Signal Frequency
Input Supply Current (100 Mbps)
(See TPC 1)
50 MHz Logic Signal Frequency,
ADuM1100BR/ADuM1100UR Only
50 MHz Logic Signal Frequency,
ADuM1100BR/ADuM1100UR Only
0 ≤ VIN ≤ VDD1
Output Supply Current2 (100 Mbps)
(See TPC 2)
2.8
Input Current
Logic High Output Voltage
II
VOH
–10
+0.01 +10
µA
V
V
V
V
VDD2 – 0.1 5.0
VDD2 – 0.8 4.6
0.0
IO = –20 µA, VI = VIH
IO = –4 mA, VI = VIH
Logic Low Output Voltage
VOL
0.1
IO = 20 µA, VI = VIL
0.03 0.1
0.3
IO = 400 µA, VI = VIL
0.8
V
IO = 4 mA, VI = VIL
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width3
Maximum Data Rate4
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width3
Maximum Data Rate4
For All Grades
Propagation Delay Time
to Logic Low Output5, 6
(See TPC 3)
PW
PW
tPHL
tPLH
40
10
ns
Mbps
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
25
6.7
150
ns
Mbps
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
100
10.5 18
10.5 18
ns
ns
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
Propagation Delay Time
to Logic High Output5, 6
(See TPC 3)
6
Pulse Width Distortion |tPLH – tPHL
Change versus Temperature7
Propagation Delay Skew
(Equal Temperature)6, 8
Propagation Delay Skew
|
PWD
tPSK1
tPSK2
tR, tF
0.5
3
2
8
6
ns
ps/°C
ns
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
ns
CL = 15 pF, CMOS Signal Levels
(Equal Temperature, Supplies)6, 8
Output Rise/Fall Time
3
35
ns
kV/µs
CL = 15 pF, CMOS Signal Levels
VI = 0 or VDD1, VCM = 1000 V,
Transient Magnitude = 800 V
Common-Mode Transient Immunity |CML|, 25
at Logic Low/High Output9
Input Dynamic Power
|CMH|
CPD1
35
8
pF
pF
Dissipation Capacitance10
Output Dynamic Power
Dissipation Capacitance10
CPD2
See Notes on page 5.
Specifications subject to change without notice.
–2–
REV. E
ADuM1100
(3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. All min/max
specifications apply over the entire recommended operation
range, unless otherwise noted. All typical specifications are at TA = 25؇C, VDD1 = VDD2 = 3.3 V.)
ELECTRICAL SPECIFICATIONS, 3.3 V OPERATION1
Parameter
Symbol
Min
Typ Max
Unit
Test Conditions
DC SPECIFICATIONS
Input Supply Current
Output Supply Current
Input Supply Current (25 Mbps)
(See TPC 1)
IDD1(Q)
IDD2(Q)
IDD1(25)
0.1
0.005 0.04
0.3
mA
mA
mA
VI = 0 V or VDD1
VI = 0 V or VDD1
12.5 MHz Logic Signal Frequency
2.0
0.3
4.0
1.2
2.8
0.7
6.0
1.6
Output Supply Current2 (25 Mbps)
(See TPC 2)
IDD2(25)
IDD1(50)
IDD2(50)
mA
mA
mA
12.5 MHz Logic Signal Frequency
Input Supply Current (50 Mbps)
(See TPC 1)
25 MHz Logic Signal Frequency,
ADuM1100BR/ADuM1100UR Only
25 MHz Logic Signal Frequency,
ADuM1100BR/ADuM1100UR Only
0 ≤ VIN ≤ VDD1
Output Supply Current2 (50 Mbps)
(See TPC 2)
Input Current
Logic High Output Voltage
II
VOH
–10
+0.01 +10
µA
V
V
V
V
VDD2 – 0.1 3.3
VDD2 – 0.5 3.0
0.0
IO = –20 µA, VI = VIH
IO = –2.5 mA, VI = VIH
Logic Low Output Voltage
VOL
0.1
IO = 20 µA, VI = VIL
0.04 0.1
0.3
IO = 400 µA, VI = VIL
0.4
V
IO = 2.5 mA, VI = VIL
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width3
Maximum Data Rate4
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width3
Maximum Data Rate4
For All Grades
PW
PW
tPHL
tPLH
40
20
ns
Mbps
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
25
50
10
100
ns
Mbps
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
Propagation Delay Time to
14.5 28
15.0 28
ns
ns
CL = 15 pF, CMOS Signal Levels
Logic Low Output5, 6
(See TPC 4)
Propagation Delay Time to
CL = 15 pF, CMOS Signal Levels
Logic High Output5, 6
(See TPC 4)
6
Pulse Width Distortion |tPLH – tPHL
Change versus Temperature7
Propagation Delay Skew
(Equal Temperature)6, 8
Propagation Delay Skew
|
PWD
tPSK1
tPSK2
tR, tF
0.5
10
3
ns
ps/°C
ns
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
15
12
ns
CL = 15 pF, CMOS Signal Levels
(Equal Temperature, Supplies)6, 8
Output Rise/Fall Time
3
35
ns
kV/µs
CL = 15 pF, CMOS Signal Levels
VI = 0 or VDD1, VCM = 1000 V,
Transient Magnitude= 800 V
Common-Mode Transient Immunity |CML|,
25
at Logic Low/High Output9
Input Dynamic Power Dissipation
Capacitance10
|CMH|
CPD1
47
14
pF
pF
Output Dynamic Power Dissipation
CPD2
Capacitance10
See Notes on page 5.
Specifications subject to change without notice.
–3–
REV. E
ADuM1100
(5 V/3 V operation: 4.5 V ≤ VDD1
≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V.
ELECTRICAL SPECIFICATIONS, MIXED 5 V/3 V or 3 V/5 V OPERATION1
3 V/5 V operation: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V. All min/max specifications apply over the entire recommended operation range,
unless otherwise noted. All typical specifications are at TA = 25؇C, VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.3 V.)
Parameter
Symbol
Min
Typ
Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current, Quiescent
5 V/3 V Operation
IDDI(Q)
0.3
0.1
0.8
0.3
mA
mA
3 V/5 V Operation
Output Supply Current, Quiescent
5 V/3 V Operation
3 V/5 V Operation
Input Supply Current, 25 Mbps
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current, 25 Mbps
5 V/3 V Operation
3 V/5 V Operation
Input Supply Current, 50 Mbps
5 V/3 V Operation
3 V/5 V Operation
Output Supply Current, 50 Mbps
5 V/3 V Operation
3 V/5 V Operation
Input Currents
Logic High Output Voltage,
5 V/3 V Operation
IDDO(Q)
IDDI(25)
IDDO(25)
IDDI(50)
IDDO(50)
0.005 0.04 mA
0.01
0.06 mA
2.2
2.0
3.5
2.8
mA
mA
12.5 MHz Logic Signal Frequency
12.5 MHz Logic Signal Frequency
0.3
0.5
0.7
1.0
mA
mA
12.5 MHz Logic Signal Frequency
12.5 MHz Logic Signal Frequency
4.5
4.0
7.0
6.0
mA
mA
25 MHz Logic Signal Frequency
25 MHz Logic Signal Frequency
1.2
1.0
+0.01 +10
1.6
1.5
mA
mA
µA
V
V
V
V
V
V
V
25 MHz Logic Signal Frequency
25 MHz Logic Signal Frequency
0 ≤ VIA, VIB, VIC, VID ≤ VDD1 or VDD2
IO = –20 µA, VI = VIH
IIA
VOH
–10
VDD2 – 0.1 3.3
VDD2 – 0.5 3.0
0.0
IO = –2.5 mA, VI = VIH
IO = 20 µA, VI = VIL
Logic Low Output Voltage,
5 V/3 V Operation
VOL
0.1
0.1
0.4
0.04
IO = 400 µA, VI = VIL
0.3
VDD2 – 0.1 5.0
VDD2 – 0.8 4.6
0.0
IO = 2.5 mA, VI = VIL
Logic High Output Voltage,
3 V/5 V Operation
Logic Low Output Voltage,
3 V/5 V Operation
VOH
VOL
IO = –20 µA, VI = VIH
IO = –4 mA, VI = VIH
0.1
0.1
0.8
V
V
V
IO = 20 µA, VI = VIL
0.03
0.3
IO = 400 µA, VI = VIL
IO = 4 mA, VI = VIL
SWITCHING SPECIFICATIONS
For ADuM1100AR
Minimum Pulse Width3
PW
40
20
ns
CL = 15 pF, CMOS Signal Levels
Maximum Data Rate4
25
50
Mbps CL = 15 pF, CMOS Signal Levels
For ADuM1100BR/ADuM1100UR
Minimum Pulse Width3
Maximum Data Rate4
PW
ns
CL = 15 pF, CMOS Signal Levels
Mbps CL = 15 pF, CMOS Signal Levels
For All Grades
Propagation Delay Time to Logic
tPHL, tPLH
Low/High Output5, 6
5 V/3 V Operation (See TPC 5)
3 V/5 V Operation (See TPC 6)
Pulse Width Distortion, |tPLH – tPHL
5 V/3 V Operation
13
16
21
26
ns
ns
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
6
|
PWD
0.5
0.5
2
3
ns
ns
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
3 V/5 V Operation
Change versus Temperature
5 V/3 V Operation
3 V/5 V Operation
3
10
ps/ºC CL = 15 pF, CMOS Signal Levels
ps/ºC CL = 15 pF, CMOS Signal Levels
Propagation Delay Skew
(Equal Temperature)6, 8
5 V/3 V Operation
tPSK1
12
15
ns
ns
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
3 V/5 V Operation
–4–
REV. E
ADuM1100
Parameter
Symbol Min Typ Max
Unit
Test Conditions
SWITCHING SPECIFICATIONS (continued)
Propagation Delay Skew
tPSK2
(Equal Temperature, Supplies)6, 8
5 V/3 V Operation
9
12
ns
ns
ns
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
CL = 15 pF, CMOS Signal Levels
3 V/5 V Operation
Output Rise/Fall Time (10% to 90%)
Common-Mode Transient Immunity at
Logic Low/High Output8
tR, tf
3
|CML|, 25
|CMH|
35
kV/µs VI = 0 or VDD1, VCM = 1000 V,
Transient Magnitude = 800 V
Input Dynamic Power Dissipation Capacitance10 CPD1
5 V/3 V Operation
35
47
pF
pF
3 V/5 V Operation
Output Dynamic Power Dissipation Capacitance10 CPD2
5 V/3 V Operation
8
14
pF
pF
3 V/5 V Operation
NOTES
1All voltages are relative to their respective ground.
2Output supply current values are with no output load present. The supply current drawn at a given signal frequency when an output load is present is given by
IDD2(L) = IDD2 + VDD2 × f × CL, where IDD2 is the unloaded output supply current, f is the input signal frequency, and CL is the output load capacitance.
3The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
4The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
5tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of
the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
6Since the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion
may be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figures 3 to 7 for information on the impact of given input
rise/fall times on these parameters.
7Pulse width distortion change versus temperature is the absolute value of the change in pulse width distortion for a 1°C change in operating temperature.
8tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that will be measured between units at the same operating temperature and output load within
the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that will be measured between units at the same operating
temperature, supply voltages, and output load within the recommended operating conditions.
9CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew
rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the
range over which the common-mode is slewed.
10The dynamic power dissipation capacitance is given by
C
PDi = (IDDi(100) – IDDi(Q))/(VDDi × f), where i = 1 or 2 and f is the input signal frequency.
The supply current consumptions at a given frequency and output load are calculated as
IDD1 = CPD1 × VDD1 × f + IDD1(Q); IDD2(L) = (CPD2 + CL) × VDD2 × f + IDD2(Q), where CL is the output load capacitance.
Specifications subject to change without notice.
PACKAGE CHARACTERISTICS
Parameter
Symbol
Min
Typ Max
Unit
Test Conditions
Resistance (Input-Output)1
Capacitance (Input-Output)1
Input Capacitance2
Input IC Junction-to-Case
Thermal Resistance
RI–O
CI–O
CI
1012
1
4.0
46
Ω
pF
f = 1 MHz
pF
°C/W
θJCI
Thermocouple Located at Center
Underside of Package
Output IC Junction-to-Case
Thermal Resistance
Package Power Dissipation
θJCO
41
°C/W
PPD
240
mW
NOTES
1Device considered a 2-terminal device: Pins 1, 2, 3, and 4 shorted together and Pins 5, 6, 7, and 8 shorted together.
2Input capacitance is measured at Pin 2 (VI).
–5–
REV. E
ADuM1100
REGULATORY INFORMATION
The ADuM1100 has been approved by the following organizations:
UL
CSA
VDE
Recognized under 1577
Approved under CSA Component
Certified according to
Component Recognition Program1 Acceptance Notice No. 5A, C22.2 No. 1-98, DIN EN 60747-5-2 (VDE 0884 Part 2): 2003–12
C22.2 No. 14-95, and C22.2 No. 950-95
File 205078
DIN EN 60950 (VDE 0805): 2001–12; EN60950: 2000
File 2471900-4880-0002
File E214100
NOTES
1In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage ≥ 3000 V rms for 1 second (leakage detection current limit, II–O ≤ 5 µA).
2In accordance with DIN EN 60747-5-2, each ADuM1100 is proof tested by applying an insulation test voltage ≥ 1050 VPEAK for 1 second (partial discharge detection
limit ≤ 5 pC). A “*” mark branded on the component designates DIN EN 60747-5-2 approval.
INSULATION AND SAFETY-RELATED SPECIFICATIONS
Parameter
Symbol Value
Unit Conditions
Minimum External Air Gap (Clearance)
L(I01)
4.90 min
mm
Measured from input terminals to output terminals,
shortest distance through air
Measured from input terminals to output terminals,
shortest distance path along body
Insulation distance through insulation
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
Minimum External Tracking (Creepage)
Minimum Internal Gap (Internal Clearance)
Tracking Resistance (Comparative Tracking Index) CTI
Isolation Group
L(I02)
4.01 min
mm
0.016 min mm
>175
IIIa
V
DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS
Description
Symbol
Characteristic
Unit
I
nstallation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms
For Rated Mains Voltage ≤ 300 V rms
For Rated Mains Voltage ≤ 400 V rms
I to IV
I to III
I to II
Climatic Classification
ADuM1100AR and ADuM1100BR
ADuM1100UR
40/105/21
40/125/21
2
Pollution Degree (DIN VDE 0110, Table I)
Maximum Working Insulation Voltage
Input-to-Output Test Voltage, Method b1
VIORM × 1.875 = VPR, 100% Production Test, tM = 1 sec, Partial Discharge < 5 pC
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VIORM × 1.6 = VPR, tM = 10 sec, Partial Discharge < 5 pC
After Input and/or Output Safety Test Subgroup 2/3
VIORM × 1.2 = VPR, tM = 10 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage, tINI = 60 sec)
Safety-Limiting Values (Maximum Value Allowed in the Event of a Failure,
See Thermal Derating Curve, Figure 1
Case Temperature
VIORM
560
VPEAK
VPR
VPR
1050
672
VPEAK
VPEAK
VPR
896
VPEAK
VPR
VTR
672
4000
VPEAK
VPEAK
TS
150
160
170
>109
°C
mA
mA
Ω
Input Current
Output Current
Insulation Resistance at TS, VIO = 500 V
IS, INPUT
IS, OUTPUT
Rs
This isolator is suitable for basic isolation only within the safety limit data. Maintenance of the safety data shall be ensured by means of protective circuits.
The * marking on the package denotes DIN EN 60747-5-2 approval for 560 VPEAK working voltage.
–6–
REV. E
ADuM1100
ABSOLUTE MAXIMUM RATINGS1
180
160
140
120
100
80
Parameter
Symbol
Min Max
Unit
Storage Temperature
Ambient Operating
Temperature
TST
TA
–55 +150
–40 +125
°C
°C
OUTPUT CURRENT
Supply Voltages2
VDD1, VDD2 –0.5 +6.5
VI
VO
V
V
V
INPUT CURRENT
Input Voltage2
–0.5 VDD1 + 0.5
–0.5 VDD2 + 0.5
Output Voltage2
60
Average Current, per Pin3
Temperature ≤ 105°C
Temperature ≤ 125°C
Input Current
–25 +25
mA
40
20
–7
+7
mA
mA
kV/µs
0
Output Current
–20 +20
–100 +100
0
50
100
150
200
Common-Mode Transients4
CASETEMPERATURE (؇C)
NOTES
Figure 1. Thermal Derating Curve, Dependence of
Safety-Limiting Values with Case Temperature per
DIN EN 60747-5-2
1 Stresses above those listed under Absolute Maximum Ratings may cause permanent
damage to the device. This is a stress rating only. Functional operation of the device at
these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions may affect
device reliability. Ambient temperature = 25°C, unless otherwise noted.
2 All voltages are relative to their respective ground.
3 See Figure 1 for information on maximum allowable current for various temperatures.
4 Refers to common-mode transients across the insulation barrier. Common-mode
transients exceeding the Absolute Maximum Rating may cause latch-up or permanent
damage.
RECOMMENDED OPERATING CONDITIONS
Parameter
Symbol
Min
Max
Unit
Operating Temperature
ADuM1100AR and ADuM1100BR
TA
TA
VDD1, VDD2
VIH
VIL
–40
–40
3.0
2.0
0.0
1.5
0.0
+105
+125
5.5
VDD1
0.8
VDD1
0.5
1.0
°C
°C
V
V
V
V
V
ms
ADuM1100UR
Supply Voltages1
Logic High Input Voltage, 5 V Operation1, 2 (See TPCs 7 and 8)
Logic Low Input Voltage, 5 V Operation1, 2 (See TPCs 7 and 8)
Logic High Input Voltage, 3.3 V Operation1, 2 (See TPCs 7 and 8)
Logic Low Input Voltage, 3.3 V Operation1, 2 (See TPCs 7 and 8)
Input Signal Rise and Fall Times
VIH
VIL
NOTES
1All voltages are relative to their respective ground.
2Input switching thresholds have 300 mV of hysteresis.
See the Method of Operation, DC Correctness, and Magnetic Field Immunity section and Figures 8 and 9 for information on immunity to external magnetic fields.
REV. E
–7–
ADuM1100
Table I. Truth Table (Positive Logic)
VI Input
VDD1 State
VDD2 State
VO Output
H
L
X
X
Powered
Powered
Unpowered
Powered
Powered
Powered
Powered
Unpowered
H
L
H*
X*
*VO returns to VI state within 1 µs of power restoration.
Note: Package branding is as follows:
PIN CONFIGURATION
ADuM1100AR,
ADuM1100BR,
ADuM1100UR,
ADuM1100AR-RL7
ADuM1100BR-RL7
ADuM1100UR-RL7
8
8
8
1
1
2
3
4
8
7
6
5
V
V
DD1
DD2
AD1100B
AD1100U
AD1100A
2
2
V
GND
I
2
ADuM1100
TOP VIEW
(Not to Scale)
R YYWW
R YYWW
R YYWW
*
*
*
1
V
O
V
XXXXXX
XXXXXX
DD1
XXXXXX
GND
GND
1
2
1
1
1
NOTES
1
where:
PIN 1 AND PIN 3 ARE INTERNALLY CONNECTED. EITHER OR BOTH
*
R
= DIN EN 60747-5-2 mark
= Package Designator (R denotes SOIC)
= Date Code
MAY BE USED FORV
PIN 5 AND PIN 7 ARE INTERNALLY CONNECTED. EITHER OR BOTH
MAY BE USED FOR GND .
.
DD1
2
2
YYWW
XXXXXX = Lot Code
ORDERING GUIDE
Max Data Min Pulse
Temperature
Range
Package
Option
Model
Rate (Mbps)
Width (ns)
Package Description
ADuM1100AR
ADuM1100AR-RL7
ADuM1100ARZ*
ADuM1100ARZ-RL7* –40°C to +105°C
ADuM1100BR
ADuM1100BR-RL7
ADuM1100BRZ*
ADuM1100BRZ-RL7* –40°C to +105°C
ADuM1100UR
ADuM1100UR-RL7
ADuM1100URZ*
ADuM1100URZ-RL7* –40°C to +125°C
ADuM1100EVAL
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
25
25
25
25
100
100
100
100
100
100
100
100
40
40
40
40
10
10
10
10
10
10
10
10
8-Lead SOIC
8-Lead SOIC, 1,000 Piece Reel R-8
8-Lead SOIC
8-Lead SOIC, 1,000 Piece Reel
8-Lead SOIC
8-Lead SOIC, 1,000 Piece Reel
8-Lead SOIC
8-Lead SOIC, 1,000 Piece Reel
8-Lead SOIC
8-Lead SOIC, 1,000 Piece Reel
8-Lead SOIC
8-Lead SOIC, 1,000 Piece Reel
Evaluation Board
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
R-8
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
–40°C to +125°C
–40°C to +125°C
–40°C to +125°C
*Z = Lead Free
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the ADuM1100 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–8–
REV. E
Typical Performance Characteristics—ADuM1100
18
20
18
16
14
12
10
8
17
16
tPHL
15
tPLH
5V
14
13
12
6
3.3V
4
2
0
–50
–25
0
25
50
75
100
125
0
25
50
75
100
125
150
TEMPERATURE (؇C)
DATA RATE (Mbps)
TPC 1. Typical Input Supply Current vs. Logic
Signal Frequency for 5 V and 3.3 V Operation
TPC 4. Typical Propagation Delays vs. Temperature,
3.3 V Operation
14
13
5
4
3
tPLH
12
tPHL
5V
11
2
3.3V
10
9
1
0
–50
–25
0
25
50
75
100
125
0
25
50
75
100
125
150
TEMPERATURE (؇C)
DATA RATE (Mbps)
TPC 2. Typical Output Supply Current vs. Logic
Signal Frequency for 5 V and 3.3 V Operation
TPC 5. Typical Propagation Delays vs. Temperature,
5 V/3 V Operation
13
12
18
17
16
tPHL
11
15
tPLH
tPLH
tPHL
14
13
12
10
9
–50
–25
0
25
50
75
100
125
–50
–25
0
25
50
75
100
125
TEMPERATURE (؇C)
TEMPERATURE (؇C)
TPC 3. Typical Propagation Delays vs. Temperature,
5 V Operation
TPC 6. Typical Propagation Delays vs. Temperature,
3 V/5 V Operation
REV. E
–9–
ADuM1100
1.7
1.4
1.3
1.2
1.1
1.0
0.9
0.8
–40؇C
+25؇C
1.6
1.5
1.4
1.3
1.2
–40؇C
+25؇C
+125؇C
+125؇C
1.1
3.0
3.5
4.0
4.5
5.0
5.5
3.0
3.5
4.0
4.5
5.0
5.5
INPUT SUPPLYVOLTAGE,V
(V)
INPUT SUPPLYVOLTAGE,V
(V)
DD1
DD1
TPC 7. Typical Input Voltage Switching Threshold,
Low-to-High Transition
TPC 8. Typical Input Voltage Switching Threshold,
High-to-Low Transition
APPLICATION INFORMATION
PC Board Layout
time to logic low output and propagation delay time to logic high
output refer to the duration between an input signal transition and
the respective output signal transition (Figure 3).
The ADuM1100 digital isolator requires no external interface
circuitry for the logic interfaces. A bypass capacitor is recom-
mended at the input and output supply pins. The input bypass
capacitor may most conveniently be connected between Pins 3
and 4 (Figure 2). Alternatively, the bypass capacitor may be located
between Pins 1 and 4. The output bypass capacitor may be con-
nected between Pins 7 and 8 or Pins 5 and 8. The capacitor value
should be between 0.01 µF and 0.1 µF. The total lead length
between both ends of the capacitor and the power supply pins
should not exceed 20 mm.
Pulse width distortion is the maximum difference between tPLH and
tPHL and provides an indication of how accurately the input signal’s
timing is preserved in the component’s output signal. Propagation
delay skew is the difference between the minimum and maximum
propagation delay values among multiple ADuM1100 compo-
nents operated at the same operating temperature and having
the same output load.
Depending on the input signal rise/fall time, the measured propa-
gation delay based on the input 50% level can vary from the true
propagation delay of the component (as measured from its input
switching threshold). This is due to the fact that the input threshold,
as is the case with commonly used optocouplers, is at a different
voltage level than the 50% point of typical input signals. This
propagation delay difference is given by
V
V
DD2
DD1
(OPTIONAL)
V
(DATA)
1
V
O
(DATA OUT)
GND
1
GND
2
Figure 2. Recommended Printed Circuit Board Layout
∆
∆
= t'PLH − tPLH = t / 0.8V 0.5V −V
(
)
(
LH
HL
r
I
1
)
ITH L−H
(
)
INPUT (V )
50%
I
= t'PHL − tPHL = t / 0.8V 0.5V −V
(
)
(
f
I
1
)
ITH H−L
(
)
tPLH
tPHL
where:
PLH, tPHL
OUTPUT (V
)
50%
O
t
= propagation delays as measured from the
input 50% level.
= propagation delays as measured from the
input switching thresholds.
= input 10% to 90% rise/fall time.
= amplitude of input signal (0 to VI levels
assumed).
Figure 3. Propagation Delay Parameters
t′PLH, t′PHL
Propagation Delay-Related Parameters
Propagation delay time describes the length of time it takes for a
logic signal to propagate through a component. Propagation delay
tr , tf
VI
VITH(L–H), VITH(H–L) = input switching thresholds.
⌬
⌬
LH
HL
V
I
V
50%
ITH(L–H)
V
ITH(H–L)
tPLH
t'PHL
INPUT (V )
I
tPHL
t'PLH
50%
OUTPUT (V
)
O
Figure 4. Impact of Input Rise/Fall Time on Propagation Delay
–10–
REV. E
ADuM1100
4
3
2
1
0
6
5
4
3
2
1
0
5V INPUT SIGNAL
5V INPUT SIGNAL
3.3V INPUT SIGNAL
3.3V INPUT SIGNAL
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
9
10
INPUT RISE TIME (10%–90%, ns)
INPUT RISE/FALLTIME (10%–90%, ns)
Figure 5. Typical Propagation Delay Change due to
Input Rise Time Variation (for VDD1 = 3.3 V and 5 V)
Figure 7. Typical Pulse Width Distortion Adjustment due
to Input Rise/Fall Time Variation (at VDD1 = 3.3 V and 5 V)
0
Method of Operation, DC Correctness, and
Magnetic Field Immunity
Referring to the functional block diagram, the two coils act as a
pulse transformer. Positive and negative logic transitions at the
isolator input cause narrow (2 ns) pulses to be sent via the trans-
former to the decoder. The decoder is bistable and therefore
either set or reset by the pulses indicating input logic transitions.
In the absence of logic transitions at the input for more than 2 µs,
a periodic update pulse of the appropriate polarity is sent to ensure
dc correctness at the output. If the decoder receives none of
these update pulses for more than about 5 µs, the input side is
assumed to be unpowered or nonfunctional, in which case the
isolator output is forced to a logic high state by the watchdog
timer circuit.
–1
5V INPUT SIGNAL
–2
3.3V INPUT SIGNAL
–3
–4
1
2
3
4
5
6
7
8
9
10
INPUT RISE TIME (10%–90%, ns)
The limitation on the ADuM1100’s magnetic field immunity is set
by the condition in which induced voltage in the transformer’s
receiving coil is sufficiently large to either falsely set or reset the
decoder. The analysis that follows defines the conditions under
which this may occur. The ADuM1100’s 3.3 V operating condi-
tion is examined because it represents the most susceptible mode
of operation.
Figure 6. Typical Propagation Delay Change due to
Input Fall Time Variation (for VDD1 = 3.3 V and 5 V)
The impact of the slower input edge rates can also affect the
measured pulse width distortion as based on the input 50% level.
This impact may either increase or decrease the apparent pulse
width distortion depending on the relative magnitudes of tPHL
tPLH, and PWD. The case of interest here is the condition
that leads to the largest increase in pulse width distortion. The
change in this case is given by
,
The pulses at the transformer output are greater than 1.0 V in
amplitude. The decoder has sensing thresholds at about 0.5 V,
therefore establishing a 0.5 V margin in which induced voltages can
be tolerated. The induced voltage induced across the receiving
coil is given by
∆
= PWD′ – PWD = ∆LH – ∆HL =
PWD
V = –dβ /dt Σπ r2;n = 1, 2,.... , N
(
)
n
t/0.8V V –V
(
–VITH H–L , for t = t = t
)
(
(
)
1
)
r
f
ITH L–H
(
)
(
)
where:
where:
β = magnetic flux density (Gauss).
N = number of turns in receiving coil.
rn = radius of nth turn in receiving coil (cm).
PWD = tPLH – tPHL
PWD′ = t′PLH – t′PHL
This adjustment in pulse width distortion is plotted as a func-
tion of input rise/fall time in Figure 7.
REV. E
–11–
ADuM1100
Given the geometry of the receiving coil in the ADuM1100 and an
imposed requirement that the induced voltage be at most 50% of
the 0.5 V margin at the decoder, a maximum allowable magnetic
field is calculated as shown in Figure 8.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances away from the ADuM1100
transformers. Figure 9 expresses these allowable current magnitudes
as a function of frequency for selected distances. As can be seen,
the ADuM1100 is extremely immune and can be affected only
by extremely large currents operated at high frequency and very
close to the component. For the 1 MHz example noted, one
would have to place a current of 0.5 kA 5 mm away from the
ADuM1100 to affect the component’s operation.
100
10
1000
1
DISTANCE = 1m
100
0.1
10
0.01
DISTANCE = 100mm
1
0.001
1k
10k
100k
1M
10M
100M
DISTANCE = 5mm
MAGNETIC FIELD FREQUENCY (Hz)
0.1
Figure 8. Maximum Allowable External Magnetic Field
For example, at a magnetic field frequency of 1 MHz, the maximum
allowable magnetic field of 0.2 KGauss induces a voltage of
0.25 V at the receiving coil. This is about 50% of the sensing
threshold and will not cause a faulty output transition. Similarly,
if such an event were to occur during a transmitted pulse (and was
of the worst-case polarity), it would reduce the received pulse
from >1.0 V to 0.75 V—still well above the 0.5 V sensing
threshold of the decoder.
0.01
1k
10k
100k
1M
10M
100M
MAGNETIC FIELD FREQUENCY (Hz)
Figure 9. Maximum Allowable Current for
Various Current-to-ADuM1100 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by printed circuit board traces could
induce sufficiently large error voltages to trigger the thresholds
of succeeding circuitry. Care should be taken in the layout of
such traces to avoid this possibility.
–12–
REV. E
ADuM1100
OUTLINE DIMENSIONS
8-Lead Standard Small Outline Package [SOIC]
Narrow Body
(R-8)
Dimensions shown in millimeters and (inches)
5.00 (0.1968)
4.80 (0.1890)
8
1
5
4
6.20 (0.2440)
5.80 (0.2284)
4.00 (0.1574)
3.80 (0.1497)
0.50 (0.0196)
0.25 (0.0099)
1.27 (0.0500)
BSC
؋
45؇ 1.75 (0.0688)
1.35 (0.0532)
0.25 (0.0098)
0.10 (0.0040)
8؇
0.51 (0.0201)
0.31 (0.0122)
0؇ 1.27 (0.0500)
COPLANARITY
0.10
0.25 (0.0098)
0.17 (0.0067)
SEATING
PLANE
0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-012AA
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. E
–13–
ADuM1100
Revision History
Location
Page
10/03—Data Sheet changed from REV. D to REV. E.
Changes to Product Name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to RECOMMENDED OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
6/03—Data Sheet changed from REV. C to REV. D.
Changed DIN EN 60747-5-2 (VDE 0884 Part 2) INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Updated ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4/03—Data Sheet changed from REV. B to REV. C.
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to Patent note . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to INSULATION CHARACTERISTICS section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to Package Branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Changes to Method of Operation, DC Correctness, and Magnetic Field Immunity section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Replaced Figure 9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1/03—Data Sheet changed from REV. A to REV. B.
Added ADuM1100UR Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changed ADuM1100AR/ADuM1100BR to ADuM1100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Added Electrical Specifications, Mixed 5 V/3 V or 3 V/5 V Operation table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to VDE 0884 INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Changes to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Changes to Package Branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Updated TPCs 3–8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Deleted iCoupler in Field Bus Networks section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Changes to Figure 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Added a new Figure 9 and related text . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
11/02—Data Sheet changed from REV. 0 to REV. A.
Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to REGULATORY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Edits to VDE 0884 INSULATION CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Added Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
–14–
REV. E
–15–
–16–
相关型号：
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