ADG731BCP-REEL_技术文档

16-/32-Channel, Serially Controlled 4 ⍀

1.8 V to 5.5 V, ؎2.5 V, Analog Multiplexers

a

ADG725/ADG731

FEATURES

FUNCTIONAL BLOCK DIAGRAM

3-Wire SPI Compatible Serial Interface

1.8 V to 5.5 V Single Supply

؎2.5 V Dual-Supply Operation

4 ⍀ On Resistance

0.5 ⍀ On Resistance Flatness

7 mm x 7 mm 48-Lead Chip Scale Package (LFCSP)

or 48-Lead TQFP Package

ADG731

ADG725

S1

S1A

DA

DB

S16A

D

Rail-to-Rail Operation

Power-On Reset

S1B

42 ns Switching Times

S32

S16B

Single 32-to-1 Channel Multiplexer

Dual/Differential 16-to-1 Channel Multiplexer

TTL/CMOS Compatible Inputs

For Functionally Equivalent Devices with Parallel

Interface, See ADG726/ADG732

INPUT SHIFT

REGISTER

INPUT SHIFT

REGISTER

SCLK DIN

SYNC

APPLICATIONS

Optical Applications

Data Acquisition Systems

Communication Systems

Relay Replacement

Audio and Video Switching

Battery-Powered Systems

Medical Instrumentation

Automatic Test Equipment

GENERAL DESCRIPTION

These parts can operate equally well as either multiplexers or

demultiplexers and have an input signal range that extends to the

supplies. In the OFF condition, signal levels up to the supplies

are blocked. All channels exhibit break-before-make switching

action, preventing momentary shorting when switching channels.

The ADG731/ADG725 are monolithic, CMOS, 32-channel/

dual 16-channel analog multiplexers with a serially controlled

3-wire interface. The ADG731 switches one of 32 inputs

(S1–S32) to a common output, D. The ADG725 can be config-

ured as a dual mux switching one of 16 inputs to one output, or a

differential mux switching one of 16 inputs to a differential output.

The ADG731 and ADG725 are serially controlled 32-channel,

and dual/differential 16-channel multiplexers, respectively. They

are available in either a 48-lead LFCSP or TQFP package.

These mulitplexers utilize a 3-wire serial interface that is com-

patible with SPI^®, QSPI^™, MICROWIRE^™, and some DSP

interface standards. On power-up, the Internal Shift Register

contains all zeros and all switches are in the OFF state.

PRODUCT HIGHLIGHTS

1. 3-Wire Serial Interface.

These multiplexers are designed on an enhanced submicron

process that provides low power dissipation yet gives high switch-

ing speed with very low on resistance and leakage currents.

They operate from a single supply of 1.8 V to 5.5 V or a

±2.5 V dual supply, making them ideally suited to a variety of

applications. On resistance is in the region of a few ohms, is

closely matched between switches, and is very flat over the full

signal range.

2. 1.8 V to 5.5 V Single-Supply or ±2.5 V Dual-Supply

Operation. These parts are specified and guaranteed

with 5 V ±10%, 3 V ±10% single-supply,

and ±2.5 V ±10% dual-supply rails.

3. On Resistance of 4 W.

4. Guaranteed Break-Before-Make Switching Action.

5. 7 mm ¥ 7 mm 48-Lead Chip Scale Package (LFCSP) or

48-Lead TQFP Package.

REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its

use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat

may result from its use. No license is granted by implication or otherwise

under any patent or patent rights of Analog Devices. Trademarks and

registered trademarks are the property of their respective companies.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781/329-4700

Fax: 781/326-8703

www.analog.com

ADG725/ADG731–SPECIFICATIONS¹

(V_DD= 5 V 10%, V_SS= 0 V, GND = 0 V, unless otherwise noted.)

B Version

Parameter

+25ЊC

–40ЊC to +85ЊC

Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

0 to V_DD

V

On Resistance (R_ON

)

4

5.5

Ω typ

Ω max

Ω typ

Ω max

Ω typ

Ω max

V_S= 0 V to V_DD, I_DS= 10 mA;

Test Circuit 1

V_S= 0 V to V_DD, I_DS= 10 mA

6

0.3

0.8

On Resistance Match between

Channels (∆R_ON

)

On Resistance Flatness (R_FLAT(ON)

)

0.5

V_S= 0 V to V_DD, I_DS= 10 mA

1

LEAKAGE CURRENTS

Source OFF Leakage I_S(OFF)

V_DD= 5.5 V

V_D= 4.5 V/1 V, V_S= 1 V/4.5 V;

Test Circuit 2

V_D= 4.5 V/1 V, V_S= 1 V/4.5 V;

Test Circuit 3

0.01

0.25

0.05

0.5

1

0.05

0.5

1

nA typ

nA max

nA typ

nA max

nA typ

nA max

1

Drain OFF Leakage I_D(OFF)

ADG725

ADG731

Channel ON Leakage I_D, I_S(ON)

ADG725

2.5

5

V_D= V_S= 1 V or 4.5 V;

Test Circuit 4

2.5

5

ADG731

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

2.4

0.8

V min

V max

I_INLor I_INH

0.005

5

µA typ

µA max

pF typ

V_IN= V_INLor V_INH

0.5

C_IN, Digital Input Capacitance

DYNAMIC CHARACTERISTICS²

t_TRANSITION

42

53

30

ns typ

ns max

ns typ

ns min

pC typ

R_L= 300 Ω, C_L= 35 pF; Test Circuit 5

V_S1= 3 V/0 V, V_S32= 0 V/3 V

R_L= 300 Ω, C_L= 35 pF

V_S= 3 V; Test Circuit 6

V_S= 2.5 V, R_S= 0 Ω, C_L= 1 nF;

Test Circuit 7

62

1

Break-Before-Make Time Delay, t_D

Charge Injection

5

Off Isolation

–72

dB typ

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 8

Channel-to-Channel Crosstalk

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 9

–3 dB Bandwidth

ADG725

ADG731

C_S(OFF)

34

18

15

MHz typ

pF typ

R_L= 50 Ω, C_L= 5 pF; Test Circuit 10

f = 1 MHz

C

_D(OFF)

ADG725

ADG731

170

340

pF typ

f = 1 MHz

C_D, C_S(ON)

ADG725

175

350

pF typ

f = 1 MHz

ADG731

POWER REQUIREMENTS

I_DD

V

_DD= 5.5 V

10

µA typ

µA max

Digital Inputs = 0 V or 5.5 V

20

NOTES

¹Temperature range is as follows: B Version: –40°C to +85°C.

²Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–2–

REV. A

ADG725/ADG731

SPECIFICATIONS¹

(V_DD= 3 V ꢀ 10%, V_SS= 0 V, GND = 0 V, unless otherwise noted.)

B Version

Parameter

+25ЊC

–40ЊC to +85ЊC

Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

0 to V_DD

V

On Resistance (R_ON

)

7

11

Ω typ

Ω max

Ω typ

Ω max

V_S= 0 V to V_DD, I_DS= 10 mA;

Test Circuit 1

V_S= 0 V to V_DD, I_DS= 10 mA

12

0.35

1

On Resistance Match between

Channels (∆R_ON

)

On Resistance Flatness (R_FLAT(ON)

)

3

V_S= 0 V to V_DD, I_DS= 10 mA

LEAKAGE CURRENTS

Source OFF Leakage I_S(OFF)

V_DD= 3.3 V

V_S= 3 V/1 V, V_D= 1 V/3 V;

Test Circuit 2

V_S= 1 V/3 V, V_D= 3 V/1 V;

Test Circuit 3

0.01

0.25

0.05

0.5

1

0.05

0.5

1

nA typ

nA max

nA typ

nA max

nA typ

nA max

1

Drain OFF Leakage I_D(OFF)

ADG725

ADG731

Channel ON Leakage I_D, I_S(ON)

ADG725

2.5

5

V_S= V_D= 1 V or 3 V;

Test Circuit 4

2.5

5

ADG731

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

2.0

0.7

V min

V max

I_INLor I_INH

0.005

5

µA typ

µA max

pF typ

V_IN= V_INLor V_INH

0.5

C_IN, Digital Input Capacitance

DYNAMIC CHARACTERISTICS²

t_TRANSITION

60

80

30

ns typ

ns max

ns typ

ns min

pC typ

R_L= 300 Ω, C_L= 35 pF; Test Circuit 5

V_S1= 2 V/0 V, V_S32= 0 V/2 V

R_L= 300 Ω, C_L= 35 pF

V_S= 2 V; Test Circuit 6

V_S= 0 V, R_S= 0 Ω, C_L= 1 nF;

Test Circuit 7

90

1

Break-Before-Make Time Delay, t_D

Charge Injection

1

Off Isolation

–72

dB typ

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 8

Channel-to-Channel Crosstalk

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 9

–3 dB Bandwidth

ADG725

ADG731

C_S(OFF)

34

18

15

MHz typ

pF typ

R_L= 50 Ω, C_L= 5 pF; Test Circuit 10

f = 1 MHz

C

_D(OFF)

ADG725

ADG731

170

340

pF typ

f = 1 MHz

C_D, C_S(ON)

ADG725

175

350

pF typ

f = 1 MHz

ADG731

POWER REQUIREMENTS

I_DD

V

_DD= 3.3 V

5

µA typ

µA max

Digital Inputs = 0 V or 3.3 V

10

NOTES

¹Temperature range is as follows: B Version: –40°C to +85°C.

²Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

REV. A

–3–

ADG725/ADG731

(V_DD= +2.5 V ꢀ 10%, V_SS= –2.5 V ꢀ 10%, GND = 0 V,

DUAL-SUPPLY SPECIFICATIONS¹^{unless otherwise noted.)}

B Version

Parameter

+25ЊC

–40ЊC to +85ЊC

Unit

Test Conditions/Comments

ANALOG SWITCH

Analog Signal Range

V

6

0.3

0.8

_SSto V_DD

V

On Resistance (R_ON

)

4

5.5

Ω typ

Ω max

Ω typ

Ω max

Ω typ

Ω max

V_S= V_SSto V_DD, I_DS= 10 mA;

Test Circuit 1

V_S= V_SSto V_DD, I_DS= 10 mA

On Resistance Match Between

Channels (∆R_ON

)

On Resistance Flatness (R_FLAT(ON)

)

0.5

V_S= V_SSto V_DD, I_DS= 10 mA

1

LEAKAGE CURRENTS

Source OFF Leakage I_S(OFF)

V_DD= +2.75 V, V_SS= –2.75 V

V_S= +2.25 V/–1.25 V, V_D= –1.25 V/+2.25 V;

Test Circuit 2

V_S= +2.25 V/–1.25 V, V_D= –1.25 V/+2.25 V;

Test Circuit 3

0.01

0.25

0.05

0.5

1

0.01

0.5

1

nA typ

nA max

nA typ

nA max

nA typ

nA max

0.5

Drain OFF Leakage I_D(OFF)

ADG725

ADG731

Channel ON Leakage I_D, I_S(ON)

ADG725

2.5

5

V_S= V_D= +2.25 V/–1.25 V; Test Circuit 4

2.5

5

ADG731

DIGITAL INPUTS

Input High Voltage, V_INH

Input Low Voltage, V_INL

Input Current

1.7

0.7

V min

V max

I_INLor I_INH

0.005

5

µA typ

µA max

pF typ

V_IN= V_INLor V_INH

0.5

C_IN, Digital Input Capacitance

DYNAMIC CHARACTERISTICS²

t_TRANSITION

55

75

15

ns typ

ns max

ns typ

ns min

pC typ

dB typ

R_L= 300 Ω, C_L= 35 pF; Test Circuit 5

V_S1= 1.5 V/0 V, V_S32= 0 V/1.5 V

R_L= 300 Ω, C_L= 35 pF

84

1

Break-Before-Make Time Delay, t_D

V_S= 1.5 V; Test Circuit 6

Charge Injection

Off Isolation

1

–72

V_S= 0 V, R_S= 0 Ω, C_L= 1 nF; Test Circuit 7

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 8

Channel-to-Channel Crosstalk

–72

dB typ

R_L= 50 Ω, C_L= 5 pF, f = 1 MHz;

Test Circuit 9

–3 dB Bandwidth

ADG725

34

18

13

MHz typ R_L= 50 Ω, C_L= 5 pF; Test Circuit 10

ADG731

MHz typ

pF typ

C_S(OFF)

C_D(OFF)

ADG725

130

260

pF typ

f = 1 MHz

ADG731

C_D, C_S(ON)

ADG725

150

300

pF typ

f = 1 MHz

ADG731

POWER REQUIREMENTS

I_DD

V_DD= +2.75 V

Digital Inputs = 0 V or 2.75 V

10

µA typ

µA max

µA typ

µA max

20

I_SS

V_SS= –2.75 V

Digital Inputs = 0 V or 2.75 V

NOTES

¹Temperature range is as follows: B Version: –40°C to +85°C.

²Guaranteed by design, not subject to production test.

Specifications subject to change without notice.

–4–

REV. A

ADG725/ADG731

TIMING CHARACTERISTICS^{1, 2}

Parameter

Limit at T_MIN, T_MAX

Unit

Conditions/Comments

f_SCLK

t₁

t₂

t₃

t₄

t₅

t₆

t₇

t₈

30

33

13

40

5

MHz max

ns min

SCLK Cycle Frequency

SCLK Cycle Time

SCLK High Time

SCLK Low Time

SYNC to SCLK Falling Edge Setup Time

Minimum SYNC Low Time

Data Setup Time

4.5

33

Data Hold Time

Minimum SYNC High Time

NOTES

¹See Figure 1.

²All input signals are specified with tr = tf = 5 ns (10% to 90% of V_DD) and timed from a voltage level of (V_IL+ V_IH)/2.

Specifications subject to change without notice.

t₁

SCLK

t₂

t₃

t₈

t₄

t₅

SYNC

t₇

t₆

DB0

DIN

DB7

Figure 1. 3-Wire Serial Interface Timing Diagram

DB0 (LSB)

A1 A0

DB7 (MSB)

CSA CSB

DB0 (LSB)

A1 A0

DB7 (MSB)

EN CS

A3

A2

X

EN

A4

A3

A2

X

DATA BITS

Figure 2. ADG725 Input Shift Register Contents

Figure 3. ADG731 Input Shift Register Contents

REV. A

–5–

ADG725/ADG731

ABSOLUTE MAXIMUM RATINGS¹

(T_A= 25°C, unless otherwise noted.)

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C

Thermal Impedance (4-Layer Board)

48-lead LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 25°C/W

48-lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.6°C/W

Lead Temperature, Soldering (10 seconds) . . . . . . . . . . 300°C

IR Reflow, Peak Temperature (<20 seconds) . . . . . . . . 235°C

V_DDto V_SS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V

V_DDto GND . . . . . . . . . . . . . . . . . . . . . . . . . . .–0.3 V to +7 V

V_SSto GND . . . . . . . . . . . . . . . . . . . . . . . . . . . .+0.3 V to –7 V

Analog Inputs². . . . . . . . . . . . . . V_SS– 0.3 V to V_DD+ 0.3 V or

30 mA, Whichever Occurs First

Digital Inputs². . . . . . . . . . . . . . . . . . –0.3 V to V_DD+ 0.3 V or

30 mA, Whichever Occurs First

NOTES

¹Stresses above those listed under Absolute Maximum Ratings may cause perma-

nent damage to the device. This is a stress rating only; functional operation of the

device at these or any other conditions above those listed in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability. Only one absolute

maximum rating may be applied at any one time.

Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA

(Pulsed at 1 ms, 10% Duty Cycle max)

Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA

Operating Temperature Range

²Overvoltages at SCLK, SYNC, DIN, S, or D will be clamped by internal diodes.

Current should be limited to the maximum ratings given.

Industrial (B Version) . . . . . . . . . . . . . . . . –40°C to +85°C

ORDERING GUIDE

Model

Temperature Range

Package Description

Package Option

ADG725BCP

–40^oC to +85^oC

Lead Frame Chip-Scale Package (LFCSP)

Thin Plastic Quad Flat Package (TQFP)

Lead Frame Chip-Scale Package (LFCSP)

Thin Plastic Quad Flat Package (TQFP)

CP-48

SU-48

CP-48

SU-48

ADG725BCP-REEL

ADG725BCP-REEL7

ADG725BSU

ADG725BSU-REEL

ADG731BCP

ADG731BCP-REEL

ADG731BCP-REEL7

ADG731BSU

ADG731BSU-REEL

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

ADG725/ADG731 features proprietary ESD protection circuitry, permanent damage may occur on

devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are

recommended to avoid performance degradation or loss of functionality.

WARNING!

ESD SENSITIVE DEVICE

–6–

REV. A

ADG725/ADG731

PIN CONFIGURATIONS

48-Lead LFCSP and TQFP

48 47 46 45 44 43 42 41 40 39 38 37

1

2

S12A

S11A

S10A

S9A

S8A

S7A

S6A

S5A

S4A

S3A

S2A

S1A

36

35

34

33

32

31

30

29

28

1

2

S12B

S12

S11

S10

S9

36

35

34

33

32

31

30

29

28

S28

S27

S26

S25

S24

S23

S22

S21

S20

PIN 1

S11B

S10B

S9B

S8B

S7B

S6B

S5B

S4B

IDENTIFIER

3

4

5

S8

ADG725

6

ADG731

6

S7

TOP VIEW

7

S6

(Not to Scale)

8

S5

9

S4

10

11

12

27 S3B

26 S2B

25 S1B

10

11

12

S3

27 S19

26 S18

25 S17

S2

S1

13 14 15 16 17 18 19 20 21 22 23 24

NC = NO CONNECT

PIN FUNCTION DESCRIPTIONS

ADG725

ADG731

Mnemonic Function

Source. May be an input or output.

1–12, 25–40, 1–12, 25–40, Sxx

45–48

13, 14

45–48

13, 14

V_DD

Power Supply Input. These parts can be operated from a single supply of 1.8 V to 5.5 V

and a dual supply of ±2.5 V.

17

SYNC

Active Low Control Input. This is the frame synchronization signal for the input

data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input

Shift Register is enabled. An 8-bit counter is also enabled. Data is transferred on the

falling edges of the following clocks. After eight falling clock edges, switch conditions

are automatically updated. SYNC may be used to frame the signal or just pulled low

for a short period of time to enable the counter and input buffers.

18

19

18

19

DIN

Serial Data Input. Data is clocked into the 8-bit Input Register MSB first on the falling

edge of the serial clock input.

SCLK

Serial Clock Input. Data is clocked into the Input Shift Register on the falling edge of

the serial clock input. These devices can accommodate serial input rates of up to 30 MHz.

23

24

23

24

GND

V_SS

Ground Reference

Most Negative Power Supply in a Dual-Supply Application. In single-supply applications,

connect to GND.

41, 43

N/A

43

DA, DB

D

Drain. May be an input or output.

REV. A

–7–

ADG725/ADG731

Table I. ADG725 Truth Table

Switch Condition

A3

A2

A1 A0 EN

CSA CSB

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

0

1

X

0

1

X

0

Retains Previous Switch Condition

All Switches OFF

S1A – DA, S1B – DB

S2A – DA, S2B – DB

S3A – DA, S3B – DB

S4A – DA, S4B – DB

S5A – DA, S5B – DB

S6A – DA, S6B – DB

S7A – DA, S7B – DB

S8A – DA, S8B – DB

S9A – DA, S9B – DB

S10A – DA, S10B – DB

S11A – DA, S11B – DB

S12A – DA, S12B – DB

S13A – DA, S13B – DB

S14A – DA, S14B – DB

S15A – DA, S15B – DB

S16A – DA, S16B – DB

X = Don’t Care

Table II. ADG731 Truth Table

Switch Condition

A4

A3

A2 A1 A0

EN

CSA

X

0

1

X

0

1

0

1

X

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

1

0

1

X

0

Retains Previous Switch Condition

All Switches OFF

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

X = Don’t Care

–8–

REV. A

ADG725/ADG731

TERMINOLOGY

Most Positive Power Supply Potential.

Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect to GND.

Positive Supply Current.

V_DD

V_SS

I_DD

I_SS

Negative Supply Current.

GND

S

D

V_D(V_S)

R_ON

⌬R_ON

R_FLAT(ON)

Ground (0 V) Reference.

Source Terminal. May be an input or output.

Drain Terminal. May be an input or output.

Analog Voltage on Terminals D, S.

Ohmic Resistance between D and S.

On Resistance Match between any Two Channels.

Flatness is defined as the difference between the maximum and minimum value of on resistance,

as measured over the specified analog signal range.

I_S(OFF)

Source Leakage Current with the Switch OFF.

Drain Leakage Current with the Switch OFF.

Channel Leakage Current with the Switch ON.

Maximum Input Voltage for Logic 0.

I

_D(OFF)

I_D, I_S(ON)

V_INL

V_INH

Minimum Input Voltage for Logic 1.

I

_INL(I_INH

C_S(OFF)

_D(OFF)

)

Input Current of the Digital Input.

OFF Switch Source Capacitance. Measured with reference to ground.

OFF Switch Drain Capacitance. Measured with reference to ground.

ON Switch Capacitance. Measured with reference to ground.

Digital Input Capacitance.

C

C_D, C_S(ON)

C_IN

t_TRANSITION

Delay time measured between the 50% points of the eighth clock falling edge and 90% points of the output

when switching from one address state to another.

t_D

OFF time measured between the 80% points of both switches when switching from one address state to another.

Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching.

OFF Isolation

Crosstalk

On Response

Insertion Loss

A measure of unwanted signal coupling through an OFF switch.

A measure of unwanted signal is coupled through from one channel to another as a result of parasitic capacitance.

The Frequency Response of the ON Switch.

The Loss Due to the On Resistance of the Switch.

REV. A

–9–

ADG725/ADG731–Typical Performance Characteristics

8

7

6

5

4

3

2

8

7

6

5

4

3

2

1

0

8

7

6

5

4

3

2

V

= 2.7V

DD

V

= 0V

T

V

= 25ꢂC

SS

A

= 0V

SS

T

V

= 25ꢂC

A

V

= +2.25V

= –2.25V

DD

V

= 3.0V

DD

= +2.5V

= –2.5V

DD

V

SS

V

= 5.5V

DD

SS

V

= 3.3V

DD

+85ꢂC

+25ꢂC

V

= +2.75V

DD

V

= –2.75V

SS

–40ꢂC

V

= 4.5V

DD

V

= 5V

DD

1

0

1

0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0

0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

–2.75 –1.75 –0.75

0.25

V , V –V

D

1.25

2.25

V

, V –V

V

, V –V

D

S

D

S

TPC 3. On Resistance vs. V_D(V_S)

for Different Temperatures,

Single Supply

TPC 2. On Resistance vs.

V_D(V_S), Dual Supply

TPC 1. On Resistance vs.

V_D(V_S), Single Supply

0.5

0.4

8

7

6

5

4

3

8

7

6

5

4

3

2

V

= 5V

= 0V

V

= 0V

DD

SS

V

SS

0.3

+25ꢂC

+85ꢂC

–40ꢂC

I

(OFF)

D

0.2

0.1

+85ꢂC

+25ꢂC

0.0

–0.1

–0.2

–0.3

–0.4

–0.5

I

(ON)

I

(OFF)

D

S

–40ꢂC

2

1

0

1

0

–2.5–2.0–1.5–1.0–0.5 0.0 0.5 1.0 1.5 2.0 2.5

5

15

25

35

45

55

65

75

85

0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0

V

, V –V

TEMPERATURE – ꢂC

V

, V –V

D

S

D

S

TPC 5. On Resistance vs.

V_D(V_S), Dual Supply

TPC 4. On Resistance vs. V_D(V_S),

Single Supply

TPC 6. Leakage Currents vs.

Temperature

80

25

1.8

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0

V

= 0V

SS

V

= 3V

DD

20

15

10

5

70

60

50

40

30

20

V

= +2.5

= –2.5

DD

V

SS

RISING

V

= +3V

= 0V

DD

FALLING

V

SS

0

V

= 5V

DD

V

= +5V

= 0V

DD

–5

–10

–15

V

SS

10

0

T

= 25ꢂC

A

T

= 25ꢂC

A

–3 –2 –1

0

1

2

3

4

5

–40

–20

0

20

40

60

80

0

1

2

3

4

5

6

V

, V –V

TEMPERATURE – ꢂC

V

–V

D

S

DD

TPC 9. Logic Threshold Voltage

vs. Supply Voltage

TPC 8. Switching Times vs.

Temperature

TPC 7. ADG731 Charge Injection

vs. Source Voltage

–10–

REV. A

ADG725/ADG731

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

ADG725

V

= 5V

= 25ꢂC

DD

V

= 3V, 5V

= 25ꢂC

DD

V

= 5V

DD

T

A

–2

T

A

T

A

= 25ꢂC

–4

–6

ADG731

–8

–10

–12

–14

0.03 0.1

1

10

100

0.003

0.1

1

10

100

0.03 0.1

1

10

100

FREQUENCY – MHz

TPC 10. OFF Isolation vs. Frequency

TPC 11. Crosstalk vs. Frequency

TPC 12. ON Response vs. Frequency

Test Circuits

I

DS

V

DD

SS

V1

V

SS

DD

S1

S2

I

(OFF)

D

A

S

D

S32

V

D

EN

V

S

LOGIC 1

GND

V

S

R

= V /I

1 DS

ON

Test Circuit 1. On Resistance

Test Circuit 3. I_D(OFF)

V

SS

DD

V

SS

V

DD

SS

(

I

D

)

ON

I

(OFF)

A

S

V

SS

DD

D

S1

S2

A

S32

D

V

S

V

D

S32

EN

V

S

GND

LOGIC 1

V

S

V

GND

D

Test Circuit 2. I_S(OFF)

Test Circuit 4. I_D(ON)

REV. A

–11–

ADG725/ADG731

TEST CIRCUITS (continued)

8TH FALLING EDGE

50%

8TH FALLING EDGE

50%

V

SS

DD

V

SS

SCLK

VS1

DD

S1

V

S1

S2 TO S31

S32

D

V

S32

ADG731*

90%

V

OUT

C

35pF

V

R

300ꢁ

L

OUT

L

GND

90%

VS32

t

*SIMILAR CONNECTION FOR ADG725

TRANSITION

Test Circuit 5. Switching Time of Multiplexer, t_TRANSITION

V

SS

DD

8TH FALLING EDGE

SCLK

V

SS

DD

1

V

S

0V

V

S2 THRU S31

ADG731*

S32

D

S

V

OUT

80%

C

R

L

V

OUT

GND

35pF

300ꢁ

t_OPEN

*SIMILAR CONNECTION FOR ADG725

Test Circuit 6. Break-Before-Make Delay, t_OPEN

V

DD

SS

8th FALLING EDGE

V

DD

SS

SCLK

ADG731*

R

S

D

V

OUT

C

L

1nF

V

S

V

OUT

ꢃV

OUT

GND

ꢄ ꢃ

V

OUT

Q

= C

INJ

L

*SIMILAR CONNECTION FOR ADG725

Test Circuit 7. Charge Injection

–12–

REV. A

ADG725/ADG731

POWER-ON RESET

V

SS

DD

On power-up of the device, all switches will be in the OFF

condition. The Internal Shift Register is filled with zeros and

will remain so until a valid write takes place.

␮

0.1 F

␮

0.1

F

NETWORK

ANALYZER

V

SS

DD

SERIAL INTERFACE

50⍀

S

The ADG725 and ADG731 have a 3-wire serial interface

(SYNC, SCLK, and DIN) that is compatible with SPI, QSPI,

and MICROWIRE interface standards and most DSPs.

Figure 1 shows the timing diagram of a typical write sequence.

50⍀

V

S

D

V

OUT

R

L

ADG731*

50⍀

GND

Data is written to the 8-bit Shift Register via DIN under the

control of the SYNC and SCLK signals.

V

OUT

OFF ISOLATION = 20 LOG

V

When SYNC goes low, the Input Shift Register is enabled. An

8-bit counter is also enabled. Data from DIN is clocked into the

Shift Register on the falling edge of SCLK. Figures 2 and 3

show the contents of the Input Shift Registers for these devices.

When the part has received eight clock cycles after SYNC has

been pulled low, the switches are automatically updated with

the new configuration and the Input Shift Register is disabled.

S

*SIMILAR CONNECTION FOR ADG725

Test Circuit 8. OFF Isolation

V

SS

DD

S1

V

DD

SS

NETWORK

ANALYZER

50⍀

The ADG725 CSA and CSB data bits allow the user the flex-

ibility to change the configuration of either or both banks of the

multiplexer.

ADG731* ^S2

50⍀

S32

V

S

V

D

OUT

R

L

MICROPROCESSOR INTERFACING

GND

50⍀

Microprocessor interfacing to the ADG725/ADG731 is via a serial

bus that uses standard protocol compatible with microcontrollers

and DSP processors. The communications channel is a 3-wire

interface consisting of a clock signal, a data signal, and a

synchronization signal. The ADG725/ADG731 requires an

8-bit data-word with data valid on the falling edge of SCLK.

*SIMILAR CONNECTION FOR ADG725

CHANNEL-TO-CHANNEL CROSSTALK = 20 LOG

V

OUT

V

S

Test Circuit 9. Channel-to-Channel Crosstalk

Figures 4–7 illustrate simple 3-wire interfaces with popular

microcontrollers and DSPs.

V

SS

DD

␮

F

␮

0.1 F

0.1

ADSP-21xx to ADG725/ADG731 Interface

NETWORK

ANALYZER

The ADSP-21xx family of DSPs are easily interfaced to the

ADG725/ADG731 without the need for extra logic. Figure 4

shows an example of an SPI interface between the ADG725/

ADG731 and the ADSP-2191M. SCK of the ADSP-2191M

drives the SCLK of the mux, while the MOSI output drives the

serial data line, DIN. SYNC is driven from one of the port lines,

in this case SPIxSEL.

V

SS

DD

S

50⍀

V

S

D

V

OUT

R

ADG731^*

L

50⍀

GND

V

WITH SWITCH

SYNC

OUT

SPIxSEL

INSERTION LOSS = 20 LOG

V

WITHOUT SWITCH

OUT

ADG725/ADG731

ADSP-2191M

*

*SIMILAR CONNECTION FOR ADG725

MOSI

DIN

Test Circuit 10. Bandwidth

SCLK

SCK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 4. ADSP-2191M to ADG725/ADG731 Interface

REV. A

–13–

ADG725/ADG731

A serial interface between the ADG725/ADG731 and the ADSP-

2191M SPORT is shown in Figure 5. In this interface example,

SPORT0 is used to transfer data to the switch. Transmission is

initiated by writing a word to the Tx Register after the SPORT

has been enabled. In a write sequence, data is clocked out on

each rising edge of the DSP’s serial clock and clocked into the

ADG725/ADG731 on the falling edge of its SCLK. The update

of each switch condition takes place automatically after the eighth

SCLK falling edge, regardless of the frame sync condition.

MC68HC11 Interface to ADG725/ADG731

Figure 7 shows an example of a serial interface between the

ADG725/ADG731 and the MC68HC11 microcontroller. SCK

of the 68HC11 drives the SCLK of the mux, while the MOSI

output drives the serial data line, DIN. SYNC is driven from

one of the port lines, in this case PC7. The 68HC11 is config-

ured for Master Mode: MSTR = 1, CPOL = 0, and CPHA = 1.

When data is transferred to the part, PC7 is taken low, and data

is transmitted MSB first. Data appearing on the MOSI output is

valid on the falling edge of SCK.

Communication between two devices at a given clock speed is

possible when the following specs are compatible: frame sync

delay and frame sync setup and hold, data delay and data setup

and hold, and SCLK width. The ADG725/ADG31 expects a

t₄(SYNC falling edge to SCLK falling edge set-up time) of 13 ns

minimum. Consult the ADSP-21xx User Manual for information

on clock and frame sync frequencies for the SPORT Register.

PC7

SYNC

MC68HC11

*

ADG725/ADG731

MOSI

DIN

SCK

SCLK

The SPORT Control Register should be set up as follows:

TFSW = 1, Alternate Framing

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 7. MC68HC11 Interface to ADG725/ADG731

INVTFS = 1, Active Low Frame Signal

DTYPE = 00, Right Justify Data

APPLICATION CIRCUITS

ADG725/ADG731 in an Optical Network Control Loop

The ADG725/ADG731 can be used in optical network applica-

tions that have higher port counts and greater multiplexing

requirements. The ADG725/ADG731 are well suited to these

applications because they allow a single control circuit to con-

nect a higher number of channels without increasing board size

and design complexity.

ISCLK = 1, Internal Serial Clock

TFSR = 1, Frame Every Word

ITFS = 1, Internal Framing Signal

SLEN = 0111, 8-Bit Data-Word

SYNC

TFS

In the circuit shown in Figure 8, the 0 V to 5 V outputs of the

AD5532HS are amplified to a range of 0 V to 180 V and then

used to control actuators that determine the position of MEMS

mirrors in an optical switch. The exact position of each mirror is

measured using sensors. The sensor readings are muxed using

the ADG731, a 32-channel switch, and fed back to a single-

channel 14-bit ADC (AD7894).

ADSP-2191M

*

ADG725/ADG731

DIN

DT

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 5. ADSP-2191M to ADG725/ADG731 Interface

The control loop is driven by an ADSP-2191L, a 32-bit DSP

with an SPI compatible SPORT interface. It writes data to the

DAC, controls the multiplexer, and reads data from the ADC

via a 3-wire serial interface.

8051 to ADG725/ADG731 Interface

A serial interface between the ADG725/ADG731 and the 8051

is shown in Figure 6. TXD of the 8051 drives SCLK of the

ADG725/ADG731, while RXD drives the serial data line, DIN.

P3.3 is a bit-programmable pin on the serial port and is used to

drive SYNC.

1

MEMS

MIRROR

ARRAY

The 8051 provides the LSB of its SBUF Register as the first bit

in the data stream. The user will have to ensure that the data in

the SBUF Register is arranged correctly as the switch expects

MSB first.

AD5532HS

ADG731

AD7894

32

When data is to be transmitted to the switch, P3.3 is taken low.

Data on RXD is clocked out of the microcontroller on the rising

edge of TXD and is valid on the falling edge. As a result, no

glue logic is required between the ADG725/ADG731 and

microcontroller interface.

ADSP-2191M

Figure 8. Optical Network Control Loop

P3.3

SYNC

Expand the Number of Selectable Serial Devices Using the

ADG725/ADG731

80C51/80L51

*

The SYNC pin of the ADG725/ADG731 can be used to select

one of a number of multiplexers. All devices receive the same

serial clock and serial data, but only one device will receive the

RXD

DIN

TXD

SCLK

*ADDITIONAL PINS OMITTED FOR CLARITY

Figure 6. 8051 to ADG725/ADG731 Interface

–14–

REV. A

ADG725/ADG731

SYNC signal at any one time. The mux addressed will be deter-

mined by the decoder. There will be some digital feedthrough

from the digital input lines. Using a burst clock will minimize the

effects of digital feedthrough on the analog signal channels.

Figure 9 shows a typical circuit.

ADG725/

SCLK

DIN

ADG731

SYNC

D

DIN

VDD

SCLK

ADG725/

ENABLE

EN

ADG731

SYNC

CODED

ADDRESS

DECODER

DGND

D

DIN

SCLK

OTHER SPI

DEVICE

SYNC

D

DIN

SCLK

OTHER SPI

DEVICE

SYNC

D

DIN

SCLK

Figure 9. Addressing Multiple ADG725/ADG731s

Using a Decoder

REV. A

–15–

ADG725/ADG731

OUTLINE DIMENSIONS

48-Lead Lead Frame Chip Scale Package [LFCSP]

(CP-48)

Dimensions shown in millimeters

0.30

7.00

BSC SQ

0.23

0.18

0.60 MAX

PIN 1

INDICATOR

37

48

36

1

PIN 1

INDICATOR

5.25

5.10 SQ

4.95

6.75

BSC SQ

BOTTOM

VIEW

TOP

VIEW

0.50

0.40

0.30

25

24

12

13

5.50

REF

0.80 MAX

0.65 NOM

1.00

0.90

0.80

12ꢂ MAX

0.05 MAX

0.02 NOM

0.20

REF

0.50 BSC

COPLANARITY

0.08

SEATING

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2

48-Lead Thin Plastic Quad Flat Package [TQFP]

(SU-48)

Dimensions shown in millimeters

1.20

9.00

0.75

0.60

0.45

MAX

BSC SQ

37

48

36

1

SEATING

PLANE

7.00

BSC SQ

TOP VIEW

(PINS DOWN)

COPLANARITY

0.08 MAX

12

25

0ꢂ

13

24

MIN

0.15 MAX

0.05 MIN

0.27

0.22

0.17

0.50

BSC

1.05

1.00

0.95

0.20

0.09

7ꢂ

0ꢂ

COMPLIANT TO JEDEC STANDARDS MS-026ABC

Revision History

Location

Page

6/03—Data Sheet changed from REV. 0 to REV. A.

Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Edits to PIN CONFIGURATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Edits to PIN FUNCTION DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Changes to Test Circuit 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

–16–

REV. A


型号：	ADG731BCP-REEL
厂家：	ADI
描述：	16-/32-Channel, Serially Controlled 4 1.8 V to 5.5 V, 2.5 V, Analog Multiplexers 16位/ 32通道，串行控制4 1.8 ？ V至5.5 V ，？ 2.5 V ，模拟多路复用器复用器
文件：	总16页 (文件大小：362K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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