ADG731BSU [ADI]
16-/32- Channel, Serially Controlled 4 з 1.8 V to 5.5 V, 【2.5 V, Analog Multiplexers; 16位/ 32通道，串行控制4 з 1.8 V至5.5 V ， 【 2.5 V ，模拟多路复用器
| 型号： | ADG731BSU |
| 厂家： | 
ADI |
| 描述： | 16-/32- Channel, Serially Controlled 4 з 1.8 V to 5.5 V, 【2.5 V, Analog Multiplexers |
| 文件： | 总15页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
16-/32- Channel, Serially Controlled 4 Ω
1.8 V to 5.5 V, 2.5 V, Analog Multiplexers
a
ADG725/ADG731
Preliminary Technical Data
3-Wire SPI Serial Interface
1.8 V to 5.5 V Single Supply
2.5 V Dual Supply Operation
4 Ω On Resistance
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
ADG731
ADG725
S1
S1A
0.5 Ω On Resistance Flatness
7mm x 7mm 48 lead Chip Scale Package (CSP)
or 48 lead TQFP package.
DA
S16A
Rail to Rail Operation
D
Power On Reset
Fast Switching Times
S1B
Single 32 to 1 Channel Multiplexer
Dual/Differential 16 to 1 Channel Multiplexer
TTL/CMOSCompatibleInputs
For Functionally Equivalent devices with Parallel Interface
See ADG726/ADG732
DB
S32
S16B
INPUT SHIFT
REGISTER
INPUT SHIFT
REGISTER
APPLICATIONS
SCLK
DIN
SCLK
DIN SYNC
SYNC
OpticalApplications
Data Acquisition Systems
CommunicationSystems
Relay replacement
Audio and Video Switching
Battery Powered Systems
MedicalInstrumentation
Automatic Test Equipment
GENERAL DESCRIPTION
and have an input signal range which extends to the sup-
plies. In the OFF condition, signal levels up to the
supplies are blocked. All channels exhibit break before
make switching action preventing momentary shorting
when switching channels.
The ADG725/ADG731 are monolithic CMOS 32
channel/dual 16 channel analog multiplexers with a
serially controlled 3-wire interface. The ADG732 switches
one of thirty-two inputs (S1-S32) to a common output, D.
The ADG725 can be configured as a dual mux switching
one of sixteen inputs to one output or a differential mux
switching one of sixteen inputs to a differential output.
They are available in either 48 lead CSP or TQFP
package.
These mulitplexers utilize a 3-wire serial interface that is
compatible with SPITM, QSPITM, MICROWIRETM and
some DSP interface standards. On power-up, the internal
shift register contains all zeros and all switch are in the
OFF state.
PRODUCT HIGHLIGHTS
1. 3-Wire Serial Interface.
2. +1.8 V to +5.5 V Single or 2.5 V Dual Supply
operation. These parts are specified and guaranteed
with +5 V 1ꢀ0, +3 V 1ꢀ0 single supply and
2.5 V 1ꢀ0 dual supply rails.
These multiplexers are designed on an enhanced submi-
cron process that provides low power dissipation yet gives
high switching speed, very low on resistance and leakage
currents. They operate from single supply of 1.8V to 5.5V
and 2.5 V dual supply, making them ideally suited to a
variety of applications. On resistance is in the region of a
few Ohms and is closely matched between switches and
very flat over the full signal range. These parts can operate
equally well as either Multiplexers or De-Multiplexers
3. On Resistance of 4 Ω.
4. Guaranteed Break-Before-Make Switching Action.
5. 7mm x 7mm 48 lead Chip Scale Package (CSP)
or 48 lead TQFP package.
REV. PrD May 2002
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
Analog Devices, Inc., 2002
PRELIMINARY TECHNICAL DATA
1
(VDD = 5V 1ꢀ0, VSS = ꢀV, GND = ꢀ V, unless otherwise noted)
ADG725/ADG731–SPECIFICATIONS
B Version
–40°C
Parameter
+25oC
to +85°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
ꢀ V to VDD
V
On-Resistance (RON
)
4
5.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = ꢀ V to VDD, IDS = 1ꢀ mA;
Test Circuit 1
VS = ꢀ V to VDD , IDS = 1ꢀ mA
6
ꢀ.3
ꢀ.8
On-Resistance Match Between
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
ꢀ.5
VS = ꢀ V to VDD, IDS = 1ꢀ mA
1
LEAKAGE CURRENTS
VDD = 5.5 V
Source OFF Leakage IS (OFF)
ꢀ.ꢀ1
ꢀ.25
ꢀ.ꢀ5
ꢀ.5
1
ꢀ.ꢀ5
ꢀ.5
1
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 3
ꢀ.5
Drain OFF Leakage ID (OFF)
ADG725
ADG731
Channel ON Leakage ID, IS (ON)
ADG725
ADG726
2.5
5
VD = VS = 1 V, or 4.5V;
Test Circuit 4
2.5
5
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
ꢀ.8
V min
V max
IINL or IINH
ꢀ.ꢀꢀ5
5
µA typ
µA max
pF typ
VIN = VINL or VINH
ꢀ.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
4ꢀ
3ꢀ
5
ns typ
ns max
ns typ
ns min
pC typ
RL = 3ꢀꢀ Ω, CL = 35 pF,Test Circuit 5;
VS1 = 3 V/ꢀ V, VS32 = ꢀ V/3V
RL = 3ꢀꢀ Ω, CL = 35 pF;
VS = 3 V, Test Circuit 6
VS = ꢀ V, RS = ꢀ Ω, CL = 1 nF;
Test Circuit 7
6ꢀ
1
Break-Before-Make Time Delay, tD
Charge Injection
Off Isolation
-6ꢀ
-6ꢀ
dB typ
dB typ
RL = 5ꢀ Ω, CL = 5 pF, f = 1ꢀꢀ kHz;
Test Circuit 8
RL = 5ꢀ Ω, CL = 5 pF, f = 1ꢀꢀ kHz;
Test Circuit 9
Channel to Channel Crosstalk
-3 dB Bandwidth
ADG725
ADG731
CS (OFF)
CD (OFF)
ADG725
34
18
13
MHz typ RL = 5ꢀ Ω, CL = 5 pF, Test Circuit 1ꢀ
MHz typ
pF typ
f = 1 MHz
18ꢀ
36ꢀ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG731
CD, CS (ON)
ADG725
2ꢀꢀ
4ꢀꢀ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG731
POWER REQUIREMENTS
IDD
VDD = +5.5 V
Digital Inputs = ꢀ V or +5.5 V
1ꢀ
µA typ
2ꢀ
µA max
NOTES
1Temperature range is as follows: B Version: –4ꢀ°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
1
(VDD = 3V 1ꢀ0, VSS = ꢀV, GND = ꢀ V, unless otherwise noted)
SPECIFICATIONS
B Version
–40°C
Parameter
+25oC
to +85°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
ꢀ V to VDD
V
On-Resistance (RON
)
7
11
Ω typ
Ω max
Ω typ
Ω max
Ω max
VS = ꢀ V to VDD, IDS = 1ꢀ mA;
Test Circuit 1
VS = ꢀ V to VDD , IDS = 1ꢀ mA
12
ꢀ.4
1
On-Resistance Match Between
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
3
VS = ꢀ V to VDD, IDS = 1ꢀ mA
LEAKAGE CURRENTS
VDD = 3.3 V
Source OFF Leakage IS (OFF)
ꢀ.ꢀ1
ꢀ.25
ꢀ.ꢀ5
ꢀ.5
1
ꢀ.ꢀ5
ꢀ.5
1
nA typ
nA max
nA typ
nA max
nA max
nA typ
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = 1 V/3 V, VD = 3 V/1 V;
Test Circuit 3
ꢀ.5
Drain OFF Leakage ID (OFF)
ADG725
ADG731
Channel ON Leakage ID, IS (ON)
ADG725
ADG731
2.5
5
VS = VD = +1 V or +3 V;
Test Circuit 4
2.5
5
nA max
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.ꢀ
ꢀ.8
V min
V max
IINL or IINH
ꢀ.ꢀꢀ5
5
µA typ
µA max
pF typ
VIN = VINL or VINH
ꢀ.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
45
3ꢀ
5
ns typ
ns max
ns typ
ns min
pC typ
RL = 3ꢀꢀ Ω, CL = 35 pF Test Circuit 5
VS1 = 2 V/ꢀ V, VS32 = ꢀ V/2 V
RL = 3ꢀꢀ Ω, CL = 35 pF;
VS = 2 V, Test Circuit 6
VS = ꢀ V, RS = ꢀ Ω, CL = 1 nF;
Test Circuit 7
75
1
Break-Before-Make Time Delay, tD
Charge Injection
Off Isolation
-6ꢀ
-6ꢀ
dB typ
dB typ
RL = 5ꢀ Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
RL = 5ꢀ Ω, CL = 5 pF, f = 1 MHz;
Channel to Channel Crosstalk
Test Circuit 9
-3 dB Bandwidth
ADG725
ADG731
CS (OFF)
CD (OFF)
ADG725
34
18
13
MHz typ
MHz typ
pF typ
RL = 5ꢀ Ω, CL = 5 pF, Test Circuit 1ꢀ
f = 1 MHz
18ꢀ
36ꢀ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG731
CD, CS (ON)
ADG725
ADG731
2ꢀꢀ
4ꢀꢀ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +3.3 V
Digital Inputs = ꢀ V or +3.3 V
1ꢀ
µA typ
2ꢀ
µA max
NOTES
1Temperature ranges are as follows: B Version: –4ꢀ°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. PrD
–3–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731–SPECIFICATIONS1
Dual Supply
(VDD = +2.5 V 1ꢀ0, VSS = -2.5 V 1ꢀ0, GND = ꢀ V, unless otherwise noted)
B Version
–40°C
Parameter
+25oC
to +85°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VSS to VDD
V
On-Resistance (RON
)
4
5.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = VSS to VDD, IDS = 1ꢀ mA;
Test Circuit 1
VS = VSS to VDD, IDS = 1ꢀ mA
6
ꢀ.3
ꢀ.8
On-Resistance Match Between
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
ꢀ.5
VS = VSS to VDD, IDS = 1ꢀ mA
1
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
VDD = +2.75 V, VSS = -2.75 V
VS =+2.25V/-1.25V,VD =-1.25V/+2.25V;
Test Circuit 2
VS =+2.25V/-1.25V,VD =-1.25V/+2.25V;
Test Circuit 3
ꢀ.ꢀ1
ꢀ.25
ꢀ.ꢀ5
ꢀ.5
1
ꢀ.ꢀ1
ꢀ.5
1
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
ꢀ.5
Drain OFF Leakage ID (OFF)
2.5
5
Channel ON Leakage ID, IS (ON)
VS =VD =+2.25V/-1.25V,TestCircuit4
2.5
5
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
1.7
ꢀ.7
V min
V max
IINL or IINH
ꢀ.ꢀꢀ5
5
µA typ
µA max
pF typ
VIN = VINL or VINH
ꢀ.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
4ꢀ
15
ns typ
ns max
ns typ
ns min
pC typ
dB typ
RL = 3ꢀꢀ Ω, CL = 35 pF Test Circuit 5
VS1 = 1.5 V/ꢀ V,VS32 = ꢀ V/1.5 V
RL = 3ꢀꢀ Ω, CL = 35 pF;
6ꢀ
1
Break-Before-Make Time Delay, tD
VS = 1.5 V, Test Circuit 6
Charge Injection
Off Isolation
8
-6ꢀ
VS = ꢀ V, RS = ꢀ Ω, CL = 1 nF; Test 7
RL = 5ꢀ Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 8
Channel to Channel Crosstalk
-6ꢀ
dB typ
RL = 5ꢀ Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 9
-3 dB Bandwidth
ADG725
ADG731
CS (OFF)
CD (OFF)
ADG725
34
18
13
MHz typ RL = 5ꢀ Ω, CL = 5 pF, Test Circuit 1ꢀ
MHz typ
pF typ
18ꢀ
36ꢀ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG731
CD, CS (ON)
ADG725
2ꢀꢀ
4ꢀꢀ
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG731
POWER REQUIREMENTS
IDD
VDD = +2.75 V
Digital Inputs = ꢀ V or +2.75 V
1ꢀ
1ꢀ
µA typ
µA max
µA typ
µA max
2ꢀ
2ꢀ
ISS
VSS = -2.75 V
Digital Inputs = ꢀ V or +2.75 V
NOTES
1Temperature range is as follows: B Version: –4ꢀ°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TIMINGCHARACTERISTICS1,2
Parameter
Limit at TMIN, TMAX
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
33
13
13
13
4ꢀ
5
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
SCLK Cycle time
SCLK High Time
SCLK Low Time
SYNC to SCLK falling edge setup time
Minimum SYNC low time
Data Setup Time
4.5
33
Data Hold Time
Minimum SYNC high time
NOTES
1See Figure 1.
2All input signals are specified with tr =tf = 5ns (1ꢀ0 to 9ꢀ0 of VDD) and timed from a voltage level of (VIL + VIH)/2.
Specifications subject to change without notice.
t
1
SCLK
t
t
2
3
t
8
t
4
t
5
SYNC
DIN
t
7
t
6
DB7
DB0
Figure 1. 3-Wire Serial Interface Timing Diagram.
DB0 (LSB)
A1 A0
DB7 (MSB)
EN CS
DB0 (LSB)
A1 A0
DB7 (MSB)
EN CSA
A3
DATA BITS
A2
A4
A3
A2
CSB
X
X
DATA BITS
Figure 2. ADG725 Input Shift Register Contents
Figure 3. ADG731 Input Shift Register Contents
REV. PrD
–5–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
ABSOLUTE MAXIMUM RATINGS1
Storage Temperature Range
Junction Temperature
–65°C to +15ꢀ°C
+15ꢀ°C
(TA = +25°C unless otherwise noted)
48 lead CSP θJA Thermal Impedance
48 lead TQFP θJA Thermal Impedance
Lead Temperature, Soldering (1ꢀseconds)
TBD°C/W
TBD°C/W
VDD to VSS
+7 V
–ꢀ.3 V to +7 V
+ꢀ.3 V to -7 V
VDD to GND
VSS to GND
3ꢀꢀ°C
+22ꢀ°C
Analog Inputs2
VSS - ꢀ.3 V to VDD +ꢀ.3 Vor
3ꢀ mA, Whichever Occurs First
-ꢀ.3V to VDD +ꢀ.3 V or
3ꢀ mA, Whichever Occurs First
6ꢀmA
IR Reflow, Peak Temperature
NOTES
1Stressesabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanent
damagetothedevice.Thisisastressratingonlyandfunctionaloperationofthedevice
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extendedperiodsmayaffectdevicereliability.Onlyoneabsolutemaximumratingmay
be applied at any one time.
Digital Inputs2
Peak Current, S or D
(Pulsed at 1 ms, 1ꢀ0 Duty Cycle max)
Continuous Current, S or D
Operating Temperature Range
Industrial (B Version)
3ꢀmA
2Overvoltages at SCLK, SYNC, DIN, RS, S or D will be clamped by internal diodes.
Current should be limited to the maximum ratings given.
–4ꢀ°C to +85°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4ꢀꢀꢀ V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG725/ADG731 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
o
o
ADG725BCP
ADG725BSU
ADG731BCP
ADG731BSU
-4ꢀ C to +85 C
Chip Scale Package (CSP)
Thin Quad Flatpack
Chip Scale Package (CSP)
Thin Quad Flatpack
CP-48
SU-48
CP-48
SU-48
o
o
-4ꢀ C to +85 C
o
o
-4ꢀ C to +85 C
o
o
-4ꢀ C to +85 C
–6–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
PIN FUNCTION DESCRIPTION
ADG725
ADG731 Mnemonic Function
SCLK
Serial Clock Input. Data is clocked into the input shift register on the falling edge of
the serial clock input. These devices can accomodate serial input rates of up to
3ꢀMHz.
RS
Active low control input that clears the input register and turns all switches to the
OFF condition.
DIN
Serial Data Input. Data is clocked into the 8-bit input register on the falling edge of
the serial clock input.
SXX
DX
Source. May be an input or output.
Drain. May be an input or output.
VDD
Power Supply Input. These parts can be operated from a supply of +1.8V to +5.5V
and dual supply of +/-2.5V.
GND
Ground reference.
SYNC
Active Low Control Input. This is the frame synchronization signal for the input
data. When SYNC goes low, it powers on the SCLK and DIN buffers and the input
shift register is enabled. An 8-bit counter is also enabled. Data is transferred on the
falling edges of the following clocks. After 8 falling clock edges, switch conditions
are automaticaly updated. SYNC may be used to frame the signal, or just pulled low
for a short period of time to enable the counter and input buffers.
PIN CONFIGURATIONS
CSP & TQFP
48 47 46 45 44 43 42 41 40 39 38 37
48 47 46 45 44 43 42 41 40 39 38 37
1
2
1
2
S12A
S11A
S10A
S9A
S8A
S7A
S6A
S5A
S4A
S3A
S2A
S1A
36
35
34
33
32
31
30
29
28
27
26
25
S12
S11
S10
S9
36
35
34
33
32
31
30
29
28
27
26
25
S12B
S11B
S10B
S9B
S8B
S7B
S6B
S5B
S4B
S3B
S2B
S1B
S28
S27
S26
S25
S24
S23
S22
S21
S20
S19
S18
S17
PIN 1
IDENTIFIER
PIN 1
IDENTIFIER
3
3
4
4
5
5
S8
ADG725
TOP VIEW
(Not to Scale)
ADG731
TOP VIEW
(Not to Scale)
6
6
S7
7
7
S6
8
8
S5
9
9
S4
10
11
12
10
11
12
S3
S2
S1
13 14 15 16 17 18 19 20 21 22 23 24
13 14 15 16 17 18 19 20 21 22 23 24
NC = NO CONNECT
NC = NO CONNECT
REV. PrD
–7–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
Table 1. ADG725 Truth Table
A3
A2
A1 A0 E N
C S A C S B
SwitchCondition
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
1
1
1
1
X
X
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
X
X
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
X
X
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
X
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Retains previous switch condition
All Switches OFF
S1A - DA, S1B - DB
S2A - DA, S2B - DB
S3A - DA, S3B - DB
S4A - DA, S4B - DB
S5A - DA, S5B - DB
S6A - DA, S6B - DB
S7A - DA, S7B - DB
S8A - DA, S8B - DB
S9A - DA, S9B - DB
S1ꢀA - DA, S1ꢀB - DB
S11A - DA, S11B - DB
S12A - DA, S12B - DB
S13A - DA, S13B - DB
S14A - DA, S14B - DB
S15A - DA, S15B - DB
S16A - DA, S16B - DB
Table 2. ADG731 Truth Table
A2 A1 A0 E N C S SwitchCondition
A4
A3
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
1
1
1
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
1
1
1
1
X
X
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
ꢀ
ꢀ
ꢀ
ꢀ
1
1
1
1
X
X
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
ꢀ
ꢀ
1
1
X
X
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
ꢀ
1
X
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
1
1
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
Retains previous switch condition
All Switches OFF
1
2
3
4
5
6
7
8
9
1ꢀ
11
12
13
14
15
16
17
18
19
2ꢀ
21
22
23
24
25
26
27
28
29
3ꢀ
31
32
X = Don’t Care
–8–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TERMINOLOGY
VDD
VSS
Most positive power supply potential.
Most Negative power supply in a dual supply application. In single supply applications, connect to GND.
Positive supply current.
IDD
ISS
Negative supply current.
GND
S
Ground (ꢀ V) reference.
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input.
D
IN
VD (VS)
RON
∆RON
RFLAT(ON)
Analog voltage on terminals D, S
Ohmic resistance between D and S.
On resistance match between any two channels, i.e. RONmax - RONmin
Flatness is defined as the difference between the maximum and minimum value of on-resistance as mea
sured over the specified analog signal range.
IS (OFF)
ID (OFF)
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
ID, IS (ON) Channel leakage current with the switch “ON.”
VINL
Maximum input voltage for logic “ꢀ”.
VINH
Minimum input voltage for logic “1”.
IINL(IINH
)
Input current of the digital input.
CS (OFF)
CD (OFF)
“OFF” switch source capacitance. Measured with reference to ground.
“OFF” switch drain capacitance. Measured with reference to ground.
CD,CS(ON) “ON” switch capacitance. Measured with reference to ground.
CIN
Digital input capacitance.
tTRANSITION
Delay time measured between the 5ꢀ0 and 9ꢀ0 points of the SYNC and the switch “ON” condi
tion when switching from one address state to another.
tOPEN
“OFF” time measured between the 8ꢀ0 points of both switches when switching from one address state to
another.
Charge
Injection
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
Off Isolation A measure of unwanted signal coupling through an “OFF” switch.
Crosstalk
A measure of unwanted signal is coupled through from one channel to another as a result of parasitic
capacitance.
On Response The Frequency response of the “ON” switch.
Insertion
Loss
The loss due to the ON resistance of the switch.
REV. PrD
–9–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TYPICAL PERFORMANCE CHARACTERISTICS
TBD
TBD
TBD
TPC 7. Leakage Currents vs. VD(VS)
TPC 4. On Resistance vs. VD(VS) for
Different Temperatures, Single
Supply
TPC 1. On Resistance vs. VD(VS) for for
SingleSupply
TBD
TBD
TBD
TPC 8. Leakage Currents vs. VD(VS)
TPC 5. On Resistance vs. VD(VS) for
Different Temperatures, Dual Supply
TPC 2. On Resistance vs. VD(VS) for
Dual Supply
TBD
TBD
TBD
TPC 9. Leakage Currents vs.
Temperature
TPC 6. Leakage Currents vs. VD(VS)
TPC 3. On Resistance vs. VD(VS) for
Different Temperatures, Single
Supply
–10–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TBD
TBD
TBD
TPC 10. Leakage Currents vs.
Temperature
TPC 13. TON/TOFF Times vs.
Temperature
TPC 16. On Response vs. Frequency
TBD
TBD
TPC 11. Supply Currents vs. Input
Switching Frequency
TPC 14. Off Isolation vs. Frequency
TBD
TBD
TPC 12. Charge Injection vs. Source
Voltage
TPC 15. Crosstalk vs. Frequency
REV. PrD
–11–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
GENERAL DESCRIPTION
The ADG725 and ADG731 are serially controlled, 32
channel and dual/differential 16 channel multiplexers re-
spectively.
POWER ON RESET
On power up of the device, all switches will be in the
OFF condition and the internal shift register is filled with
zeros and will remain so until a valid write takes place.
SERIAL INTERFACE
The ADG725 and ADG731 have a three wire serial inter-
face (SYNC, SCLK, and DIN), which is compatible with
SPI, QSPI, MICROWIRE interface standards and most
DSP’s. Figure 1 shows the timing diagram of a typical
write sequence.
Data is written to the 8-bit shift register via DIN under
the control of the SYNC and SCLK signals.
When SYNC goes low, the input shift register is enabled.
An 8-bit counter is also enabled. Data from DIN is
clocked into the shift register on the falling edge of
SCLK. Figures 2 & 3 show the contents of the input shift
registers for these devices. When the part has received
eight clock cycles after SYNC has been pulled low, the
switches are automatically updated with the new
configuration and the input shift register is disabled. With
SYNC held high, any further data or noise on the DIN
line will have no effect on the shift register.
The ADG725 CSA and CSB data bits allow the user the
flexibility to change the configuration of either or both
banks of the multiplexer.
–12–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
TestCircuits
I
DS
V
V
SS
DD
V1
V
V
SS
DD
S1
S2
I
(OFF)
A
D
D
D
S
S32
V
D
V
S
GND
V
S
R
= V /I
1
ON
DS
Test Circuit 3. ID (OFF)
Test Circuit 1. On Resistance.
V
V
DD
SS
V
V
SS
DD
V
V
DD
SS
V
V
SS
DD
I
(OFF)
S
I
(ON)
A
D
S1
S2
D
S1
D
S32
V
V
D
S
S32
V
S
GND
GND
V
D
Test Circuit 4. ID (ON)
Test Circuit 2. IS (OFF).
V
V
SS
DD
V
V
SYNC
DD
SS
S1
50%
50%
V
S1
0V
S2 THRU S31
ADG731*
S32
D
V
S32
V
S1
90%
V
OUT
C
35pF
V
R
300 Ω
L
OUT
V
L
GND
90%
S32
t
t
TRANSITION
* SIMILAR CONNECTION FOR ADG725
TRANSITION
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
.
V
V
V
V
SS
DD
SYNC
SS
S1
DD
V
S
0V
S2 THRU S31
ADG731*
S32
V
S
D
V
OUT
80%
80%
C
35pF
V
R
300
L
OUT
L
GND
Ω
t
OPEN
*SIMILAR CONNECTION FOR ADG725
Test Circuit 6. Break Before Make Delay, tOPEN
.
REV. PrD
–13–
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
V
V
V
DD
SS
V
DD
SS
SYNC
ADG731*
R
S
D
S
V
OUT
C
1nF
L
V
S
V
OUT
V
∆
OUT
GND
Q
= C
x
V
∆
OUT
INJ
L
*SIMILAR CONNECTION FOR ADG725
Test Circuit 7. Charge Injection.
V
V
DD
SS
0.1µF
0.1µF
V
V
V
DD
SS
NETWORK
ANALYZER
V
V
SS
DD
S1
V
SS
DD
NETWORK
ANALYZER
50
Ω
S
50
Ω
S2
50
Ω
V
S
50
Ω
S32
ADG731*
GND
V
D
S
V
OUT
R
ADG731*
GND
L
D
V
OUT
50
Ω
R
L
50
Ω
V
OUT
OFF ISOLATION = 20 LOG
V
S
*SIMILAR CONNECTION FOR ADG725
*SIMILAR CONNECTION FOR ADG725
CHANNEL TO CHANNEL CROSSTALK=
20LOG (V
/V )
10 OUT
S
Test Circuit 8. OFF Isolation
Test Circuit 9. Channel-to-Channel Crosstalk.
V
V
DD
SS
0.1µF
0.1µF
NETWORK
ANALYZER
V
V
SS
DD
S
50
Ω
V
S
D
V
OUT
R
ADG731*
GND
L
50
Ω
INSERTION LOSS = 20 LOG
VOUT WITH SWITCH
VOUT WITHOUT SWITCH
*SIMILAR CONNECTION FOR ADG725
Test Circuit 10. Bandwidth
–14–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG725/ADG731
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead CSP
(CP-48)
0.024 (0.60)
0.017 (0.42)
0.010 (0.25)
MIN
0.276(7.0)
BSC SQ
0.009 (0.24)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
37
36
48
1
PIN 1
INDICATOR
0.207 (5.25)
0.201 (5.10) SQ
0.195 (4.95)
0.266 (6.75)
BSC SQ
TOP
VIEW
BOTTOM
VIEW
25
24
12
13
0.020 (0.50)
0.016 (0.40)
0.012 (0.30)
0.217 (5.5)
REF
0.028 (0.70) MAX
0.026 (0.65) NOM
0.002 (0.05)
o MAX
12
0.035 (0.90) MAX
0.033 (0.85) NOM
0.0004 (0.01)
0.0 (0.0)
0.020 (0.50)
BSC
0.008(0.20)
REF
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
48-Lead TQFP
(SU-48)
0.047 (1.20) MAX
0.354 (9.00) BSC
0.276 (7.0) BSC
0.041 (1.05)
0.037 (0.95)
0.030 (0.75)
0.018 (0.45)
37
48
36
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.006 (0.15)
0.002 (0.05)
12
25
24
13
0° MIN
°
0° –7
0.008 (0.20)
0.004 (0.09)
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
REV. PrD
–15–
相关型号：
ADG731BSU-REEL
16-/32-Channel, Serially Controlled 4, 1.8 V to 5.5 V, 2.5 V, Analog Multiplexers
ADI
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