ADG732BCP-REEL [ROCHESTER]
32-CHANNEL, SGL ENDED MULTIPLEXER, QCC48, 7 X 7 MM, MO-220VKKD-2, LFCSP-48;
| 型号： | ADG732BCP-REEL |
| 厂家： | 
Rochester Electronics |
| 描述： | 32-CHANNEL, SGL ENDED MULTIPLEXER, QCC48, 7 X 7 MM, MO-220VKKD-2, LFCSP-48 |
| 文件： | 总13页 (文件大小：944K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16-/32-Channel, 4 ꢀ
a+1.8 V to +5.5 V, ꢁ2.5 V Analog Multiplexers
ADG726/ADG732
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
1.8 V to 5.5 V Single Supply
ꢁ2.5 V Dual-Supply Operation
4 ꢀ On Resistance
0.5 ꢀ On Resistance Flatness
48-Lead TQFP or 48-Lead 7 mm ꢂ 7 mm CSP Packages
Rail-to-Rail Operation
ADG726
ADG732
S1A
S1
DA
DB
S16A
D
30 ns Switching Times
S1B
Single 32-to-1 Channel Multiplexer
Dual/Differential 16-to-1 Channel Multiplexer
TTL/CMOS Compatible Inputs
For Functionally Equivalent Devices with Serial Interface
See ADG725/ADG731
S32
S16B
WR
CSA
CSB
WR
CS
1-OF-16
DECODER
1-OF-32
DECODER
A0 A1 A2 A3
A0 A1 A2 A3 A4
EN
EN
APPLICATIONS
Optical Applications
Data Acquisition Systems
Communication Systems
Relay Replacement
Audio and Video Switching
Battery-Powered Systems
Medical Instrumentation
Automatic Test Equipment
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG726/ADG732 are monolithic CMOS 32-channel/dual
16-channel analog multiplexers. The ADG732 switches one of
32 inputs (S1-S32) to a common output, D, as determined by
the 5-bit binary address lines A0, A1, A2, A3, and A4. The
ADG726 switches one of 16 inputs as determined by the 4-bit
binary address lines A0, A1, A2, and A3.
1. +1.8 V to +5.5 V single- or 2.5 V dual-supply operation.
These parts are specified and guaranteed with +5 V 10%,
+3 V 10% single-supply, and 2.5 V 10% dual-
supply rails.
2. On resistance of 4 Ω
3. Guaranteed break-before-make switching action
On-chip latches facilitate microprocessor interfacing. The
ADG726 device may also be configured for differential opera-
tion by tying CSA and CSB together. An EN input is used to
enable or disable the devices. When disabled, all channels are
switched OFF.
4. 7 mm × 7 mm 48-lead chip scale package (CSP)
or 48-lead TQFP package
These multiplexers are designed on an enhanced submicron
process that provides low power dissipation yet gives high
switching speed, very low on resistance, and leakage currents.
They operate from a single supply of +1.8 V to +5.5 V and a 2.5 V
dual supply, making them ideally suited to a variety of applications.
On resistance is in the region of a few ohms and is closely
matched between switches and very flat over the full signal
range. These parts can operate equally well as either multiplexers
or demultiplexers and have an input signal range that extends to
the supplies. In the OFF condition, signal levels up to the supplies
are blocked. All channels exhibit break-before-make switching
action, preventing momentary shorting when switching channels.
They are available in either 48-lead CSP or TQFP packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
ADG726/ADG732–SPECIFICATIONS1
(VDD = 5 V ꢁ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
B Version
–40ꢃC
Parameter
+25ꢃC
to +85ꢃC
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
4
5.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IDS = 10 mA
6
0.3
0.8
On Resistance Match Between
Channels (∆RON
)
On Resistance Flatness (RFLAT(ON)
)
0.5
VS = 0 V to VDD, IDS = 10 mA
1
LEAKAGE CURRENTS
VDD = 5.5 V
Source OFF Leakage IS (OFF)
0.01
0.25
0.05
0.5
1
0.05
0.5
1
nA typ
nA max
nA typ
nA max
nA max
nA typ
nA max
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 3
1
Drain OFF Leakage ID (OFF)
ADG726
ADG732
Channel ON Leakage ID, IS (ON)
ADG726
ADG732
2.5
5
VD = VS = 1 V, or 4.5 V;
Test Circuit 4
2.5
5
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
5
µA typ
µA max
pF typ
VIN = VINL or VINH
0.5
40
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
23
34
18
1
18
25
17
23
24
32
16
22
5
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF, Test Circuit 5
VS1 = 3 V/0 V, VS32 = 0 V/3 V
RL = 300 Ω, CL = 35 pF;
VS = 3 V; Test Circuit 6
VS = 3 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = 3 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF;
RL = 300 Ω, CL = 35 pF;
VS = 3 V; Test Circuit 8
RL = 300 Ω, CL = 35 pF;
VS = 3 V; Test Circuit 8
VS = 2.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 9
Break-Before-Make Time Delay, tD
tON(CS, WR)
32
29
40
25
tOFF(CS, WR)
tON(EN)
tOFF(EN)
Charge Injection
OFF Isolation
–72
–72
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 11
Channel-to-Channel Crosstalk
–3 dB Bandwidth
ADG726
ADG732
CS (OFF)
CD (OFF)
ADG726
RL = 50 Ω, CL = 5 pF; Test Circuit 12
34
18
13
MHz typ
MHz typ
pF typ
f = 1 MHz
170
340
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG732
CD, CS (ON)
ADG726
ADG732
175
350
pF typ
pF typ
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 5.5 V
Digital Inputs = 0 V or 5.5 V
10
µA typ
µA max
20
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design; not subject to production test.
Specifications subject to change without notice.
–2–
REV. 0
ADG726/ADG732
SPECIFICATIONS1
(VDD = 3 V ꢁ 10%, VSS = 0 V, GND = 0 V, unless otherwise noted.)
B Version
–40ꢃC
Parameter
+25ꢃC
to +85ꢃC
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On Resistance (RON
)
7
11
Ω typ
Ω max
Ω typ
Ω max
Ω typ
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD, IDS = 10 mA
12
0.35
1
On Resistance Match Between
Channels (∆RON
)
On Resistance Flatness (RFLAT(ON)
)
3
VS = 0 V to VDD, IDS = 10 mA
LEAKAGE CURRENTS
VDD = 3.3 V
Source OFF Leakage IS (OFF)
0.01
0.25
0.05
0.5
1
0.05
0.5
1
nA typ
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = 1 V/3 V, VD = 3 V/1 V;
Test Circuit 3
1
nA max
nA max
nA max
nA max
nA typ
Drain OFF Leakage ID (OFF)
ADG726
ADG732
Channel ON Leakage ID, IS (ON)
ADG726
ADG732
2.5
5
VS = VD = 1 V or 3 V;
Test Circuit 4
2.5
5
nA max
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.7
V min
V max
IINL or IINH
0.005
5
µA typ
µA max
pF typ
VIN = VINL or VINH
0.5
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
34
52
26
1
29
43
26
38
33
48
19
25
1
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF; Test Circuit 5
VS1 = 2 V/0 V, VS32 = 0 V/2 V
RL = 300 Ω, CL = 35 pF;
VS = 2 V; Test Circuit 6
62
Break-Before-Make Time Delay, tD
tON(WR, CS)
VS = 2 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = 2 V; Test Circuit 7
RL = 300 Ω, CL = 35 pF;
RL = 300 Ω, CL = 35 pF;
VS = 3 V; Test Circuit 8
RL = 300 Ω, CL = 35 pF;
VS = 2 V; Test Circuit 8
VS = 1.5 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 9
52
42
55
28
tOFF(WR, CS)
tON(EN, WR)
tOFF(EN)
Charge Injection
Off Isolation
–72
–72
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 11
Channel-to-Channel Crosstalk
–3 dB Bandwidth
ADG726
ADG732
CS (OFF)
CD (OFF)
ADG726
RL = 50 Ω, CL = 5 pF; Test Circuit 12
34
18
13
MHz typ
MHz typ
pF typ
f = 1 MHz
170
340
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG732
CD, CS (ON)
ADG726
ADG732
175
350
pF typ
pF typ
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = 3.3 V
Digital Inputs = 0 V or 3.3 V
5
µA typ
10
µA max
NOTES
1Temperature ranges are as follows: B Version: –40°C to +85°C.
2Guaranteed by design; not subject to production test.
Specifications subject to change without notice.
–3–
REV. 0
ADG726/ADG732 SPECIFICATIONS1
(V = +2.5 V ؎ 10%, V = –2.5 V ؎ 10%, GND = 0 V, unless otherwise noted.)
DUAL SUPPLY
DD
SS
B Version
–40؇C
Parameter
+25؇C
to +85؇C
Unit
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
V
6
0.3
0.8
SS to VDD
V
On Resistance (RON
)
4
5.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = VSS to VDD, IDS = 10 mA;
Test Circuit 1
VS = VSS to VDD, IDS = 10 mA
On Resistance Match Between
Channels (∆RON
)
On Resistance Flatness (RFLAT(ON)
)
0.5
VS = VSS to VDD, IDS = 10 mA
1
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
VDD = +2.75 V, VSS = –2.75 V
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
Test Circuit 2
VS = +2.25 V/–1.25 V, VD = –1.25 V/+2.25 V;
Test Circuit 3
0.01
0.25
0.05
0.5
1
0.05
0.5
1
nA typ
0.5
nA max
nA max
nA max
nA max
nA typ
Drain OFF Leakage ID (OFF)
ADG726
ADG732
Channel ON Leakage ID, IS (ON)
ADG726
ADG732
2.5
5
VS = VD = +2.25 V/–1.25 V;
Test Circuit 4
2.5
5
nA max
nA max
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
1.7
0.7
V min
V max
IINL or IINH
0.005
5
µA typ
µA max
pF typ
VIN = VINL or VINH
0.5
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
33
45
15
1
21
30
20
29
26
37
18
26
1
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 ⍀, CL = 35 pF; Test Circuit 5
VS1 = 1.5 V/0 V, VS32 = 0 V/1.5 V
RL = 300 ⍀, CL = 35 pF;
VS = 1.5 V; Test Circuit 6
VS = 1.5 V; Test Circuit 7
RL = 300 ⍀, CL = 35 pF;
VS = 1.5 V; Test Circuit 7
RL = 300 ⍀, CL = 35 pF;
RL = 300 ⍀, CL = 35 pF;
VS = 1.5 V; Test Circuit 8
RL = 300 ⍀, CL = 35 pF;
VS = 1.5 V; Test Circuit 8
VS = 0 V, RS = 0 ⍀, CL = 1 nF;
Test Circuit 9
51
Break-Before-Make Time Delay, tD
tON(CS, WR)
37
35
tOFF(CS, WR)
tON(EN, WR)
tOFF(EN)
29
Charge Injection
OFF Isolation
–72
–72
dB typ
dB typ
RL = 50 ⍀, CL = 5 pF, f = 1 MHz;
Test Circuit 10
RL = 50 ⍀, CL = 5 pF, f = 1 MHz;
Test Circuit 11
Channel-to-Channel Crosstalk
–3 dB Bandwidth
ADG726
ADG732
RL = 50 ⍀, CL = 5 pF; Test Circuit 12
34
18
13
MHz typ
MHz typ
pF typ
CS (OFF)
CD (OFF)
ADG726
ADG732
137
275
pF typ
pF typ
f = 1 MHz
f = 1 MHz
CD, CS (ON)
ADG726
ADG732
150
300
pF typ
pF typ
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
10
10
µA typ
µA max
µA typ
µA max
VDD = +2.75 V
Digital Inputs = 0 V or +2.75 V
VSS = –2.75 V
20
20
ISS
Digital Inputs = 0 V or +2.75 V
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design; not subject to production test.
Specifications subject to change without notice.
–4–
REV. 0
ADG726/ADG732
TIMING CHARACTERISTICS1, 2, 3
Parameter
Limit at TMIN, TMAX
Unit
Conditions/Comments
t1
t2
t3
t4
t5
t6
0
0
10
10
5
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup Time
CS to WR Hold Time
WR Pulsewidth
Time between WR Cycles
Address, Enable Setup Time
Address, Enable Hold Time
2
NOTES
1See Figure 1.
2All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD).
3Guaranteed by design and characterization, not production tested.
Specifications subject to change without notice.
CS
t1
t2
t3
t4
WR
t5
t6
A0, A1, A2, A3, (A4)
EN
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch
address and enable inputs. The latches are level sensitive; there-
fore, while WR is held low, the latches are transparent and the
switches respond to changing the address and enable the inputs.
Input data is latched on the rising edge of WR. The ADG726
has two CS inputs. This enables the part to be used either as a
dual 16-1 channel multiplexer or a differential 16-channel
multiplexer. If a differential output is required, tie CSA and
CSB together.
REV. 0
–5–
ADG726/ADG732
ABSOLUTE MAXIMUM RATINGS1
(TA = 25°C, unless otherwise noted.)
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Thermal Impedence (Four-layer board)
48-Lead LFCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . 25ЊC/W
48-Lead TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . 54.6ЊC/W
Lead Temperature, Soldering (10 sec) . . . . . . . . . . . . . 300°C
IR Reflow, Peak Temperature (<20 sec) . . . . . . . . . . . . 235°C
VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –7 V
Analog Inputs2 . . . . . . . . . . . . . . VSS – 0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
Digital Inputs2 . . . . . . . . . . . . . . . . . . –0.3 V to VDD + 0.3 V or
30 mA, Whichever Occurs First
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability. Only one absolute
maximum rating may be applied at any one time.
Peak Current, S or D . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 mA
(Pulsed at 1 ms, 10% Duty Cycle Max)
Continuous Current, S or D . . . . . . . . . . . . . . . . . . . . . 30 mA
Operating Temperature Range
2Overvoltages at A, EN, WR, CS, S, or D will be clamped by internal diodes.
Current should be limited to the maximum ratings given.
Industrial (B Version) . . . . . . . . . . . . . . . . . –40°C to +85°C
ORDERING GUIDE
Temperature Range Package Description
Model
Package Option
Chip Scale Package (LPCSP) CP-48
ADG726BCP
ADG726BSU
ADG732BCP
ADG732BSU
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
Thin Quad Flatpack (TQFP) SU-48
Chip Scale Package (LPCSP) CP-48
Thin Quad Flatpack (TQFP) SU-48
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG726/ADG732 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
PIN CONFIGURATIONS
LFCSP and TQFP
S12A
S11A
S10A
S9A
S8A
S7A
S6A
S5A
S4A
1
2
3
4
5
6
7
8
9
36 S12B
35 S11B
34 S10B
33 S9B
32 S8B
31 S7B
30 S6B
29 S5B
28 S4B
27 S3B
26 S2B
25 S1B
36 S28
35 S27
34 S26
33 S25
32 S24
31 S23
30 S22
29 S21
28 S20
27 S19
26 S18
25 S17
S12
S11
S10
S9
S8
S7
S6
S5
S4
1
2
3
4
5
6
7
8
9
PIN 1
PIN 1
INDICATOR
INDICATOR
ADG726
ADG732
TOP VIEW
TOP VIEW
S3A 10
S2A 11
S1A 12
S310
11
S2
S112
NC = NO CONNECT
NC = NO CONNECT
–6–
REV. 0
ADG726/ADG732
Table I. ADG726 Truth Table
EN CSA CSB WR
A3
A2
A1
A0
ON Switch
L->H Retains Previous Switch Condition
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No Change in Switch Condition
NONE
S1A–DA, S1B–DB
S2A–DA, S2B–DB
S3A–DA, S3B–DB
S4A–DA, S4B–DB
S5A–DA, S5B–DB
S6A–DA, S6B–DB
S7A–DA, S7B–DB
S8A–DA, S8B–DB
S9A–DA, S9B–DB
S10A–DA, S10B–DB
S11A–DA, S11B–DB
S12A–DA, S12B–DB
S13A–DA, S13B–DB
S14A–DA, S14B–DB
S15A–DA, S15B–DB
S16A–DA, S16B–DB
X = Don’t Care
Table II. ADG732 Truth Table
A4
A3
A2
A1
A0
EN
CS
WR
Switch Condition
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L->H Retains Previous Switch Condition
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No Change in Switch Condition
NONE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
X = Don’t Care
REV. 0
–7–
ADG726/ADG732
TERMINOLOGY
VDD
VSS
Most Positive Power Supply Potential
Most Negative Power Supply in a Dual-Supply Application. In single-supply applications, connect to GND.
Positive Supply Current
IDD
ISS
Negative Supply Current
GND
S
Ground (0 V) Reference
Source Terminal. May be an input or output.
Drain Terminal. May be an input or output.
Logic Control Input
D
IN
VD (VS)
RON
∆RON
RFLAT(ON)
Analog Voltage on Terminals D and S
Ohmic Resistance between D and S
On Resistance Match between any two channels, i.e., RONmax – RONmin
Flatness is defined as the difference between the maximum and minimum value of on resistance as measured
over the specified analog signal range.
IS (OFF)
ID (OFF)
ID, IS (ON)
VINL
Source Leakage Current with the Switch OFF
Drain Leakage Current with the Switch OFF
Channel Leakage Current with the Switch ON
Maximum Input Voltage for Logic “0”
VINH
Minimum Input Voltage for Logic “1”
IINL(IINH
)
Input Current of the Digital Input
CS (OFF)
CD (OFF)
CD, CS(ON)
CIN
OFF Switch Source Capacitance. Measured with reference to ground.
OFF Switch Drain Capacitance. Measured with reference to ground.
ON Switch Capacitance. Measured with reference to ground.
Digital Input Capacitance
tTRANSITION
Delay Time Measured between the 50% and 90% Points of the Digital Inputs and the Switch ON Condition
when Switching from One Address State to Another
t
ON(EN)
Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch ON Condition
Delay Time between the 50% and 90% Points of the EN Digital Input and the Switch OFF Condition
OFF Time Measured between the 80% Points of Both Switches when Switching from One Address State to Another
A Measure of the Glitch Impulse Transferred from the Digital Input to the Analog Output During Switching
tOFF(EN)
tOPEN
Charge
Injection
OFF Isolation
Crosstalk
A Measure of Unwanted Signal Coupling through an OFF Switch
A Measure of Unwanted Signal Coupling from One Channel to Another as a Result of Parasitic Capacitance
The Frequency Response of the ON Switch
ON Response
Insertion
Loss
The Loss Due to the On Resistance of the Switch
–8–
REV. 0
Typical Performance Characteristics—ADG726/ADG732
8
8
7
6
5
4
3
2
1
0
8
V
= 2.7V
V
= 0V
DD
T
V
= +25ꢃC
SS
A
7
6
5
4
3
2
1
0
= 0V
7
6
5
4
3
2
1
0
SS
T
V
V
= +25ꢃC
A
V
= +2.25V
= –2.25V
DD
V
= 3.0V
DD
= +2.5V
= –2.5V
DD
V
SS
V
= 5.5V
DD
SS
V
= 3.3V
DD
+85ꢃC
+25ꢃC
V
= +2.75V
DD
V
= –2.75V
SS
–40ꢃC
V
= 4.5V
DD
V
= 5V
DD
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
, V –V
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
, V –V
–2.75 –1.75 –0.75
0.25
, V –V
1.25
2.25
V
V
V
D
S
D
S
D
S
TPC 2. On Resistance vs. VD(VS),
Dual Supply
TPC 1. On Resistance vs. VD(VS),
Single Supply
TPC 3. On Resistance vs. VD(VS)
for Different Temperatures,
Single Supply
0.5
0.4
8
8
7
6
5
V
= 0V
V
= 5V
= 0V
SS
DD
V
7
6
5
4
3
2
1
0
SS
0.3
+25ꢃC
+85ꢃC
–40ꢃC
0.2
0.1
+85ꢃC
0
4
+25ꢃC
–0.1
–0.2
–0.3
–0.4
–0.5
3
–40ꢃC
2
1
0
0
0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0
, V –V
–2.5–2.0–1.5–1.0–0.5
0
0.5 1.0 1.5 2.0 2.5
5
15
25
35
45
55
65
75
85
V
V
D
, V –V
TEMPERATURE – ꢃC
D
S
S
TPC 4. On Resistance vs. VD(VS),
Single Supply
TPC 5. On Resistance vs. VD(VS),
Dual Supply
TPC 6. Leakage Currents vs.
Temperature
45
25
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
V
= 0V
SS
40
35
30
25
20
15
10
5
20
15
10
5
V
= 3V
= 5V
DD
RISING
V
tON
DD
V
= 3V
DD
FALLING
0
V
= 5V
tOFF
DD
–5
–10
–15
T
= +25ꢃC
A
T
= 25ꢃC
A
0
–40
–3 –2 –1
0
1
2
3
4
5
–20
0
20
40
60
80
0
1
2
3
4
5
6
V
, V –V
TEMPERATURE – ꢃC
D
S
V
–V
DD
TPC 8. tON/tOFF Times vs. Temperature
TPC 9. Logic Threshold Voltage
vs. Supply Voltage
TPC 7. ADG732 Charge Injection
vs. Source Voltage
–9–
REV. 0
ADG726/ADG732
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
ADG726
V
= 5V
= 25ꢃC
V
= 3V, 5V
= 25ꢃC
DD
DD
V
= 5V
= 25ꢃC
DD
T
A
T
–2
A
T
A
–4
–6
ADG732
–8
–10
–12
–14
0.03
0.1
1
10
100
0.03 0.1
1
10
100
0.03 0.1
1
10
100
FREQUENCY – MHz
FREQUENCY – MHz
FREQUENCY – MHz
TPC 10. OFF Isolation vs. Frequency
TPC 12. ON Response vs. Frequency
TPC 11. Crosstalk vs. Frequency
Test Circuits
I
V
V
SS
DS
DD
V
V
SS
DD
S1
S2
V1
I
(OFF)
D
D
A
S
D
S32
V
D
EN
V
LOGIC “1”
GND
S
V
S
R
=V /I
1 DS
ON
Test Circuit 1. On Resistance
Test Circuit 3. ID (OFF)
V
V
V
V
SS
DD
SS
DD
I (OFF)
S
V
V
V
V
SS
DD
SS
DD
S1
S2
A
I
(ON)
D
D
D
S1
V
S
A
S32
S32
V
D
EN
EN
LOGIC “1”
V
S
V
LOGIC “ 0”
V
GND
GND
S
D
Test Circuit 2. IS (OFF)
Test Circuit 4. ID (ON)
V
V
DD
SS
3V
V
V
ADDRESS
SS
DD
50%
50%
DRIVE (V
)
IN
A4
A0
S1
V
S1
V
0V
IN
50ꢀ
S2 THRU S31
S32
V
S1
V
90%
S32
ADG732*
V
OUT
D
V
OUT
R
300ꢀ
C
L
35pF
L
90%
tTRANSITION
GND
EN CS
WR
V
S32
tTRANSITION
*SIMILAR CONNECTION FOR ADG726
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
V
V
SS
DD
3V
V
V
DD
SS
A4
A0
S1
V
S
ADDRESS
V
IN
DRIVE (V
)
50ꢀ
IN
S2 THRU S31
S32
0V
V
S
ADG732*
D
V
OUT
R
300ꢀ
C
80%
80%
L
L
V
OUT
GND
EN CS
WR
35pF
tOPEN
*SIMILAR CONNECTION FOR ADG726
Test Circuit 6. Break-Before-Make Delay, tOPEN
–10–
REV. 0
ADG726/ADG732
V
V
SS
DD
3V
0V
V
V
50%
WR
DD
SS
A4
A0
S1
V
S
S2 THRU S32
V
CSADG732*
O
tON (WR)
SWITCH
OUTPUT
V
CS
20%
20%
V
D
OUT
R
300ꢀ
C
L
35pF
0V
L
WR
GND
EN
tOFF (WR)
V
WR
*SIMILAR CONNECTION FOR ADG726
Test Circuit 7. Write Turn-ON and Turn-OFF Time, tON, tOFF (WR)
V
V
SS
DD
V
V
DD
SS
3V
0V
A4
S1
S2 THRU S32
V
S
50%
50%
EN
A0
tON (EN)
tOFF (EN)
10%
EN
V
ADG732*
EN
V
D
OUT
V
O
R
300ꢀ
C
35pF
90%
L
L
SWITCH
OUTPUT
GND
CS
WR
0V
*SIMILAR CONNECTION FOR ADG726
Test Circuit 8. Enable Delay, tON (EN), tOFF (EN)
V
V
SS
DD
V
V
DD
SS
A4
A0
3V
LOGIC
INPUT (V
)
ADG732*
IN
R
S
S
D
0V
V
OUT
C
1nF
L
EN
CS
V
S
V
OUT
ꢄV
GND
WR
OUT
V
Q
= C ꢂ ꢄV
IN
INJ L OUT
*SIMILAR CONNECTION FOR ADG726
Test Circuit 9. Charge Injection
V
DD
V
SS
0.1ꢅF
0.1ꢅF
V
DD
V
SS
NETWORK
ANALYZER
A4
A0
50ꢀ
S
50ꢀ
V
S
D
V
OUT
EN
LOGIC “ 1”
R
50ꢀ
L
ADG732*
GND
V
OUT
OFF ISOLATION = 20 LOG
V
S
*
SIMILAR CONNECTION FOR ADG726
Test Circuit 10. OFF Isolation
REV. 0
–11–
ADG726/ADG732
V
DD
V
SS
0.1ꢁF
0.1ꢁF
V
V
SS
DD
V
V
SS
DD
NETWORK
ANALYZER
50ꢀ
50ꢀ
V
V
SS
NETWORK
ANALYZER
50ꢀ
DD
S1
A4
A0
A4
A0
S
S2
V
S
V
S32
S
D
V
ADG732*
OUT
EN
V
D
OUT
R
L
ADG732*
R
L
50ꢀ
50ꢀ
GND
GND
EN CS
WR
V
WITH SWITCH
OUT
INSERTION LOSS = 20 LOG
V
WITHOUT SWITCH
OUT
*SIMILAR CONNECTION FOR ADG726
CHANNEL-TO-CHANNEL CROSSTALK = 20LOG (V
/V )
*
SIMILAR CONNECTION FOR ADG726
10
OUT
S
Test Circuit 11. Channel-to-Channel Crosstalk
Test Circuit 12. Bandwidth
OUTLINE DIMENSIONS
48-Lead Frame Chip Scale Package [LFCSP]
(CP-48)
Dimensions shown in millimeters
0.30
0.23
0.18
7.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
0.60 MAX
37
48
36
1
PIN 1
INDICATOR
5.25
4.70
2.25
6.75
BSC SQ
BOTTOM
VIEW
TOP
VIEW
0.50
0.40
0.30
12
25
24
13
5.50
REF
0.70 MAX
0.65 NOM
1.00
0.90
0.80
12ꢂ MAX
COPLANARITY
0.05 MAX
0.02 NOM
0.25
REF
0.50 BSC
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
48-Lead Thin Plastic Quad Flatpack [TQFP]
(SU-48)
Dimensions shown in millimeters
1.20 MAX
9.00 BSC SQ
0.75
0.60
0.45
37
48
36
1
7.00
BSC
SQ
TOP VIEW
(PINS DOWN)
COPLANARITY
0.15
0.05
12
25
0ꢂ
MIN
13
24
0.27
0.22
0.17
0.5
BSC
0.20
0.09
1.05
1.00
0.95
7ꢂ
0ꢂ
SEATING
PLANE
COMPLIANT TO JEDEC STANDARDS MS-026BBC
–12–
REV. 0
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