ADG732 [ADI]
16-/32- Channel, 3.5 з 1.8 V to 5.5 V, 【2.5 V, Analog Multiplexers; 16位/ 32通道， 3.5 з 1.8 V至5.5 V ， 【 2.5 V ，模拟多路复用器
| 型号： | ADG732 |
| 厂家： | 
ADI |
| 描述： | 16-/32- Channel, 3.5 з 1.8 V to 5.5 V, 【2.5 V, Analog Multiplexers |
| 文件： | 总13页 (文件大小：200K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
16-/32- Channel, 3.5 Ω
1.8 V to 5.5 V, 2.5 V, Analog Multiplexers
a
ADG726/ADG732
Preliminary Technical Data
1.8 V to 5.5 V Single Supply
2.5 V Dual Supply Operation
3.5 Ω On Resistance
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
ADG732
ADG726
0.5 Ω On Resistance Flatness
Rail to Rail Operation
30ns Switching Times
Single 32 to 1 Channel Multiplexer
Dual/Differential 16 to 1 Channel Multiplexer
TTL/CMOSCompatibleInputs
For Functionally Equivalent devices with Serial Interface
See ADG725/ADG731
S1
S1A
DA
DB
S16A
D
S1B
S32
S16B
APPLICATIONS
OpticalApplications
WR
CSA
CSB
WR
CS
1 OF 32
DECODER
1 OF 16
DECODER
Data Acquisition Systems
CommunicationSystems
Relay replacement
Audio and Video Switching
Battery Powered Systems
MedicalInstrumentation
Automatic Test Equipment
A1
A3 EN
A0
A2
EN
A2 A3 A4
A0
A1
GENERAL DESCRIPTION
and have an input signal range which extends to the sup-
plies. In the OFF condition, signal levels up to the
supplies are blocked. All channels exhibit break before
make switching action preventing momentary shorting
when switching channels.
The ADG726/ADG732 are monolithic CMOS 32
channel/dual 16 channel analog multiplexers. The
ADG732 switches one of thirty-two inputs (S1-S32) to a
common output, D, as determined by the 5-bit binary
address lines A0, A1, A2, A3 and A4. The ADG726
switches one of sixteen inputs as determined by the four
bit binary address lines, A0, A1, A2 and A3.
They are available in either 48 lead LFCSP or TQFP
package.
On chip latches facilitate microprocessor interfacing. The
ADG726 device may also be configured for differential
operation by tying CSA and CSB together. An EN input
is used to enable or disable the devices. When disabled, all
channels are switched OFF.
PRODUCT HIGHLIGHTS
1. +1.8 V to +5.5 V Single or 2.5 V Dual Supply
operation. These parts are specified and guaranteed
with +5 V 10ꢀ, +3 V 10ꢀ single supply and
2.5 V 10ꢀ dual supply rails.
These multiplexers are designed on an enhanced submi-
cron process that provides low power dissipation yet gives
high switching speed, very low on resistance and leakage
currents. They operate from single supply of 1.8V to 5.5V
and 2.5 V dual supply, making them ideally suited to a
variety of applications. On resistance is in the region of a
few Ohms and is closely matched between switches and
very flat over the full signal range. These parts can operate
equally well as either Multiplexers or De-Multiplexers
2. On Resistance of 3.5 Ω.
3. Guaranteed Break-Before-Make Switching Action.
4. 7mm x 7mm 48 lead LF Chip Scale Package (CSP)
or 48 lead TQFP package.
REV. PrD 2001
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
WorldWide Web Site: http://www.analog.com
Analog Devices, Inc., 2001
Fax: 781/326-8703
PRELIMINARY TECHNICAL DATA
1
(VDD = 5V 1ꢀ0, VSS = ꢀV, GND = ꢀ V, unless otherwise noted)
ADG726/ADG732–SPECIFICATIONS
B Version
–40°C
Parameter
+25oC
to +85°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On-Resistance (RON
)
3.5
5.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD , IDS = 10 mA
6
0.3
0.8
On-Resistance Match Between
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
0.5
VS = 0 V to VDD, IDS = 10 mA
1.2
LEAKAGE CURRENTS
VDD = 5.5 V
Source OFF Leakage IS (OFF)
0.01
0.5
0.01
0.5
0.01
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 2
VD = 4.5 V/1 V, VS = 1 V/4.5 V;
Test Circuit 3
VD = VS = 1 V, or 4.5V;
Test Circuit 4
5
Drain OFF Leakage ID (OFF)
5
Channel ON Leakage ID, IS (ON)
10
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.4
0.8
V min
V max
IINL or IINH
0.005
5
µA typ
µA max
pF typ
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
40
30
32
10
5
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
pC typ
RL = 300 Ω, CL = 35 pF,Test Circuit 5;
VS1 = 3 V/0 V, VS32 = 0 V/3V
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = 3 V, Test Circuit 8
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 9
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Test Circuit 10
RL = 50 Ω, CL = 5 pF, f = 100 kHz;
Test Circuit 11
60
1
Break-Before-Make Time Delay, tD
t
ON(EN, WR)
50
14
tOFF(EN)
Charge Injection
Off Isolation
-60
-60
dB typ
dB typ
Channel to Channel Crosstalk
-3 dB Bandwidth
CS (OFF)
CD (OFF)
ADG726
10
13
MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 10
pF typ
f = 1 MHz
180
360
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG732
CD, CS (ON)
ADG726
200
400
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG732
POWER REQUIREMENTS
IDD
VDD = +5.5 V
Digital Inputs = 0 V or +5.5 V
10
µA typ
20
µA max
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–2–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
1
(VDD = 3V 1ꢀ0, VSS = ꢀV, GND = ꢀ V, unless otherwise noted)
SPECIFICATIONS
B Version
–40°C
Parameter
+25oC
to +85°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
0 V to VDD
V
On-Resistance (RON
)
6
11
Ω typ
Ω max
Ω typ
Ω max
Ω max
VS = 0 V to VDD, IDS = 10 mA;
Test Circuit 1
VS = 0 V to VDD , IDS = 10 mA
12
0.4
1.2
3
On-Resistance Match Between
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
VS = 0 V to VDD, IDS = 10 mA
LEAKAGE CURRENTS
VDD = 3.3 V
Source OFF Leakage IS (OFF)
0.01
1
0.01
1
0.01
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
VS = 3 V/1 V, VD = 1 V/3 V;
Test Circuit 2
VS = 1 V/3 V, VD = 3 V/1 V;
Test Circuit 3
VS = VD = +1 V or +3 V;
Test Circuit 4
5
Drain OFF Leakage ID (OFF)
5
Channel ON Leakage ID, IS (ON)
10
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
2.0
0.8
V min
V max
IINL or IINH
0.005
5
µA typ
µA max
pF typ
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
45
30
40
20
5
ns typ
ns max
ns typ
ns min
ns typ
ns max
ns typ
ns max
RL = 300 Ω, CL = 35 pF Test Circuit 5
VS1 = 2 V/0 V, VS32 = 0 V/2 V
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = 2 V, Test Circuit 8
VS = 0 V, RS = 0 Ω, CL = 1 nF;
Test Circuit 9
75
1
Break-Before-Make Time Delay, tD
t
t
ON(EN, WR)
70
28
OFF(EN)
Charge Injection
pC typ
Off Isolation
-60
-60
dB typ
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 11
Channel to Channel Crosstalk
-3 dB Bandwidth
CS (OFF)
CD (OFF)
ADG726
10
13
MHz typ
pF typ
RL = 50 Ω, CL = 5 pF, Test Circuit 10
f = 1 MHz
180
360
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG732
CD, CS (ON)
ADG726
ADG732
200
400
pF typ
pF typ
f = 1 MHz
f = 1 MHz
POWER REQUIREMENTS
IDD
VDD = +3.3 V
Digital Inputs = 0 V or +3.3 V
10
µA typ
20
µA max
NOTES
1Temperature ranges are as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
REV. PrD
–3–
PRELIMINARY TECHNICAL DATA
ADG726/ADG732–SPECIFICATIONS1
Dual Supply
(VDD = +2.5 V 1ꢀ0, VSS = -2.5 V 1ꢀ0, GND = ꢀ V, unless otherwise noted)
B Version
–40°C
Parameter
+25oC
to +85°C
Units
Test Conditions/Comments
ANALOG SWITCH
Analog Signal Range
VSS to VDD
V
On-Resistance (RON
)
3.5
5.5
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
VS = VSS to VDD, IDS = 10 mA;
Test Circuit 1
VS = VSS to VDD, IDS = 10 mA
6
0.3
0.8
On-Resistance Match Between
Channels (∆RON
)
On-Resistance Flatness (RFLAT(ON)
)
0.5
VS = VSS to VDD, IDS = 10 mA
1.2
LEAKAGE CURRENTS
Source OFF Leakage IS (OFF)
VDD = +2.75 V, VSS = -2.75 V
VS =+2.25V/-1.25V,VD =-1.25V/+2.25V;
Test Circuit 2
VS =+2.25V/-1.25V,VD =-1.25V/+2.25V;
Test Circuit 3
0.01
1
0.01
1
0.01
1
nA typ
nA max
nA typ
nA max
nA typ
nA max
5
Drain OFF Leakage ID (OFF)
5
Channel ON Leakage ID, IS (ON)
VS =VD =+2.25V/-1.25V,TestCircuit4
10
DIGITAL INPUTS
Input High Voltage, VINH
Input Low Voltage, VINL
Input Current
1.7
0.7
V min
V max
IINL or IINH
0.005
5
µA typ
µA max
pF typ
VIN = VINL or VINH
0.1
CIN, Digital Input Capacitance
DYNAMIC CHARACTERISTICS2
tTRANSITION
40
15
32
16
ns typ
ns max
ns typ
ns min
ns typ
ns max
RL = 300 Ω, CL = 35 pF Test Circuit 5
VS1 = 1.5 V/0 V,VS32 = 0 V/1.5 V
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 6
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 7
RL = 300 Ω, CL = 35 pF;
VS = 1.5 V, Test Circuit 8
VS = 0 V, RS = 0 Ω, CL = 1 nF; Test 9
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 10
60
1
Break-Before-Make Time Delay, tD
t
ON(EN, WR)
50
26
tOFF(EN)
ns typ
ns max
pC typ
dB typ
Charge Injection
Off Isolation
8
-60
Channel to Channel Crosstalk
-60
dB typ
RL = 50 Ω, CL = 5 pF, f = 1 MHz;
Test Circuit 11
-3 dB Bandwidth
CS (OFF)
CD (OFF)
ADG726
10
13
MHz typ RL = 50 Ω, CL = 5 pF, Test Circuit 10
pF typ
180
360
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG732
CD, CS (ON)
ADG726
200
400
pF typ
pF typ
f = 1 MHz
f = 1 MHz
ADG732
POWER REQUIREMENTS
IDD
VDD = +2.75 V
Digital Inputs = 0 V or +2.75 V
10
10
µA typ
µA max
µA typ
µA max
20
20
ISS
VSS = -2.75 V
Digital Inputs = 0 V or +2.75 V
NOTES
1Temperature range is as follows: B Version: –40°C to +85°C.
2Guaranteed by design, not subject to production test.
Specifications subject to change without notice.
–4–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
TIMINGCHARACTERISTICS1,2,3
Parameter
Limit at TMIN, TMAX
Units
Conditions/Comments
t1
t2
t3
t4
t5
t6
0
0
20
10
5
ns min
ns min
ns min
ns min
ns min
ns min
CS to WR Setup Time
CS to WR Hold Time
WR pulse width
Time between WR cycles
Address, Enable Setup Time
Address, Enable Hold Time
2
NOTES
1See Figure 1.
2All input signals are specified with tr =tf = 5ns (10ꢀ to 90ꢀ of VDD) and timed from a voltage level of (VIL + VIH)/2.
3Guaranteedbydesignandcharacterisation, notproductiontested.
Specifications subject to change without notice.
CS
t
t
2
1
t
t
3
4
WR
t
t
5
6
A0, A1, A2, A3, (A4)
EN
Figure 1. Timing Diagram
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive;
therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs.
This input data is latched on the rising edge of WR. The ADG726 has two CS inputs. This enables the part to be used
either as a dual 16-1 channel multiplexer or a differential 16 channel multiplexer. If a differential output is required, tie
CSA and CSB together.
REV. PrD
–5–
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
ABSOLUTE MAXIMUM RATINGS1
Storage Temperature Range
Junction Temperature
–65°C to +150°C
+150°C
(TA = +25°C unless otherwise noted)
48 lead CSP θJA Thermal Impedance
48 lead TQFP θJA Thermal Impedance
Lead Temperature, Soldering (10seconds)
TBD°C/W
TBD°C/W
VDD to VSS
+7 V
–0.3 V to +7 V
+0.3 V to -7 V
VDD to GND
VSS to GND
300°C
+220°C
Analog Inputs2
VSS - 0.3 V to VDD +0.3 Vor
30 mA, Whichever Occurs First
-0.3V to VDD +0.3 V or
30 mA, Whichever Occurs First
60mA
IR Reflow, Peak Temperature
NOTES
1Stressesabovethoselistedunder“AbsoluteMaximumRatings”maycausepermanent
damagetothedevice.Thisisastressratingonlyandfunctionaloperationofthedevice
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extendedperiodsmayaffectdevicereliability.Onlyoneabsolutemaximumratingmay
be applied at any one time.
Digital Inputs2
Peak Current, S or D
(Pulsed at 1 ms, 10ꢀ Duty Cycle max)
Continuous Current, S or D
Operating Temperature Range
Industrial (B Version)
30mA
2OvervoltagesatA, WR, RS,SorDwillbeclampedbyinternaldiodes.Currentshould
be limited to the maximum ratings given.
–40°C to +85°C
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the ADG726/ADG732 features proprietary ESD protection circuitry, permanent damage
may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
o
o
ADG726BCP
ADG726BSU
ADG732BCP
ADG732BSU
-40 C to +85 C
Chip Scale Package (CSP)
Thin Quad Flatpack
Chip Scale Package (CSP)
Thin Quad Flatpack
CP-48
SU-48
CP-48
SU-48
o
o
-40 C to +85 C
o
o
-40 C to +85 C
o
o
-40 C to +85 C
PIN CONFIGURATIONS
CSP & TQFP
S12A
S11A
S10A
S9A
S8A
S7A
S6A
S5A
S4A
36 S12B
35 S11B
34 S10B
33 S9B
32 S8B
31 S7B
30 S6B
29 S5B
28 S4B
27 S3B
26 S2B
25 S1B
1
2
3
4
5
6
7
8
9
36 S28
35 S27
34 S26
33 S25
32 S24
31 S23
30 S22
29 S21
28 S20
27 S19
26 S18
25 S17
PIN 1
S12
1
2
3
4
5
6
7
8
9
PIN 1
INDICATOR
INDICATOR
S11
S10
S9
S8
S7
S6
S5
S4
ADG726
ADG732
TOP VIEW
TOP VIEW
S3A 10
11
S310
11
S2A
S2
S112
S1A 12
NC = NO CONNECT
NC = NO CONNECT
–6–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
Table 1. ADG726 Truth Table
A3
A2
A1 A0 E N C S A
C S B
W R
ONSwitch
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L->H Retains previous switch condition
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
No Change in Switch condition
NONE
S1A - DA, S1B - DB
S2A - DA, S2B - DB
S3A - DA, S3B - DB
S4A - DA, S4B - DB
S5A - DA, S5B - DB
S6A - DA, S6B - DB
S7A - DA, S7B - DB
S8A - DA, S8B - DB
S9A - DA, S9B - DB
S10A - DA, S10B - DB
S11A - DA, S11B - DB
S12A - DA, S12B - DB
S13A - DA, S13B - DB
S14A - DA, S14B - DB
S15A - DA, S15B - DB
S16A - DA, S16B - DB
Table 2. ADG732 Truth Table
A4
A3
A2 A1 A0 E N C S W R
SwitchCondition
X
X
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
X
X
X
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
X
X
X
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
X
X
X
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
X
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
L->H
X
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Retains previous switch condition
No Change in Switch Condition
NONE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
0
0
X = Don’t Care
REV. PrD
–7–
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
TERMINOLOGY
VDD
VSS
Most positive power supply potential.
Most Negative power supply in a dual supply application. In single supply applications, connect to GND.
Positive supply current.
IDD
ISS
Negative supply current.
GND
S
Ground (0 V) reference.
Source terminal. May be an input or output.
Drain terminal. May be an input or output.
Logic control input.
D
IN
VD (VS)
RON
∆RON
RFLAT(ON)
Analog voltage on terminals D, S
Ohmic resistance between D and S.
On resistance match between any two channels, i.e. RONmax - RONmin
Flatness is defined as the difference between the maximum and minimum value of on-resistance as mea
sured over the specified analog signal range.
IS (OFF)
ID (OFF)
Source leakage current with the switch “OFF.”
Drain leakage current with the switch “OFF.”
ID, IS (ON) Channel leakage current with the switch “ON.”
VINL
Maximum input voltage for logic “0”.
VINH
Minimum input voltage for logic “1”.
IINL(IINH
)
Input current of the digital input.
CS (OFF)
CD (OFF)
“OFF” switch source capacitance. Measured with reference to ground.
“OFF” switch drain capacitance. Measured with reference to ground.
CD,CS(ON) “ON” switch capacitance. Measured with reference to ground.
CIN
Digital input capacitance.
tTRANSITION
Delay time measured between the 50ꢀ and 90ꢀ points of the digital inputs and the switch “ON” condi
tion when switching from one address state to another.
t
ON(EN)
Delay time between the 50ꢀ and 90ꢀ points of the EN digital input and the switch “ON” condition.
Delay time between the 50ꢀ and 90ꢀ points of the EN digital input and the switch “OFF” condition.
tOFF(EN)
tOPEN
“OFF” time measured between the 80ꢀ points of both switches when switching from one address state to
another.
Charge
Injection
A measure of the glitch impulse transferred from the digital input to the analog output during switching.
Off Isolation A measure of unwanted signal coupling through an “OFF” switch.
Crosstalk
A measure of unwanted signal is coupled through from one channel to another as a result of parasitic
capacitance.
On Response The Frequency response of the “ON” switch.
Insertion
Loss
The loss due to the ON resistance of the switch.
–8–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
TYPICAL PERFORMANCE CHARACTERISTICS
TBD
TBD
TBD
TPC 7. Leakage Currents as a function
of VD(VS)
TPC 4. On Resistance as a Function of
VD(VS) for Different Temperatures,
SingleSupply
TPC 1. On Resistance as a Function of
VD(VS) for for Single Supply
TBD
TBD
TBD
TPC 8. Leakage Currents as a function
of VD(VS)
TPC 5. On Resistance as a Function of
VD(VS) for Different Temperatures,
Dual Supply
TPC 2. On Resistance as a Function of
VD(VS) for Dual Supply
TBD
TBD
TBD
TPC 9. Leakage Currents as a function
of Temperature
TPC 6. Leakage Currents as a function
of VD(VS)
TPC 3. On Resistance as a Function of
VD(VS) for Different Temperatures,
SingleSupply
REV. PrD
–9–
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
TBD
TBD
TBD
TPC 10. Leakage Currents as a
Function of Temperature
TPC 13. TON/TOFF Times vs.
Temperature
TPC 16. On Response vs. Frequency
TBD
TBD
TPC 11. Supply Currents vs. Input
Switching Frequency
TPC 14. Off Isolation vs. Frequency
TBD
TBD
TPC 12. Charge Injection vs. Source
Voltage
TPC 15. Crosstalk vs. Frequency
–10–
REV. PrD
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
TestCircuits
I
DS
V
V
SS
DD
V1
V
V
SS
DD
S1
S2
I
(OFF)
A
D
D
D
S
S32
V
+0.8V
D
V
S
EN
GND
V
S
R
= V /I
1
ON
DS
Test Circuit 3. ID (OFF)
Test Circuit 1. On Resistance.
V
V
DD
SS
V
V
DD
SS
V
V
DD
SS
V
V
DD
SS
I
(OFF)
S
I
(ON)
A
D
S1
S2
D
S1
D
S32
V
V
D
S
+2.4V
S32
+0.8V
EN
V
S
GND
EN
GND
V
D
Test Circuit 4. ID (ON)
Test Circuit 2. IS (OFF).
V
V
SS
DD
3V
ADDRESS
DRIVE (V
V
V
DD
SS
S1
50%
50%
)
A4
IN
V
S1
V
50Ω
IN
0V
S2 THRU S31
A0
ADG732*
S32
D
V
S32
V
S1
90%
V
OUT
C
35pF
V
R
300 Ω
L
OUT
V
L
EN CS GND WR
90%
S32
t
t
TRANSITION
* SIMILAR CONNECTION FOR ADG726
TRANSITION
Test Circuit 5. Switching Time of Multiplexer, tTRANSITION
.
V
V
V
V
SS
DD
3V
ADDRESS
SS
S1
DD
)
DRIVE (V
IN
A4
A0
V
S
V
50
Ω
0V
IN
S2 THRU S31
ADG732*
S32
V
S
D
V
OUT
80%
V
80%
C
35pF
R
300
OUT
L
L
EN CS GND WR
Ω
t
OPEN
*SIMILAR CONNECTION FOR ADG726
Test Circuit 6. Break Before Make Delay, tOPEN
.
REV. PrD
–11–
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
V
V
DD
SS
V
3V
0V
V
DD
SS
A4
A0
50%
WR
S1
V
S
S2 THRU S32
ADG732*
CS
D
V
V
OUT
O
t
( )
WR
WR
SWITCH
OUTPUT
ON
V
C
35pF
CS
R
L
L
EN GND
20%
80%
300Ω
0V
V
WR
t
(
)
WR
OFF
*SIMILAR CONNECTION FOR ADG726
Test Circuit 7. Write Turn-On and Turn Off Time, tON , tOFF
(WR).
V
V
V
DD
SS
V
DD
SS
3V
A4
A0
S1
50%
(
V
50%
(
EN
S
0V
S2 THRU S32
ADG732*
)
t
)
EN
t
EN
OFF
ON
EN
CS GND
D
V
OUT
V
O
10%
C
35pF
R
300Ω
90%
SWITCH
OUTPUT
L
L
WR
V
EN
0V
*SIMILAR CONNECTION FOR ADG726
Test Circuit 8. Enable Delay, tON(EN), tOFF(EN)
V
V
V
DD
SS
3V
LOGIC
V
DD
SS
A4
+2.4V
RS
INPUT (V
)
IN
ADG732*
0V
A0
S
R
S
D
V
OUT
EN
C
1nF
L
V
S
V
OUT
V
∆
OUT
V
IN
Q
= C
x
V
∆
INJ
L
OUT
*SIMILAR CONNECTION FOR ADG726
Test Circuit 9. Charge Injection.
V
V
V
V
V
V
DD
SS
DD
SS
S1
A4
A0
A4
A0
V
DD
V
SS
NETWORK
ANALYZER
SS
NETWORK
ANALYZER
DD
50
Ω
S2
S1
50
Ω
50
Ω
S32
ADG732*
ADG732*
V
S
S32
V
S
EN**
CS GND
D
V
OUT
D
V
OUT
R
L
R
L
EN CS GND WR
WR
50
Ω
50
Ω
*SIMILAR CONNECTION FOR ADG726
** CONNECT TO 2.4V FOR CROSSTALK MEASUREMENTS
*SIMILAR CONNECTION FOR ADG726
CHANNEL TO CHANNEL CROSSTALK=
OFF ISOLATION = 20LOG (V
10
/V )
S
OUT
V
20LOG (V /V )
10 OUT S
INSERTION LOSS = 20LOG
WITH SWITCH
10
OUT
(
)
V
WITHOUT SWITCH
OUT
Test Circuit 11. Channel-to-Channel Crosstalk.
REV. PrD
Test Circuit 10. OFF Isolation and Bandwidth.
–12–
PRELIMINARY TECHNICAL DATA
ADG726/ADG732
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
48-Lead CSP
(CP-48)
0.024 (0.60)
0.017 (0.42)
0.010 (0.25)
MIN
0.276(7.0)
BSC SQ
0.009 (0.24)
0.024 (0.60)
0.017 (0.42)
0.009 (0.24)
37
36
48
1
PIN 1
INDICATOR
0.207 (5.25)
0.201 (5.10) SQ
0.195 (4.95)
0.266 (6.75)
BSC SQ
TOP
VIEW
BOTTOM
VIEW
25
24
12
13
0.020 (0.50)
0.016 (0.40)
0.012 (0.30)
0.217 (5.5)
REF
0.028 (0.70) MAX
0.026 (0.65) NOM
0.002 (0.05)
o MAX
12
0.035 (0.90) MAX
0.033 (0.85) NOM
0.0004 (0.01)
0.0 (0.0)
0.020 (0.50)
BSC
0.008(0.20)
REF
0.012 (0.30)
0.009 (0.23)
0.007 (0.18)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS
48-Lead TQFP
(SU-48)
0.047 (1.20) MAX
0.354 (9.00) BSC
0.276 (7.0) BSC
0.041 (1.05)
0.037 (0.95)
0.030 (0.75)
0.018 (0.45)
37
48
36
1
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.006 (0.15)
0.002 (0.05)
12
25
24
13
0° MIN
°
0° –7
0.008 (0.20)
0.004 (0.09)
0.011 (0.27)
0.006 (0.17)
0.019 (0.5)
BSC
REV. PrD
–13–
相关型号：
ADG733BRQ
TRIPLE 1-CHANNEL, SGL POLE DOUBLE THROW SWITCH, PDSO16, 0.025 INCH PITCH, MO-137AB, QSOP-16
ROCHESTER
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ADI
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