AD9773EB [ADI]
12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter; 12位， 160 MSPS 2 】 / 4 】 / 8 】内插双通道TxDAC + D / A转换器
| 型号： | AD9773EB |
| 厂家： | 
ADI |
| 描述： | 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter |
| 文件： | 总19页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY TECHNICAL DATA
12-Bit, 160 MSPS
2×/4×/8× Interpolating
a
Dual TxDAC+® D/A Converter
Preliminary Technical Data 01-19-01
AD9773
FEATURES
APPLICATIONS
Communications:
12 bit Resolution, 160 MSPS Conversion Rate
Selectable 2×/4×/8× Interpolating Filter
Programmable Channel Gain and Offset Adjustment
Fs/2,4,8 Digital Quadrature Modulation Capability
Direct IF Transmission Mode for 70MHz+ IFs
Enables Image Rejection Architecture
Fully Compatible SPI Port
Analog Quadrature Modulation Architectures
3G, Multi-Carrier GSM,TDMA, CDMA Systems
Multi-Level QAM Modulators, Instrumentation
PRODUCT DESCRIPTION
The AD9773 is the 12 bit member of the AD977x family of
pin-compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+s. The AD977x family features a serial
port interface (SPI) providing a high level of programmabil-
ity thus allowing for enhanced system level options. These
options include: selectable 2×/4×/8× interpolation filters;
Fs/2, Fs/4 or Fs/8 digital quadrature modulation with image
rejection; a direct IF mode; programmable channel gain
and offset control; programmable internal clock divider;
straight binary or two’s complement data interface; and a
single port or dual port data interface.
Excellent AC Performance
- SFDR -69dBc @ 2-35MHz
-WCDMA ACPR -70dB @ IF=16.25 MHz
Internal PLL Clock Multiplier
Selectable Internal Clock Divider
Versatile Clock Input
-Differential/Single Ended
-Sine Wave or TTL/CMOS/LVPECL Compatible
Versatile Input Data Interface
-2’s Complement/Straight Binary Data Coding
-Dual Port or Single Port Interleaved Data
Single +3.3V Supply Operation
Power Dissipation: <700 mW @ 3.3V
On-chip 1.2 V Reference, 80-Lead LQFP
PROGRAMABLE DUAL INTERPOLATION DAC
WITH IMAGE REJECTION/DIGITAL MODULATION
I
I DAC
OUT
COS
+
T
E
HALF-BAND
FILTER #1*
N
HALF-BAND
FILTER #2*
HALF-BAND
FILTER#3*
I
C
C
GA
DA
FFS
-/+
SIN
DATA
O
DA
ASSEMBLER
22
22
12
12
22
22
I
12
12
T
LATCH
E
FDAC/2,4,8
F
F
S
I
O
SIN
+/-
Q
LATCH
22
22
+
COS
FILTER
BYPASS MUX
I
OUT
Q DAC
WRITE
MUX
CONTROL
SELECT
Ϭ2
(F
DAC
)
CLOCK OUT
Ϭ2
Ϭ2
Ϭ2
DIFF.
REFCLK
PRESCALER
SPI INTERFACE &
CONTROL REGISTERS
-
PHASE DETEC
TOR & VCO
*Half-Band Filters also can be configured for "Zero-Stuffing Only"
PLL CLOCK MULTIPLIER
AND CLOCK DIVIDER
REV. PrA
BLOCK DIAGRAM
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
World Wide Web Site: http://www.analog.com
© Analog Devices, Inc., 2000
1
PRELIMINARY TECHNICAL DATA
AD9773
PRODUCT DESCRIPTION (Continued)
PRODUCT HIGHLIGHTS
The selectable 2×/4×/8× interpolation filters simplify the
requirements of the reconstruction filters while simulta-
neously enhancing the TxDAC+ family’s passband noise/
distortion performance. The independent channel gain and
offset registers allow the user to calibrate LO feedthrough
and sideband suppression errors associated with analog
quadrature modulators. The 6 dB of gain adjustment range
also can be used to control the output power level of each
DAC.
1. The AD9773 is the 12 bit member of the AD977x family of
pin-compatible, high performance, programmable 2×/4×/8×
interpolating TxDAC+s.
2. Direct IF Transmission capability for 70MHz +IFs
through a novel digital mixing process
3. Fs/8 Digital Quadrature Modulation and user selectable
image rejection to simplify /remove cascaded SAW filter
stages
4. 2×/4×/8× User Selectable Interpolating Filter eases data
rate and output signal reconstruction filter requirements.
The AD9773 features the ability to perform Fs/4 and Fs/8
digital modulation and image rejection when combined
with an analog quadrature modulator. In this mode, the
AD9773 would accept I and Q complex data (representing a
single or multicarrier waveform), generate a quadrature
modulated IF signal along with its orthogonal representa-
tion via its dual DACs, and present these two recon-
structed orthogonal IF carriers to an analog quadrature
modulator to complete the image rejection upconversion
process. Another digital modulation mode (i.e. the Direct
IF Mode) allows the original baseband signal representa-
tion to be frequency translated such that pairs of images
fall at multiples of 1/2 the DAC update rate.
5. User selectable 2’s Complement/Straight Binary Data
Coding.
6. User programmable Channel Gain Control over 1 dB
range in 0.01dB increments
7. User programmable Channel Offset +/-10% over the FSR
8. Ultra high speed 400 MSPS DAC conversion rate.
9. Internal Clock Divider provides data rate clock for easy
interfacing.
10. Flexible Clock Input with Single Ended or Differential
Input, CMOS or 1V p-p LO Sinewave input capability.
The AD9773 family includes a flexible clock interface
accepting differential or single-ended sinewave or digital
logic inputs. An internal PLL clock multiplier is also
included to generate the necessary on-chip high frequency
clocks. It can also be disabled to allow the use of a higher
performance external clock source. An internal program-
mable divider simplifies clock generation in the converter
when using an external clock source. A flexible data input
interface allows for straight binary or 2’s complement
formats as well as supports single port interleaved or dual
port data.
11. Low Power: Complete CMOS DAC operates on <700
mW from a 3.0V to 3.6V single supply. The 20ma full-scale
current can be reduced for lower power operation, and a
several sleep functions are provided to reduce power
during idle periods.
12. On-chip Voltage Reference: The AD9773 includes a 1.20
V temperature-compensated bandgap voltage reference.
13. Small 80 lead LQFP
Dual high performance TxDAC+s provides a differential
current output programmable over a 0-20mA range. The
AD9773 is manufactured on an advanced 0.35 micron
CMOS process, operates from a single supply of 3.0V to 3.6
V and consumes <700 mW of power.
Targeted at wide dynamic range, Multi-Carrier and Multi-
Standard systems, the superb baseband performance of the
AD9773 is ideal for Wideband-CDMA, Multi-Carrier
CDMA, Multi-Carrier TDMA, Multi-Carrier GSM and high
performance systems employing high order QAM modula-
tion schemes. The image rejection feature simplifies and
can help to reduce the number of signal band filters needed
in an transmit signal chain. The direct IF mode helps to
eliminate a costly mixer stage for a variety of communica-
tions systems.
2
REV. PrA
PRELIMINARY TECHNICAL DATA
AD9773–SPECIFICATIONS
DC SPECIFICATIONS (TMIN to TMAX, AVDD = +3.3 V, CLKVDD = +3.3 V, DVDD = +3.3 V, PLLVDD = +3.3v, IOUTFS = 20 mA,
unless otherwise noted)
PARAMETER
MIN
12
TYP
MAX
UNITS
bits
RESOLUTION
DCAccuracy1
Integral Non-Linearity
Differential Non_Linearity
Monotonicity
LSB
LSB
ANALOG OUTPUT
Offset Error
% of FSR
% of FSR
% of FSR
mA
V
kΩ
Gain Error (Without Internal Reference)
Gain Error (With Internal Reference)
Full-Scale Output Current2
Output Compliance Range
Output Resistance
20
–1.0
+1.25
1.26
200
3
Output Capacitance
pF
REFERENCE OUTPUT
Reference Voltage
1.14
0.1
1.20
1
V
µA
Reference Output Current3
REFERENCE INPUT
Input Compliance Range
1.25
10
V
Reference Input Resistance (REFLO = 3 V)
Small Signal Bandwidth
MΩ
MHz
0.5
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
ppm of FSR/°C
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
Gain Drift (Without Internal Reference)
Gain Drift (With Internal Reference)
ReferenceVoltage Drift
POWERSUPPLY
AVDD
Voltage Range
3.0
3.3
3.6
V
mA
mA
Analog Supply Current (IAVDD
IAVDD in SLEEP Mode
CLKVDD
)
Voltage Range
Clock Supply Current (ICLKVDD
PLLVDD
Voltage Range
PLL Multiplier Supply Current (IPLLVDD
DVDD
Voltage Range
3.0
3.0
3.0
3.3
3.3
3.6
3.6
3.6
V
mA
)
V
mA
)
3.3
V
Digital Supply Current (IDVDD
Nominal Power Dissipation
)
mA
mW
<700
Power Supply Rejection Ratio –AVDD
Power Supply Rejection Ratio – DVDD
% of FSR/V
% of FSR/V
OPERATINGRANGE
–40
+85
°C
NOTES
1MeasuredatIOUTA drivingavirtualground.
2Nominalfull-scalecurrent, IOUTFS, is32×theIREF current.
3Use an external amplifier to drive any external load.
Specifications subject to change without notice.
REV. PrA
3
PRELIMINARY TECHNICAL DATA
AD9773–SPECIFICATIONS
(TMIN to TMAX, AVDD = +3.3 V, CLKVDD = +3.3 V, DVDD = +3.3 V, PLLVDD = 0 V, IOUTFS = 20 mA,
DYNAMIC SPECIFICATIONS
Differential Transformer Coupled Output, 50Ω Doubly Terminated, unless otherwise noted)
Parameter
Min
Typ
Max
Units
DYNAMICPERFORMANCE
MaximumDACOutputUpdateRate(fDAC
)
400
MSPS
ns
ns
ns
ns
OutputSettlingTime(tST)(to0.025%)
OutputPropagationDelay1(tPD
)
OutputRiseTime(10%to90%)2
OutputFallTime(10%to90%)2
OutputNoise(IOUTFS =20mA)
pA√Hz
ACLINEARITY–BASEBANDMODE
Spurious-FreeDynamicRange(SFDR)toNyquist(fOUT=0dBFS)
fDATA
fDATA
fDATA
fDATA
fDATA
fDATA
=
=
=
=
=
=
MSPS; fOUT
MSPS; fOUT
MSPS; fOUT
MSPS; fOUT
MSPS; fOUT
MSPS; fOUT
=
=
=
=
=
=
MHz
MHz
MHz
MHz
MHz
MHz
dBc
dBc
dBc
dBc
dBc
dBc
Two-ToneIntermodulation(IMD)toNyquist(fOUT1 =fOUT2 =–6dBFS)
fDATA
fDATA
fDATA
fDATA
fDATA
fDATA
=
=
=
=
=
=
MSPS; fOUT1 = MHz; fOUT2
MSPS; fOUT1 = MHz; fOUT2
MSPS; fOUT1 = MHz; fOUT2
MSPS; fOUT1 = MHz; fOUT2
MSPS; fOUT1 = MHz; fOUT2
MSPS; fOUT1 = MHz; fOUT2
=
=
=
=
=
MHz
MHz
MHz
MHz
MHz
MHz
dBc
dBc
dBc
dBc
dBc
dBc
=
TotalHarmonicDistortion(THD)
fDATA
fDATA
=
=
MSPS; fOUT
MSPS; fOUT
=
=
MHz; 0 dBFS
MHz; 0 dBFS
dB
dB
Signal-to-NoiseRatio(SNR)
fDATA
fDATA
=
=
MSPS; fOUT
MSPS; fOUT
=
=
MHz; 0 dBFS
MHz; 0 dBFS
dB
dB
AdjacentChannelPowerRatio(ACPR)
WCDMA with MHz BW,
IF=16MHz,fDATA =65.536MSPS
IF=32MHz,fDATA =131.072MSPS
Four-ToneIntermodulation
MHz Channel Spacing
dBc
dBc
MHz,
(fDATA
MHz,
MSPS,MissingCenter)
MHz and
MHz at –12 dBFS
dBFS
=
ACLINEARITY–IFMODE
Four-ToneIntermodulationatIF= MHz
MHz,
MHz,
MSPS, fDAC
MHz and
=
MHz at dBFS
MHz
dBFS
fDATA
=
NOTES
1PropagationdelayisdelayfromCLKinputtoDACupdate.
2Measuredsingle-endedinto50Ω load.
Specificationssubjecttochangewithoutnotice.
4
REV. PrA
PRELIMINARY TECHNICAL DATA
AD9773–SPECIFICATIONS
(TMIN to TMAX, AVDD = +3.3 V, CLKVDD = +3.3 V, PLLVDD = +0 V, DVDD = +3.3 V, IOUTFS = 20
mA, unless otherwise noted)
DIGITALSPECIFICATIONS
Parameter
Min
Typ
Max
Units
DIGITALINPUTS
Logic“1”Voltage
Logic“0”Voltage
Logic“1”Current1
Logic“0”Current
InputCapacitance
2.1
3
0
V
V
µA
µA
pF
0.9
+10
+10
–10
–10
5
CLOCKINPUTS
InputVoltageRange
Common-ModeVoltage
DifferentialVoltage
0
0.75
0.5
3
2.25
V
V
V
1.5
1.5
PLLCLOCKENABLED
InputSetupTime(tS)
InputHoldTime(tH)
0.2
1.8
1.5
ns
ns
ns
LatchPulsewidth(tLPW
)
PLLCLOCKDISABLED
InputSetupTime(tS)
InputHoldTime(tH)
-1.2
3.2
1.5
ns
ns
ns
ns
LatchPulsewidth(tLPW
)
CLK/PLLLOCKDelay(tOD
)
TBD
Specificationssubjecttochangewithoutnotice.
ORDERING GUIDE
Temperature
Range
Package
Description
Package
Option*
Model
AD9773AST –40°C to +85°C 80-Lead LQFP ST-80
AD9773EB
Evaluation Board
*ST = Thin Plastic Quad Flatpack.
REV. PrA
5
PRELIMINARY TECHNICAL DATA
AD9773–SPECIFICATIONS
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
CLKVDD
LPF
FSADJ1
FSADJ2
REFIO
RESET
SPI_CSB
SPI_CLK
SPI_SDIO
SPI_SDO
DCOM
DVDD
NC
3
CLKVDD
CLKCOM
CLK+
4
5
6
CLK-
7
CLKCOM
DATACLK/PLL_LOCK
DCOM
8
9
AD9773+ TSP
10
11
12
13
14
15
16
17
18
19
20
DVDD
P1B11(MSB)
P1B10
NC
P1B9
NC
NC
P1B8
P1B7
P2B0(LSB)
P2B1
P1B6
DVDD
DCOM
DVDD
P2B2
DCOM
P1B5
P1B4
P2B3
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
6
REV. PrA
PRELIMINARY TECHNICAL DATA
AD9773–SPECIFICATIONS
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
73,72
69,68
I
, I
Differential DAC current outputs, I Channel
Differential DAC current outputs, Q Channel
OUTA1 OUTB1
I
, I
OUTA2 OUTB2
58
60
59
REFIO
FSADJ1
FSADJ2
Reference output, 1.2V nominal
Full-scale current adjust, I channel
Full-scale current adjust, Q channel
5
6
8
CLK+
CLK-
DATACLK/PLL_LOCK
Differential Clock input
Differential Clock input
With the PLL enabled, this pin indicates the state of the PLL.A
read of a logic 1 indicates the PLL is in the locked state. Logic
0 indicates the PLL has not achieved lock. With the PLL dis-
abled, and theAD9773 in two port mode,this pin becomes a
clock signal, running at the input data rate, which may either be
input to theAD9773,or generated by theAD9773, depending
on the state of address 2h, bit 3 in the SPI control register.
PLL Loop Filter
2
LPF
57
RESET
Logic one resets all of the SPI port registers, including address
0h,to their default values. A software reset can also be done
by writing a logic one to SPI register 0h, bit 5. However, the
software reset has no effect on the bits in address 0h.
Port 1 data inputs
In one port mode, IQSEL = 1 followed by a rising edge of the
differential input clock will latch the data into the I channel
input register. IQSEL = 0 will latch the data into the Q
channel input register. In two port mode, this pin becomes the
port 2 MSB.
11-16,19-24
31
P1B11 to P1B0
IQSEL/P2B15
32
ONEPORTCLK/P2B14
With the PLL disabled,and theAD9773 in one port mode, this
pin becomes a clock output which runs at twice the input data
rate of the I and Q channels.This allows theAD9773 to accept
and demux interleaved I and Q data to the I and Q input reg-
isters.
33,34,37-42,45,46 P2B11 to P2B0
Port 2 data inputs.
56
55
SPI_CSB
SPI_CLK
Chip select/SPI data synchronization.On momentary logic
high, resets SPI port logic and initializes instruction cycle.
Data input to the SPI port is registered on the rising edge of
SPI_CLK. Data output on the SPI port is registered on the
falling edge.
54
53
SPI_SDIO
SPI_SDO
Bidirectional data pin. Data direction is controlled by bit 7 of
register address 0h.The default setting for this bit is 0, which
sets SDIO as an input.
In the case where SDIO is an input, SDO acts as an output.
When SDIO becomes an output, SDO enters a high Z state.
79,77,75,74,71,70,
67,66,64,62
ACOM
Analog Common
80.78.76,65,63,61 AVDD
Analog SupplyVoltage
51,43,36,26,17,10 DVDD
Digital SupplyVoltage
Digital Common
52,44,35,25,18,9
DCOM
1,3
4,7
CLKVDD
CLKCOM
Clock SupplyVoltage
Clock Supply Common
REV. PrA
7
PRELIMINARY TECHNICAL DATA
AD9773–SPECIFICATIONS
DIGITAL FILTER SPECIFICATIONS
0
-20
Halfband Filter #1 (43 coefficients)
tap
coefficient
1,43
8
2,42
0
-40
3,41
4,40
-29
0
-60
5,39
67
-80
6,38
7,37
8,36
0
-134
0
-100
0
0.2
0.4
0.6
0.8
1
9,35
244
0
-414
0
673
0
-1079
0
1772
0
-3280
0
10364
16384
10,34
11,33
12,32
13,31
14,30
15,29
16,28
17,27
18,26
19,25
20,24
21,23
22
Figure 1a. 2x Interpolating Filter Response
0
-20
-40
-60
-80
-100
0
0.2
0.4
0.6
0.8
1
Halfband Filter #2 (19 coefficients)
tap
coefficient
1,19
2,18
3,17
4,16
5,15
6,14
7,13
8,12
9,11
10
19
0
-120
0
438
0
-1288
0
5047
8192
Figure 1b. 4x Interpolating Filter Response
0
-20
-40
-60
-80
Halfband Filter #3 (11 coefficients)
tap
1,11
2,10
3,9
4,8
5,7
6
coefficient
7
0
-53
0
-100
0
0.2
0.4
0.6
0.8
1
Figure 1c. 8x Interpolating Filter Response
302
512
REV. PrA
8
PRELIMINARY TECHNICAL DATA
AD9773
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity
or INL)
Linearity error is defined as the maximum deviation of
the actual analog output from the ideal output, deter-
mined by a straight line drawn from zero to full scale.
fundamental. It is expressed as a percentage or in deci-
bels (dB).
Signal-to-Noise Ratio (SNR)
S/N is the ratio of the rms value of the measured out-
put signal to the rms sum of all other spectral com-
ponents below the Nyquist frequency, excluding the
first six harmonics and dc. The value for SNR is ex-
pressed in decibels.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value,
normalized to full scale, associated with a 1 LSB change
in digital input code.
Interpolation Filter
If the digital inputs to the DAC are sampled at a mul-
tiple rate of fDATA (interpolation rate), a digital filter
can be constructed which has a sharp transition band
near fDATA/2. Images which would typically appear
around fDAC (output data rate) can be greatly supressed.
Monotonicity
A D/A converter is monotonic if the output either
increases or remains constant as the digital input in-
creases.
Offset Error
Passband
The deviation of the output current from the ideal of
zero is called offset error. For IOUTA, 0 mA output is
expected when the inputs are all 0s. For IOUTB, 0 mA
output is expected when all inputs are set to 1s.
Frequency band in which any input applied therein
passes unattenuated to the DAC output.
Stopband Rejection
The amount of attenuation of a frequency outside the
passband applied to the DAC, relative to a full-scale
signal applied at the DAC input within the passband.
Gain Error
The difference between the actual and ideal output
span. The actual span is determined by the output
when all inputs are set to 1s, minus the output when all
inputs are set to 0s.
Group Delay
Number of input clocks between an impulse applied at
the device input and peak DAC output current. A half-
band FIR filter has constant group delay over its entire
frequency range
Output Compliance Range
The range of allowable voltage at the output of a cur-
rent-output DAC. Operation beyond the maximum
compliance limits may cause either output stage satu-
ration or breakdown, resulting in nonlinear perfor-
mance.
Impulse Response
Response of the device to an impulse applied to the
input.
Adjacent Channel Power Ratio (or ACPR)
A ratio in dBc between the measured power within a
channel relative to its adjacent channel.
Temperature Drift
Temperature drift is specified as the maximum change
from the ambient (+25°C) value to the value at either
TMIN or TMAX. For offset and gain drift, the drift is
reported in ppm of full-scale range (FSR) per degree
C. For reference drift, the drift is reported in ppm per
degree C.
Complex Modulation
The process of passing the real and imaginary compo-
nents of a signal through a complex modulator (trans-
fer function = ejωt = cosωt+jsinωt) and realizing real
and imaginary components on the modulator output.
Power Supply Rejection
Complex Image Rejection
The maximum change in the full-scale output as the
supplies are varied from minimum to maximum speci-
fied voltages.
In a traditional two part upconversion, two images are
created around the second IF frequency. These images
are redundant and have the effect of wasting transmit-
ter power and system bandwidth. By placing the real
part of a second complex modulator in series with the
first complex modulator, either the upper or lower
frequency image near the second IF can be rejected.
Settling Time
The time required for the output to reach and remain
within a specified error band about its final value,
measured from the start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to
undesired output transients that are quantified by a
glitch impulse. It is specified as the net area of the
glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of
the output signal and the peak spurious signal over the
specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the rms sum of the first six har-
monic components to the rms value of the measured
9
REV. PrA
PRELIMINARY TECHNICAL DATA
Mode Control (via SPI Port)
AD9773
Address
00
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1R/2R Mode. DAC output
current set by one or two
external resistors.
Sleep Mode. Logic 1 shuts
down the DAC output
currents.
SDIO Bidirectional
LSB, MSB first
Software reset on
logic 1
Powerdown Mode. Logic 1 shuts
down all digital and analog functions.
PLL_LOCK
indicator
0 = Input, 1 = I/O
0 = MSB, 1 = LSB
0 = 2R, 1 = 1R
Modulation Mode
(none, fs/2, fs/4,
fs/8)
0 = No Zero Stuffing on
Interpolation Filters
Logic 1 enables zero stuffing
0 = e-jw
1 = e+jw
1 = Real Mix Mode,
0 = Complex Mix Mode
Filter Interpolation Rate
(1×, 2×, 4×, 8×)
Filter Interpolation Rate
(1×, 2×, 4×, 8×)
Modulation Mode
(none, fs/2, fs/4, fs/8)
01
0 = Internally Generated
DATACLK driver
strength
0 = signed input data
,
0 = two port mode,
02
03
04
Data Clock,
1 = Externally Applied
1 = unsigned
1=one port mode
PLL divide
PLL divide
(prescaler) ratio
(prescaler) ratio
0 = automatic charge
pump control,
1 = programmable
PLL charge pump
control
PLL charge pump
control
PLL charge pump
control
0 = PLL off,
1 - PLL on
IDAC fine gain
adjustment
IDAC fine gain
adjustment
IDAC fine gain
adjustment
IDAC fine gain
adjustment
IDAC fine gain
adjustment
IDAC fine gain
adjustment
IDAC fine gain
adjustment
IDAC fine gain
adjustment
05
06
07
IDAC coarse gain
adjustment
IDAC coarse gain
adjustment
IDAC coarse gain
adjustment
IDAC coarse gain
adjustment
IDAC offset
adjustment bit 9
IDAC offset
adjustment bit 8
IDAC offset
adjustment bit 7
IDAC offset
adjustment bit 6
IDAC offset
adjustment bit 5
IDAC offset
adjustment bit 4
IDAC offset
adjustment bit 3
IDAC offset
adjustment bit 2
IDAC IOFFSET direction.
0 = IOFFSET on IOUTN,
1 = IOFFSET on IOUTP
IDAC offset
adjustment bit 1
IDAC offset
adjustment bit 0
08
QDAC fine gain
adjustment
QDAC fine gain
adjustment
QDAC fine gain
adjustment
QDAC fine gain
adjustment
QDAC fine gain
adjustment
QDAC fine gain
adjustment
QDAC fine gain
adjustment
QDAC fine gain
adjustment
09
0A
0B
QDAC coarse gain
adjustment
QDAC coarse gain
adjustment
QDAC coarse gain QDAC coarse gain
adjustment
adjustment
QDAC offset
adjustment bit 9
QDAC offset
adjustment bit 8
QDAC offset
adjustment bit 7
QDAC offset
adjustment bit 6
QDAC offset
adjustment bit 5
QDAC offset
adjustment bit 4
QDAC offset
adjustment bit 3
QDAC offset
adjustment bit 2
QDAC IOFFSET direction.
0 = IOFFSET on IOUTN,
1 = IOFFSET on IOUTP
QDAC offset
adjustment bit 1
QDAC offset
adjustment bit 0
0C
0D
version register
version register
version register
version register
Table 1. Mode Control via SPI Port for AD9773 (default values are highlighted)
10
REV. PrA
PRELIMINARY TECHNICAL DATA
AD9773
Register Description
Address 00h Bit 7
Logic 0 (default), causes the SDIO pin to act as an input during the data transfer (phase 2) of
the communications cycle.When set to a 1, SDIO can act as an input or output, depending on
bit 7 of the instruction byte.
Bit 6
Bit 5
Logic 0 (default). Determines the direction (LSB/MSB first) of the communications and data
transfer communications cycles. Refer to the section MSB/LSB Transfers on page 9 for a
detailed description.
Writing a one to this bit resets the registers to their default values and restarts the chip.The
RESET bit always reads back 0. Register address 0h bits are not cleared by this software reset.
However, a high level at the RESET pin forces all registers, including those in address 0h, to
their default state.
Bit 4
Bit 3
Bit 2
A logic 1 to this bit shuts down the DAC output currents.
Powerdown. Logic 1 shuts down all analog and digital functions.
1R/2R Mode. The default (0) places the AD9773 in 2 resistor mode. In this mode, the IREF
currents for the I and the Q DAC references are set separately by FSADJ1 and FSADJ2 on
pins 60 and 59. In this case, IREF1 = 32*VREF/FSADJ1 and IREF2 = 32*VREF/FSADJ2.With this
bit set to 1, the reference currents for both I and Q DACs are controlled by a single resistor on
pin 60. IREF in one resistor mode for both the I and Q DACs = 16*VREF/FSADJ1
PLL_LOCK indicator.When the PLL is enabled, reading this bit will give the status of the
PLL. A logic 1 indicates the PLL is locked. A logic 0 indicates an unlocked state.
Bit 1
Address 01h Bit 7,6
Filter interpolation rate according to the following table:
00
01
10
11
1×
2×
4×
8×
Bit 5,4
Modulation mode according to the following table:
00
01
10
11
none
fs/2
fs/4
fs/8
Address 01h Bit 3
Logic 1 enables zero stuffing mode for interpolation filters
Bit 2
Default(1) enables the real mix mode.The I and Q data channels are individually modulated
by Fs/2,Fs/4 or Fs/8 after the interpolation filters. However, no complex modulation is done.
In the complex mix mode (logic 0), the digital modulators on the I and Q data channels are
coupled to create a digital complex modulator.When the AD9773 is applied in conjunction
with an external quadrature modulator, rejection can be achieved of either the higher or lower
frequency image around the 2nd IF frequency (i.e., the 2nd IF frequency is the LO of
the analog quadrature modulator external to the AD9773) according to the bit value of
register 01h, bit 1.
Bit 1
Logic 0(default) causes the complex modulation to be of the form e-jwt, resulting in the
rejection of the higher frequency image when the AD9773 is used with an external quadrature
modulator.A logic 1 causes the modulation to be of the form e+jwt, which causes rejection of
the lower frequency image
Address 02h Bit 7
Logic 0 (default) causes data to be accepted on the inputs as 2’s complement binary. Logic 1
causes data to be accepted as straight binary.
Bit 6
Logic 0 (default) places the AD9773 in two port mode. I and Q data enters the AD9773 via
ports one and two, respectively. A logic 1 places the AD9773 in one port mode in which
interleaved I and Q data is applied to port one. See pin function descriptions for DATACLK/
PLL_LOCK, IQSEL and ONEPORTCLK for detailed information on how to use these
modes.
Bit 5
Bit 3
DATACLK driver strength.With the internal PLL disabled, and this bit set to logic 0, it is
recommended that DATACLK be buffered.When this bit is set to logic 1, DATACLK acts as
a stronger driver capable of driving small capacitive loads.
External dataclock. With the PLL disabled, pin 8 (DATACLK/PLL_LOCK) becomes a data
clock which must run at the same rate as the input data.If this bit is set to a 0 (default), pin 8 is
an output and theAD9773 creates this clock. If this bit is a logic 1, pin 8 is an input and an
external data clock must be applied and sychronized with the higher rate clock driving CLK+
and CLK-.
REV. PrA
11
PRELIMINARY TECHNICAL DATA
AD9773
Address 03h Bit 1,0
Setting this divide ratio to a higher number allows theVCO in the PLL to run at a high rate (for
best performance) while the DAC input and output clocks run substantially slower. The
divider ratio is set according to the following table:
00
01
10
11
÷1
÷2
÷4
÷8
Address 04h Bit 7
Logic 0 (default) disables the internal PLL. Logic 1 enables the PLL.
Logic 0 (default) sets the charge pump control to automatic. In this mode, the charge pump
bias current is controlled by the divider ratio defined in address 3h, bits 1 and 0. Logic 1
allows the user to manually define the charge pump bias current using address 4h, bits 2, 1
and 0. Adjusting the charge pump bias current allows the user to optimize the noise/settling
performance of the PLL.
Bit 6
Bit 2,1,0
With the charge pump control set to manual, these bits define the charge pump bias current
according to the following table:
000
001
010
011
100
50µamps
100
200
400
800
Address 05h,09h
Address 06h,0Ah
Bits 7-0 These bits represent an 8 bit binary number (bit 7, MSB) which defines the fine gain
adjustment of the I (5h) and Q (9h) DAC according to the equation given below.
Bits 3-0 These bits represent a 4 bit binary number (bit 3, MSB) which defines the coarse
gain adjustment of the I (6h) and Q (Ah) DACs according to the equation below.
Bits 7-0
Bit 1,0 The ten bits from these two address pairs (7h,8h and Bh,Ch) represent a 10 bit
binary number which defines the offset adjustment of the I and Q DACs according to
the equation below (7h,Bh - bit 7 MSB / 8h,Ch - bit 0 LSB)
Address 07h,0Bh
Address 08h,0Ch
Address 08h,0Ch
Bit 7
This bit determines the direction of the offset of the I (8h) and Q (Ch) DACs. A logic
0 will apply a positive offset current to IOUTA, while a logic 1 will apply a positive
offset current to IOUTB.The magnitude of the offset current is defined by the bits in
addresses 7h,Bh,8h,Ch according the the formulas given below.
×
+
×
6 IREF coarse 1
3 IREF fine
1024 data
=
×
−
×
IOUTA
8
16
32
256
24
216
6 IREF coarse 1
3 IREF fine
1024 216 -data-1
+
×
=
−
×
IOUTB
8
16
32
256
24
216
OFFSET
1024
IOFFSET = 2×IREF
(1R Mode)
(2R Mode)
OFFSET
1024
IOFFSET = 4×IREF
Figure 2. IOUTA and IOUTB as a function of fine gain, coarse gain and offset adjustment.
*Note that IREF is different for the one resistor and two resistor (1R,2R) modes. See the
description for 1R/2R mode control on page 11 (address 0h, bit 2) for the value IREF of in
either mode.
12
REV. PrA
PRELIMINARY TECHNICAL DATA
AD9773
Instruction Byte
The instruction byte contains the following information
as shown below:
SDO (pin 53)
SDIO (pin 54)
SCLK (pin 55)
CSB (pin 56)
AD9773 SPI Port
Interface
N1
0
N0
0
Description
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
0
1
1
0
1
1
Figure 3. AD9773 SPI Port Interface
R/W- bit 7 of the instruction byte determines whether a
read or a write data transfer will occur after the instruction
byte write. Logic high indicates read operation . Logic
zero indicates a write operation. N1, N0 -Bits 6 and 5 of
the instruction byte determine the number of bytes to be
transferred during the data transfer cycle. The bit decodes
are shown in the following table:
Serial Interface For Register Control
The AD9773 serial port is a flexible, synchronous serial
communications port allowing easy interface to many
industry standard microcontrollers and microprocessors.
The serial I/O is compatible with most synchronous
transfer formats, including both the Motorola SPI and
Intel SSR protocols. The interface allows read/write
access to all registers that configure the AD9773. Single
or multiple byte transfers are supported as well as MSB
first or LSB first transfer formats. The AD9773’s serial
interface port can be configured as a single pin I/O
(SDIO) or two unidirectional pins for in/out (SDIO/
SDO).
MSB
I 7
LSB
I 0
I 6
I 5
I 4
I 3
I 2
I 1
R / W
N 1
N 0
A 4
A 3
A 2
A 1
A 0
A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte
determine which register is accessed during the data
transfer portion of the communications cycle. For multibyte
transfers, this address is the starting byte address. The
remaining register addresses are generated by the AD9773.
General Operation of the Serial Interface
There are two phases to a communication cycle with
the AD9773. Phase 1 is the instruction cycle, which is
the writing of an instruction byte into the AD9773,
coincident with the first eight SCLK rising edges. The
instruction byte provides the AD9773 serial port con-
troller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle.
The Phase 1 instruction byte defines whether the up-
coming data transfer is read or write, the number of
bytes in the data transfer and the starting register ad-
dress for the first byte of the data transfer. The first
eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the
AD9773.
Serial Interface Port Pin Description
SCLK (pin55) - Serial Clock. The serial clock pin is used
to synchronize data to and from the AD9773 and to run
the internal state machines. SCLK maximum frequency
is 15 MHz. All data input to the AD9773 is registered on
the rising edge of SCLK. All data is driven out of the
AD9773 on the falling edge of SCLK.
CSB (pin 56) - Chip Select. Active low input starts and
gates a communication cycle. It allows more than one
device to be used on the same serial communications
lines. The SDO and SDIO pins will go to a high
impedance state when this input is high. Chip select
should stay low during the entire communication cycle.
A logic high on the CS pin, followed by a logic low,
will reset the SPI port timing to the initial state of the
instruction cycle. This is true regardless of the present
state of the internal registers or the other signal levels
present at the inputs to the SPI port. If the SPI port is
in the midst of an instruction cycle or a data transfer
cycle, none of the present data will be written.
SDIO (pin 54) - Serial Data I/O. Data is always written
into the AD9773 on this pin. However, this pin can be
used as a bidirectional data line. The configuration of this
pin is controlled by Bit 7 of register address 00h. The
default is logic zero, which configures the SDIO pin as
unidirectional.
SDO(pin 53) - Serial Data Out. Data is read from this pin
for protocols that use separate lines for transmitting and
receiving data. In the case where the AD9773 operates in
a single bidirectional I/O mode, this pin does not output
data and is set to a high impedance state.
The remaining SCLK edges are for Phase 2 of the
communication cycle. Phase 2 is the actual data transfer
between the AD9773 and the system controller. Phase 2
of the communication cycle is a transfer of 1, 2, 3, or 4
data bytes as determined by the instruction byte. Nor-
mally, using one multibyte transfer is the preferred
method. However, single byte data transfers are useful to
reduce CPU overhead when register access requires one
byte only. Registers change immediately upon writing to the
last bit of each transfer byte.
MSB/LSB Transfers
The AD9773 serial port can support both most signifi-
cant bit (MSB) first or least significant bit (LSB) first
data formats. This functionality is controlled by register
address 00h bit 6. The default is MSB first. When this bit
is set active high, the AD9773 serial port is in LSB first
13
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PRELIMINARY TECHNICAL DATA
AD9773
format. That is, if the AD9773 is in LSB first mode, the
instruction byte must be written from least significant bit
to most significant bit. Multibyte data transfers in MSB
format can be completed by writing an instruction byte
that includes the register address of the most significant
byte. In MSB first mode, the serial port internal byte
address generator decrements for each byte required of
the multibyte communication cycle. Multibyte data trans-
fers in LSB first format can be completed by writing an
instruction byte that includes the register address of the
least significant byte. In LSB first mode, the serial port
internal byte address generator increments for each byte
required of the multibyte communication cycle.
Instruction Cycle
Data Transfer Cycle
CS
SCLK
SDIO
SDO
R/W I6
I5
I4
I3
I2
I1
I0
D7
D7
D6
D2
D2
D1
D0
D0
(n)
(n)
n
n
0
0
0
0
0
D6
D1
n
n
0
Figure 4a. Serial Register Interface Timing MSB-First
Instruction Cycle
Data Transfer Cycle
The AD9773 serial port controller address will incre-
ment from 1Fh to 00h for multibyte I/O operations if the
MSB first mode is active. The serial port controller
address will decrement from 00h to 1Fh for multibyte I/
O operations if the LSB first mode is active.
CS
SCLK
SDIO
SDO
I0
I1
I2
I3
I4 I5
I6
R/W D0
D1
D2
D6
D6
D7
n
(n)
(n)
0
0
0
n
D0
D1
D2
D7
n
0
0
0
n
Notes on Serial Port Operation
The AD9773 serial port configuration bits reside in bits
6 and 7 of register address 00h. It is important to note that
the configuration changes immediately upon writing to the
last bit of the register. For multibyte transfers, writing to
this register may occur during the middle of communi-
cation cycle. Care must be taken to compensate for this
new configuration for the remaining bytes of the current
communication cycle.
Figure 4b. Serial Register Interface Timing LSB-First
t
t
DS
SCLK
CS
SCLK
SDIO
t
t
PW L
PW H
The same considerations apply to setting the reset bit in
register address 00h. All other registers are set to their
default values but the software reset doesn’t affect the bits
in register address 00h.
t
t
DS
DH
Instruction Bit
7
Instruction Bit 6
It is recommended to use only single byte transfers when
changing serial port configurations or initiating a soft-
ware reset.
Figure 5. Timing Diagram for Register Write to AD9773
A write to bits 1, 2 and 3 of address 00h with the same
logic levels as for bits 7, 6 and 5 (bit pattern: XY1001YX
binary) allows to reprogram a lost serial port configura-
tion and to reset the registers to their default values. A
second write to address 00h with Reset bit low and serial
port configuration as specified above (XY) reprograms
the OSC IN Multiplier setting. A changed fSYSCLK fre-
quency is stable after a maximum of 200 fMCLK cycles
(=Wake-Up Time).
CS
SCLK
t
DV
SDIO
SDO
Data Bit
n
Data Bit n-1
Figure 6. Timing Diagram for Register Read from AD9773
14
REV. PrA
PRELIMINARY TECHNICAL DATA
AD9773
PROGRAMMABLE MODES
The speed of theVCO with the PLL enabled also has
an effect on phase noise. Optimal phase noise with re-
spect toVCO speed is achieved by running theVCO in
TheAD9773 has a very flexible structure, program-
mable via the SPI compliant port with registers defined
in table 1. Digital filtering and complex modulation can the range of 500MHz to 550MHz.TheVCO speed is a
be programmed, as well as fine and coarse adjustments
for the I and Q DAC channels.
function of the input data rate, of the interpolation rate
and of theVCO prescaler according to the following
function;
PLL ENABLED
VCO Speed (MHz) =
With the Phase Locked Loop (PLL) enabled, a single
ended or differential clock, running at the input data
rate, must be applied to the CLK+/CLK- inputs. If a
single ended clock is to be used, both of these inputs
should have the same dc bias. Data at the input ports
one and two is latched into theAD9773 on the rising
edge of the input clock. Care should be taken to ensure
that the transitions of the input data do not violate the
specified set-up and hold times.
Input Data Rate (MHz) × Interpolation Rate × Prescaler
It is important to note that the resistor/capacitor needed
for the PLL loop filter is included on the AD9773.This
will suffice unless the input data rate is below 10MHz,
in which case an external series RC will need to be
added between the LPF and PLLVDD pins.
PLL DISABLED,TWO PORT MODE
With the PLL disabled, and theAD9773 in two port
mode, a single ended or differential clock, running at
the DAC output rate, must be applied to the CLK+/
CLK- inputs. In this mode, the internal clock dividers
on theAD9773 are used to create a clock, available at
the DATACLK pin, which runs at the input data rate.
This can be used synchronize the input data. Figure 8
shows a functional block diagram of theAD9773 clock
circuitry with the PLL disabled.
The PLL clock multiplier and distribution circuitry
produces the necessary internal synchronized 1×, 2×, 4×,
and 8× clocks for the rising edge triggered latches, in-
terpolation filters, modulators and DACs. Figure 7
shows a functional block diagram of theAD9773 clock
circuitry with the PLL enabled.This circuitry consists
of a phase detector, charge pump, voltage controlled
oscillator (VCO), prescaler, clock distribution and SPI
port control.The charge pump andVCO are powered
from PLLVDD while the differential clock input buffer,
phase detector, prescaler and clock distribution are
powered from CLKVDD. PLL lock status is indicated
by the logic signal at the PLL_LOCK pin.To ensure
optimum phase noise performance from the PLL clock
multiplier and clock distribution,PLLVDD and
CLKVDD must originate from the same clean analog
supply.
CLK+
+
CLK-
-
DATACLK
AD9773
PHASE
DETECTOR
CHARGE
PUMP
INTERPOLATION
FILTERS,
MODULATORS
AND DACS
2× 4× 8×
1×
CLK+
+
CLK-
-
CLOCK
DISTRIBUTION
CIRCUITRY
PRESCALER
VCO
PLL_LOCK
1=LOCK
0=NO LOCK
PLLVDD
INPUT
DATA
AD9773
LATCHES
PLL DIVIDER
(PRESCALER)
CONTROL
INTERNAL SPI
CONTROL
REGISTERS
INTERPOLATION
RATE
LPF
PLL
CONTROL
(PLL OFF)
PHASE
DETECTOR
CHARGE
PUMP
INTERPOLATION
FILTERS,
MODULATION
RATE
CONTROL
MODULATORS
AND DACS
CONTROL
SPI PORT
2× 4× 8×
1×
Figure 8. AD9773 PLL and Clock Circuitry with PLL Disabled
CLOCK
PRESCALER
VCO
DISTRIBUTION
CIRCUITRY
INPUT
DATA
The two port mode is selected by setting control
register 02h, bit 6, to logic 0. Data is latched into input
ports one and two of theAD9773 on the rising edge of
the clock at the DATACLK/PLL_LOCK pin (pin 8).
This clock can be internally generated by theAD9773
or externally applied by setting control register 02h, bit
3 to the desired value.Whether externally or internally
generated, the speed of this clock is defined by the
speed of the clock at CLK+/CLK-, divided by the
LATCHES
PLL DIVIDER
(PRESCALER)
CONTROL
INTERNAL SPI
CONTROL
REGISTERS
INTERPOLATION
RATE
PLL
CONTROL
(PLL ON)
MODULATION
RATE
CONTROL
CONTROL
SPI PORT
Figure 7. AD9773 PLL and Clock Circuitry with PLL Enabled
REV. PrA
15
PRELIMINARY TECHNICAL DATA
AD9773
interpolation rate.The input data rate must also match
INTERPOLATING (COMPLEX MIX MODE)
this clock speed. Note that in this mode, the data rate at Complex Modulation is enabled by setting control
the input to the interpolation filters is the same as the
input data rate at ports one and two.
register 01h, bit 2, to a logic 0. In this mode the two
digital modulators on theAD9773 are coupled to
provide a complex modulation function. In conjunction
with an external quadrature modulator, this complex
modulation can be used to realize a transmit image
PLL DISABLED,ONE PORT MODE
The one port mode is selected by setting control reg-
ister 02h, bit 6, to logic 1. Data to the I and Q channels rejection architecture.The complex modulation function
must now be multiplexed onto the data entering data
port 1. Pin 32 (ONEPORTCLK) is now a clock signal
output . Because the multiplexed data must run at twice
the data rate of the inputs to the I and Q channels, the
speed of ONEPORTCLK is defined as 2× the speed of
the clock at CLK+/CLK-, divided by the interpolation
rate. Pin 31 (IQSEL) can be used to select the I or Q
channels for input. IQSEL =1, followed by a rising
clock edge will latch the input data into the I channel,
while IQSEL =0, followed by a rising clock edge will
latch the input data into the Q channel.
can be programmed for e+jωt ore-jωt to give upper or
lower image rejection.The modulation frequency ω can
be programmed via the SPI port for fs/2, fs/4 and fs/8,
where fs represents the DAC output rate.
AMPLITUDE MODULATION
Given two sine waves at the same frequency, but with a
90 phase difference, a point of view in time can be taken
such the waveform which leads in phase is cosinusoidal,
and the waveform which lags is sinusoidal. Analysis of
complex variables states that the cosine waveform can
then be defined with real positive and negative fre-
quency components, while the sine waveform consists of
imaginary positive and negative frequency components.
These waves are shown graphically in the frequency
domain in figure 9.
One port mode is very useful when interfacing with
devices, such as theAnalog DevicesAD6622Transmit
Signal Processor, in which two digital data channels
have been interlaced (multiplexed).
As defined in control register 02h, bit 7, theAD9773
can accept either signed or unsigned input data.
jωt
e
/2j
sine
DIGITAL FILTER MODES
dc
-jωt
The I and Q data paths of theAD9773 each have their
own independent half-band FIR filters, providing up to
8× interpolation for each channel. Each channel consists
of 3 FIR filters. Figure 1 shows the response of the
digital filters when theAD9773 is set to 2×, 4×, and 8×
modes. Note that the frequency axis of these graphs
have been normalized to the output data rate of the
DAC.As the graphs show, the digital filters can provide
greater than 75dB of out of band rejection.
e
/2j
jωt
-jωt
e
/2
e
/2
cosine
dc
MODULATION MODES
Figure 9. Real and Imaginary Components of Sinusoidal
and Cosinusoidal Waveforms.
INTERPOLATING (NO MODULATION)
With control register 01h, bits 5 and 4, set to 00, the
digital modulators on theAD9773 are disabled.The
AD9773 operates in this mode simply as a dual interpo-
lating (1×, 2×, 4×, 8×) DAC. Filter responses for this
mode are defined in Figure 1.
Amplitude modulating a real baseband signal with a
sine or a cosine convolves the baseband signal with the
modulating carrier in the frequency domain.Amplitude
scaling of the modulated signal occurs and is dependent
on whether the modulating carrier is sine or cosinusoid-
al, again with respect to the reference point of the
viewer.An example of sine and cosine modulation is
given in figure 10.
INTERPOLATING (REAL MIX MODULATION)
The digital modulators in theAD9773 can be enabled
by setting control register 01h, bits 5 and 4, to corre-
spond to the desired fs/2, fs/4, fs/8 modulation mode
(see register descriptions on page 11). Real mix mode is
enabled by setting control register 01h, bit 2, to a logic
1. In this mode, the modulators act individually on each
data path, with no complex mixing between modulators.
OPERATIONS ON COMPLEX SIGNALS
Truly complex signals can not be realized outside of a
computer simulation. However, two data channels, both
consisting of real data, can be defined as the real and
imaginary components of a complex signal. I (real) and
Q (imaginary) data paths are often defined this way. By
16
REV. PrA
PRELIMINARY TECHNICAL DATA
AD9773
BW
input (real)
A (amplitude)
+
-
×
baseband
signal
input
(imaginary)
Σ
output (real)
×
dc
BW
jωt
Ae /2j
sinusoidal
modulation
90°
sinωt
cosωt
BW
dc
-jωt
Ae
Ae
/2j
-jωt
output
(imaginary)
+
jωt
Ae /2
×
/2
cosinusoidal
modulation
Σ
+
×
BW
BW
dc
jωt
e
= cosωt + jsinωt
Figure 10. Identical Baseband Signals, Amplitude
Modulated with Sine and Cosine Carriers.
Figure 12. Implementation of Complex Modulator
using the architecture defined in figure 11, a system can
be realized which operates on complex signals, giving a
complex (real and imaginary) output.
A more efficient method of suppressing the unwanted
image can be achieved by using a complex modulator
followed by a quadrature modulator. Figure 13 shows a
block diagram of of a quadrature modulator. Note that
it is in fact the real output half of a complex modulator.
real
a(t)
c × a(t)-d × b(t)
d × a(t)+c × b(t)
input output
input (real)
complex filter
= (c+jd)
complex input
= (a+jb)
+
×
input
(imaginary)
imaginary
input output
Σ
output
b(t)
-
×
Figure 11. Realization of a Complex Filter
sinωt
If a complex modulation function (e+jωt) is desired, the
real and imaginary components of the system corre-
spond to the real and imaginary components of e+jωt, or
cosωt and sinωt.As Figure 12 shows,the complex
modulation function can be realized by applying these
components to the structure of the complex system
defined in Figure 11.
90°
cosωt
Figure 13. Quadrature Modulator
The complete upconversion can actually be referred to
as two complex upconversion stages, the real output of
which becomes the transmitted signal.
COMPLEX MODULATIONAND IMAGE
REJECTION
The entire upconversion, from baseband to transmit
frequency, is represented graphically in figure 14.The
resulting spectrum shown in figure 14 represents the
complex data consisting of the baseband real and
imaginary channels,now modulated onto orthogonal
(cosine and negative sine) carriers at the transmit
frequency. Note that by changing the sign of the
sinusoidal multiplying term in the complex modulator,
the upper sideband image could have been suppressed
while passing the lower one.
In many applications, a two step upconversion is done
in which the baseband signal is modulated by one
carrier to an IF (intermediate frequency) and then mod-
ulated a second time to the transmit frequency.Although
this approach has several benefits, a major drawback is
that two images are created near the transmit frequency.
Only one image is needed, the other being an exact
duplicate. Unless the unwanted image is filtered, typi-
cally with analog components, transmit power is wasted
and the usable bandwidth available in the system is
reduced.
REV. PrA
17
PRELIMINARY TECHNICAL DATA
AD9773
real channel (out)
a/2
-f *
a/2
f
C
C
real channel (in)
a
-
-b/2j b/2j
f
-f
dc
C
C
complex
modulator
to quadrature
modulator
imaginary channel (out)
-a/2j a/2j
imaginary channel (in)
b
f
-f
C
C
+
dc
b/2
b/2
f
-f
C
C
*f = complex modulation frequency
C
*f = quadrature modulation frequency
Q
a/4+b/4j a/4-b/4j a/4+b/4j a/4-b/4j
real
out
-f
*
-f +f
f
Q
Q
quadrature
modulator
f
+f
C
f
-f
C
-f -f
Q
Q
Q
C
Q C
imaginary
-
-a/4-b/4j a/4-b/4j a/4+b/4j -a/4+b/4j
-f
f
Q
Q
=
rejected images
a/2+b/2j
-f
a/2-b/2j
f
Q
Q
Figure 14. Two Stage Upconversion and Resulting Image Rejection
In purely complex terms, figure 15 represents the two
stage upconversion from complex baseband to carrier.
In this example, ω1 and ω2 represent the modulation
frequencies of the digital complex modulator and the
quadrature modulator.
complex baseband
signal
1
output = real
j(ω1+ω2) t
×
e
1/2
1/2
= real
frequency
dc
−ω1-ω2
ω1+ω2
Figure 15. Complex Representation of Two Stage
Upconversion
18
REV. PrA
PRELIMINARY TECHNICAL DATA
AD9773
ST-80A
80-Lead Thin Plastic Quad Flatpack - 1.4mm Thick [LQFP]
0.559 (14.20)
0.543 (13.80)
SQ
0.063 (1.60)
MAX
0.476 (12.10)
0.469 (11.90)
SQ
0.030 (0.75)
0.020 (0.50)
80
61
1
60
SEATING
PLANE
TOP VIEW
(PINS DOWN)
0.003 (0.08)
MAX
0.006 (0.15)
0.002 (0.05)
20
41
21
40
0.020 (0.50) 0.011 (0.27)
0.057 (1.45)
0.053 (1.35)
BSC
0.007 (0.17)
REV. PrA
19
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