AD9775BSVZ_技术文档

14-Bit, 160 MSPS, 2×/4×/8× Interpolating

Dual TxDAC+^®Digital-to-Analog Converter

AD9775

Versatile input data interface

FEATURES

Twos complement/straight binary data coding

Dual-port or single-port interleaved input data

Single 3.3 V supply operation

Power dissipation: 1.2 W @ 3.3 V typical

On-chip, 1.2 V reference

14-bit resolution, 160 MSPS/400 MSPS input/output

data rate

Selectable 2×/4×/8× interpolating filter

Programmable channel gain and offset adjustment

f_S/4, f_S/8 digital quadrature modulation capability

Direct IF transmission mode for 70 MHz + IFs

Enables image rejection architecture

Fully compatible SPI® port

80-lead, thin quad flat package, exposed pad (TQFP_EP)

APPLICATIONS

Communications

Excellent ac performance

Analog quadrature modulation architecture

3G, multicarrier GSM, TDMA, CDMA systems

Broadband wireless, point-to-point microwave radios

Instrumentation/ATE

SFDR: −71 dBc @ 2 MHz to 35 MHz

W-CDMA ACPR: −71 dB @ IF = 19.2 MHz

Internal PLL clock multiplier

Selectable internal clock divider

Versatile clock input

Differential/single-ended sine wave or TTL/CMOS/LVPECL

compatible

FUNCTIONAL BLOCK DIAGRAM

IDAC

COS

AD9775

HALF-

BAND

FILTER1*

HALF-

BAND

HALF-

BAND

GAIN

DAC

OFFSET

DAC

FILTER2* FILTER3*

DATA

SIN

f_DAC/2, 4, 8

SIN

ASSEMBLER

IMAGE

REJECTION/

DUAL DAC

MODE

BYPASS

MUX

14

16

I

I/Q DAC

GAIN/OFFSET

REGISTERS

LATCH

I AND Q

NONINTERLEAVED

OR INTERLEAVED

DATA

16

Q

LATCH

14

FILTER

BYPASS

MUX

COS

WRITE

MUX

CONTROL

I

IDAC

SELECT

OUT

/2

(f_DAC)

CLOCK OUT

/2

SPI INTERFACE AND

CONTROL REGISTERS

PRESCALER

DIFFERENTIAL

CLK

PHASE DETECTOR

AND VCO

* HALF-BAND FILTERS ALSO CAN BE

CONFIGURED FOR ZERO STUFFING ONLY

PLL CLOCK MULTIPLIER AND CLOCK DIVIDER

Figure 1.

Rev. E

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarks and registeredtrademarks arethe property of their respective owners.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Fax: 781.461.3113

www.analog.com

AD9775

TABLE OF CONTENTS

Features .............................................................................................. 1

1R/2R Mode ................................................................................ 25

Clock Input Configurations...................................................... 25

Programmable PLL .................................................................... 26

Power Dissipation....................................................................... 27

Sleep/Power-Down Modes........................................................ 28

Two-Port Data Input Mode ...................................................... 28

PLL Enabled, Two-Port Mode.................................................. 28

DATACLK Inversion.................................................................. 29

DATACLK Driver Strength....................................................... 29

PLL Enabled, One-Port Mode .................................................. 29

ONEPORTCLK Inversion......................................................... 29

ONEPORTCLK Driver Strength.............................................. 30

IQ Pairing.................................................................................... 30

PLL Disabled, Two-Port Mode................................................. 30

PLL Disabled, One-Port Mode................................................. 30

Digital Filter Modes ................................................................... 31

Amplitude Modulation.............................................................. 31

Modulation, No Interpolation.................................................. 32

Modulation, Interpolation = 2× ............................................... 33

Modulation, Interpolation = 4× ............................................... 34

Modulation, Interpolation = 8× ............................................... 35

Zero Stuffing ............................................................................... 36

Interpolating (Complex Mix Mode)........................................ 36

Operations on Complex Signals............................................... 36

Applications....................................................................................... 1

Functional Block Diagram .............................................................. 1

Revision History ............................................................................... 3

General Description......................................................................... 4

Product Highlights....................................................................... 4

Specifications..................................................................................... 5

DC Specifications ......................................................................... 5

Dynamic Specifications ............................................................... 6

Digital Specifications ................................................................... 7

Digital Filter Specifications......................................................... 8

Absolute Maximum Ratings............................................................ 9

ESD Caution.................................................................................. 9

Thermal Resistance ...................................................................... 9

Pin Configuration and Function Descriptions........................... 10

Typical Performance Characteristics ........................................... 12

Terminology .................................................................................... 17

Mode Control (via SPI Port)......................................................... 18

Register Descriptions ..................................................................... 19

Address 0x00............................................................................... 19

Address 0x01............................................................................... 19

Address 0x02............................................................................... 19

Address 0x03............................................................................... 20

Address 0x04............................................................................... 20

Address 0x05, Address 0x09 ..................................................... 20

Address 0x06, Address 0x0A..................................................... 20

Address 0x07, Address 0x0B..................................................... 20

Address 0x08, Address 0x0C..................................................... 20

Functional Description.................................................................. 21

Serial Interface for Register Control........................................ 21

General Operation of the Serial Interface............................... 21

Instruction Byte .......................................................................... 22

Serial Interface Port Pin Descriptions ..................................... 22

MSB/LSB Transfers..................................................................... 22

Notes on Serial Port Operation ................................................ 22

DAC Operation........................................................................... 24

Complex Modulation and Image Rejection of Baseband

Signals .......................................................................................... 37

Image Rejection and Sideband Suppression of Modulated

Carriers........................................................................................ 38

Applying the Output Configurations........................................... 42

Unbuffered Differential Output, Equivalent Circuit ............. 42

Differential Coupling Using a Transformer............................ 42

Differential Coupling Using an Op Amp................................ 43

Interfacing the AD9775 with the AD8345 Quadrature

Modulator.................................................................................... 43

Evaluation Board ............................................................................ 44

Outline Dimensions....................................................................... 54

Ordering Guide .......................................................................... 54

Rev. E | Page 2 of 56

AD9775

REVISION HISTORY

2/03—Rev. 0 to Rev. A

12/06—Rev. D to Rev. E

Edits to Features ...............................................................................1

Edits to DC Specifications ..............................................................3

Edits to Dynamic Specifications ....................................................4

Edits to Pin Function Descriptions ...............................................8

Edits to Table I............................................................................... 14

Edits to Register Description—Address 02h............................. 15

Edits to Register Description—Address 03h............................. 16

Edits to Register Description—Address 07h, 0Bh.................... 16

Edits to Equation 1........................................................................ 16

Edits to MSB/LSB Transfers......................................................... 18

Edits to Programmable PLL......................................................... 21

Added New Figure 14................................................................... 22

Renumbered Figures 15–69......................................................... 22

Added Two-Port Data Input Mode Section............................... 23

Edits to PLL Enabled, Two-Port Mode ...................................... 24

Edits to Figure 19 .......................................................................... 24

Edits to Figure 21 .......................................................................... 25

Edits to PLL Disabled, Two-Port Mode ..................................... 25

Edits to Figure 22 .......................................................................... 25

Edits to Figure 23 .......................................................................... 26

Edits to Figure 26a ........................................................................ 27

Edits to Complex Modulation and Image Rejection of Baseband

Signals............................................................................................. 31

Edits to Evaluation Board ............................................................ 39

Edits to Figures 56–59 .................................................................. 40

Replaced Figures 60–69................................................................ 42

Updated Outline Dimensions...................................................... 49

Changes to Figure 52, Figure 54, Figure 55, and Figure 56 .......29

1/06—Rev. C to Rev. D

Updated Formatting..........................................................Universal

Changes to Figure 32 .................................................................... 22

Changes to Figure 108 .................................................................. 55

Updated Outline Dimensions...................................................... 58

Changes to Ordering Guide......................................................... 58

6/04—Rev. B to Rev. C

Updated Layout .................................................................Universal

Changes to DC Specifications ....................................................... 5

Changes to Absolute Maximum Ratings...................................... 9

Changes to the DAC Operation Section .................................... 25

Inserted Figure 38.......................................................................... 25

Changes to Figure 40 .................................................................... 26

Changes to Table 11 ...................................................................... 28

Changes to Programmable PLL Section..................................... 28

Changes to Figures 49, 50, and 51............................................... 29

Changes to the PLL Enabled, One-Port Mode Section............ 30

Changes to the PLL Disabled, One-Port Mode Section........... 31

Changes to the Ordering Guide .................................................. 57

Updated Outline Dimensions...................................................... 57

3/03—Rev. A to Rev. B

Changes to Register Description—Address 04h....................... 16

Changes to Equation 1.................................................................. 16

Changes to Figure 8....................................................................... 20

Rev. E | Page 3 of 56

AD9775

GENERAL DESCRIPTION

The AD9775¹is the 14-bit member of the AD977x pin-

compatible, high performance, programmable 2×/4×/8×

interpolating TxDAC+ family. The AD977x family features a

serial port interface (SPI) that provides a high level of

programmability, thus allowing for enhanced system-level

options. These options include selectable 2×/4×/8×

interpolation filters; f_S/2, f_S/4, or f_S/8 digital quadrature

modulation with image rejection; a direct IF mode;

programmable channel gain and offset control; programmable

internal clock divider; straight binary or twos complement data

interface; and a single-port or dual-port data interface.

The AD9775 is manufactured on an advanced 0.35 micron

CMOS process, operates from a single supply of 3.1 V to 3.5 V,

and consumes 1.2 W of power.

Targeted at wide dynamic range, multicarrier and multistandard

systems, the superb baseband performance of the AD9775 is

ideal for wideband CDMA, multicarrier CDMA, multicarrier

TDMA, multicarrier GSM, and high performance systems

employing high order QAM modulation schemes. The image

rejection feature simplifies and can help reduce the number of

signal band filters needed in a transmit signal chain. The direct

IF mode helps to eliminate a costly mixer stage for a variety of

communications systems.

The selectable 2×/4×/8× interpolation filters simplify the

requirements of the reconstruction filters while simultaneously

enhancing the pass-band noise/distortion performance of

TxDAC+ devices. The independent channel gain and offset

adjust registers allow the user to calibrate LO feedthrough and

sideband suppression errors associated with analog quadrature

modulators. The 6 dB of gain adjustment range can also be used

to control the output power level of each DAC.

PRODUCT HIGHLIGHTS

1. The AD9775 is the 14-bit member of the AD977x pin-

compatible, high performance, programmable 2×/4×/8×

interpolating TxDAC+ family.

2. Direct IF transmission capability for 70 MHz + IFs through

a novel digital mixing process.

3. f_S/2, f_S/4, and f_S/8 digital quadrature modulation and user-

selectable image rejection to simplify/remove cascaded

SAW filter stages.

4. A 2×/4×/8× user-selectable, interpolating filter eases data

rate and output signal reconstruction filter requirements.

5. User-selectable, twos complement/straight binary data

coding.

6. User-programmable, channel gain control over 1 dB range

in 0.01 dB increments.

The AD9775 can perform f_S/2, f_S/4, and f_S/8 digital modulation

and image rejection when combined with an analog quadrature

modulator. In this mode, the AD9775 accepts I and Q complex

data (representing a single or multicarrier waveform), generates

a quadrature modulated IF signal along with its orthogonal

representation via its dual DACs, and presents these two

reconstructed orthogonal IF carriers to an analog quadrature

modulator to complete the image rejection upconversion

process. Another digital modulation mode (that is, the direct IF

mode) allows the original baseband signal representation to be

frequency translated such that pairs of images fall at multiples

of one-half the DAC update rate.

7. User programmable channel offset control 10ꢀ over the

FSR.

8. Ultrahigh speed 400 MSPS DAC conversion rate.

9. Internal clock divider provides data rate clock for easy

interfacing.

10. Flexible clock input with single-ended or differential input,

CMOS, or 1 V p-p LO sine wave input capability.

11. Low power: complete CMOS DAC operates on 1.2 W from

a 3.1 V to 3.5 V single supply. The 20 mA full-scale current

can be reduced for lower power operation and several sleep

functions are provided to reduce power during idle

periods.

The AD977x family includes a flexible clock interface that

accepts differential or single-ended sine wave or digital logic

inputs. An internal PLL clock multiplier is included and

generates the necessary on-chip high frequency clocks. It can

also be disabled to allow the use of a higher performance

external clock source. An internal programmable divider

simplifies clock generation in the converter when using an

external clock source. A flexible data input interface allows for

straight binary or twos complement formats and supports

single-port interleaved or dual-port data.

12. On-chip voltage reference. The AD9775 includes a 1.20 V

temperature compensated band gap voltage reference.

13. 80-lead, thin quad flat package, exposed pad (TQFP_EP).

Dual high performance DAC outputs provide a differential

current output programmable over a 2 mA to 20 mA range.

¹Protected by U.S. Patent Numbers 5,568,145; 5,689,257; and 5,703,519. Other patents pending.

Rev. E | Page 4 of 56

AD9775

SPECIFICATIONS

DC SPECIFICATIONS

T_MINto T_MAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, I_OUTFS= 20 mA, unless otherwise noted.

Table 1.

Parameter

Min

Typ

Max

Unit

RESOLUTION

DC Accuracy¹

14

Bits

Integral Nonlinearity

−5

−3

1.5

1.0

+5

+3

LSB

Differential Nonlinearity

ANALOG OUTPUT (for 1R and 2R Gain Setting Modes)

Offset Error

Gain Error (with Internal Reference)

Gain Matching

Full-Scale Output Current²

Output Compliance Range

Output Resistance

−0.02

−1.0

2

0.01

+0.02

+1.0

20

% of FSR

mA

V

kΩ

0.1

−1.0

+1.25

200

3

Output Capacitance

pF

Gain, Offset Cal DACs, Monotonicity Guaranteed

REFERENCE OUTPUT

Reference Voltage

1.14

0.1

1.20

100

1.26

1.25

V

nA

Reference Output Current³

REFERENCE INPUT

Input Compliance Range

Reference Input Resistance

Small Signal Bandwidth

TEMPERATURE COEFFICIENTS

Offset Drift

Gain Drift (with Internal Reference)

Reference Voltage Drift

POWER SUPPLY

V

kΩ

MHz

7

0.5

0

50

ppm of FSR/°C

ppm/°C

AVDD

Voltage Range

Analog Supply Current (I_AVDD

I_AVDDin SLEEP Mode

CLKVDD

Voltage Range

Clock Supply Current (I_CLKVDD

CLKVDD (PLL ON)

Clock Supply Current (I_CLKVDD

DVDD

3.1

3.3

72.5

23.3

3.5

76

26

V

mA

4

)

3.3

8.5

3.5

10.0

V

mA

4

)

23.5

mA

Voltage Range

Digital Supply Current (I_DVDD

3.1

3.3

34

3.5

41

V

mA

4

)

Nominal Power Dissipation

P_DIS

P_DISIN PWDN

380

1.75

6.0

0.4

410

mW

W

mW

% of FSR/V

°C

5

Power Supply Rejection Ratio—AVDD

OPERATING RANGE

−40

+85

¹Measured at I_OUTAdriving a virtual ground.

²Nominal full-scale current, I_OUTFS, is 32 × the I_REFcurrent.

³Use an external amplifier to drive any external load.

⁴100 MSPS f_DACwith f_OUT= 1 MHz, all supplies = 3.3 V, no interpolation, no modulation.

⁵400 MSPS f_DAC= 50 MSPS, f_S/2 modulation, PLL enabled.

Rev. E | Page 5 of 56

AD9775

DYNAMIC SPECIFICATIONS

T_MINto T_MAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 0 V, I_OUTFS= 20 mA, interpolation = 2×, differential

transformer-coupled output, 50 Ω doubly terminated, unless otherwise noted.

Table 2.

Parameter

Min Typ

Max Unit

DYNAMIC PERFORMANCE

Maximum DAC Output Update Rate (f_DAC

Output Settling Time (t_ST) to 0.025%

Output Rise Time 10% to 90%¹

Output Fall Time 10% to 90%¹

Output Noise, I_OUTFS= 20 mA

AC LINEARITY—BASEBAND MODE

)

400

11

MSPS

ns

pA/√Hz

0.8

50

Spurious-Free Dynamic Range (SFDR) to Nyquist (f_OUT= 0 dBFS)

f_DATA= 100 MSPS, f_OUT= 1 MHz

f_DATA= 65 MSPS, f_OUT= 1 MHz

f_DATA= 65 MSPS, f_OUT= 15 MHz

f_DATA= 78 MSPS, f_OUT= 1 MHz

f_DATA= 78 MSPS, f_OUT= 15 MHz

f_DATA= 160 MSPS, f_OUT= 1 MHz

f_DATA= 160 MSPS, f_OUT= 15 MHz

71

84.5

84

80

84

80

dBc

82

80

Spurious-Free Dynamic Range Within a 1 MHz Window

f_OUT= 0 dBFS, f_DATA= 100 MSPS, f_OUT= 1 MHz

Two-Tone Intermodulation (IMD) to Nyquist (f_OUT1= f_OUT2= −6 dBFS)

f_DATA= 65 MSPS, f_OUT1= 10 MHz; f_OUT2= 11 MHz

f_DATA= 65 MSPS, f_OUT1= 20 MHz; f_OUT2= 21 MHz

f_DATA= 78 MSPS, f_OUT1= 10 MHz; f_OUT2= 11 MHz

f_DATA= 78 MSPS, f_OUT1= 20 MHz; f_OUT2= 21 MHz

f_DATA= 160 MSPS, f_OUT1= 10 MHz; f_OUT2= 11 MHz

f_DATA= 160 MSPS, f_OUT1= 20 MHz; f_OUT2= 21 MHz

Total Harmonic Distortion (THD)

73

91.3

dBc

81

76

81

76

81

76

dBc

f_DATA= 100 MSPS, f_OUT= 1 MHz; 0 dBFS

−71 −82.5

dB

Signal-to-Noise Ratio (SNR)

f_DATA= 78 MSPS, f_OUT= 5 MHz; 0 dBFS

f_DATA= 160 MSPS, f_OUT= 5 MHz; 0 dBFS

76

74

dB

Adjacent Channel Power Ratio (ACPR)

W-CDMA with 3.84 MHz BW, 5 MHz Channel Spacing

IF = Baseband, f_DATA= 76.8 MSPS

IF = 19.2 MHz, f_DATA= 76.8 MSPS

71

dBc

Four-Tone Intermodulation

21 MHz, 22 MHz, 23 MHz, and 24 MHz at −12 dBFS (f_DATA= MSPS, Missing Center)

AC LINEARITY—IF MODE

Four-Tone Intermodulation at IF = 200 MHz

201 MHz, 202 MHz, 203 MHz, and 204 MHz at −12 dBFS (f_DATA= 160 MSPS, f_DAC= 320 MHz)

75

72

dBFS

¹Measured single-ended into 50 Ω load.

Rev. E | Page 6 of 56

AD9775

DIGITAL SPECIFICATIONS

T_MINto T_MAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, I_OUTFS= 20 mA, unless otherwise noted.

Table 3.

Parameter

Min

Typ

Max

Unit

DIGITAL INPUTS

Logic 1 Voltage

Logic 0 Voltage

2.1

3

0

V

0.9

Logic 1 Current

Logic 0 Current

Input Capacitance

CLOCK INPUTS

−10

+10

μA

pF

5

Input Voltage Range

Common-Mode Voltage

Differential Voltage

SERIAL CONTROL BUS

Maximum SCLK Frequency (f_SLCK

0

0.75

0.5

3

2.25

V

1.5

)

15

30

MHz

ns

Minimum Clock Pulse Width High (t_PWH

Minimum Clock Pulse Width Low (t_PWL

)

Maximum Clock Rise/Fall Time

1

ms

ns

Minimum Data/Chip Select Setup Time (t_DS)

Minimum Data Hold Time (t_DH)

Maximum Data Valid Time (t_DV)

RESET Pulse Width

Inputs (SDI, SDIO, SCLK, CSB)

Logic 1 Voltage

25

0

30

1.5

2.1

3

0

V

Logic 0 Voltage

0.9

Logic 1 Current

Logic 0 Current

Input Capacitance

−10

+10

μA

pF

5

SDIO Output

Logic 1 Voltage

DRVDD − 0.6

V

Logic 0 Voltage

0.4

V

Logic 1 Current

Logic 0 Current

30

50

mA

Rev. E | Page 7 of 56

AD9775

DIGITAL FILTER SPECIFICATIONS

20

0

Table 4. Half-Band Filter No. 1 (43 Coefficients)

Tap

Coefficient

1, 43

2, 42

3, 41

4, 40

5, 39

6, 38

7, 37

8, 36

8

0

−29

0

67

–20

–40

–60

–80

–100

–120

0

−134

0

244

0

−414

0

673

0

−1079

0

1772

0

−3280

0

10,364

16,384

9, 35

10, 34

11, 33

12, 32

13, 31

14, 30

15, 29

16, 28

17, 27

18, 26

19, 25

20, 24

21, 23

22

0

0.5

1.0

1.5

2.0

8

f_OUT(NORMALIZED TO INPUT DATA RATE)

Figure 2. 2× Interpolating Filter Response

20

0

–20

–40

–60

–80

–100

–120

Table 5. Half-Band Filter No. 2 (19 Coefficients)

Tap

Coefficient

1, 19

2, 18

3, 17

4, 16

5, 15

6, 14

7, 13

8, 12

9, 11

10

19

0

−120

0

438

0

−1288

0

5,047

8,192

0.5

1.0

1.5

f_OUT(NORMALIZED TO INPUT DATA RATE)

Figure 3. 4× Interpolating Filter Response

20

0

–20

–40

–60

–80

–100

–120

Table 6. Half-Band Filter No. 3 (11 Coefficients)

Tap

1, 11

2, 10

3, 9

4, 8

5, 7

6

Coefficient

7

0

−53

0

302

512

2

4

6

f_OUT(NORMALIZED TO INPUT DATA RATE)

Figure 4. 8× Interpolating Filter Response

Rev. E | Page 8 of 56

AD9775

ABSOLUTE MAXIMUM RATINGS

Table 7.

Parameter

With RespectTo

AGND, DGND, CLKGND

AVDD, DVDD, CLKVDD

AGND, DGND, CLKGND

AGND

DGND

CLKGND

Rating

AVDD, DVDD, CLKVDD

AGND, DGND, CLKGND

REFIO, FSADJ1/FSADJ2

I_OUTA, I_OUTB

P1B13 to P1B0, P2B13 to P2B0, RESET

DATACLK, PLL_LOCK

CLK+, CLK–

−0.3 V to +4.0 V

−4.0 V to +4.0 V

−0.3 V to +0.3 V

−0.3 V to AVDD + 0.3 V

−1.0 V to AVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

−0.3 V to CLKVDD + 0.3 V

−0.3 V to DVDD + 0.3 V

125°C

LPF

CLKGND

DGND

SPI_CSB, SPI_CLK, SPI_SDIO, SPI_SDO

Junction Temperature

Storage Temperature

Lead Temperature (10 sec)

−65°C to +150°C

300°C

Stresses above those listed under Absolute Maximum Ratings

may cause permanent damage to the device. This is a stress

rating only; functional operation of the device at these or any

other conditions above those indicated in the operational

section of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect

device reliability.

THERMAL RESISTANCE

θ_JAis specified for the worst-case conditions, that is, a device

soldered in a circuit board for surface-mount packages.

Table 8. Thermal Resistance

Package Type

θ_JA

Unit

80-Lead Thin Quad Flat Package

(TQFP_EP), Exposed Pad

23.5

°C/W

ESD CAUTION

Rev. E | Page 9 of 56

AD9775

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61

1

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

CLKVDD

LPF

FSADJ1

FSADJ2

REFIO

RESET

SPI_CSB

SPI_CLK

SPI_SDIO

SPI_SDO

DGND

DVDD

PIN 1

2

3

CLKVDD

CLKGND

CLK+

4

5

6

CLK–

7

CLKGND

DATACLK/PLL_LOCK

DGND

AD9775

TxDAC+

TOP VIEW

(Not to Scale)

8

9

10

11

12

13

14

15

16

17

18

19

20

DVDD

P1B13 (MSB)

P1B12

NC

P1B11

P2B0 (LSB)

P2B1

P1B10

P1B9

P2B2

P1B8

P2B3

DGND

DVDD

P2B4

P1B7

P1B6

P2B5

21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

NC = NO CONNECT

Figure 5. Pin Configuration

Rev. E | Page 10 of 56

AD9775

Table 9. Pin Function Descriptions

Pin No.

Mnemonic

CLKVDD

LPF

Description

1, 3

2

Clock Supply Voltage.

PLL Loop Filter.

4, 7

5

6

CLKGND

CLK+

CLK−

Clock Supply Common.

Differential Clock Input.

8

DATACLK/PLL_LOCK

With the PLL enabled, this pin indicates the state of the PLL. A read of a Logic 1

indicates the PLL is in the locked state. Logic 0 indicates the PLL has not achieved

lock. This pin may also be programmed to act as either an input or output

(Address 02h, Bit 3) DATACLK signal running at the input data rate.

9, 17, 25, 35, 44, 52

10, 18, 26, 36, 43, 51

11 to 16, 19 to 24, 27, 28

DGND

DVDD

P1B13 (MSB) to P1B0

(LSB)

Digital Common.

Digital Supply Voltage.

Port 1 Data Inputs.

29, 30, 49, 50

31

NC

No Connect.

IQSEL/P2B13 (MSB)

In one-port mode, IQSEL = 1 followed by a rising edge of the differential input

clock latches the data into the I channel input register. IQSEL = 0 latches the data

into the Q channel input register. In two-port mode, this pin becomes the Port 2

MSB.

32

ONEPORTCLK/P2B12

With the PLL disabled and the AD9775 in one-port mode, this pin becomes a

clock output that runs at twice the input data rate of the I and Q channels. This

allows the AD9775 to accept and demux interleaved I and Q data to the I and Q

input registers.

33, 34, 37 to 42, 45 to 48

53

P2B11 to P2B0 (LSB)

SPI_SDO

Port 2 Data Inputs.

In the case where SDIO is an input, SDO acts as an output. When SDIO becomes an

output, SDO enters a High-Z state. This pin can also be used as an output for the

data rate clock. For more information, see the Two-Port Data Input Mode section.

54

55

56

57

SPI_SDIO

SPI_CLK

SPI_CSB

RESET

Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register Address 0x00.

The default setting for this bit is 0, which sets SDIO as an input.

Data input to the SPI port is registered on the rising edge of SPI_CLK. Data output

on the SPI port is registered on the falling edge.

Chip Select/SPI Data Synchronization. On momentary logic high, resets SPI port

logic and initializes instruction cycle.

Logic 1 resets all of the SPI port registers, including Address 0x00, to their default

values. A software reset can also be done by writing a Logic 1 to SPI Register 00h,

Bit 5. However, the software reset has no effect on the bit in Address 0x00.

58

59

60

REFIO

Reference Output, 1.2 V Nominal.

Full-Scale Current Adjust, Q Channel.

Full-Scale Current Adjust, I Channel.

Analog Supply Voltage.

FSADJ2

FSADJ1

AVDD

61, 63, 65, 76, 78, 80

62, 64, 66, 67, 70, 71,

74, 75, 77, 79

AGND

Analog Common.

68, 69

72, 73

I_OUTB2, I_OUTA2

I_OUTB1, I_OUTA1

Differential DAC Current Outputs, Q Channel.

Differential DAC Current Outputs, I Channel.

Rev. E | Page 11 of 56

AD9775

TYPICAL PERFORMANCE CHARACTERISTICS

T = 25°C, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, I_OUTFS= 20 mA, interpolation = 2×, differential transformer-coupled output,

50 Ω doubly terminated, unless otherwise noted.

10

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

65

130

0

50

100

150

FREQUENCY (MHz)

Figure 6. Single-Tone Spectrum @ f_DATA= 65 MSPS with f_OUT= f_DATA/3

Figure 9. Single-Tone Spectrum @ f_DATA= 78 MSPS with f_OUT= f_DATA/3

90

0dBFS

85

80

75

–6dBFS

80

75

–12dBFS

70

–12dBFS

70

–6dBFS

65

60

55

50

65

60

55

50

0

5

10

15

20

25

30

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 7. In-Band SFDR vs. f_OUT@ f_DATA= 65 MSPS

Figure 10. In-Band SFDR vs. f_OUT@ f_DATA= 78 MSPS

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

–6dBFS

0dBFS

–12dBFS

0

5

10

15

20

25

30

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 8. Out-of-Band SFDR vs. f_OUT@ f_DATA= 65 MSPS

Figure 11. Out-of-Band SFDR vs. f_OUT@ f_DATA= 78 MSPS

Rev. E | Page 12 of 56

AD9775

10

0

90

85

80

75

70

65

60

55

50

–6dBFS

–3dBFS

–10

–20

–30

–40

–50

–60

–70

–80

–90

0dBFS

0

100

200

300

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 12. Single-Tone Spectrum @ f_DATA= 160 MSPS with f_OUT= f_DATA/3

Figure 15. Third-Order IMD Products vs. f_OUT@ f_DATA= 65 MSPS

90

–6dBFS

0dBFS

85

80

75

70

65

60

55

50

85

80

75

70

65

60

55

50

0dBFS

–12dBFS

–3dBFS

0

10

20

30

40

50

0

5

10

15

20

25

30

FREQUENCY (MHz)

Figure 13. In-Band SFDR vs. f_OUT@ f_DATA= 160 MSPS

Figure 16. Third-Order IMD Products vs. f_OUT@ f_DATA= 78 MSPS

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

50

–6dBFS

0dBFS

–3dBFS

0dBFS

–12dBFS

0

10

20

30

40

50

0

10

20

30

40

50

60

FREQUENCY (MHz)

Figure 14. Out-of-Band SFDR vs. f_OUT@ f_DATA= 160 MSPS

Figure 17. Third-Order IMD Products vs. f_OUT@ f_DATA= 160 MSPS

Rev. E | Page 13 of 56

AD9775

90

85

80

75

70

65

60

55

50

90

85

80

75

70

65

60

55

–3dBFS

8

×

0dBFS

–6dBFS

4

×

2×

1

×

50

0

3.1

3.2

3.3

AVDD (V)

3.4

3.5

10

20

30

40

50

60

FREQUENCY (MHz)

Figure 18. Third-Order IMD Products vs. f_OUTand Interpolation Rate,

1× f_DATA= 160 MSPS, 2× f_DATA= 160 MSPS, 4× f_DATA= 80 MSPS,

8× f_DATA= 50 MSPS

Figure 21. Third-Order IMD Products vs. AVDD @ f_OUT= 10 MHz,

f

_DAC= 320 MSPS, f_DATA= 160 MSPS

90

85

80

75

70

65

60

55

50

4×

8×

85

80

75

70

65

60

55

50

2×

1×

PLL OFF

PLL ON

–15

–10

–5

0

50

100

150

A

(dBFS)

OUT

INPUT DATA RATE (MSPS)

Figure 19. Third-Order IMD Products vs. A_OUTand Interpolation Rate,

f_DATA= 50 MSPS for All Cases, 1× f_DAC= 50 MSPS, 2× f_DAC= 100 MSPS,

4× f_DAC= 200 MSPS, 8× f_DAC= 400 MSPS

Figure 22. SNR vs. Data Rate for f_OUT= 5 MHz

90

85

80

75

70

65

60

55

50

90

78MSPS

0dBFS

85

80

75

70

f

= 65MSPS

DATA

160MSPS

–12dBFS

–6dBFS

65

60

55

50

–50

0

TEMPERATURE (

50

C)

100

3.1

3.2

3.3

AVDD (V)

3.4

3.5

°

Figure 23. SFDR vs. Temperature @ f_OUT= f_DATA/11

Figure 20. SFDR vs. AVDD @ f_OUT= 10 MHz, f_DAC= 320 MSPS, f_DATA= 160 MSPS

Rev. E | Page 14 of 56

AD9775

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

5

10

15

20

25

30

35

40

45

50

0

50

100

150

FREQUENCY (MHz)

Figure 27. Two-Tone IMD Performance, f_DATA= 150 MSPS, Interpolation = 4×

Figure 24. Single-Tone Spurious Performance, f_OUT= 10 MHz,

f_DATA= 150 MSPS, No Interpolation

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–20

–40

–60

–80

–100

0

50

100

150

200

250

300

0

10

20

30

40

50

FREQUENCY (MHz)

Figure 25. Two-Tone IMD Performance, f_DATA= 150 MSPS, No Interpolation

Figure 28. Single-Tone Spurious Performance, f_OUT= 10 MHz,

_DATA= 80 MSPS, Interpolation = 4×

f

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

5

10

15

20

25

0

50

100

150

200

250

300

FREQUENCY (MHz)

Figure 29. Two-Tone IMD Performance, f_OUT= 10 MHz,

f_DATA= 50 MSPS, Interpolation = 8×

Figure 26. Single-Tone Spurious Performance, f_OUT= 10 MHz,

_DATA= 150 MSPS, Interpolation = 2×

f

Rev. E | Page 15 of 56

AD9775

0

–20

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–40

–60

–80

–100

–120

–100

0

20

40

60

80

100

200

300

400

FREQUENCY (MHz)

Figure 31. Eight-Tone IMD Performance, f_DATA= 160 MSPS,

Interpolation = 8×

Figure 30. Single-Tone Spurious Performance, f_OUT= 10 MHz,

f_DATA= 50 MSPS, Interpolation = 8×

Rev. E | Page 16 of 56

AD9775

TERMINOLOGY

Monotonicity

Adjacent Channel Power Ratio (ACPR)

A ratio in dBc between the measured power within a channel

relative to its adjacent channel.

A DAC is monotonic if the output either increases or remains

constant as the digital input increases.

Offset Error

Complex Image Rejection

The deviation of the output current from the ideal of 0 is called

offset error. For I_OUTA, 0 mA output is expected when the inputs

are all 0. For I_OUTB, 0 mA output is expected when all inputs are

set to 1.

In a traditional two-part upconversion, two images are created

around the second IF frequency. These images are redundant

and have the effect of wasting transmitter power and system

bandwidth. By placing the real part of a second complex

modulator in series with the first complex modulator, either the

upper or lower frequency image near the second IF can be

rejected.

Output Compliance Range

The range of allowable voltage at the output of a current output

DAC. Operation beyond the maximum compliance limits may

cause either output stage saturation or breakdown, resulting in

nonlinear performance.

Complex Modulation

The process of passing the real and imaginary components of a

signal through a complex modulator (transfer function = e^jωt

=

Pass Band

cosωt + jsinωt) and realizing real and imaginary components

on the modulator output.

Frequency band in which any input applied therein passes

unattenuated to the DAC output.

Differential Nonlinearity (DNL)

Power Supply Rejection

DNL is the measure of the variation in analog value, normalized

to full scale, associated with a 1 LSB change in digital input

code.

The maximum change in the full-scale output as the supplies

are varied from minimum to maximum specified voltages.

Settling Time

Gain Error

The time required for the output to reach and remain within a

specified error band about its final value, measured from the

start of the output transition.

The difference between the actual and ideal output span. The

actual span is determined by the output when all inputs are set

to 1 minus the output when all inputs are set to 0.

Signal-to-Noise Ratio (SNR)

Glitch Impulse

SNR is the ratio of the rms value of the measured output signal

to the rms sum of all other spectral components below the

Nyquist frequency, excluding the first six harmonics and dc.

The value for SNR is expressed in decibels.

Asymmetrical switching times in a DAC give rise to undesired

output transients that are quantified by a glitch impulse. It is

specified as the net area of the glitch in pV-s.

Group Delay

Spurious-Free Dynamic Range

Number of input clocks between an impulse applied at the

device input and the peak DAC output current. A half-band FIR

filter has constant group delay over its entire frequency range.

The difference, in dB, between the rms amplitude of the output

signal and the peak spurious signal over the specified

bandwidth.

Impulse Response

Stop-Band Rejection

Response of the device to an impulse applied to the input.

The amount of attenuation of a frequency outside the pass band

applied to the DAC, relative to a full-scale signal applied at the

DAC input within the pass band.

Interpolation Filter

If the digital inputs to the DAC are sampled at a multiple rate of

f_DATA(interpolation rate), a digital filter can be constructed with

a sharp transition band near fDATA/2. Images that would

typically appear around f_DAC(output data rate) can be greatly

suppressed.

Temperature Drift

Temperature drift is specified as the maximum change from the

ambient (25°C) value to the value at either T_MINor T_MAX. For

offset and gain drift, the drift is reported in ppm of full-scale

range (FSR) per °C. For reference drift, the drift is reported in

ppm per °C.

Linearity Error

(Also called integral nonlinearity or INL.) It is defined as the

maximum deviation of the actual analog output from the ideal

output, determined by a straight line drawn from zero scale to

full scale.

Total Harmonic Distortion (THD)

THD is the ratio of the rms sum of the first six harmonic

components to the rms value of the measured fundamental. It is

expressed as a percentage or in decibels (dB).

Rev. E | Page 17 of 56

AD9775

MODE CONTROL (VIA SPI PORT)

Table 10. Mode Control via SPI Port¹

Address

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

0x00

SDIO

LSB, MSB

First, 0 = MSB

1 = LSB

Software

Reset on

Logic 1

Sleep Mode

Logic 1

Shuts Down

the DAC

Output

Currents

Power-Down

Mode Logic 1

Shuts Down All

Digital and

Analog

1R/2R Mode

DAC Output

Current Set

by One or

Two External

Resistors

PLL_LOCK

Indicator

Bidirectional

0 = Input

1 = I/O

Functions

0 = 2R,

1 = 1R

0 = e^−jωt

0x 01

0x 02

Filter

Interpolation

Rate (1×, 2×, 4×, (None, f_S/2,

8×)

Modulation

Mode

Modulation

Mode

(None, f_S/2,

DATACLK/

PLL_LOCK²

Select

0 = PLLLOCK

1 = DATACLK

0 = No Zero

Stuffing on

Interpolation

Filters, Logic 1

Enables Zero

Stuffing.

1 = Real

Interpolation

Rate (1×, 2×,

4×, 8×)

1 = e^+jωt

Mix Mode

0 = Complex

Mix Mode

f_S/4, f_S/8)

DATACLK

Driver

Strength

DATACLK

Invert

0 = No Invert

1 = Invert

ONEPORTCLK IQSEL Invert

Invert

Q First

0 = No Invert 0 = I First

0 = Signed

Input Data

1 = Unsigned

0 = Two-Port

Mode

1 = One-Port

Mode

0 = No Invert

1 = Invert

1 = Q First

0x 03

0x 04

Data Rate

PLL Divide

(Prescaler)

Ratio

PLL Divide

(Prescaler)

Ratio

Clock Output²

0 = PLL OFF²

1 = PLL ON

PLL Charge

Pump

Control

PLL Charge

Pump

Control

PLL Charge

Pump Control

0 = Automatic

Charge Pump

Control, 1 =

Programmable

0x 05

0x 06

0x 07

IDAC Fine Gain Adjustment

IDAC Coarse Gain Adjustment

IDAC Offset

Adjustment

Bit 9

IDAC Offset

Adjustment

Bit 8

IDAC Offset

Adjustment

Bit 7

IDAC Offset

Adjustment

Bit 6

IDAC Offset

Adjustment

Bit 5

IDAC Offset

Adjustment

Bit 4

IDAC Offset

Adjustment

Bit 3

IDAC Offset

Adjustment

Bit 2

0x 08

IDAC I_OFFSET

Direction

0 = I_OFFSET

on I_OUTA

IDAC Offset

Adjustment

Bit 1

IDAC Offset

Adjustment

Bit 0

1 = I_OFFSET

on I_OUTB

0x 09

0x 0A

QDAC Fine Gain Adjustment

QDAC Coarse Gain Adjustment

0x 0B

0x 0C

QDAC Offset

Adjustment

Bit 9

QDAC Offset

Adjustment

Bit 8

QDAC Offset QDAC Offset QDAC Offset

QDAC Offset

Adjustment

Bit 4

QDAC Offset QDAC Offset

Adjustment

Bit 7

Adjustment

Bit 6

Adjustment

Bit 5

Adjustment

Bit 3

Adjustment

Bit 2

QDAC I_OFFSET

Direction

0 = I_OFFSET

on I_OUTA

QDAC Offset QDAC Offset

Adjustment

Bit 1

Adjustment

Bit 0

1 = I_OFFSET

on I_OUTB

0x 0D

Version Register

¹Default values are shown in bold.

²See the Two-Port Data Input Mode section.

Rev. E | Page 18 of 56

AD9775

REGISTER DESCRIPTIONS

ADDRESS 0x00

Bit 3: Logic 1 enables zero-stuffing mode for interpolation filters.

Bit 7: Logic 0 (default) causes the SPI_SDIO pin to act as an

input during the data transfer (Phase 2) of the communications

cycle. When set to 1, SPI_SDIO can act as an input or output,

depending on Bit 7 of the instruction byte.

Bit 2: Default (1) enables the real mix mode. The I and Q data

channels are individually modulated by f_S/2, f_S/4, or f_S/8 after

the interpolation filters. However, no complex modulation is

done. In the complex mix mode (Logic 0), the digital

modulators on the I and Q data channels are coupled to create a

digital complex modulator. When the AD9775 is applied in

conjunction with an external quadrature modulator, rejection

can be achieved of either the higher or lower frequency image

around the second IF frequency (that is, the LO of the analog

quadrature modulator external to the AD9775) according to the

bit value of Register 0x01, Bit 1.

Bit 6: Logic 0 (default) determines the direction (LSB/MSB

first) of the communications and data transfer communications

cycles. Refer to the MSB/LSB Transfers section for more details.

Bit 5: Writing 1 to this bit resets the registers to their default

values and restarts the chip. The RESET bit always reads back 0.

Register Address 0x00 bits are not cleared by this software reset.

However, a high level at the RESET pin forces all registers,

including those in Address 0x00, to their default state.

Bit 1: Logic 0 (default) causes the complex modulation to be of

the form e^{− jωt}, resulting in the rejection of the higher frequency

image when the AD9775 is used with an external quadrature

modulator. A Logic 1 causes the modulation to be of the form

e^+jωt, which causes rejection of the lower frequency image.

Bit 4: Sleep Mode. A Logic 1 to this bit shuts down the DAC

output currents.

Bit 3: Power Down. Logic 1 shuts down all analog and digital

functions except for the SPI port.

Bit 0: In two-port mode, a Logic 0 (default) causes Pin 8 to act

as a lock indicator for the internal PLL. A Logic 1 in this register

causes Pin 8 to act as a DATACLK. For more information, see

the Two-Port Data Input Mode section.

Bit 2: 1R/2R Mode. The default (0) places the AD9775 in two-

resistor mode. In this mode, the I_REFcurrents for the I and Q

DAC references are set separately by the R_SETresistors on FSADJ1

and FSADJ2 (Pin 60 and Pin 59). In 2R mode, assuming the coarse

gain setting is full scale and the fine gain setting is zero,

ADDRESS 0x02

I

_FULLSCALE1= 32 × V_REF/FSADJ1 and I_FULLSCALE2= 32 × V_REF/FSADJ2.

Bit 7: Logic 0 (default) causes data to be accepted on the inputs

as twos complement binary. Logic 1 causes data to be accepted

as straight binary.

With this bit set to 1, the reference currents for both I and Q

DACs are controlled by a single resistor on Pin 60. I_FULLSCALEin

one-resistor mode for both of the I and Q DACs is half of what

Bit 6: Logic 0 (default) places the AD9775 in two-port mode.

I and Q data enters the AD9775 via Ports 1 and 2, respectively.

A Logic 1 places the AD9775 in one-port mode in which

interleaved I and Q data is applied to Port 1. See Table 9 for

detailed information on how to use the DATACLK/PLL_LOCK,

IQSEL, and ONEPORTCLK modes.

it would be in 2R mode, assuming all other conditions (R_SET

,

register settings) remain unchanged. The full-scale current of

each DAC can still be set to 20 mA by choosing a resistor of half

the value of the R_SETvalue used in 2R mode.

Bit 1: PLL_LOCK Indicator. When the PLL is enabled, reading

this bit gives the status of the PLL. A Logic 1 indicates the PLL

is locked. A Logic 0 indicates an unlocked state.

Bit 5: DATACLK Driver Strength. With the internal PLL

disabled and this bit set to Logic 0, it is recommended that

DATACLK be buffered. When this bit is set to Logic 1,

DATACLK acts as a stronger driver capable of driving small

capacitive loads.

ADDRESS 0x01

Bit 7 and Bit 6: This is the filter interpolation rate according to

the following table.

Bit 4: Logic 0 (default). A value of 1 inverts DATACLK at Pin 8.

Table 11.

Bit 2: Logic 0 (default). A value of 1 inverts ONEPORTCLK at

Pin 32.

00

01

10

11

1×

2×

4×

8×

Bit 1: Logic 0 (default) causes IQSEL = 0 to direct input data to

the I channel, while IQSEL = 1 directs input data to the Q

channel.

Bit 5 and Bit 4: This is the modulation mode according to the

following table.

Bit 0: Logic 0 (default) defines IQ pairing as IQ, IQ… while

programming a Logic 1 causes the pair ordering to be QI, QI…

Table 12.

00

01

10

11

None

f_S/2

f_S/4

f_S/8

Rev. E | Page 19 of 56

AD9775

ADDRESS 0x03

ADDRESS 0x05, ADDRESS 0x09

Bit 7: Allows the data rate clock (divided down from the DAC

clock) to be output at either the DATACLK/PLL_LOCK pin

(Pin 8) or at the SPI_SDO pin (Pin 53). The default of 0 in this

register enables the data rate clock at DATACLK/ PLL_LOCK,

while a 1 in this register causes the data rate clock to be output

at SPI_SDO. For more information, see the Two-Port Data

Input Mode section.

Bit 7 to Bit 0: These bits represent an 8-bit binary number

(Bit 7 MSB) that defines the fine gain adjustment of the I (0x05)

and Q (0x09) DAC, according to Equation 1.

ADDRESS 0x06, ADDRESS 0x0A

Bit 3 to Bit 0: These bits represent a 4-bit binary number (Bit 3

MSB) that defines the coarse gain adjustment of the I (0x06)

and Q (0x0A) DACs, according to Equation 1.

Bit 1 and Bit 0: Setting this divide ratio to a higher number

allows the VCO in the PLL to run at a high rate (for best

performance) while the DAC input and output clocks run

substantially slower. The divider ratio is set according to the

following table.

ADDRESS 0x07, ADDRESS 0x0B

Bit 7 to Bit 0: These bits are used in conjunction with Address

0x08, 0x0C, Bit 1 and Bit 0.

ADDRESS 0x08, ADDRESS 0x0C

Table 13.

Bit 1 and Bit 0: The 10 bits from these two address pairs

(0x07, 0x08 and 0x0B, 0x0C) represent a 10-bit binary number

that defines the offset adjustment of the I and Q DACs,

according to Equation 1 (0x07, 0x0B—Bit 7 MSB/0x08, 0x0C—

Bit 0 LSB).

00

01

10

11

÷1

÷2

÷4

÷8

ADDRESS 0x04

ADDRESS 0x08, ADDRESS 0x0C

Bit 7: Logic 0 (default) disables the internal PLL. Logic 1

enables the PLL.

Bit 7: This bit determines the direction of the offset of the

I (0x08) and Q (0x0C) DACs. A Logic 0 applies a positive offset

current to I_OUTA, while a Logic 1 applies a positive offset current

to I_OUTB. The magnitude of the offset current is defined by the

bits in Addresses 0x07, 0x0B, 0x08, and 0x0C, according to

Equation 1.

Bit 6: Logic 0 (default) sets the charge pump control to

automatic. In this mode, the charge pump bias current is

controlled by the divider ratio defined in Address 0x03, Bits 1

and 0. Logic 1 allows the user to manually define the charge

pump bias current using Address 0x04, Bits 2, 1, and 0.

Adjusting the charge pump bias current allows the user to

optimize the noise/settling performance of the PLL.

Equation 1 shows I_OUTAand I_OUTBas a function of fine gain,

coarse gain, and offset adjustment when using the 2R mode. In

1R mode, the current I_REFis created by a single FSADJ resistor

(Pin 60). This current is divided equally into each channel so

that a scaling factor of one-half must be added to these

equations for full-scale currents for both DACs and the offset.

Bit 2 to Bit 0: With the charge pump control set to manual,

these bits define the charge pump bias current according to the

following table.

Table 14.

000

001

010

011

111

50 μA

100 ꢀA

200 ꢀA

400 ꢀA

800 ꢀA

6 × I

COARSE + 1

3 × I

⎡

⎤

⎥

FINE

⎡ 1024 DATA ⎤

⎛

⎞⎛

⎞

⎛

⎞

⎛

⎞

⎛

⎞⎛

⎞

REF

⎜

⎟

I_OUTA= ⎜

⎟

− ⎜

⎜

⎟

×

(A)

⎥

⎜

⎟

⎜

⎟⎜

⎟

⎢

⎜

⎟⎜

⎠⎝

8

16

32

256

24

2¹⁴

⎝

⎣

⎠⎝

⎠

⎢

⎝

⎣

⎝

⎠

⎠⎥

⎦

⎠

⎝

⎦

14

⎡

⎤

⎥

⎛

⎞

⎟

6 × I

COARSE + 1

3 × I

2

− DATA − 1

2¹⁴

⎡

⎤

FINE

1024

24

⎛

⎞⎛

⎞

⎛

⎞

⎛

⎞

⎛

⎜

⎞

⎟

REF

⎜

⎢

I_OUTB= ⎜

⎟⎜

⎟

− ⎜

⎜

⎟

×

(A)

(1)

⎜

⎟

⎠

⎢

⎥

⎜

⎝

⎟

⎠

8

16

32

256

⎢

⎝

⎥

⎦

⎢

⎝

⎣

⎝

⎠

⎥

⎦

⎠

⎠⎝

⎠

⎝

⎣

OFFSET

⎛

⎜

⎞

⎟

I_OFFSET= 4 × I_REF

(A)

1024

⎝

⎠

Rev. E | Page 20 of 56

AD9775

FUNCTIONAL DESCRIPTION

The AD9775 dual interpolating DAC consists of two data

channels that can be operated independently or coupled to form

a complex modulator in an image reject transmit architecture.

Each channel includes three FIR filters, making the AD9775

capable of 2×, 4×, or 8× interpolation. High speed input and

output data rates can be achieved within the following

limitations.

SDO (PIN 53)

SDIO (PIN 54)

AD9775 SPI PORT

INTERFACE

SPI_CLK (PIN 55)

CSB (PIN 56)

Figure 32. SPI Port Interface

Table 15.

Interpolation Rate

(MSPS)

SERIAL INTERFACE FOR REGISTER CONTROL

Input Data Rate

(MSPS)

DAC Sample Rate

(MSPS)

The AD9775 serial port is a flexible, synchronous serial

communications port that allows easy interface to many

industry-standard microcontrollers and microprocessors.

The serial I/O is compatible with most synchronous transfer

formats, including both the Motorola SPI and Intel SSR

protocols. The interface allows read/write access to all registers

that configure the AD9775. Single- or multiple-byte transfers

are supported, as well as MSB-first or LSB-first transfer formats.

The AD9775 serial interface port can be configured as a single

pin I/O (SDIO) or two unidirectional pins for I/O (SDIO/SDO).

1×

2×

4×

8×

160

100

50

160

320

400

Both data channels contain a digital modulator capable of

mixing the data stream with an LO of f_DAC/2, f_DAC/4, or f_DAC/8,

where f_DACis the output data rate of the DAC. A zero-stuffing

feature is also included and can be used to improve pass-band

flatness for signals being attenuated by the sin(x)/x

characteristic of the DAC output. The speed of the AD9775,

combined with the digital modulation capability, enables direct

IF conversion architectures at 70 MHz and higher.

GENERAL OPERATION OF THE SERIAL INTERFACE

There are two phases to a communication cycle with the

AD9775. Phase 1 is the instruction cycle, which is the writing of

an instruction byte into the AD9775 coincident with the first

eight SCLK rising edges. The instruction byte provides the

AD9775 serial port controller with information regarding the

data transfer cycle, which is Phase 2 of the communication

cycle. The Phase 1 instruction byte defines whether the

upcoming data transfer is read or write, the number of bytes in

the data transfer, and the starting register address for the first

byte of the data transfer. The first eight SCLK rising edges of

each communication cycle are used to write the instruction byte

into the AD9775.

The digital modulators on the AD9775 can be coupled to form

a complex modulator. By using this feature with an external

analog quadrature modulator, such as the Analog Devices

AD8345, an image rejection architecture can be enabled. To

optimize the image rejection capability, as well as LO feed-

through in this architecture, the AD9775 offers programmable

(via the SPI port) gain and offset adjust for each DAC.

Also included on the AD9775 are a phase-locked loop (PLL)

clock multiplier and a 1.20 V band gap voltage reference. With

the PLL enabled, a clock applied to the CLK+/CLK− inputs is

frequency multiplied internally and generates all necessary

internal synchronization clocks. Each 14-bit DAC provides two

complementary current outputs whose full-scale currents can

be determined either from a single external resistor or

independently from two separate resistors (see the 1R/2R Mode

section). The AD9775 features a low jitter, differential clock

input that provides excellent noise rejection while accepting a

sine or square wave input. Separate voltage supply inputs are

provided for each functional block to ensure optimum noise

and distortion performance.

A Logic 1 on the SPI_CSB pin, followed by a logic low, resets

the SPI port timing to the initial state of the instruction cycle.

This is true regardless of the present state of the internal

registers or the other signal levels present at the inputs to the

SPI port. If the SPI port is in the middle of an instruction cycle

or a data transfer cycle, none of the present data is written.

The remaining SCLK edges are for Phase 2 of the

communication cycle. Phase 2 is the actual data transfer

between the AD9775 and the system controller. Phase 2 of the

communication cycle is a transfer of one to four data bytes as

determined by the instruction byte. Typically, using one

multibyte transfer is the preferred method. However, single byte

data transfers are useful to reduce CPU overhead when register

access requires one byte only. Registers change immediately

upon writing to the last bit of each transfer byte.

Sleep and power-down modes can be used to turn off the DAC

output current (sleep) or the entire digital and analog sections

(power-down) of the chip. An SPI-compliant serial port is used

to program the many features of the AD9775. Note that in

power-down mode, the SPI port is the only section of the chip

still active.

Rev. E | Page 21 of 56

AD9775

SPI_SDO (Pin 53)—Serial Data Out

INSTRUCTION BYTE

Data is read from this pin for protocols that use separate lines

for transmitting and receiving data. In the case where the

AD9775 operates in a single bidirectional I/O mode, this pin

does not output data and is set to a high impedance state.

The instruction byte contains the information shown next

Table 16.

N1

N0

0

1

0

1

Description

0

1

Transfer 1 Byte

Transfer 2 Bytes

Transfer 3 Bytes

Transfer 4 Bytes

MSB/LSB TRANSFERS

The AD9775 serial port can support both most significant bit

(MSB) first or least significant bit (LSB) first data formats. This

functionality is controlled by the LSB-first bit in Register 0. The

default is MSB first.

R/W

Bit 7 of the instruction byte determines whether a read or a

write data transfer occurs after the instruction byte write.

Logic 1 indicates read operation. Logic 0 indicates a write

operation.

When this bit is set active high, the AD9775 serial port is in

LSB-first format. In LSB-first mode, the instruction byte and

data bytes must be written from LSB to MSB. In LSB-first mode,

the serial port internal byte address generator increments for

each byte of the multibyte communication cycle.

N1, N0

Bit 6 and Bit 5 of the instruction byte determine the number of

bytes to be transferred during the data transfer cycle. The bit

decodes are shown next.

When this bit is set default low, the AD9775 serial port is in

MSB-first format. In MSB-first mode, the instruction byte and

data bytes must be written from MSB to LSB. In MSB-first

mode, the serial port internal byte address generator

Table 17.

decrements for each byte of the multibyte communication cycle.

MSB

LSB

When incrementing from 0x1F, the address generator changes

to 0x00. When decrementing from 0x00, the address generator

changes to 0x1F.

I7

I6

I5

I4

I3

I2

I1

I0

R/W

N1

N0

A4

A3

A2

A1

A0

A4, A3, A2, A1, A0

NOTES ON SERIAL PORT OPERATION

Bit 4 to Bit 0 of the instruction byte determine which register is

accessed during the data transfer portion of the communications

cycle. For multibyte transfers, this address is the starting byte

address. The remaining register addresses are generated by

the AD9775.

The AD9775 serial port configuration bits reside in Bit 6 and

Bit 7 of Register Address 0x00. It is important to note that the

configuration changes immediately upon writing to the last bit

of the register. For multibyte transfers, writing to this register

may occur during the middle of the communication cycle. Care

must be taken to compensate for this new configuration for the

remaining bytes of the current communication cycle.

SERIAL INTERFACE PORT PIN DESCRIPTIONS

SPI_CLK (Pin 55)—Serial Clock

The serial clock pin is used to synchronize data to and from the

AD9775 and to run the internal state machines. SPI_CLK

maximum frequency is 15 MHz. All data input to the AD9775

is registered on the rising edge of SPI_CLK. All data is driven

out of the AD9775 on the falling edge of SPI_CLK.

The same considerations apply to setting the reset bit in

Register Address 0x00. All other registers are set to their

default values, but the software reset does not affect the bits in

Register Address 0x00.

It is recommended to use only single-byte transfers when

changing serial port configurations or initiating a software reset.

SPI_CSB (Pin 56)—Chip Select

Active low input starts and gates a communication cycle. It

allows more than one device to be used on the same serial

communications lines. The SDO and SDIO pins go to a high

impedance state when this input is high. Chip select should stay

low during the entire communication cycle.

A write to Bit 1, Bit 2, and Bit 3 of Address 0x00 with the same

logic levels as for Bit 7, Bit 6, and Bit 5 (bit pattern is XY1001YX

binary) allows the user to reprogram a lost serial port

configuration and to reset the registers to their default values. A

second write to Address 0x00 with reset bit low and serial port

configuration as specified above (XY) reprograms the OSC IN

multiplier setting. A changed f_SYSCLKfrequency is stable after a

maximum of 200 f_MCLKcycles (equals wake-up time).

SPI_SDIO (Pin 54)—Serial Data I/O

Data is always written into the AD9775 on this pin. However,

this pin can be used as a bidirectional data line. The

configuration of this pin is controlled by Bit 7 of Register

Address 0x00. The default is Logic 0, which configures the

SDIO pin as unidirectional.

Rev. E | Page 22 of 56

AD9775

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CS

SCLK

SDIO

R/W

I6

I5

I4

I3

I2

I1

I0

D7

D6

D2

D1

D0

(N)

N

0

SDO

0

N

Figure 33. Serial Register Interface Timing MSB First

INSTRUCTION CYCLE

DATA TRANSFER CYCLE

CS

SCLK

SDIO

I0

I1

I2

I3

I4

I5

I6

R/W

D0

D1

D2

D6

D7

(N)

0

N

SDO

D2

D6

D7

Figure 34. Serial Register Interface Timing LSB First

t_SCLK

t_DS

CS

t_PWH

t_PWL

SCLK

SDIO

t_DS

t_DH

INSTRUCTION BIT 7

INSTRUCTION BIT 6

Figure 35. Timing Diagram for Register Write to AD9775

CS

SCLK

t_DV

SDIO

SDO

DATA BIT N

DATA BIT N–1

Figure 36. Timing Diagram for Register Read from AD9775

Rev. E | Page 23 of 56

AD9775

25

20

15

10

5

DAC OPERATION

The dual, 14-bit DAC output of the AD9775, along with the

reference circuitry, gain, and offset registers, is shown in Figure 37.

Note that an external reference can be used by simply overdriving

the internal reference with the external reference. Referring to the

transfer functions in Equation 1, a reference current is set by the

internal 1.2 V reference, the external R_SETresistor, and the values

in the coarse gain register. The fine gain DAC subtracts a small

amount from this and the result is input to IDAC and QDAC,

where it is scaled by an amount equal to 1024/24. Figure 38 and

Figure 39 show the scaling effect of the coarse and fine adjust

DACs. IDAC and QDAC are PMOS current source arrays,

segmented in a 5-4-5 configuration. The 5 MSBs control an array

of 31 current sources. The next four bits consist of 15 current

sources whose values are all equal to 1/16 of an MSB current

source. The 5 LSBs are binary weighted fractions of the middle

bits’ current sources. All current sources are switched to either

2R MODE

1R MODE

0

5

10

15

20

COARSE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9kΩ)

Figure 38. Coarse Gain Effect on I_FULLSCALE

0

–0.5

–1.0

–1.5

–2.0

–2.5

–3.0

I_OUTAor I_OUTB, depending on the input code.

1R MODE

2R MODE

The fine adjustment of the gain of each channel allows for

improved balance of QAM modulated signals, resulting in

improved modulation accuracy and image rejection.

In the section Interfacing the AD9775 with the AD8345

Quadrature Modulator, the performance data shows to what

degree image rejection can be improved when the AD9775 is

used with an AD8345 quadrature modulator from Analog

Devices, Inc.

AVDD

0

200

400

600

800

1000

FINE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9kΩ)

84μA

REFIO

Figure 39. Fine Gain Effect on I_FULLSCALE

7kΩ

0.7V

Figure 37. Equivalent Internal Reference Circuit

OFFSET

CONTROL

REGISTERS

OFFSET

DAC

FINE

GAIN

DAC

GAIN

CONTROL

REGISTERS

FINE

GAIN

DAC

I

IDAC

OUTA1

OUTB1

1.2VREF

REFIO

0.1μF

COARSE COARSE

QDAC

I

OUTA2

OUTB2

GAIN

DAC

GAIN

DAC

FSADJ1

RSET1

OFFSET

CONTROL

REGISTERS

FSADJ2

OFFSET

DAC

GAIN

CONTROL

RSET2

REGISTERS

Figure 40. DAC Outputs, Reference Current Scaling, and Gain/Offset Adjust

Rev. E | Page 24 of 56

AD9775

0

–10

–20

–30

–40

–50

–60

–70

–80

The offset control defines a small current that can be added to

_OUTAor I_OUTB(not both) on the IDAC and QDAC. The selection

I

of which I_OUTthis offset current is directed toward is programmable

via Register 0x08, Bit 7 (IDAC) and Register 0x0C, Bit 7 (QDAC).

Figure 41 shows the scale of the offset current that can be added

to one of the complementary outputs on the IDAC and QDAC.

Offset control can be used for suppression of LO leakage resulting

from modulation of dc signal components. If the AD9775 is dc-

coupled to an external modulator, this feature can be used to

cancel the output offset on the AD9775 as well as the input offset

on the modulator. Figure 42 shows a typical example of the effect

that the offset control has on LO suppression.

OFFSET REGISTER 1 ADJUSTED

OFFSET REGISTER 2

ADJUSTED, WITH OFFSET

REGISTER 1 SET

TO OPTIMIZED VALUE

–1024 –768

–512

–256

0

256

512

768

1024

In Figure 42, the negative scale represents an offset added to I_OUTB

,

DAC1, DAC2 (OFFSET REGISTER CODES)

while the positive scale represents an offset added to I_OUTAof the

respective DAC. Offset Register 1 corresponds to IDAC, while

Offset Register 2 corresponds to QDAC. Figure 42 represents the

AD9775 synthesizing a complex signal that is then dc-coupled to

an AD8345 quadrature modulator with an LO of 800 MHz. The

dc coupling allows the input offset of the AD8345 to be calibrated

out as well. The LO suppression at the AD8345 output was opti-

mized first by adjusting Offset Register 1 in the AD9775. When

an optimal point was found (roughly Code 54), this code was

held in Offset Register 1, and Offset Register 2 was adjusted. The

resulting LO suppression is 70 dBFS. These are typical numbers;

the specific code for optimization varies from part to part.

Figure 42. Offset Adjust Control, Effect on LO Suppression

CLOCK INPUT CONFIGURATIONS

The clock inputs to the AD9775 can be driven differentially

or single-ended. The internal clock circuitry has supply and

ground (CLKVDD, CLKGND) separate from the other supplies

on the chip to minimize jitter from internal noise sources.

Figure 43 shows the AD9775 driven from a single-ended

clock source. The CLK+/CLK− pins form a differential input

(CLKIN) so that the statically terminated input must be dc-

biased to the midswing voltage level of the clock driven input.

1R/2R MODE

AD9775

In 2R mode, the reference current for each channel is set

independently by the FSADJ resistor on that channel. The

AD9775 can be programmed to derive its reference current

from a single resistor on Pin 60 by placing the part into 1R

mode. The transfer functions in Equation 1 are valid for 2R

mode. In 1R mode, the current developed in the single FSADJ

resistor is split equally between the two channels. The result is

that in 1R mode, a scale factor of 1/2 must be applied to the

formulas in Equation 1. The full-scale DAC current in 1R mode

can still be set to as high as 20 mA by using the internal 1.2 V

reference and a 950 Ω resistor instead of the 1.9 kΩ resistor

typically used in the 2R mode.

R

SERIES

CLK+

CLKVDD

CLK–

V

THRESHOLD

0.1μF

CLKGND

Figure 43. Single-Ended Clock Driving Clock Inputs

A configuration for differentially driving the clock inputs is

given in Figure 44. DC-blocking capacitors can be used to

couple a clock driver output whose voltage swings exceed

CLKVDD or CLKGND. If the driver voltage swings are within

the supply range of the AD9775, the dc-blocking capacitors and

bias resistors are not necessary.

5

4

3

AD9775

1kΩ

0.1μF

CLK+

2R MODE

1kΩ

2

0.1μF

ECL/PECL

CLKVDD

CLK–

1kΩ

1R MODE

1

CLKGND

0

200

400

600

800

1000

COARSE GAIN REGISTER CODE

(ASSUMING RSET1, RSET2 = 1.9kΩ)

Figure 44. Differential Clock Driving Clock Inputs

Figure 41. DAC Output Offset Current

Rev. E | Page 25 of 56

AD9775

A transformer, such as the T1-1T from Mini-Circuits®, can also

be used to convert a single-ended clock to differential. This

method is used on the AD9775 evaluation board so that an external

sine wave with no dc offset can be used as a differential clock.

CLK+ CLK–

PLLVDD

PLL_LOCK

1 = LOCK

0 = NO LOCK

AD9775

PECL/ECL drivers require varying termination networks,

the details of which are left out of Figure 43 and Figure 44 but

can be found in application notes such as AND8020/D from

ON Semiconductor®. These networks depend on the assumed

transmission line impedance and power supply voltage of the

clock driver.

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

PHASE

DETECTOR

CHARGE

PUMP

LPF

2

4

8

1

CLOCK

DISTRIBUTION

CIRCUITRY

PRESCALER

VCO

INPUT

DATA

LATCHES

Optimum performance of the AD9775 is achieved when the

driver is placed very close to the AD9775 clock inputs, thereby

negating any transmission line effects such as reflections due to

mismatch.

PLL DIVIDER

(PRESCALER)

CONTROL

INTERNAL SPI

CONTROL

REGISTERS

INTERPOLATION

RATE

PLL

CONTROL

(PLL ON)

MODULATION

CONTROL

RATE

SPI PORT

CONTROL

The quality of the clock and data input signals is important in

achieving optimum performance. The external clock driver

circuitry should provide the AD9775 with a low jitter clock

input that meets the minimum/maximum logic levels while

providing fast edges. Although fast clock edges help minimize

any jitter that manifests itself as phase noise on a reconstructed

waveform, the high gain bandwidth product of the AD9775

clock input comparator can tolerate differential sine wave

inputs as low as 0.5 V p-p with minimal degradation of the

output noise floor.

Figure 45. PLL and Clock Circuitry with PLL Enabled

CLK+ CLK–

PLL_LOCK

1 = LOCK

0 = NO LOCK

AD9775

INTERPOLATION

FILTERS,

MODULATORS,

AND DACS

PHASE

DETECTOR

CHARGE

PUMP

PROGRAMMABLE PLL

2

4

8

1

CLKIN can function either as an input data rate clock (PLL

enabled) or as a DAC data rate clock (PLL disabled) according

to the state of Address 0x02, Bit 7 in the SPI port register. The

internal operation of the AD9775 clock circuitry in these two

modes is illustrated in Figure 45 and Figure 46.

CLOCK

DISTRIBUTION

CIRCUITRY

PRESCALER

VCO

INPUT

DATA

LATCHES

PLL DIVIDER

(PRESCALER)

CONTROL

INTERNAL SPI

CONTROL

REGISTERS

INTERPOLATION

RATE

CONTROL

PLL

CONTROL

(PLL ON)

MODULATION

RATE

CONTROL

The PLL clock multiplier and distribution circuitry produce the

necessary internal synchronized 1×, 2×, 4×, and 8× clocks for

the rising edge triggered latches, interpolation filters,

modulators, and DACs. This circuitry consists of a phase

detector, charge pump, voltage controlled oscillator (VCO),

prescaler, clock distribution, and SPI port control.

SPI PORT

Figure 46. PLL and Clock Circuitry with PLL Disabled

Table 18. PLL Optimization

Interpolation Divider

Minimum

f_DATA

Maximum

f_DATA

Rate

Setting

The charge pump, VCO, differential clock input buffer, phase

detector, prescaler, and clock distribution are all powered from

CLKVDD. PLL lock status is indicated by the logic signal at the

DATACLK_PLL_LOCK pin, as well as by the status of Bit 1,

Register 0x00. To ensure optimum phase noise performance

from the PLL clock multiplier and distribution, CLKVDD

should originate from a clean analog supply. Table 18 defines

the minimum input data rates vs. the interpolation and PLL

divider setting. If the input data rate drops below the defined

minimum under these conditions, VCO noise may increase

significantly. The VCO speed is a function of the input data

rate, the interpolation rate, and the VCO prescaler, according to

the following function:

1

2

4

8

1

2

4

8

1

2

4

8

1

2

4

8

1

2

4

8

32

16

8

160

112

56

160

112

56

28

100

56

28

14

50

28

14

7

4

24

12

6

3

24

12

6

3

24

12

6

VCO Speed (MHz) =

Input Data Rate (MHz) × Interpolation Rate × Prescaler

3

Rev. E | Page 26 of 56

AD9775

In addition, if the zero-stuffing option is enabled, the VCO

doubles its speed again. Phase noise may be slightly higher with

the PLL enabled. Figure 47 illustrates typical phase noise perform-

ance of the AD9775 with 2× interpolation and various input

data rates. The signal synthesized for the phase noise measurement

was a single carrier at a frequency of f_DATA/4. The repetitive

nature of this signal eliminates quantization noise and distortion

spurs as a factor in the measurement. Although the curves blend

together in Figure 47, the different conditions are given for clarity

in Table 19. Figure 47 also contains a table detailing the maximum

and minimum f_DATArates for each combination of interpolation

rate and PLL divider setting. These rates are guaranteed over

the entire supply and operating temperature range. Figure 48

shows typical performance of the PLL lock signal (Pin 8 or

Pin 53) when the PLL is in the process of locking.

It is important to note that the resistor/capacitor needed for the

PLL loop filter is internal on the AD9775. This suffices unless the

input data rate is below 10 MHz, in which case an external series

RC is required between the LPF pin and CLKVDD pins.

POWER DISSIPATION

The AD9775 has three voltage supplies: DVDD, AVDD, and

CLKVDD. Figure 49 through Figure 51 show the current

required from each of these supplies when each is set to the 3.3 V

nominal specified for the AD9775. Power dissipation (P_D) can

easily be extracted by multiplying the given curves by 3.3. As

Figure 49 shows, I_DVDDis very dependent on the input data rate,

the interpolation rate, and the activation of the internal digital

modulator. I_DVDD, however, is relatively insensitive to the

modulation rate by itself. In Figure 50, I_AVDDshows the same type

of sensitivity to the data, the interpolation rate, and the modu-

lator function but to a much lesser degree (<10ꢀ). In Figure 51,

Table 19. Required PLL Prescaler Ratio vs. f_DATA

f_DATA

PLL

Prescaler Ratio

I_CLKVDDvaries over a wide range yet is responsible for only a small

125 MSPS

100 MSPS

75 MSPS

50 MSPS

0

Disabled

Enabled

percentage of the overall AD9775 supply current requirements.

Div 1

Div 2

Div 4

400

8×, (MOD. ON)

2

×

, (MOD. ON)

350

300

250

200

150

100

50

4×, (MOD. ON)

8×

4×

–10

2

×

–20

–30

–40

–50

1×

–60

–70

0

–80

0

50

100

f_DATA(MHz)

150

200

–90

–100

Figure 49. I_DVDDvs. f_DATAvs. Interpolation Rate, PLL Disabled

–110

0

1

2

3

4

5

76.0

75.5

75.0

74.5

74.0

73.5

73.0

72.5

72.0

FREQUENCY OFFSET (MHz)

4×, (MOD. ON)

8×, (MOD. ON)

Figure 47. Phase Noise Performance

2×, (MOD. ON)

4×

8

×

2

×

1

×

0

50

100

f_DATA(MHz)

150

200

Figure 50. I_AVDDvs. f_DATAvs. Interpolation Rate, PLL Disabled

Figure 48. PLL_LOCK Output Signal (Pin 8) in the Process of Locking

(Typical Lock Time)

Rev. E | Page 27 of 56

AD9775

35

30

25

20

15

10

5

PLL On (Register 4, Bit 7 = 1)

8

×

Register 3, Bit 7 = 0, Register 1, Bit 0 = 0; PLL lock indicator out

of Pin 8.

Register 3, Bit 7 = 1, Register 1, Bit 0 = 0; PLL lock indicator out

of Pin 53.

Register 3, Bit 7 = 0, Register 1, Bit 0 = 1; DATACLK out of Pin 8.

Register 3, Bit 7 = 1, Register 1, Bit 0 = 1; DATACLK out of Pin 53.

4

×

2

×

1

×

In one-port mode, P2B14 and P2B15 from Input Data Port 2

are redefined as IQSEL and ONEPORTCLK, respectively. The

input data in one-port mode is steered to one of the two inter-

nal data channels based on the logic level of IQSEL. A clock

signal, ONEPORTCLK, is generated by the AD9775 in this

mode for the purpose of data synchronization. ONEPORTCLK

runs at the input interleaved data rate, which is 2× the data rate

at the internal input to either channel.

0

50

100

150

200

f_DATA(MHz)

Figure 51 I_CLKVDDvs. f_DATAvs. Interpolation Rate, PLL Disabled

Figure 101 through Figure 104 illustrate the test configurations

showing the various clocks that are required and generated by

the AD9775 with the PLL enabled/disabled and in the one-

port/two-port modes. Jumper positions needed to operate the

AD9775 evaluation board in these modes are given as well.

SLEEP/POWER-DOWN MODES

(Control Register 0x00, Bit 3 and Bit 4)

The AD9775 provides two methods for programmable

reduction in power savings. The sleep mode, when activated,

turns off the DAC output currents but the rest of the chip

remains functioning. When coming out of sleep mode, the

AD9775 immediately returns to full operation. Power-down

mode, on the other hand, turns off all analog and digital

circuitry in the AD9775 except for the SPI port. When

returning from power-down mode, enough clock cycles must

be allowed to flush the digital filters of random data acquired

during the power-down cycle.

PLL ENABLED, TWO-PORT MODE

(Control Register 0x02, Bit 6 to Bit 0 and

Control Register 0x04, Bit 7 to Bit 1)

With the phase-locked loop (PLL) enabled and the AD9775 in

two-port mode, the speed of CLKIN is inherently that of the

input data rate. In two-port mode, Pin 8 (DATACLK/PLL_

LOCK) can be programmed (Control Register 0x01, Bit 0) to

function as either a lock indicator for the internal PLL or as a

clock running at the input data rate. When Pin 8 is used as a

clock output (DATACLK), its frequency is equal to that of

CLKIN. Data at the input ports is latched into the AD9775 on

TWO-PORT DATA INPUT MODE

The digital data input ports can be configured as two independ-

ent ports or as a single (one-port mode) port. In two-port mode,

data at the two input ports is latched into the AD9775 on every

rising edge of the data rate clock (DATACLK). Also, in two-port

mode, the AD9775 can be programmed to generate an externally

available DATACLK for the purpose of data synchronization.

the rising edge of the CLKIN. Figure 52 shows the delay, t_OD

,

inherent between the rising edge of CLKIN and the rising edge

of DATACLK, as well as the setup and hold requirements for

the data at Ports 1 and 2. The setup and hold times given in

Figure 52 are the input data transitions with respect to CLKIN.

Note that in two-port mode (PLL enabled or disabled), the data

rate at the interpolation filter inputs is the same as the input

data rate at Port 1 and Port 2.

This data rate clock can be programmed to be available at either

Pin 8 (DATACLK/PLL_LOCK) or Pin 53 (SPI_SDO). Because

Pin 8 can also function as a PLL lock indicator when the PLL is

enabled, there are several options for configuring Pin 8 and

Pin 53. The following sections describe the options.

The DAC output sample rate in two-port mode is equal to the

clock input rate multiplied by the interpolation rate. If zero

stuffing is used, another factor of 2 must be included to

calculate the DAC sample rate.

PLL Off (Register 4, Bit 7 = 0)

Register 3, Bit 7 = 0; DATACLK out of Pin 8.

Register 3, Bit 7 = 1; DATACLK out of Pin 53.

Rev. E | Page 28 of 56

AD9775

DATACLK INVERSION

PLL ENABLED, ONE-PORT MODE

(Control Register 0x02, Bit 4)

(Control Register 0x02, Bit 6 to Bit 1 and

Control Register 0x04, Bit 7 to Bit 1)

By programming this bit, the DATACLK signal shown in

Figure 52 can be inverted. With inversion enabled, t_ODrefers to

the time between the rising edge of CLKIN and the falling edge

of DATACLK. No other effect on timing occurs.

In one-port mode, the I and Q channels receive their data from an

interleaved stream at digital input Port 1. The function of Pin 32 is

defined as an output (ONEPORTCLK) that generates a clock at the

interleaved data rate, which is 2× the internal input data rate of the I

and Q channels. The frequency of CLKIN is equal to the internal

input data rate of the I and Q channels. The selection of the data for

the I or the Q channel is determined by the state of the logic level at

Pin 31 (IQSEL when the AD9775 is in one-port mode) on the

rising edge of ONEPORTCLK. Under these conditions, IQSEL = 0

latches the data into the I channel on the clock rising edge, while

IQSEL = 1 latches the data into the Q channel. It is possible to

invert the I and Q selection by setting Control Register 0x02, Bit 1

to the invert state (Logic 1). Figure 54 illustrates the timing

t_OD

CLKIN

DATACLK

requirements for the data inputs as well as the IQSEL input. Note

that the 1× interpolation rate is not available in the one-port mode.

DATA AT PORTS

1 AND 2

The DAC output sample rate in one-port mode is equal to

CLKIN multiplied by the interpolation rate. If zero stuffing is

used, another factor of 2 must be included to calculate the DAC

sample rate.

t_OD= 1.5ns (MIN) TO 2.5ns (MAX)

t_S= 0.0ns (MIN)

t_H= 2.5ns (MIN)

t_St_H

Figure 52. Timing Requirements in Two-Port Input Mode, with PLL Enabled

ONEPORTCLK INVERSION

(Control Register 0x02, Bit 2)

DATACLK DRIVER STRENGTH

(Control Register 0x02, Bit 5)

By programming this bit, the ONEPORTCLK signal shown in

Figure 54 can be inverted. With inversion enabled, t_ODrefers to

the delay between the rising edge of the external clock and the

falling edge of ONEPORTCLK. The setup and hold times, t_S

and t_H, are with respect to the falling edge of ONEPORTCLK.

There is no other effect on timing.

The DATACLK output driver strength is capable of driving

>10 mA into a 330 Ω load while providing a rise time of 3 ns.

Figure 53 shows DATACLK driving a 330 ꢀ resistive load at a

frequency of 50 MHz. By enabling the drive strength option

(Control Register 0x02, Bit 5), the amplitude of DATACLK

under these conditions increases by approximately 200 mV.

t_OD

3.0

2.5

2.0

1.5

1.0

0.5

t_OD= 4.0ns (MIN)

TO 5.5ns (MAX)

CLKIN

t_S= 3.0ns (MIN)

t_H= –0.5ns (MIN)

t_IQS= 3.5ns (MIN)

t_IQH= –1.5ns (MIN)

ONEPORTCLK

I AND Q INTERLEAVED

INPUT DATA AT PORT 1

0

DELTA APPROX. 2.8ns

–0.5

0

10

20

30

40

50

t_St_H

TIME (ns)

Figure 53. DATACLK Driver Capability into 330 Ω at 50 MHz

IQSEL

t_IQS

t_IQH

Figure 54. Timing Requirements in One-Port

Input Mode with the PLL Enabled

Rev. E | Page 29 of 56

AD9775

t_OD

ONEPORTCLK DRIVER STRENGTH

The drive capability of ONEPORTCLK is identical to that of

DATACLK in the two-port mode. Refer to Figure 53 for

performance under load conditions.

CLKIN

IQ PAIRING

(Control Register 0x02, Bit 0)

DATACLK

In one-port mode, the interleaved data is latched into the

AD9775 internal I and Q channels in pairs. The order of how

the pairs are latched internally is defined by this control register.

The following is an example of the effect that this has on

incoming interleaved data.

DATA AT PORTS

1 AND 2

t_OD= 6.5ns (MIN) TO 8.0ns (MAX)

t_S= 5.0ns (MIN)

t_S

t_H

Given the following interleaved data stream, where the data

indicates the value with respect to full scale:

t_H= –3.2ns (MIN)

Figure 55. Timing Requirements in Two-Port Input Mode with PLL Disabled

Table 20.

t_OD

I

Q

I

Q

1

I

Q

I

Q

0

I

Q

0.5

1

0.5

0

0.5

CLKIN

With the control register set to 0 (I first), the data appears at the

internal channel inputs in the following order in time:

Table 21.

I Channel

0.5

1

0.5

0

0.5

ONEPORTCLK

Q Channel

With the control register set to 1 (Q first), the data appears at

the internal channel inputs in the following order in time:

Table 22.

I Channel

I AND Q INTERLEAVED

INPUT DATA AT PORT 1

0.5

y

1

0.5

1

0

0.5

0

x

Q Channel

0.5

t_St_H

The values x and y represent the next I value and the previous

Q value in the series.

IQSEL

t_OD= 4.0ns (MIN)

TO 5.5ns (MAX)

PLL DISABLED, TWO-PORT MODE

t_S= 3.0ns (MIN)

With the PLL disabled, a clock at the DAC output rate must be

applied to CLKIN. Internal clock dividers in the AD9775

synthesize the DATACLK signal at Pin 8, which runs at the

input data rate and can be used to synchronize the input data.

Data is latched into input Port 1 and Port 2 of the AD9775 on

the rising edge of DATACLK. DATACLK speed is defined as the

speed of CLKIN divided by the interpolation rate. With zero

stuffing enabled, this division increases by a factor of 2. Figure 55

illustrates the delay between the rising edge of CLKIN and the

rising edge of DATACLK, as well as t_Sand t_Hin this mode.

t_IQS

t_IQH

t_H= –1.0ns (MIN)

t_IQS= 3.5ns (MIN)

t_IQH= –1.5ns (MIN)

Figure 56. Timing Requirements in One-Port Input Mode with PLL Disabled

PLL DISABLED, ONE-PORT MODE

In one-port mode, data is received into the AD9775 as an

interleaved stream on Port 1. A clock signal (ONEPORTCLK)

running at the interleaved data rate, which is 2× the input data

rate of the internal I and Q channels, is available for data

synchronization at Pin 32.

The programmable modes DATACLK inversion and DATACLK

driver strength described in the previous section (PLL Enabled,

Two-Port Mode) have identical functionality with the PLL

disabled.

With PLL disabled, a clock at the DAC output rate must be

applied to CLKIN. Internal dividers synthesize the

ONEPORTCLK signal at Pin 32. The selection of the data for

the I or Q channel is determined by the state of the logic level

applied to Pin 31 (IQSEL when the AD9775 is in one-port

mode) on the rising edge of ONEPORTCLK. Under these

conditions, IQSEL = 0 latches the data into the I channel on the

clock rising edge, while IQSEL = 1 latches the data into the Q

channel.

The data rate clock created by dividing down the DAC clock in

this mode can be programmed (via Register 0x03, Bit 7) to be

output from the SPI_SDO pin rather than the DATACLK/

PLL_LOCK pin. In some applications, this may improve

complex image rejection. When SPI_SDO is used as data rate

clock out, t_ODincreases by 1.6 ns.

Rev. E | Page 30 of 56

AD9775

It is possible to invert the I and Q selection by setting control

Register 0x02, Bit 1 to the invert state (Logic 1). Figure 56

illustrates the timing requirements for the data inputs as well as

the IQSEL input. Note that the 1× interpolation rate is not

available in the one-port mode.

frequency images. This is shown graphically in the frequency

domain in Figure 57.

–jωt

e

/2j

SINE

DC

–jωt

One-port mode is very useful when interfacing with devices

such as the Analog Devices AD6622 or AD6623 transmit signal

processors, in which two digital data channels have been

interleaved (multiplexed).

e

/2j

–jωt

/2

–jωt

e

/2

COSINE

The programmable modes’ ONEPORTCLK inversion,

ONEPORTCLK driver strength, and IQ pairing described in

the PLL Enabled, One-Port Mode section have identical

functionality with the PLL disabled.

DC

Figure 57. Real and Imaginary Components of

Sinusoidal and Cosinusoidal Waveforms

Amplitude modulating a baseband signal with a sine or a cosine

convolves the baseband signal with the modulating carrier in

the frequency domain. Amplitude scaling of the modulated

signal reduces the positive and negative frequency images by a

factor of 2.

DIGITAL FILTER MODES

The I and Q datapaths of the AD9775 have their own

independent half-band FIR filters. Each datapath consists of

three FIR filters, providing up to 8× interpolation for each

channel. The rate of interpolation is determined by the state of

Control Register 0x01, Bit 7 and Bit 6. Figure 2 to Figure 4 show

the response of the digital filters when the AD9775 is set to 2×,

4×, and 8× modes. The frequency axes of these graphs are

normalized to the input data rate of the DAC. As the graphs

show, the digital filters can provide greater than 75 dB of

out-of-band rejection.

This scaling is very important in the discussion of the various

modulation modes. The phase relationship of the modulated

signals is dependent on whether the modulating carrier is

sinusoidal or cosinusoidal, again with respect to the reference

point of the viewer. Examples of sine and cosine modulation are

given in Figure 58.

–jωt

Ae

/2j

An online tool is available for quick and easy analysis of the

AD9775 interpolation filters in the various modes. The link can

be accessed at www.analog.com/ad9777image.

SINUSOIDAL

MODULATION

DC

AMPLITUDE MODULATION

–jωt

Ae

/2j

/2

Given two sine waves at the same frequency, but with a

90 degree phase difference, a point of view in time can be taken

such that the waveform that leads in phase is cosinusoidal and

the waveform that lags is sinusoidal. Analysis of complex

variables states that the cosine waveform can be defined as

having real positive and negative frequency components, while

the sine waveform consists of imaginary positive and negative

–jωt

Ae

/2

COSINUSOIDAL

MODULATION

DC

Figure 58. Baseband Signal, Amplitude Modulated

with Sine and Cosine Carriers

Rev. E | Page 31 of 56

AD9775

domain spectrum to the DAC sin(x)/x roll-off, an estimate can

be made for the characteristics required for the DAC recon-

struction filter.

MODULATION, NO INTERPOLATION

With Control Register 0x01, Bit 7 and Bit 6 set to 00, the

interpolation function on the AD9775 is disabled. Figure 59

through Figure 62 show the DAC output spectral characteristics

of the AD9775 in the various modulation modes, all with the

interpolation filters disabled. The modulation frequency is

determined by the state of Control Register 0x01, Bit 5 and Bit 4.

The tall rectangles represent the digital domain spectrum of a

baseband signal of narrow bandwidth. By comparing the digital

Note also, per the previous discussion on amplitude

modulation, that the spectral components (where modulation is

set to f_S/4 or f_S/8) are scaled by a factor of 2. In the situation

where the modulation is f_S/2, the modulated spectral

components add constructively, and there is no

scaling effect.

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation Disabled

0

–20

–40

–60

–80

–40

–60

–80

–100

0

0.2

0.4

0.6

0.8

1.0

0

0.2

0.4

0.6

0.8

1.0

f_OUT

(×

f_DATA

)

f_OUT

(×f_DATA)

Figure 59. No Interpolation, Modulation Disabled

Figure 61. No Interpolation, Modulation = f_DAC/4

0

–20

–40

0

–20

–40

–60

–80

–100

0

0.2

0.4

f_OUT

0.6

f_DATA

0.8

1.0

0

0.2

0.4

f_OUT

0.6

f_DATA

0.8

1.0

(×

)

(×

)

Figure 60. No Interpolation, Modulation = f_DAC/2

Figure 62. No Interpolation, Modulation = f_DAC/8

Rev. E | Page 32 of 56

AD9775

MODULATION, INTERPOLATION = 2×

With Control Register 0x01, Bit 7 and Bit 6 set to 01, the

interpolation rate of the AD9775 is 2×. Modulation is achieved

by multiplying successive samples at the interpolation filter

output by the sequence (+1, −1). Figure 63 through Figure 66

represent the spectral response of the AD9775 DAC output with

2× interpolation in the various modulation modes to a narrow-

band baseband signal (the tall rectangles in the graphic). The

advantage of interpolation becomes clear in Figure 63 through

Figure 66, where the images that would normally appear in the

spectrum around the input data rate frequency are suppressed

by >70 dB.

Another significant point is that the interpolation filtering is

done previous to the digital modulator. For this reason, as

Figure 63 through Figure 66 show, the pass band of the

interpolation filters can be frequency shifted, giving the equivalent

of a high-pass digital filter.

Note that when using the f_S/4 modulation mode, there is no

true stop band as the band edges coincide with each other. In

the f_S/8 modulation mode, amplitude scaling occurs over only a

portion of the digital filter pass band due to constructive

addition over just that section of the band.

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 2×

0

–20

–40

–60

–80

–40

–60

–80

–100

0

0.5

1.0

f_OUT(×f_DATA

1.5

2.0

0

0.5

1.0

f_OUT(×f_DATA

1.5

2.0

)

Figure 63. 2× Interpolation, Modulation = Disabled

Figure 65. 2× Interpolation, Modulation = f_DAC/4

0

–20

–40

–60

–80

–40

–60

–80

–100

0

0.5

1.0

f_OUT(×f_DATA

1.5

2.0

0

0.5

1.0

f_OUT(×f_DATA

1.5

2.0

)

Figure 64. 2× Interpolation, Modulation = f_DAC/2

Figure 66. 2× Interpolation, Modulation = f_DAC/8

Rev. E | Page 33 of 56

AD9775

MODULATION, INTERPOLATION = 4×

With Control Register 0x01, Bit 7 and Bit 6 set to 10, the

interpolation rate of the AD9775 is 4×. Modulation is achieved

by multiplying successive samples at the interpolation filter

output by the sequence (0, +1, 0, −1).

Figure 67 through Figure 70 represent the spectral response of

the AD9775 DAC output with 4× interpolation in the various

modulation modes to a narrow-band baseband signal.

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 4×

0

–20

–40

–60

–80

–40

–60

–80

–100

0

1

2

3

4

0

1

2

3

4

f_OUT(×f_DATA

)

f_OUT(×f_DATA)

Figure 67. 4× Interpolation, Modulation Disabled

Figure 69. 4× Interpolation, Modulation = f_DAC/2

0

–20

–40

–60

–80

–40

–60

–80

–100

0

1

2

3

4

0

1

2

3

4

f_OUT(×f_DATA

)

f_OUT(×f_DATA

)

Figure 70. 4× Interpolation, Modulation = f_DAC/8

Figure 68. 4× Interpolation, Modulation = f_DAC/4

Rev. E | Page 34 of 56

AD9775

MODULATION, INTERPOLATION = 8×

With Control Register 0x01, Bit 7 and Bit 6 set to 11, the

interpolation rate of the AD9775 is 8×. Modulation is achieved

by multiplying successive samples at the interpolation filter

output by the sequence (0, +0.707, +1, +0.707, 0, −0.707, −1,

+0.707). Figure 71 through Figure 74 represent the spectral

response of the AD9775 DAC output with 8× interpolation in the

various modulation modes to a narrow-band baseband signal.

Looking at Figure 63 through Figure 74, the user can see how

higher interpolation rates reduce the complexity of the recon-

struction filter needed at the DAC output. It also becomes

apparent that the ability to modulate by f_S/2, f_S/4, or f_S/8 adds a

degree of flexibility in frequency planning.

The Effects of the Digital Modulation on the DAC Output Spectrum, Interpolation = 8×

0

–20

–40

–60

–40

–60

–80

–100

0

1

2

3

4

5

6

7

8

0

1

2

3

4

f_OUT(×f_DATA

)

f_OUT(×f_DATA

)

Figure 73. 8× Interpolation, Modulation = f_DAC/4

Figure 71. 8× Interpolation, Modulation Disabled

0

–20

–40

–60

–40

–60

–80

–100

0

1

2

3

4

5

6

7

8

0

1

2

3

4

f_OUT(×f_DATA

)

f_OUT(×f_DATA

)

Figure 74. 8× Interpolation, Modulation = f_DAC/8

Figure 72. 8× Interpolation, Modulation = f_DAC/2

Rev. E | Page 35 of 56

AD9775

Note that the zero-stuffing option by itself does not change the

location of the images but rather their amplitude, pass-band

flatness, and relative weighting. For instance, in the previous

example, the pass-band amplitude flatness of the image at

3 × f_DATA/4 improved to +0.59 dB while the signal level increased

slightly from −10.5 dBFS to −8.1 dBFS.

ZERO STUFFING

(Control Register 0x01, Bit 3)

As shown in Figure 75, a 0 or null in the output frequency

response of the DAC (after interpolation, modulation, and DAC

reconstruction) occurs at the final DAC sample rate (f_DAC). This

is due to the inherent sin(x)/x roll-off response in the digital-to-

analog conversion. In applications where the desired frequency

content is below f_DAC/2, this may not be a problem. Note that at

INTERPOLATING (COMPLEX MIX MODE)

(Control Register 0x01, Bit 2)

f

_DAC/2 the loss due to sin(x)/x is 4 dB. In direct RF applications,

In the complex mix mode, the two digital modulators on the

AD9775 are coupled to provide a complex modulation function.

In conjunction with an external quadrature modulator, this

complex modulation can be used to realize a transmit image

rejection architecture. The complex modulation function can be

programmed for e^+jωtor e^−jωtto give upper or lower image

rejection. As in the real modulation mode, the modulation

frequency ω can be programmed via the SPI port for f_DAC/2,

this roll-off may be problematic due to the increased pass-band

amplitude variation as well as the reduced amplitude of the

desired signal.

Consider an application where the digital data into the AD9775

represents a baseband signal around f_DAC/4 with a pass band of

f_DAC/10. The reconstructed signal out of the AD9775 would

experience only a 0.75 dB amplitude variation over its pass band.

However, the image of the same signal occurring at 3 × f_DAC/4

suffers from a pass-band flatness variation of 3.93 dB. This image

may be the desired signal in an IF application using one of the

various modulation modes in the AD9775. This roll-off of image

frequencies can be seen in Figure 59 to Figure 74, where the effect

of the interpolation and modulation rate is apparent as well.

f

_DAC/4, and f_DAC/8, where f_DACrepresents the DAC output rate.

OPERATIONS ON COMPLEX SIGNALS

Truly complex signals cannot be realized outside of a computer

simulation. However, two data channels, both consisting of real

data, can be defined as the real and imaginary components of a

complex signal. I (real) and Q (imaginary) datapaths are often

defined this way. By using the architecture defined in Figure 76,

a system can be realized that operates on complex signals,

giving a complex (real and imaginary) output.

10

ZERO STUFFING

ENABLED

0

If a complex modulation function (e^+jωt) is desired, the real and

imaginary components of the system correspond to the real and

imaginary components of e^+jωtor cosωt and sinωt. As Figure 77

shows, the complex modulation function can be realized by

applying these components to the structure of the complex

system defined in Figure 76.

–10

–20

ZERO STUFFING

–30

DISABLED

–40

a(t)

c(t) × b(t) + d × b(t)

INPUT

OUTPUT

–50

COMPLEX FILTER

= (c + jd)

0

0.5

1.0

1.5

2.0

f_OUT, NORMALIZED TO f_DATAWITH ZERO STUFFING DISABLED (Hz)

IMAGINARY

b(t)

INPUT

OUTPUT

b(t) × a(t) + c × b(t)

Figure 75. Effect of Zero Stuffing on DAC’s sin(x)/x Response

Figure 76. Realization of a Complex System

To improve upon the pass-band flatness of the desired image,

the zero stuffing mode can be enabled by setting the control

register bit to Logic 1. This option increases the ratio of

INPUT

(REAL)

OUTPUT

(REAL)

INPUT

f

_DAC/f_DATAby a factor of 2 by doubling the DAC sample rate and

(IMAGINARY)

inserting a midscale sample (that is, 1000 0000 0000 0000) after

every data sample originating from the interpolation filter. This

is important as it affects the PLL divider ratio needed to keep

the VCO within its optimum speed range. Note that the zero

stuffing takes place in the digital signal chain at the output of

the digital modulator before the DAC.

90°

OUTPUT

(IMAGINARY)

The net effect is to increase the DAC output sample rate by a

factor of 2× with the 0 in the sin(x)/x DAC transfer function

occurring at twice the original frequency. A 6 dB loss in

amplitude at low frequencies is also evident (see Figure 75).

–jωt

e

= COSωt + jSINωt

Figure 77. Implementation of a Complex Modulator

Rev. E | Page 36 of 56

AD9775

the baseband real and imaginary channels, now modulated onto

orthogonal (cosine and negative sine) carriers at the transmit

frequency. It is important to remember that in this application

(two baseband data channels) the image rejection is not

dependent on the data at either of the AD9775 input channels.

In fact, image rejection still occurs with either one or both of

the AD9775 input channels active. Note that by changing the

sign of the sinusoidal multiplying term in the complex

modulator, the upper sideband image could have been

suppressed while passing the lower one. This is easily done in

the AD9775 by selecting the e^+jωtbit (Register 0x01, Bit 1). In

purely complex terms, Figure 79 represents the two-stage

upconversion from complex baseband to carrier.

COMPLEX MODULATION AND IMAGE REJECTION

OF BASEBAND SIGNALS

In traditional transmit applications, a two-step upconversion is

done in which a baseband signal is modulated by one carrier to

an intermediate frequency (IF) and then modulated a second

time to the transmit frequency. Although this approach has

several benefits, a major drawback is that two images are

created near the transmit frequency. Only one image is needed,

the other being an exact duplicate. Unless the unwanted image

is filtered, typically with analog components, transmit power is

wasted and the usable bandwidth available in the system is reduced.

A more efficient method of suppressing the unwanted image

can be achieved by using a complex modulator followed by a

quadrature modulator. Figure 78 is a block diagram of a

quadrature modulator. Note that it is in fact the real output half

of a complex modulator. The complete upconversion can

actually be referred to as two complex upconversion stages, the

real output of which becomes the transmitted signal.

INPUT

(REAL)

OUTPUT

INPUT

(IMAGINARY)

SINωt

90°

COSωt

The entire upconversion, from baseband to transmit frequency,

is represented graphically in Figure 79. The resulting spectrum

shown in Figure 79 represents the complex data consisting of

Figure 78. Quadrature Modulator

REAL CHANNEL (OUT)

A/2 A/2

1

–F

F

C

REAL CHANNEL (IN)

A

–B/2J

B/2J

DC

–F

C

F

C

COMPLEX

MODULATOR

TO QUADRATURE

MODULATOR

IMAGINARY CHANNEL (OUT)

–A/2J A/2J

IMAGINARY CHANNEL (IN)

–F

C

B

DC

B/2

–F

F

C

A/4 + B/4J A/4 – B/4J

2

–F

F

Q

–F – F

–F + F

F

– F

F + F

Q C

Q

C

Q

C

Q

C

OUT

REAL

–A/4 – B/4J A/4 – B/4J

A/4 + B/4J –A/4 + B/4J

QUADRATURE

MODULATOR

–F

F

Q

IMAGINARY

REJECTED IMAGES

A/2 + B/2J

A/2 – B/2J

–F

F

Q

1

2

F

= COMPLEX MODULATION FREQUENCY

= QUADRATURE MODULATION FREQUENCY

C

Q

Figure 79. Two-Stage Upconversion and Resulting Image Rejection

Rev. E | Page 37 of 56

AD9775

data on any channel. Image rejection on a channel occurs if

either the real or imaginary data, or both, is present on the

baseband channel.

IMAGE REJECTION AND SIDEBAND SUPPRESSION

OF MODULATED CARRIERS

As shown in Figure 79, image rejection can be achieved by

applying baseband data to the AD9775 and following the

AD9775 with a quadrature modulator. To process multiple

carriers while still maintaining image reject capability, each

carrier must be complex modulated. As Figure 80 shows, single

or multiple complex modulators can be used to synthesize

complex carriers. These complex carriers are then summed and

applied to the real and imaginary inputs of the AD9775.

It is important to remember that the magnitude of a complex

signal can be 1.414× the magnitude of its real or imaginary

components. Due to this 3 dB increase in signal amplitude, the

real and imaginary inputs to the AD9775 must be kept at least

3 dB below full scale when operating with the complex modu-

lator. Overranging in the complex modulator results in severe

distortion at the DAC output.

COMPLEX BASEBAND

SIGNAL

A system in which multiple baseband signals are complex

modulated and then applied to the AD9775 real and imaginary

inputs followed by a quadrature modulator is shown in Figure 82,

which also describes the transfer function of this system and the

spectral output. Note the similarity of the transfer functions

given in Figure 82 and Figure 80. Figure 82 adds an additional

complex modulator stage for the purpose of summing multiple

carriers at the AD9775 inputs. Also, as in Figure 79, the image

rejection is not dependent on the real or imaginary baseband

1

j(ω1 + ω2)t

×

OUTPUT = REAL

1/2

e

1/2

= REAL

–ω1 – ω2

DC

ω1 + ω2

FREQUENCY

Figure 80. Two-Stage Complex Upconversion

BASEBAND CHANNEL 1

R(1)

REAL INPUT

COMPLEX

MULTICARRIER

REAL OUTPUT =

R(1) + R(2) + . . .R(N)

(TO REAL INPUT OF AD9775)

MODULATOR 1

R(1)

IMAGINARY INPUT

BASEBAND CHANNEL 2

REAL INPUT

R(2)

COMPLEX

MODULATOR 2

MULTICARRIER

IMAGINARY OUTPUT =

I(1) + I(2) + . . .I(N)

IMAGINARY INPUT

(TO IMAGINARY INPUT OF AD9775)

R(N) = REAL OUTPUT OF N

I(N) = IMAGINARY OUTPUT OF N

BASEBAND CHANNEL N

REAL INPUT

R(N)

COMPLEX

MODULATOR N

IMAGINARY INPUT

Figure 81. Synthesis of Multicarrier Complex Signal

MULTIPLE

BASEBAND

CHANNELS

REAL

MULTIPLE

COMPLEX

MODULATORS

AD9775

COMPLEX

MODULATOR

FREQUENCY = ω

QUADRATURE

MODULATOR

FREQUENCY = ω

IMAGINARY

Q

FREQUENCY = ω , ω ...ω

1

2

N

C

COMPLEX BASEBAND

SIGNAL

×

OUTPUT = REAL

j(ω + ω + ω )t

e

N

C

Q

–ω – ω – ω

ω

+ ω + ω

Q

DC

REJECTED IMAGES

1

C

Q

1

C

Figure 82. Image Rejection with Multicarrier Signals

Rev. E | Page 38 of 56

AD9775

The complex carrier synthesized in the AD9775 digital

the high end of the DAC output spectrum in these graphs is the

modulator is accomplished by creating two real digital carriers

in quadrature. Carriers in quadrature cannot be created with

the modulator running at f_DAC/2. As a result, complex modula-

tion only functions with modulation rates of f_DAC/4 and f_DAC/8.

first null point for the sin(x)/x roll-off, and the asymmetry of the

DAC output images is representative of the sin(x)/x roll-off over the

spectrum. The internal PLL was enabled for these results. In

addition, a 35 MHz third-order low-pass filter was used at the

AD9775/AD8345 interface to suppress DAC images.

Regions A and B of Figure 83 to Figure 88 are the result of the

complex signal described previously, when complex modulated

in the AD9775 by +e^jωt. Regions C and D are the result of the

complex signal described previously, again with positive

frequency components only, modulated in the AD9775 by –e^jωt.

The analog quadrature modulator after the AD9775 inherently

modulates by +e^jωt.

An important point can be made by looking at Figure 91 and

Figure 93. Figure 91 represents a group of positive frequencies

modulated by complex +fDAC/4, while Figure 93 represents a

group of negative frequencies modulated by complex −fDAC/4.

When looking at the real or imaginary outputs of the AD9775,

as shown in Figure 91 and Figure 93, the results look identical.

However, the spectrum analyzer cannot show the phase

relationship of these signals. The difference in phase between

the two signals becomes apparent when they are applied to the

AD8345 quadrature modulator, with the results shown in

Figure 92 and Figure 94.

Region A

Region A is a direct result of the upconversion of the complex

signal near baseband. If viewed as a complex signal, only the

images in Region A remain. The complex Signal A, consisting

of positive frequency components only in the digital domain,

has images in the positive odd Nyquist zones (1, 3, 5, …), as

well as images in the negative even Nyquist zones. The

appearance and rejection of images in every other Nyquist zone

becomes more apparent at the output of the quadrature

modulator. The A images appear on the real and the imaginary

outputs of the AD9775, as well as on the output of the quadrature

modulator, where the center of the spectral plot now represents

the quadrature modulator LO, and the horizontal scale now

represents the frequency offset from this LO.

0

–20

D

A

B

C

D

A

B

C

–40

–60

–80

Region B

Region B is the image (complex conjugate) of Region A. If a

spectrum analyzer is used to view the real or imaginary DAC

outputs of the AD9775, Region B appears in the spectrum.

However, on the output of the quadrature modulator, Region B

is rejected.

–100

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

(LO)

f_OUT(×f_DATA

)

Figure 83. 2× Interpolation, Complex f_DAC/4 Modulation

Region C

Region C is most accurately described as a downconversion, as

the modulating carrier is –e^jωt. If viewed as a complex signal, only

the images in Region C remain. This image appears on the real

and imaginary outputs of the AD9775, as well as on the output of

the quadrature modulator, where the center of the spectral plot

now represents the quadrature modulator LO and the horizontal

scale represents the frequency offset from this LO.

0

–20

–40

–60

–80

D

A

B

C

D

A

B

C

Region D

Region D is the image (complex conjugate) of Region C. If a

spectrum analyzer is used to view the real or imaginary DAC

outputs of the AD9775, Region D appears in the spectrum.

However, on the output of the quadrature modulator, Region D

is rejected.

–100

–4.0

–3.0

–2.0

–1.0

0

1.0

2.0

3.0

4.0

(LO)

f_OUT(×f_DATA

)

Figure 89 to Figure 96 show the measured response of the AD9775

and AD8345 given the complex input signal to the AD9775 in

Figure 89. The data in these graphs was taken with a data rate of

12.5 MSPS at the AD9775 inputs. The interpolation rate of 4× or 8×

gives a DAC output data rate of 50 MSPS or 100 MSPS. As a result,

Figure 84. 4× Interpolation, Complex fDAC/4 Modulation

Rev. E | Page 39 of 56

AD9775

0

–20

–40

–60

–80

0

–20

D A

B C

D A

B C

D

A

B

C

D

A

B

C

–40

–60

–80

–100

–8.0

–6.0

–4.0

–2.0

0

2.0

4.0

6.0

8.0

–8.0

–6.0

–4.0

–2.0

0

2.0

4.0

6.0

8.0

(LO)

f_OUT(×f_DATA

)

f_OUT(×f_DATA

)

Figure 85. 8× Interpolation, Complex f_DAC/4 Modulation

Figure 88. 8× Interpolation, Complex f_DAC/8 Modulation

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–20

–40

–60

–80

D

A

B

C D

A

B

C

–100

–2.0

–1.5

–1.0

–0.5

0

0.5

1.0

1.5

2.0

0

10

20

30

40

50

(LO)

FREQUENCY (MHz)

f_OUT(×f_DATA

)

Figure 86. 2× Interpolation, Complex f_DAC/8 Modulation

Figure 89. AD9775 Real DAC Output of Complex Input Signal Near Baseband

(Positive Frequencies Only), Interpolation = 4×, No Modulation in AD9775

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–20

–40

–60

–80

D

A

B

C

D

A

B

C

–100

–4.0

–3.0

–2.0

–1.0

0

1.0

2.0

3.0

4.0

750 760 770 780 790 800 810 820 830 840 850

(LO)

f_OUT(×f_DATA

FREQUENCY (MHz)

)

Figure 90. AD9775 Complex Output from Figure 89,

Now Quadrature Modulated by AD8345 (LO = 800 MHz)

Figure 87. 4× Interpolation, Complex f_DAC/8 Modulation

Rev. E | Page 40 of 56

AD9775

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

750 760 770 780 790 800 810 820 830 840 850

0

10

20

30

40

50

FREQUENCY (MHz)

Figure 91. AD9775 Real DAC Output of Complex Input Signal Near

Baseband (Positive Frequencies Only), Interpolation = 4×,

Complex Modulation in AD9775 = +fDAC/4

Figure 94. AD9775 Complex Output from Figure 93,

Now Quadrature Modulated by AD8345 (LO = 800 MHz)

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

750 760 770 780 790 800 810 820 830 840 850

0

20

40

60

80

100

FREQUENCY (MHz)

Figure 92. AD9775 Complex Output from Figure 91,

Now Quadrature Modulated by AD8345 (LO = 800 MHz)

Figure 95. AD9775 Real DAC Output of Complex Input Signal Near

Baseband (Positive Frequencies Only), Interpolation = 8×,

Complex Modulation in AD9775 = +f_DAC/8

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

700 720 740 760 780 800 820 840 860 880 900

0

10

20

30

40

50

FREQUENCY (MHz)

Figure 93. AD9775 Real DAC Output of Complex Input Signal Near

Baseband (Negative Frequencies Only), Interpolation = 4×,

Complex Modulation in AD9775 = −f_DAC/4

Figure 96. AD9775 Complex Output from Figure 95,

Now Quadrature Modulated by AD8345 (LO = 800 MHz)

Rev. E | Page 41 of 56

AD9775

APPLYING THE OUTPUT CONFIGURATIONS

For the typical situation, where I_OUTFS= 20 mA and R_Aand R_B

both equal 50 Ω, the equivalent circuit values become

The following sections illustrate typical output configurations

for the AD9775. Unless otherwise noted, it is assumed that

IOUTFS is set to a nominal 20 mA. For applications requiring

optimum dynamic performance, a differential output configu-

ration is suggested. A simple differential output may be

achieved by converting IOUTA and IOUTB to a voltage output

by terminating them to AGND via equal value resistors. This

type of configuration may be useful when driving a differential

voltage input device such as a modulator. If a conversion to a

single-ended signal is desired and the application allows for ac

coupling, an RF transformer may be useful, or if power gain is

required, an op amp may be used. The transformer configu-

ration provides optimum high frequency noise and distortion

performance. The differential op amp configuration is suitable

for applications requiring dc coupling, signal gain, and/or level

shifting within the bandwidth of the chosen op amp.

V_SOURCE= 2 V p-p

R_OUT= 100 ꢁ

Note that the output impedance of the AD9775 DAC itself is

greater than 100 kΩ and typically has no effect on the

impedance of the equivalent output circuit.

DIFFERENTIAL COUPLING USING A

TRANSFORMER

An RF transformer can be used to perform a differential-to-

single-ended signal conversion, as shown in Figure 98. A dif-

ferentially coupled transformer output provides the optimum

distortion performance for output signals whose spectral content

lies within the transformer’s pass band. An RF transformer, such

as the Mini-Circuits T1-1T, provides excellent rejection of

common-mode distortion (that is, even-order harmonics) and

noise over a wide frequency range. It also provides electrical

isolation and the ability to deliver twice the power to the load.

Transformers with different impedance ratios can also be used for

impedance matching purposes.

A single-ended output is suitable for applications requiring a

unipolar voltage output. A positive unipolar output voltage

results if I_OUTAand/or I_OUTBis connected to a load resistor, R_LOAD

referred to AGND. This configuration is most suitable for a

single-supply system requiring a dc-coupled, ground-referred

output voltage. Alternatively, an amplifier could be configured

as an I-V converter, thus converting I_OUTAor I_OUTBinto a

negative unipolar voltage. This configuration provides the best

DAC dc linearity as I_OUTAor I_OUTBare maintained at ground or

virtual ground.

,

MINI-CIRCUITS

T1-1T

I

OUTA

DAC

R

LOAD

I

OUTB

Figure 98. Transformer-Coupled Output Circuit

UNBUFFERED DIFFERENTIAL OUTPUT,

EQUIVALENT CIRCUIT

The center tap on the primary side of the transformer must be

connected to AGND to provide the necessary dc current path

for both I_OUTAand I_OUTB. The complementary voltages appearing

at I_OUTAand I_OUTB(that is, V_OUTAand V_OUTB) swing symmetrically

around AGND and should be maintained within the specified

output compliance range of the AD9775. A differential resistor,

In many applications, it may be necessary to understand the

equivalent DAC output circuit. This is especially useful when

designing output filters or when driving inputs with finite input

impedances. Figure 97 illustrates the output of the AD9775 and

the equivalent circuit. A typical application where this

information may be useful is when designing an interface filter

between the AD9775 and Analog Devices’ AD8345 quadrature

modulator.

R

_DIFF, can be inserted in applications where the output of the

transformer is connected to the load, R_LOAD, via a passive

reconstruction filter or cable. R_DIFFis determined by the

transformer’s impedance ratio and provides the proper source

termination that results in a low VSWR. Note that approxi-

V

+

I

OUT

OUTA

OUTB

mately half the signal power dissipates across R_DIFF

.

V

–

OUT

R

+ R

B

A

V

=

SOURCE

× (R + R )

B

V

OUT

(DIFFERENTIAL)

I

OUTFS

A

p-p

Figure 97. DAC Output Equivalent Circuit

Rev. E | Page 42 of 56

AD9775

Gain/Offset Adjust

DIFFERENTIAL COUPLING USING AN OP AMP

The matching of the DAC output to the common-mode input

of the AD8345 allows the two components to be dc-coupled,

with no level shifting necessary. The combined voltage offset of

the two parts can therefore be compensated for via the AD9775

programmable offset adjust. This allows excellent LO cancella-

tion at the AD8345 output. The programmable gain adjust

allows for optimal image rejection as well.

An op amp can also be used to perform a differential-to-single-

ended conversion, as shown in Figure 99. This has the added

benefit of providing signal gain as well. In Figure 99, the

AD9775 is configured with two equal load resistors, R_LOAD, of

25 ꢁ. The differential voltage developed across I_OUTAand I_OUTBis

converted to a single-ended signal via the differential op amp

configuration. An optional capacitor can be installed across

I

_OUTAand I_OUTB, forming a real pole in a low-pass filter. The

The AD9775 evaluation board includes an AD8345 and

recommended interface (Figure 104 and Figure 105). On the

output of the AD9775, R9 and R10 convert the DAC output

current to a voltage. R16 may be used to do a slight common-

mode shift if necessary. The (now voltage) signal is applied to a

low-pass reconstruction filter to reject DAC images. The

components installed on the AD9775 provide a 35 MHz cutoff

but may be changed to fit the application. A balun (Mini-

Circuits ADTL1-12) is used to cross the ground plane boundary

to the AD8345. Another balun (Mini-Circuits ETC1-1-13) is

used to couple the LO input of the AD8345. The interface

requires a low ac impedance return path from the AD8345, so a

single connection between the AD9775 and AD8345 ground

planes is recommended.

addition of this capacitor also enhances the op amp distortion

performance by preventing the DAC fast slewing output from

overloading the input of the op amp.

500Ω

225Ω

I

OUTA

AD8021

DAC

I

OUTB

C

OPT

225Ω

AVDD

R

OPT

25Ω

500Ω

225Ω

Figure 99. Op Amp-Coupled Output Circuit

The common-mode (and second-order distortion) rejection of

this configuration is typically determined by the resistor

matching. The op amp used must operate from a dual supply

because its output is approximately 1.0 V. A high speed

amplifier, such as the AD8021, capable of preserving the

differential performance of the AD9775 while meeting other

system level objectives (such as cost and power) is

recommended. The op amp differential gain, its gain setting

resistor values, and full-scale output swing capabilities should

all be considered when optimizing this circuit. R_OPTis only

necessary if level shifting is required on the op amp output. In

Figure 99, AVDD, which is the positive analog supply for both

the AD9775 and the op amp, is also used to level shift the

differential output of the AD9775 to midsupply, that is,

AVDD/2.

The performance of the AD9775 and AD8345 in an image reject

transmitter, reconstructing three W-CDMA carriers, can be seen in

Figure 100. The LO of the AD8345 in this application is 800 MHz.

Image rejection (50 dB) and LO feedthrough (−78 dBFS) have been

optimized with the programmable features of the AD9775. The

average output power of the digital waveform for this test was set

to −15 dBFS to account for the peak-to-average ratio of the

W-CDMA signal.

0

–10

–20

–30

–40

–50

–60

–70

–80

–90

–100

INTERFACING THE AD9775 WITH THE AD8345

QUADRATURE MODULATOR

The AD9775 architecture was defined to operate in a transmit

signal chain using an image reject architecture. A quadrature

modulator is also required in this application and should be

designed to meet the output characteristics of the DAC as much

as possible. The AD8345 from Analog Devices meets many of

the requirements for interfacing with the AD9775. As with any

DAC output interface, there are a number of issues that have to

be resolved. The following sections list some of these issues.

762.5

782.5

802.5

822.5

842.5

FREQUENCY (MHz)

Figure 100. AD9775/AD8345 Synthesizing a Three-Carrier

W-CDMA Signal at an LO of 800 MHz

DAC Compliance Voltage/Input Common-Mode Range

The dynamic range of the AD9775 is optimal when the DAC

outputs swing between 1.0 V. The input common-mode range

of the AD8345, at 0.7 V, allows optimum dynamic range to be

achieved in both components.

Rev. E | Page 43 of 56

AD9775

EVALUATION BOARD

DAC Differential Outputs

The AD9775 evaluation board allows easy configuration of the

various modes, programmable via the SPI port. Software is

available for programming the SPI port from PCs running

Windows® 95, Windows 98, or Windows NT®/2000. The

evaluation board also contains an AD8345 quadrature

modulator and support circuitry that allows the user to

optimally configure the AD9775 in an image reject transmit

signal chain.

Transformers T2 and T3 should be in place. Note that the lower

band of operation for these transformers is 300 kHz to 500 kHz.

Jumper 4, Jumper 8, Jumper 13 to Jumper 17, and Jumper 28 to

Jumper 30 should remain unsoldered. The outputs are taken

from S3 and S4.

Using the AD8345

Remove Transformers T2 and T3. Jumper JP4 and Jumper 28 to

Jumper 30 should remain unsoldered. Jumper 13 to Jumper 16

should be soldered. The desired components for the low-pass

interface filter L6, L7, C55, and C81 should be in place. The LO

drive is connected to the AD8345 via J10 and the balun T4, and

the AD8345 output is taken from J9.

Figure 101 to Figure 104 show how to configure the evaluation

board in the one-port and two-port input modes with the PLL

enabled and disabled. Refer to Figure 105 to Figure 114, the

schematics, and the layout for the AD9775 evaluation board for

the jumper locations described in the DAC Single-Ended

Outputs section. The AD9775 outputs can be configured for

various applications by referring to the following instructions.

DAC Single-Ended Outputs

Remove Transformers T2 and T3. Solder jumper links JP4 or JP28

to look at the DAC1 outputs. Solder jumper links JP29 or JP30 to

look at the DAC2 outputs. Jumper 8 and Jumper 13 to Jumper 17

should remain unsoldered. Jumper JP35 to Jumper JP38 can be

used to ground one of the DAC outputs while the other is

measured single ended. Optimum single-ended distortion

performance is typically achieved in this manner. The outputs

are taken from S3 and S4.

Rev. E | Page 44 of 56

AD9775

LECROY

PULSE

GENERATOR

SIGNAL GENERATOR

TRIG

INP

DATACLK

CLK+/CLK–

INPUT CLOCK

AWG2021

OR

DG2020

40-PIN RIBBON CABLE

DAC1, DB13–DB0

DAC2, DB13–DB0

AD9775

JUMPER CONFIGURATION FOR TWO-PORT MODE PLL ON

SOLDERED/IN UNSOLDERED/OUT

JP1 –

JP2 –

×

JP3 –

JP5 –

×

JP6 –

×

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

×

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25

AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT

PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE

FOR MORE INFORMATION.

Figure 101. Test Configuration for AD9775 in Two-Port Mode with PLL Enabled, Signal Generator Frequency = Input Data Rate,

DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

LECROY

PULSE

GENERATOR

SIGNAL GENERATOR

TRIG

INP

ONEPORTCLK

CLK+/CLK–

INPUT CLOCK

AWG2021

OR

DG2020

DAC1, DB13–DB0

DAC2, DB13–DB0

AD9775

JUMPER CONFIGURATION FOR ONE-PORT MODE PLL ON

SOLDERED/IN UNSOLDERED/OUT

JP1 –

JP2 –

×

JP3 –

×

JP5 –

JP6 –

×

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

×

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

Figure 102. Test Configuration for AD9775 in One-Port Mode with PLL Enabled, Signal Generator Frequency = One-Half Interleaved Input Data Rate,

ONEPORTCLK = Interleaved Input Data Rate, DAC Output Data Rate = Signal Generator Frequency × Interpolation Rate

Rev. E | Page 45 of 56

AD9775

LECROY

PULSE

GENERATOR

SIGNAL GENERATOR

TRIG

INP

DATACLK

CLK+/CLK–

INPUT CLOCK

AWG2021

OR

DG2020

40-PIN RIBBON CABLE

DAC1, DB13–DB0

DAC2, DB13–DB0

AD9775

JUMPER CONFIGURATION FOR TWO-PORT MODE PLL OFF

SOLDERED/IN UNSOLDERED/OUT

JP1 –

JP2 –

×

JP3 –

JP5 –

×

JP6 –

×

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

×

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

2. IN TWO-PORT MODE, IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT PIN 8, JP25

AND JP39 SHOULD BE SOLDERED. IF DATACLK/PLL_LOCK IS PROGRAMMED TO OUTPUT

PIN 53, JP46 AND JP47 SHOULD BE SOLDERED. SEE THE TWO-PORT DATA INPUT MODE

FOR MORE INFORMATION.

Figure 103. Test Configuration for AD9775 in Two-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

DATACLK = Signal Generator Frequency/Interpolation Rate

LECROY

PULSE

GENERATOR

SIGNAL GENERATOR

TRIG

INP

ONEPORTCLK

CLK+/CLK–

INPUT CLOCK

AWG2021

OR

DG2020

DAC1, DB13–DB0

DAC2, DB13–DB0

AD9775

JUMPER CONFIGURATION FOR ONE-PORT MODE PLL OFF

SOLDERED/IN UNSOLDERED/OUT

JP1 –

JP2 –

×

JP3 –

×

JP5 –

JP6 –

×

JP12 –

JP24 –

JP25 –

JP26 –

JP27 –

JP31 –

JP32 –

JP33 –

×

NOTES

1. TO USE PECL CLOCK DRIVER, SOLDER JP41 AND JP42 AND REMOVE TRANSFORMER T1.

Figure 104. Test Configuration for AD9775 in One-Port Mode with PLL Disabled, DAC Output Data Rate = Signal Generator Frequency,

ONEPORTCLK = Interleaved Input Data Rate = 2× Signal Generator Frequency/Interpolation Rate

Rev. E | Page 46 of 56

AD9775

0 6 C 0 R 3

G 2

G 3

N E B L

V P S 1

T

V O U

L O I P

L O I N

G 1 B

G 1 A

V P S 2

G 4 A

G 4 B

Q B B N I B B N

Q B B P I B B P

A D T L 1 - 1 2

0 6 C 0 C 3

0 8 C 0 C 5

Figure 105. AD8345 Circuitry on AD9775 Evaluation Board

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AD9775

C C 0 6 0 3

R C 1 2 0 6

C C 0 6 0 3

R C 0 6 0 3

C C 0 6 0 5

C C 0 6 0 3

C C 0 8 0 5

Figure 106. AD9775 Clock, Power Supplies, and Output Circuitry

Rev. E | Page 48 of 56

AD9775

Figure 107. AD9775 Evaluation Board Input (A Channel) and Clock Buffer Circuitry

Rev. E | Page 49 of 56

AD9775

Figure 108. AD9775 Evaluation Board Input (B Channel) and SPI Port Circuitry

Rev. E | Page 50 of 56

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Figure 109. AD9775 Evaluation Board Components, Top Side

Figure 110. AD9775 Evaluation Board Components, Bottom Side

Rev. E | Page 51 of 56

AD9775

Figure 111. AD9775 Evaluation Board Layout, Layer One (Top)

Figure 112. AD9775 Evaluation Board Layout, Layer Two (Ground Plane)

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Figure 113. AD9775 Evaluation Board Layout, Layer Three (Power Plane)

Figure 114. AD9775 Evaluation Board Layout, Layer Four (Bottom)

Rev. E | Page 53 of 56

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OUTLINE DIMENSIONS

14.20

14.00 SQ

13.80

12.20

1.20

MAX

12.00 SQ

11.80

0.75

0.60

0.45

61

80

61

1

60

1

60

PIN 1

EXPOSED

PAD

6.00

BSC SQ

TOP VIEW

(PINS DOWN)

BOTTOM VIEW

(PINS UP)

0° MIN

1.05

1.00

0.95

0.20

0.09

7°

3.5°

0°

20

41

20

40

21

VIEW A

0.15

0.05

0.50 BSC

0.27

0.22

0.17

SEATING

PLANE

LEAD PITCH

0.08 MAX

COPLANARITY

VIEW A

ROTATED 90° CCW

COMPLIANT TO JEDEC STANDARDS MS-026-ADD-HD

Figure 115. 80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

(SV-80-1)

Dimensions shown in millimeters

ORDERING GUIDE

Model

Temperature Range

−40°C to +85°C

Package Description

Package Option

AD9775BSV

AD9775BSVRL

AD9775BSVZ¹

80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

80-Lead, Thin Quad Flat Package, Exposed Pad [TQFP_EP]

80-Lead Thin Quad Flat Package, Exposed Pad [TQFP_EP]

Evaluation Board

SV-80-1

AD9775BSVZRL¹−40°C to +85°C

AD9775-EB

¹Z = Pb-free part.

Rev. E | Page 54 of 56

AD9775

NOTES

Rev. E | Page 55 of 56

AD9775

NOTES

registered trademarks are the property of their respective owners.

C02858-0-12/06(E)

Rev. E | Page 56 of 56


型号：	AD9775BSVZ
厂家：	Rochester Electronics
描述：	PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, 14-BIT DAC, PQFP80, LEAD FREE, PLASTIC, MO-026-ADD-HD, TQFP-80 输入元件转换器
文件：	总57页 (文件大小：2593K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

AD9775BSVZ [ROCHESTER]

相关型号：

AD9775BSVZRL

AD9775EB

AD9776

AD9776-EB

AD9776A

AD9776A-EBZ

AD9776ABSVZ

AD9776ABSVZRL

AD9776A_15

AD9776BSVZ

AD9776BSVZ1

AD9776BSVZRL