AD607 [ADI]
Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem; 低功率混频器/ AGC / RSSI 3 V接收器IF子系统
| 型号： | AD607 |
| 厂家： | 
ADI |
| 描述： | Low Power Mixer/AGC/RSSI 3 V Receiver IF Subsystem |
| 文件： | 总24页 (文件大小：499K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power Mixer/AGC/RSSI
3 V Receiver IF Subsystem
a
AD607
FEATURES
PIN CONFIGURATION
Complete Receiver on a Chip: Monoceiver™ Mixer
–15 dBm 1 dB Compression Point
–8 dBm Input Third Order Intercept
500 MHz RF and LO Bandwidths
Linear IF Amplifier
Linear-in-dB Gain Control
MGC or AGC with RSSI Output
Quadrature Demodulator
On-Board Phase-Locked Quadrature Oscillator
Demodulates IFs from 400 kHz to 12 MHz
Can Also Demodulate AM, CW, SSB
Low Power
20-Lead SSOP
(RS Suffix)
20 VPS1
FLTR
1
2
FDIN
COM1
PRUP
LOIP
19
3
18 IOUT
4
17 QOUT
RFLO
5
16
15
VPS2
DMIP
AD607
TOP VIEW
(Not to Scale)
6
RFHI
GREF
MXOP
VMID
IFHI
7
14 IFOP
25 mW at 3 V
8
13
12
COM2
CMOS Compatible Power-Down
Interfaces to AD7013 and AD7015 Baseband Converters
9
GAIN/RS
10
11 IFLO
APPLICATIONS
GSM, CDMA, TDMA, and TETRA Receivers
Satellite Terminals
Battery-Powered Communications Receivers
GENERAL DESCRIPTION
The I and Q demodulators provide inphase and quadrature
baseband outputs to interface with Analog Devices’ AD7013
(IS54, TETRA, MSAT) and AD7015 (GSM) baseband con-
verters. A quadrature VCO phase-locked to the IF drives the I
and Q demodulators. The I and Q demodulators can also de-
modulate AM; when the AD607’s quadrature VCO is phase
locked to the received signal, the in-phase demodulator becomes
a synchronous product detector for AM. The VCO can also be
phase-locked to an external beat-frequency oscillator (BFO),
and the demodulator serves as a product detector for CW or
SSB reception. Finally, the AD607 can be used to demodulate
BPSK using an external Costas Loop for carrier recovery.
The AD607 is a 3 V low power receiver IF subsystem for opera-
tion at input frequencies as high as 500 MHz and IFs from
400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and
Q demodulators, a phase-locked quadrature oscillator, AGC
detector, and a biasing system with external power-down.
The AD607’s low noise, high intercept mixer is a doubly-
balanced Gilbert cell type. It has a nominal –15 dBm input
referred 1 dB compression point and a –8 dBm input referred
third-order intercept. The mixer section of the AD607 also
includes a local oscillator (LO) preamplifier, which lowers the
required LO drive to –16 dBm.
The gain control input can serve as either a manual gain control
(MGC) input or an automatic gain control (AGC) voltage-
based RSSI output. In MGC operation, the AD607 accepts an
external gain-control voltage input from an external AGC detec-
tor or a DAC. In AGC operation, an onboard detector and an
external averaging capacitor form an AGC loop that holds the
IF output level at ±300 mV. The voltage across this capacitor
then provides an RSSI output.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
AD607–SPECIFICATIONS (@ TA = + 25°C, Supply = 3.0 V, IF = 10.7 MHz, unless otherwise noted)
Model
AD607ARS
Typ
Conditions
Min
Max
Units
DYNAMIC PERFORMANCE
MIXER
Maximum RF and LO Frequency Range
Maximum Mixer Input Voltage
Input 1 dB Compression Point
Input Third-Order Intercept
Noise Figure
For Conversion Gain > 20 dB
For Linear Operation; Between RFHI and RFLO
RF Input Terminated in 50 Ω
500
±54
–15
–5
14
12
±1.3
45
–16
1
30
20
MHz
mV
dBm
dBm
dB
dB
V
MHz
dBm
kΩ
RF Input Terminated in 50 Ω
Matched Input, Max Gain, f = 83 MHz, IF = 10.7 MHz
Matched Input, Max Gain, f = 144 MHz, IF = 10.7 MHz
ZIF = 165 Ω, at Input Compression
–3 dB, ZIF = 165 Ω
Mixer LO Input Terminated in 50 Ω
LOIP to VMID
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
Maximum Output Voltage at MXOP
Mixer Output Bandwidth at MXOP
LO Drive Level
LO Input Impedance
Isolation, RF to IF
Isolation, LO to IF
Isolation, LO to RF
Isolation, IF to RF
dB
dB
dB
dB
40
70
IF AMPLIFIERS
Noise Figure
Max Gain, f = 10.7 MHz
IF = 10.7 MHz
IF = 10.7 MHz
ZIF = 600 Ω
From IFOP to VMID
–3 dB at IFOP, Max Gain
17
dB
Input 1 dB Compression Point
Output Third-Order Intercept
Maximum IF Output Voltage at IFOP
Output Resistance at IFOP
Bandwidth
–15
+18
±560
15
dBm
dBm
mV
Ω
45
MHz
GAIN CONTROL
Gain Control Range
Gain Scaling
(See Figures 43 and 44)
Mixer + IF Section, GREF to 1.5 V
GREF to 1.5 V
GREF to General Reference Voltage VR
GREF to 1.5 V, 80 dB Span
90
20
75/VR
±1
5
dB
mV/dB
dB/V
dB
µA
µA
Gain Scaling Accuracy
Bias Current at GAIN/RSSI
Bias Current at GREF
1
Input Resistance at GAIN, GREF
1
MΩ
I AND Q DEMODULATORS
Required DC Bias at DMIP
Input Resistance at DMIP
Input Bias Current at DMIP
Maximum Input Voltage
VPOS/2
50
2
±150
±75
±0.2
–1.2
–100
18
V dc
kΩ
µA
mV
mV
From DMIP to VMID
IF > 3 MHz
IF ≤ 3 MHz
Amplitude Balance
Quadrature Error
IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz
IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz
IF = 10.7 MHz, F = 10 kHz
dB
Degrees
dBc/Hz
dB
V
mV
Phase Noise in Degrees
Demodulation Gain
Maximum Output Voltage
Output Offset Voltage
Output Bandwidth
Sine Wave Input, Baseband Output
R
L ≥ 20 kΩ
±1.23
10
1.5
Measured from IOUT, QOUT to VMID
Sine Wave Input, Baseband Output
MHz
PLL
Required DC Bias at FDIN
Input Resistance at FDIN
Input Bias Current at FDIN
Frequency Range
Required Input Drive Level
Acquisition Time to ±3°
VPOS/2
50
200
0.4 to 12
400
16.5
V dc
kΩ
nA
MHz
mV
µs
From FDIN to VMID
Sine Wave Input at Pin 1
IF = 10.7 MHz
POWER-DOWN INTERFACE
Logical Threshold
Input Current for Logical High
Turn-On Response Time
Standby Current
For Power Up on Logical High
To PLL Locked
2
75
16.5
550
V dc
µA
µs
µA
POWER SUPPLY
Supply Range
2.7
5.5
V
Supply Current
Midgain, IF = 10.7 MHz
8.5
mA
OPERATING TEMPERATURE
TMIN to TMAX
Operation to 2.7 V Minimum Supply Voltage
Operation to 4.5 V Minimum Supply Voltage
–25
–40
+85
+85
°C
°C
Specifications subject to change without notice.
–2–
REV. 0
AD607
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . . . +5.5 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW
2.7 V to 5.5 V Operating Temperature Range
Temperature
Range
Package
Description
Package
Option
Model
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
4.5 V to 5.5 V Operating Temperature Range
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . +300°C
AD607ARS –25°C to +85°C
for 2.7 V to 5.5 V
20-Pin Plastic
SSOP
RS-20
Operation; –40°C
to +85°C for 4.5 V
to 5.5 V Operation
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
2Thermal Characteristics: 20-lead SSOP Package: θJA = 126°C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD607 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–3–
AD607
PIN DESCRIPTION
Function
Pin Mnemonic
Reads
1
FDIN
Frequency Detector Input
PLL input for I/Q demodulator quadrature oscillator, ±400 mV
drive required from external oscillator. Must be biased at VP/2.
2
3
COM1
PRUP
Common #1
Supply common for RF front end and main bias.
Power-Up Input
3 V/5 V CMOS compatible power-up control; logical high =
powered-up; max input level = VPS1 = VPS2.
4
LOIP
Local Oscillator Input
LO input, ac coupled ±54 mV LO input required (–16 dBm for
50 Ω input termination).
5
6
7
8
RFLO
RFHI
RF “Low” Input
RF “High” Input
Gain Reference Input
Mixer Output
Usually connected to ac ground.
AC coupled, ±56 mV, max RF input for linear operation.
High impedance input, typically 1.5 V, sets gain scaling.
GREF
MXOP
High impedance, single-sided current output, ±1.3 V max voltage
output (±6 mA max current output).
9
VMID
Midsupply Bias Voltage
IF “High” Input
Output of the midsupply bias generator (VMID = VPOS/2).
AC coupled IF input, ±56 mV max input for linear operation.
Reference node for IF input; auto-offset null.
10
11
12
IFHI
IFLO
IF “Low” Voltage
GAIN/RSSI
Gain Control Input/RSSI Output
High impedance input, 0 V–2 V using 3 V supply, max gain at
V = 0. RSSI Output when using Internal AGC Detector; RSSI
voltage is across AGC Capacitor connected to this pin.
13
14
COM2
IFOP
Common #2
IF Output
Supply common for IF stages and demodulator.
Low impedance, single-sided voltage output, +5 dBm (±560 mV)
max.
15
DMIP
Demodulator Input
Signal input to I and Q demodulators ±150 mV max input at IF
> 3 MHz for linear operation; ±75 mV max input at IF < 3 MHz
for linear operation. Must be biased at VP/2.
16
17
VPS2
VPOS Supply #2
Supply to high-level IF, PLL, and demodulators.
QOUT
Quadrature Output
Low impedance Q baseband output ±1.23 V full scale in 20 kΩ
min load; ac coupled.
18
IOUT
In-Phase Output
Low impedance I baseband output; ±1.23 V full scale in 20 kΩ
min load; ac coupled.
19
20
FLTR
VPS1
PLL Loop Filter
VPOS Supply #1
Series RC PLL Loop filter, connected to ground.
Supply to mixer, low level IF, PLL, and gain control.
PIN CONNECTION
20-Pin SSOP (RS-20)
20 VPS1
FLTR
1
2
FDIN
COM1
PRUP
LOIP
19
3
18 IOUT
4
17 QOUT
RFLO
5
16
15
VPS2
DMIP
AD607
TOP VIEW
(Not to Scale)
6
RFHI
GREF
MXOP
VMID
IFHI
7
14 IFOP
8
13
12
COM2
9
GAIN/RS
10
11 IFLO
–4–
REV. 0
Typical Performance Characteristics–AD607
HP8764B
0
50Ω
HP8656B
RF_OUT
IEEE
1
0
S0
S1
V
SYNTHESIZER
HP8656B
HP8764B
50Ω
0
CHARACTERIZATION
BOARD
50Ω
RF_OUT
1
IEEE
1
0
SYNTHESIZER
S0
S1
V
MXOP
RFHI
X
R
50Ω
L
1
HP8656B
LOIP
IFHI
RF_OUT
IEEE
SYNTHESIZER
HP6633A
TEK1105
OUT1
P6205
IFOP
X10
OUT IN1
PROBE
HP8765B
VPOS
0
1
FET
HP8594E
RF_IN
SPEC
VNEG
SPOS
C
IEEE
IN2
OUT2
IEEE
AN
S0
V
S1
DMIP
FDIN
IOUT
PROBE SUPPLY
SNEG
DCPS
PLL
HP34401A
QOUT
HI
LO
I
CPIB
IEEE
VPOS
BIAS
DMM
R5
PRUP
GAIN
DP8200
1kΩ
HP8765B
VPOS
VNEG
SPOS
0
1
SNEG
C
V
REF
S0
V
S1
Figure 1. Mixer/Amplifier Test Set
HP8720C
PORT_1
PORT_2
NETWORK AN
IEEE_488
CHARACTERIZATION
BOARD
HP8765B
0
HP8765B
50Ω
0
1
HP346B
HP8970A
MXOP
RFHI
C
C
1
RF_IN
28V
NOISE
X
28V_OUT
R
S0
S1
V
S0
S1
V
NOISE SOURCE
HP8656B
L
NOISE FIGURE METER
RF_OUT
IEEE
LOIP
IFHI
SYNTHESIZER
IFOP
DMIP
FDIN
IOUT
PLL
QOUT
HP6633A
VPOS
VPOS
BIAS
PRUP
GAIN
VNEG
SPOS
SNEG
IEEE
DCPS
DP8200
VPOS
VNEG
SPOS
SNEG
IEEE
V
REF
Figure 2. Mixer Noise Figure Test Set
REV. 0
–5–
AD607
CHARACTERIZATION
BOARD
MXOP
RFHI
LOIP
IFHI
X
R
L
P6205
TEK1103
OUT1
HP346B
HP8970A
IFOP
X10
OUT IN1
PROBE
RF_IN
28V
NOISE SOURCE
NOISE
28V_OUT
FET
NOISE FIGURE METER
IN2
OUT2
PROBE SUPPLY
DMIP
FDIN
IOUT
PLL
QOUT
HP6633A
VPOS
VPOS
BIAS
PRUP
GAIN
VNEG
SPOS
SNEG
IEEE
DCPS
DP8200
VPOS
VNEG
SPOS
SNEG
IEEE
V
REF
Figure 3. IF Amp Noise Figure Test Set
CHARACTERIZATION
BOARD
HP8764B
0
50Ω
MXOP
RFHI
LOIP
X
R
HP8656B
L
RF_OUT
SYNTHESIZER
1
0
IEEE
S0
S1
V
IFOP
IFHI
50Ω
1
HP3326A
OUTPUT_1
OUTPUT_2
1103
P6205
DCFM
IEEE
DMIP
FDIN
IOUT
OUT IN1
OUT1
OUT2
X10
HP8694E
RF_IN
FET PROBE
P6205
HP8765B
0
HP8765B
C
PLL
DUAL SYNTHESIZER
0
1
IEEE
QOUT
C
1
SPEC AN
OUT IN2
X10
HP6633A
VPOS
VPOS
S0
S1
V
S0
S1
V
FET PROBE
PROBE SUPPLY
BIAS
HP54120
PRUP
GAIN
VNEG
IEEE
SPOS
CH1
CH2
CH3
CH4
TRIG
SNEG
DCPS
DP8200
VPOS
IEEE_488
VNEG
IEEE
DIGITAL
OSCILLOSCOPE
SPOS
SNEG
V
REF
Figure 4. PLL/Demodulator Test Set
–6–
REV. 0
AD607
CHARACTERIZATION
BOARD
RFHI
MXOP
R
X
L
LOIP
IFHI
HP6633A
VPOS
VNEG
SPOS
SNEG
IFOP
IEEE
DCPS
DMIP
FDIN
DP8200
IOUT
VPOS
PLL
VNEG
SPOS
QOUT
IEEE
GPIB
SNEG
VPOS
V
REF
R1
499kΩ
BIAS
PRUP
GAIN
HP34401A
HI
LO
I
DMM
Figure 5. GAIN Pin Bias Test Set
CHARACTERIZATION
BOARD
RFHI
MXOP
R
X
L
LOIP
IFHI
HP6633A
VPOS
IFOP
VNEG
SPOS
SNEG
IEEE
DCPS
DMIP
FDIN
DP8200
IOUT
VPOS
PLL
VNEG
SPOS
QOUT
IEEE
GPIB
SNEG
VPOS
V
REF
R1
499kΩ
BIAS
PRUP
GAIN
HP34401A
HI
LO
I
DMM
Figure 6. Demodulator Bias Test Set
CHARACTERIZATION
BOARD
HP3325B
RFHI
LOIP
IFHI
MXOP
RF_OUT
IEEE
R
X
SYNTHESIZER
HP6633A
L
VPOS
HP8594E
IFOP
VNEG
SPOS
RF_IN
SPEC AN
IEEE
IEEE
SNEG
DCPS
HP6633A
DMIP
FDIN
IOUT
VPOS
VNEG
SPOS
PLL
IEEE
GPIB
QOUT
SNEG
VPOS
DCPS
R1
10kΩ
BIAS
HP34401A
DMM
PRUP
GAIN
HI
LO
I
Figure 7. Power-Up Threshold Test Set
–7–
REV. 0
AD607
CHARACTERIZATION
BOARD
MXOP
RFHI
X
R
L
LOIP
IFHI
HP54120
P6205
1103
IFOP
X10
OUT IN1
OUT1
OUT2
CH1
CH2
CH3
CH4
TRIG
FET PROBE
50Ω
P6205
X10
FET PROBE
OUT IN2
PROBE SUPPLY
DMIP
FDIN
IOUT
FL6082A
RF_OUT
IEEE_488
DIGITAL
OSCILLOSCOPE
IEEE
IEEE
PLL
MOD_OUT
QOUT
HP6633A
VPOS
NOTE: MUST BE 3 RESISTOR POWER DIVIDER
VPOS
BIAS
PRUP
GAIN
VNEG
SPOS
SNEG
VPOS
DCPS
DP8200
VNEG
SPOS
IEEE
IEEE
SNEG
V
REF
HP8112
PULSE_OUT
PULSE GENERATOR
Figure 8. Power-Up Test Set
CHARACTERIZATION
BOARD
MXOP
RFHI
X
R
L
LOIP
IFHI
HP8656B
RF_OUT
SYNTHESIZER
HP8594E
1103
P6205
IFOP
X10
IEEE
OUT IN1
OUT1
RF_IN
IEEE
FET PROBE
R1
1k
SPEC AN
IN2
OUT2
PROBE SUPPLY
DMIP
FDIN
IOUT
PLL
QOUT
HP6633A
VPOS
BIAS
VPOS
PRUP
GAIN
VNEG
SPOS
IEEE
SNEG
DCPS
Figure 9. IF Output Impedance Test Set
CHARACTERIZATION
BOARD
MXOP
IFOP
RFHI
LOIP
X
R
L
IFHI
20
dB
HP54120
P6205
1103
DMIP
FDIN
IOUT
FL6082A
RF_OUT
MOD_OUT
OUT IN1
OUT1
OUT2
X10
CH1
CH2
CH3
CH4
TRIG
IEEE
IEEE
FET PROBE
P6205
PLL
QOUT
OUT IN2
X10
HP6633A
VPOS
FET PROBE
PROBE SUPPLY
IEEE_488
DIGITAL
VPOS
VNEG
SPOS
SNEG
BIAS
PRUP
GAIN
OSCILLOSCOPE
DCPS
DP8200
VPOS
VNEG
SPOS
SNEG
IEEE
V
REF
Figure 10. PLL Settling Time Test Set
–8–
REV. 0
AD607
CHARACTERIZATION
BOARD
MXOP
RFHI
X
R
L
HP3325B
RF_OUT
LOIP
IFHI
IEEE
SYNTHESIZER
IFOP
HP3326
1103
P6205
DCFM
IEEE
OUTPUT_1
OUTPUT_2
DMIP
FDIN
IOUT
OUT IN1
OUT1
OUT2
X10
FET PROBE
P6205
HP8765B
PLL
DUAL SYNTHESIZER
0
1
QOUT
HP8694E
RF_IN
SPEC AN
C
IEEE
OUT IN2
X10
HP6633A
VPOS
VPOS
S0
S1
V
FET PROBE
PROBE SUPPLY
BIAS
PRUP
GAIN
VNEG
IEEE
SPOS
SNEG
DCPS
DP8200
VPOS
VNEG
IEEE
SPOS
SNEG
V
REF
Figure 11. Quadrature Accuracy Test Set
VPOS
GND
C15
0.1µF
4.99k
R10
C11
10nF
0.1µF
C13
0.1µF
C1
FDIN
R8
VPS1 20
FLTR
1
2
FDIN
51.1
0
R12
COM1
PRUP
LOIP
19
C3
10nF
R1
1k
3
IOUT 18
PRUP
LOIP
C10
1nF
IOUT
*
4
QOUT 17
0.1µF
C2
AD607
C16
1nF
R7
51.1
5
RFLO
16
15
VPS2
DMIP
QOUT
*
6
RFHI
GREF
MXOP
VMID
IFHI
C9
1nF
R2
316
7
IFOP 14
RFHI
R6
51.1
IFOP
*
8
13
12
COM2
GAIN
R13
301
9
GAIN
*
10
IFLO 11
C5
1nF
MXOP
*
51.1
R9
C6
R14
54.9
332
R5
C7
1nF
0.1µF
DMIP
*
C8
0.1µF
IFHI
0.1µF
NOTE: CONNECTIONS MARKED * ARE DC COUPLED.
Figure 12. AD607 Characterization Board
REV. 0
–9–
AD607
20
30
25
20
19
18
17
16
15
14
13
12
11
10
V
= 0.3V
= 0.6V
GAIN
V
GAIN
15
10
5
VPOS = 5V, IF = 20 MHz
VPOS = 3V, IF = 20 MHz
V
= 1.2V
= 1.8V
GAIN
V
V
GAIN
0
= 2.4V
GAIN
–5
–10
VPOS = 5V, IF = 10 MHz
VPOS = 3V, IF = 10 MHz
50
70
90
110 130 150 170 190 210 230 250
RF FREQUENCY – MHz
0.1
1
10
100
INTERMEDIATE FREQUENCY – MHz
Figure 13. Mixer Noise Figure vs. Frequency
Figure 16. Mixer Conversion Gain vs. IF, T = +25°C,
VPOS = 3 V, VREF = 1.5 V
4500
4000
3500
4.0
3.5
3.0
2.5
80
70
CUBIC FIT OF IF_GAIN (TEMP)
60
C SHUNT COMPONENT
IF AMP GAIN
3000
2500
2000
1500
1000
500
50
40
30
2.0
1.5
20
CUBIC FIT OF CONV_GAIN (TEMP)
R SHUNT COMPONENT
1.0
0.5
0
10
MIXER CG
0
–10
–20
0
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
TEMPERATURE – °C
Figure 14. Mixer Input Impedance vs. Frequency,
VPOS = 3 V, V GAIN = 0.8 V
Figure 17. Mixer Conversion Gain and IF Amplifier Gain
vs. Temperature, VPOS = 3 V, VGAIN = 0.3 V, VREF = 1.5 V,
IF = 10.7 MHz, RF = 250 MHz
30
25
20
15
V
= 0.00V
GAIN
80
70
V
V
= 0.54V
= 1.62V
GAIN
CUBIC FIT OF IF_GAIN (V
)
POS
IF AMP GAIN
60
50
40
30
20
10
10
5
V
GAIN
= 1.08V
GAIN
0
–5
–10
–15
CUBIC FIT OF CONV_GAIN (V
)
POS
V
= 2.16V
GAIN
–20
0
50 100 150 200 250 300 350 400 450 500 550 600
RADIO FREQUENCY – MHz
MIXER CG
2.4 2.6 2.8 3.2 3.4 3.6 3.8
SUPPLY – Volts
3
4
4.2 4.4 4.6 4.8
5
5.2 5.4 5.6 5.8
6
Figure 15. Mixer Conversion Gain vs. Frequency,
T = +25°C, VPOS = 2.7 V, VREF = 1.35 V, IF = 10.7 MHz
Figure 18. Mixer Conversion Gain and IF Amplifier Gain
vs. Supply Voltage, T = +25°C, VGAIN = 0.3 V, VREF = 1.5 V,
IF = 10.7 MHz, RF = 250 MHz
–10–
REV. 0
AD607
80
70
60
50
40
30
–90.00
V
= 0.3V
GAIN
–100.00
V
V
= 0.6V
= 1.2V
GAIN
–110.00
–120.00
–130.00
–140.00
–150.00
GAIN
V
V
= 1.8V
= 2.4V
GAIN
20
10
GAIN
0
–10
0.1
1
10
100
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
INTERMEDIATE FREQUENCY – MHz
CARRIER FREQUENCY OFFSET, f(fm) – Hz
Figure 19. IF Amplifier Gain vs. Frequency,
T = +25°C, VPOS = 3 V, VREF = 1.5 V
Figure 22. PLL Phase Noise L (F) vs. Frequency,
VPOS = 3 V, C3 = 0.1 µF, IF = 10.7 MHz
10
8
2.5
6
IF AMP
4
2
0
2
–2
–4
–6
MIXER
–8
–10
1.5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8
3
0.1
1
10
100
GAIN VOLTAGE – Volts
PLL FREQUENCY – MHz
Figure 20. AD607 Gain Error vs. Gain Control Voltage,
Representative Part
Figure 23. PLL Loop Voltage at FLTR (KVCO) vs. Frequency
8
7
6
5
4
3
2
1
0
996.200 µs
1.00870 ms
1.02120 ms
Timebase
=
=
=
=
=
=
=
2.5 µs/div
Delay = 1.00870 ms
Memory 1
Timebase
Memory 2
Timebase
Delta T
100.0 mVolts/div Offset = 127.3 mVolts
2.50 µs/div Delay = 1.00870 ms
20.00 mVolts/div Offset = 155.2 mVolts
2.50 µs/div
16.5199 µs
1.00048 ms
85
86
87
88
89
90
91
92
93
94
95
Delay = 1.00870 ms
QUADRATURE ANGLE – Degrees
Start
Stop 1.01700 ms
=
Trigger on External at Pos. Edge at 134.0 mVolts
Figure 24. Demodulator Quadrature Angle, Histogram,
T = +25°C, VPOS = 3 V, IF = 10.7 MHz
Figure 21. PLL Acquisition Time
REV. 0
–11–
AD607
20
19
30
I_GAIN_CORR
25
20
18
17
16
15
14
13
12
11
10
CUBIC FIT OF I_GAIN_CORR (TEMP)
15
10
5
0
2.5
3
3.5
4
4.5
5
5.5
6
–2
–1
0
1
2
SUPPLY – Volts
IQ GAIN BALANCE – dB
Figure 28. Demodulator Gain vs. Supply Voltage
Figure 25. Demodulator Gain Balance, Histogram,
T = +25°C, VPOS = 3 V, IF = 10.7 MHz
40
35
30
25
20
15
10
5
20
19
18
17
I_GAIN_CORR
16
15
QUADRATIC FIT OF I_GAIN_CORR (IFF)
14
13
12
11
10
0
17
17.2 17.4 17.6 17.8
18
18.2 18.4 18.6 18.8
DEMODULATOR GAIN – dB
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
BASEBAND FREQUENCY – MHz
Figure 29. Demodulator Gain Histogram,
T = +25°C, VPOS = 3 V, IF = 10.7 MHz
Figure 26. Demodulator Gain vs. Frequency
14
20
19
I_GAIN_CORR
12
10
8
18
17
16
15
14
13
12
11
10
CUBIC FIT OF I_GAIN_CORR (TEMP)
6
4
2
0
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
TEMPERATURE – °C
–0.1 –0.08 –0.06 –0.04 –0.02
0
0.02 0.04 0.06 0.08 0.1
OUTPUT OFFSET – Volts
Figure 27. Demodulator Gain vs. Temperature
Figure 30. Demodulator Output Offset Voltage
Histogram, T = +25°C, VPOS = 3 V, IF = 10.7 MHz
–12–
REV. 0
AD607
PRODUCT OVERVIEW
The AD607 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero-
dyne receiver, or most of a double-conversion receiver, at input
frequencies up to 500 MHz, and with an IF of from 400 kHz to
12 MHz. The internal I/Q demodulators, and their associated
phase locked-loop, which can provide carrier recovery from the
IF, support a wide variety of modulation modes, including n-
PSK, n-QAM, and AM. A single positive supply voltage of 3 V
is required (2.7 V minimum, 5.5 V maximum) at a typical sup-
ply current of 8.5 mA at midgain. In the following discussion,
VP will be used to denote the power supply voltage, which will
be assumed to be 3 V.
40.2127 ms
40.2377 ms
40.2627 ms
Timebase
=
=
=
=
=
=
=
5.00 µs/div
Delay = 40.2377 ms
Memory 1
Timebase
Memory 2
Timebase
Delta T
100.0 mVolts/div Offset = 154.0 mVolts
5.00 µs/div Delay = 40.2377 ms
60.00 mVolts/div Offset = 209.0 mVolts
5.00 µs/div
15.7990 µs
40.2327 ms
Figure 33 shows the main sections of the AD607. It consists of a
variable-gain UHF mixer and linear four-stage IF strip, which
together provide a voltage controlled gain range of more than
90 dB; followed by dual demodulators, each comprising a multi-
plier followed by a 2-pole, 2 MHz low-pass filter; and driven by
a phase-locked loop providing the inphase and quadrature
clocks. An internal AGC detector is included, and the tempera-
ture stable gain control system provides an accurate RSSI capa-
bility. A biasing system with CMOS compatible power-down
completes the AD607.
Delay = 40.2377 ms
Start
Stop 40.2485 ms
=
Trigger on External at Pos. Edge at 40.0 mVolts
Figure 31. Power-Up Response Time to PLL Stable
15
Mixer
The UHF mixer is an improved Gilbert cell design, and can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 500 MHz. The dynamic range at the input of the
mixer is determined, at the upper end, by the maximum input
signal level of ±56 mV between RFHI and RFLO up to which
the mixer remains linear, and, at the lower end, by the noise
level. It is customary to define the linearity of a mixer in terms
of the 1 dB gain-compression point and third-order intercept,
which for the AD607 are –15 dBm and –8 dBm, respectively, in
a 50 Ω system.
10
5
0
0.5
1
1.5
2
2.5
GAIN VOLTAGE – Volts
Figure 32. Power Supply Current vs. Gain Control Voltage,
GREF = 1.5 V
LOIP
RFHI
VMID
IOUT
IFHI
MXOP
BPF
FDIN
DMIP
IFOP
BPF OR
LPF
VQFO
RFLO
FLTR
VMID
IFLO
QOUT
MID-POINT
BIAS
GENERATOR
AGC
DETECTOR
GAIN/RSSI
GREF
VPS1
PTAT
VOLTAGE
BIAS
GENERATOR
VPS2
AD607
PRUP
COM1 COM2
Figure 33. Functional Block Diagram
REV. 0
–13–
AD607
The mixer’s RF input port is differential, that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased; we will generally assume that RFLO is decoupled to ac
ground. The RF port can be modeled as a parallel RC circuit as
shown in Figure 34.
Table I. AD607 Filter Termination Resistor Values for
Common IFs
Filter
Filter Termination Resistor
IF
Impedance
Values1 for 24 dB of Mixer Gain
R1
R2
R3
AD607
450 kHz
455 kHz
6.5 MHz
1500 Ω
1500 Ω
1000 Ω
174 Ω
174 Ω
215 Ω
330 Ω
1330 Ω
1330 Ω
787 Ω
0 Ω
1500 Ω
1500 Ω
1000 Ω
330 Ω
C1
C2
RFHI
R
IN
C
IN
L1
RFLO
10.7 MHz 330 Ω
C3
NOTES
1Resistor values were calculated such that R1+ R2 = ZFILTER and
R1ʈ (R2 + ZFILTER) = 165 Ω.
C1, C2, L1: OPTIONAL MATCHING CIRCUIT
C3: COUPLES RFLO TO AC GROUND
The maximum permissible signal level at MXOP is determined
by both voltage and current limitations. Using a 3 V supply and
VMID at 1.5 V, the maximum swing is about ±1.3 V. To attain
a voltage swing of ±1 V in the standard IF filter load of 165 Ω
load requires a peak drive current of about ±6 mA, which is well
within the linear capability of the mixer. However, these upper
limits for voltage and current should not be confused with issues
related to the mixer gain, already discussed. In an operational
system, the AGC voltage will determine the mixer gain, and
hence the signal level at the IF input pin IFHI; it will always be
less than ±56 mV (–15 dBm into 50 Ω), which is the limit of
the IF amplifier’s linear range.
Figure 34. Mixer Port Modeled as a Parallel RC Network;
an Optional Matching Network Is also Shown
The local oscillator (LO) input is internally biased at VP/2 via a
nominal 1000 Ω resistor internally connected from pin LOIP to
VMID. The LO interface includes a preamplifier which mini-
mizes the drive requirements, thus simplifying the oscillator de-
sign and reducing LO leakage from the RF port. Internally, this
single-sided input is actually differential; the noninverting input
is referenced to pin VMID. The LO requires a single-sided drive
of ±50 mV, or –16 dBm in a 50 Ω system.
IF Amplifier
The mixer’s output passes through both a low-pass filter and a
buffer, which provides an internal differential to single-ended
signal conversion with a bandwidth of approximately 45 MHz.
Its output at pin MXOP is in the form of a single-ended current.
This approach eliminates the 6 dB voltage loss of the usual se-
ries termination by replacing it with shunt terminations at the
both the input and the output of the filter. The nominal conver-
sion gain is specified for operation into a total IF bandpass filter
(BPF) load of 165 Ω, that is, a 330 Ω filter, doubly-terminated
as shown in Figure 33. Note that these loads are connected to
bias point VMID, which is always at the midpoint of the supply
(that is, VP/2).
Most of the gain in the AD607 arises in the IF amplifier strip,
which comprises four stages. The first three are fully differential
and each has a gain span of 25 dB for the nominal AGC voltage
range. Thus, in conjunction with the mixer’s variable gain, the
total gain exceeds 90 dB. The final IF stage has a fixed gain of
20 dB, and it also provides differential to single-ended conversion.
The IF input is differential, at IFHI (noninverting relative to the
output IFOP) and IFLO (inverting). Figure 36 shows a simpli-
fied schematic of the IF interface. The offset voltage of this
stage would cause a large dc output error at high gain, so it is
nulled by a low-pass feedback path from the IF output, also
shown in Figure 25. Unlike the mixer output, the signal at IFOP
is a low-impedance single-sided voltage, centered at VP/2 by the
DC feedback loop. It may be loaded by a resistance as low as
50 Ω which will normally be connected to VMID.
The conversion gain is measured between the mixer input and
the input of this filter, and varies between 1.5 dB and 26.5 dB
for a 165 Ω load impedance. Using filters of higher impedance,
the conversion gain can always be maintained at its specified
value or made even higher; for filters of lower impedance, of say
ZO, the conversion gain will be lowered by 10 log10(165/ZO).
Thus, the use of a 50 Ω filter will result in a conversion gain that
is 5.2 dB lower. Figure 35 shows filter matching networks and
Table I lists resistor values.
AD607
10kΩ
IFHI
VMID
IFOP
IFLO
10kΩ
1nF
R2
BPF
MXOP
VMID
OFFSET FEEDBACK
LOOP
8
9
10
11
IFHI
R3
R1
IFLO
100nF
Figure 36. Simplified Schematic of the IF Interface
100nF
Figure 35. Suggested IF Filter Matching Network. The
Values of R1 and R2 Are Selected to Keep the Impedance
at Pin MXOP at 165 Ω
–14–
REV. 0
AD607
The IF’s small-signal bandwidth is approximately 45 MHz from
IFHI and IFLO through IFOP. The peak output at IFOP is
±560 mV at VP = 3 V and ±400 mV at the minimum VP of
2.7 V. This allows some headroom at the demodulator inputs
(pin DMIP), which accept a maximum input of ±150 mV for
IFs > 3 MHz and ±75 mV for IFs ≤ 3 MHz (at IFs ≤ 3 MHz,
the drive to the demodulators must be reduced to avoid saturat-
ing the output amplifiers with higher order mixing products that
are no longer removed by the onboard low-pass filters).
The gain control scaling is proportional to the reference voltage
applied to the pin GREF. When this pin is tied to the midpoint
of the supply (VMID), the scale is nominally 20 mV/dB (50 dB/
V) for VP = 3 V. Under these conditions, the lower 80 dB of
gain range (mixer plus IF) corresponds to a control voltage of
0.4 V ≤ VG ≤ 2.0 V. The final centering of this 1.6 V range de-
pends on the insertion losses of the IF filters used. More gener-
ally, the gain scaling using these connections is VP/150 (volts
per dB), so becomes 33.3 mV/dB (30 dB/V) using a 5 V supply,
with a proportional change in the AGC range, to 0.33 V ≤
VG ≤ 3 V, Table II lists gain control voltages and scale factors
for power supply voltages from 2.7 V to 5.5 V.
If the internal AGC detector is used, the IF output will be at an
amplitude of VP/10, that is, ±300 mV for VP = 3 V. This ±300
mV level requires the insertion of 6 dB of post-IF filter loss be-
tween IFOP and DMIP to avoid overloading the demodulators;
often, a simple RC low-pass filter with its corner frequency at
the IF will suffice.
Alternatively, pin GREF can be tied to an external voltage
reference, VR, provided, for example, by an AD1582 (2.5 V)
or AD1580 (1.21 V) voltage reference, to provide supply-
independent gain scaling of VR/75 (volts per dB). When using
the Analog Devices’ AD7013 and AD7015 baseband converters,
the external reference may also be provided by the reference
output of the baseband converter (Figure 38). For example, the
AD7015 baseband converter provides a VR of 1.23 V; when
connected to GREF the gain scaling is 16.4 mV/dB (60 dB/V).
An auxiliary DAC in the AD7015 can be used to generate the
MGC voltage. Since it uses the same reference voltage, the nu-
merical input to this DAC provides an accurate RSSI value in
digital form, no longer requiring the reference voltage to have
high absolute accuracy.
Since there is no band-limiting in the IF strip, the output-
referred noise can be quite high; in a typical application and at a
gain of 75 dB it is about 100 mV rms, making post-IF filtering
desirable. IFOP may be also used as an IF output for driving an
A/D converter, external demodulator, or external AGC detector.
Figure 37 shows methods of matching the optional second IF
filter.
VPOS
AD607
2R
2R
T
T
R
T
IFOP
DMIP
BPF
AD7013 OR
AD607
AD7015
R
IOUT
QOUT
VMID
IADC
C
R
QADC
C
IADC
QADC
a. Biasing DMIP from Power Supply (Assumes BPF AC
Coupled Internally)
GREF
(AD7015)
(AD7013)
REFOUT
BYPASS
10nF
GAIN/RSSI
AUX DAC
AD607
R
T
1nF
IFOP
BPF
DMIP
VMID
Figure 38. Interfacing the AD607 to the AD7013 or AD7015
Baseband Converters
R
T
I/Q Demodulators
C
BYPASS
Both demodulators (I and Q) receive their inputs at pin DMIP.
Internally, this single-sided input is actually differential; the
noninverting input is referenced to pin VMID. Each demodula-
tor comprises a full-wave synchronous detector followed by a
2 MHz, two-pole low-pass filter, producing single-sided outputs
at pins IOUT and QOT. Using the I and Q demodulators for
IFs above 12 MHz is precluded by the 400 kHz to 12 MHz
response of the PLL used in the demodulator section. Pin DMIP
requires an external bias source at VP/2; Figure 39 shows sug-
gested methods.
b. Biasing DMIP from VMID (Assumes BPF AC Coupled
Internally)
Figure 37. Input and Output Matching of the Optional
Second IF Filter
Gain Scaling and RSSI
The AD607’s overall gain, expressed in decibels, is linear-in-dB
with respect to the AGC voltage VG at pin GAIN/RSSI. The
gain of all sections is maximum when VG is zero, and reduces
progressively up to VG = 2.2 V (for VP = 3 V; in general, up to a
limit VP – 0.8 V). The gain of all stages changes in parallel. The
AD607 features temperature-compensation of the gain scaling.
Note that GAIN/RSSI pin is either an MGC input, when the
gain is controlled by some external means, or an RSSI output,
when the internal AGC detector is used.
Outputs IOUT and QOUT are centered at VP/2 and can swing
up to ±1.23 V even at the low supply voltage of 2.7 V. They
can therefore directly drive the RX ADCs in the AD7015
baseband converter, which require an amplitude of 1.23 V to
fully load them when driven by a single-sided signal. The con-
version gain of the I and Q demodulators is 18 dB (X8), requir-
ing a maximum input amplitude at DMIP of ±150 mV for IFs >
3 MHz.
REV. 0
–15–
AD607
VPOS
2R
quadrature accuracy of this VFQO is typically –1.2° at
10.7 MHz. The PLL uses a sequential-phase detector that
comprises low power emitter-coupled logic and a charge pump
(Figure 40).
AD607
T
T
R
T
IFOP
BPF
2R
DMIP
I
~
U
40µA
V
F
I-CLOCK
VARIABLE-
FREQUENCY
QUADRATURE
OSCILLATOR
F
U
D
a. Biasing DMIP from Power Supply (Assumes BPF AC
Coupled Internally)
SEQUENTIAL
PHASE
DETECTOR
90°
R
C
R
Q-CLOCK
(ECL OUTPUTS)
AD607
I
~
D
R
T
40µA
IFOP
BPF
REFERENCE CARRIER
(FDIN AFTER LIMITING)
DMIP
DMIP
R
T
Figure 40. Simplified Schematic of the PLL and
Quadrature VCO
C
BYPASS
The reference signal may be provided from an external source,
in the form of a high-level clock, typically a low level signal
(±400 mV) since there is an input amplifier between FDIN and
the loop’s phase detector. For example, the IF output itself can
be used by connecting DMIP to FDIN, which will then pro-
vide automatic carrier recover for synchronous AM detection
and take advantage of any post-IF filtering. Pin FDIN must be
biased at VP/2; Figure 41 shows suggested methods.
b. Biasing DMIP from VMID (Assumes BPF AC Coupled
Internally)
Figure 39. Suggested Methods for Biasing Pin DMIP
at VP/2
For IFs < 3 MHz, the on-chip low-pass filters (2 MHz cutoff)
do not attenuate the IF or feedthrough products; thus, the maxi-
mum input voltage at DMIP must be limited to ±75 mV to al-
low sufficient headroom at the I and Q outputs for not only the
desired baseband signal but also the unattenuated higher-order
demodulation products. These products can be removed by an
external low-pass filter. In the case of IS54 applications using a
455 kHz IF and the AD7013 baseband converter, a simple
1-pole RC filter with its corner above the modulation bandwidth
is sufficient to attenuate undesired outputs.
The VFQO operates from 400 kHz to 12 MHz and is con-
trolled by the voltage between VPOS and FLTR. In normal op-
eration, a series RC network, forming the PLL loop filter, is
connected from FLTR to ground. The use of an integral
sample-hold system ensures that the frequency-control voltage
on pin FLTR remains held during power-down, so reacquisition
of the carrier typically occurs in 16.5 µs.
In practice, the probability of a phase mismatch at power-up is
high, so the worst-case linear settling period to full lock needs
to be considered in making filter choices. This is typically 16.5 µs
at an IF of 10.7 MHz for a ±100 mV signal at DMIP and
FDIN.
Phase-Locked Loop
The demodulators are driven by quadrature signals that are pro-
vided by a variable frequency quadrature oscillator (VFQO),
phase locked to a reference signal applied to pin FDIN. When
this signal is at the IF, inphase and quadrature baseband out-
puts are generated at IOUT and QOUT, respectively. The
Table II. AD607 Gain and Manual Gain Control Voltage vs. Power Supply Voltage
Power Supply
Voltage
(V)
GREF
(= VMID)
(V)
Gain Control
Voltage Input Range
(V)
Scale Factor
(dB/V)
Scale Factor
(mV/dB)
2.7
3.0
3.5
4.0
4.5
5.0
5.5
1.35
1.5
1.75
2.0
2.25
2.5
2.75
55.56
50.00
42.86
37.50
33.33
30.00
27.27
18.00
20.00
23.33
26.67
30.00
33.33
36.67
0.360–1.800
0.400–2.000
0.467–2.333
0.533–2.667
0.600–3.000
0.667–3.333
0.733–3.667
NOTE
Maximum gain occurs for gain control voltage = 0 V.
–16–
REV. 0
AD607
Bias System
USING THE AD607
The AD607 operates from a single supply, VP, usually of 3 V, at
a typical supply current of 8.5 mA at midgain and T = 27°C,
corresponding to a power consumption of 25 mW. Any voltage
from 2.7 V to 5.5 V may be used.
In this section, we will focus on a few areas of special impor-
tance and include a few general application tips. As is true of
any wideband high gain component, great care is needed in PC
board layout. The location of the particular grounding points
must be considered with due regard to possibility of unwanted
signal coupling, particularly from IFOP to RFHI or IFHI or both.
The bias system includes a fast-acting active-high CMOS-
compatible power-up switch, allowing the part to idle at 550 µA
when disabled. Biasing is proportional-to-absolute-temperature
(PTAT) to ensure stable gain with temperature.
The high sensitivity of the AD607 leads to the possibility that
unwanted local EM signals may have an effect on the perfor-
mance. During system development, carefully-shielded test as-
semblies should be used. The best solution is to use a fully-
enclosed box enclosing all components, with the minimum
number of needed signal connectors (RF, LO, I and Q outputs)
in miniature coax form.
An independent regulator generates a voltage at the midpoint of
the supply (VP/2) which appears at the VMID pin, at a low im-
pedance. This voltage does not shut down, ensuring that the
major signal interfaces (e.g., mixer-to-IF and IF-to-demodula-
tors) remain biased at all times, thus minimizing transient dis-
turbances at power-up and allowing the use of substantial
decoupling capacitors on this node. The quiescent consumption
of this regulator is included in the idling current.
The I and Q output leads can include small series resistors
(about 100 Ω) inside the shielded box without significant loss of
performance, provided the external loading during testing is
light (that is, a resistive load of more than 20 kΩ and capaci-
tances of a few picofarads). These help to keep unwanted RF
emanations out of the interior.
VPOS
AD607
50kΩ
FDIN
The power supply should be connected via a through-hole ca-
pacitor with a ferrite bead on both inside and outside leads.
Close to the IC pins, two capacitors of different value should be
used to decouple the main supply (VP) and the midpoint supply
pin, VMID. Guidance on these matters is also generally in-
cluded in applications schematics.
EXTERNAL
FREQUENCY
REFERENCE
50kΩ
a. Biasing FDIN from Supply when Using
External Frequency Reference
Gain Distribution
As in all receivers, the most critical decisions in effectively using
the AD607 relate to the partitioning of gain between the various
subsections (Mixer, IF Amplifier, Demodulators) and the place-
ment of filters, so as to achieve the highest overall signal-to-
noise ratio and lowest intermodulation distortion.
AD607
FDIN
EXTERNAL
FREQUENCY
REFERENCE
50kΩ
VMID
Figure 42 shows the main RF/IF signal path at maximum and
minimum signal levels.
C
BYPASS
b. Biasing FDIN from VMID when Using
External Frequency Reference
Figure 41. Suggested Methods for Biasing Pin FDIN
at VP/2
I
±1.23V
MAX OUTPUT
±1.3V
±54mV
±54mV
±560mV
±154mV
IOUT
MAX OUTPUT
MAX INPUT
MAX INPUT
MAX OUTPUT MAX INPUT
IFOP DMIP
MXOP IFHI
IF BPF
RFHI
QOUT
IF BPF
Q
LOIP
(VMID)
330Ω
330Ω
CONSTANT
–16dBm
(±50mV)
(TYPICAL
IMPEDANCE)
(LOCATION OF OPTIONAL
SECOND IF FILTER)
Figure 42. Signal Levels for Minimum and Maximum Gain
REV. 0
–17–
AD607
30µA
˜
As noted earlier, the gain in dB is reduced linearly with the volt-
age VG on the GAIN pin. Figure 43 shows how the mixer and
IF strip gains vary with VG when GREF is connected to VMID
(1.5 V) and a supply voltage of 3 V is used. Figure 44 shows
how these vary when GREF is connected to a 1.23 V reference.
4.5µA
77µA
LAST IF STAGE
IFOP
ZERO
1.5V + 316mV
I
2
C
Q1
Q2
90dB
80dB
GAIN
TO INTERNAL
GAIN CONTROL
70dB
1.5V
(67.5dB)
CAGC
(EXT)
60dB
IF OUTPUT
AVERAGE OF IC2 IS
FORCED TO 4.5µA BY
INTEGRATION IN CAGC
50dB
40dB
30dB
20dB
10dB
0dB
IF GAIN
4.5µA
(INT)
COMM
(21.5dB)
Figure 45. Simplified Schematic of AGC Detector
MIXER GAIN
Acting against this is an internally generated 4.5 µA pull-down
current, which operates to within a few millivolts of ground. As
G, the voltage at the GAIN/RSSI pin, rises, the gain falls, so re-
ducing the amplitude of the IF output and reducing the ampli-
tude of the current spike in Q2; eventually a point is reached
where its average collector current is balanced by the pull-down
current, and the charging ceases. It will be apparent that the
loop filter is essentially a perfect integrator.
(7.5dB)
(1.5dB)
2.2V
0.4V
1.8V
0
1V
NORMAL OPERATING RANGE
2V
V
V
g
Figure 43. Gain Distribution for GREF = 1.5 V
90dB
This simple system can be used because the input impedance of
the gain-control system, also internally tied to the GAIN/RSSI
pin, is several megohms, and its bias current is small. The volt-
age VG may be used as an RSSI output; however, if it is to be
heavily loaded, a buffer amplifier must be used.
80dB
70dB
60dB
50dB
40dB
30dB
20dB
10dB
0dB
(67.5dB)
IF GAIN
Note that, unlike a post-demodulation AGC detector (via DSP),
this scheme responds to signal plus noise. Thus, when operating
at high gains, the AGC loop will “see” a substantial output at
the IFOP node, even though a filter may be added by the user
between the pins IFOP and DMIP. This will trick the loop into
lowering the gain until the composite output signal (IF plus
noise) reaches the reference level and satisfies the average-
current requirement. In these circumstances, the wanted signal
will be smaller than expected. Thus, the internal AGC system
will result in a slight compression of the demodulated output for
very small signal levels.
(21.5dB)
MIXER GAIN
(7.5dB)
(1.5dB)
0.328V
1.64V
0
1V
NORMAL OPERATING RANGE
2V
V
g
Figure 44. Gain Distribution for GREF = 1.23 V
AGC Discharge Time
Using the Internal AGC Detector
The discharge current is approximately 4.5 µA; thus, to restore
gain in the event of a rapid drop-out requires a time of
T = C × VG/4.5 µA. Using a 1 nF capacitor, and noting that an
80 dB gain change corresponds to 1.6 V, the discharge time is
355 µs. Note, however, that when GREF is tied to a different
value, the scaling changes. For GREF = 1.23 V, the scale factor
is 16.4 mV/dB, 80 dB corresponds to a 1.312 V change, and the
discharge time decreases to 290 µs.
The AD607 includes a detector cell at the output of the IF am-
plifier that allows it to provide its own AGC and output-leveling
function in receiver applications where DSP support is not
needed. It is only necessary to connect a filter capacitor between
the GAIN pin and ground to invoke this feature. The voltage
appearing on this pin may then be used as an RSSI output, with
the scaling discussed earlier; note particularly that the voltage on
GREF continues to determine this scaling.
VG could also be expressed in dB: with a scaling of 20 mV/dB, it
works out to T = C × P × 44,000, where P is the change in input
power, expressed in dB. Thus, using C = 1 nF, checking the
time needed for 80 dB we get T = 355 µs. For the case where
the scaling is 16.4 mV/dB, T = C × P × 36,000.
Figure 45 shows a simplified schematic of the detector. Transis-
tor Q2 remains cut off by a 300 mV bias (when VP = 3 V; in gen-
eral, ≈ VP/10) until the positive tip of the IF waveform causes
it to briefly conduct, charging the AGC filter capacitor CAGC in
a positive direction. The voltage across this capacitor is VG.
The AD607’s AGC detector delivers only one brief charging
pulse per cycle of the IF. At a 10.7 MHz IF, for example, this is
every 93 ns. When the AGC system is in equilibrium, this pulse
–18–
REV. 0
AD607
of current exactly balances the 4.5 µA discharge current. (It
makes no difference what the actual value of VG is at that point,
since the AGC filter is an integrator.)
pass filter does. This “input” is an INCREASED AMPLITUDE
required at IFOP. The AGC loop thus does not level the output
at IFOP.
Thus, at 20 mV/dB
Reasons for Using a Larger AGC Capacitor
1. In applications where gain modulation may be troublesome,
raise the capacitor from 1 nF to 2.7 nF; the 80 dB slew time
(at 20 mV/dB) is now close to 1 ms.
IT
C
4.5 µA × 93 ns
1 nF
VRIPPLE
=
=
= 0.42 mV
2. As the IF is lowered, the capacitor must be increased accord-
ingly if gain ripple is to be avoided. Thus, to achieve the
same ripple at 455 kHz requires the 1 nF capacitor to be in-
creased to 0.022 µF.
This corresponds to 0.021 dB, and the ripple will modulate the
gain by that amount over each cycle. The effect of such modula-
tion on the signal is hard to quantify, but it roughly translates to
a 2% amplitude modulation. Also, the gain ripple depends on
the scale factor. For this example, at GREF = 1.23 V and a
16.4 mV/dB scale factor, the gain ripple increases to 0.025 dB.
3. In AM applications, the AGC loop must not track the modu-
lation envelope. The objective should be that the gain should
not vary by more than the amount required to introduce, say,
1% THD distortion at the lowest modulation frequency, say,
300 Hz. Note that in AM applications it is the modulation
bandwidth that determines the required AGC filter capaci-
tor, not the IF.
AGC Charge Time
When the gain is too high, the IF amplifier will be overdriven to
produce a square wave output (roughly) of ±560 mV. If per-
fectly square and time- and amplitude-symmetric, this would be
sliced at the 300 mV level to generate a current of 76 µA/2, or
38 µA. After subtracting the 4.5 µA, we should have about 33 µA.
4. In some applications, even slower AGC may be desired than
that required to prevent modulation tracking.
In fact, the maximum ramp-up current is about 20 µA, because
the waveform is not a crisp square wave (and as the loop ap-
proaches equilibrium it is more nearly sinusoidal). Thus, the
ramp-up rate is 20/4.5 = 4.4 times faster than the discharge rate.
In our example, a 1.6 V change will require about 1.5 ms using
C = 1 nF.
AD607 EVALUATION BOARD
The AD607 evaluation board (Figures 46 and 47) consists of an
AD607, ground plane, I/O connectors, and a 10.7 MHz band-
pass filter. The RF and LO ports are terminated in 50 Ω to
provide a broadband match to external signal generators to al-
low a choice of RF and LO input frequencies. The IF filter is at
10.7 MHz and has 330 Ω input and output terminations; the
board is laid out to allow the user to substitute other filters for
other IFs.
Applications Hints
Do not place a resistor from Pin 12 to Ground: The resistor
converts the integrator—ideal for AGC—into a low-pass filter.
An integrator needs no input to sustain a given output; a low-
VPOS
C15
JUMPER
0.1µF
GND
R10
4.99kΩ
R11
OPEN
C11
10nF
C12
C1
0.1µF
0.1µF
FDIN
PRUP
LO
R8
51.1Ω
FDIN
COM1
PRUP
LOIP
RFLO
RFHI
GREF
MXOP
VMID
IFHI
VPS1
FLTR
IOUT
QOUT
VPS2
DMIP
IFOP
C3
R1
1kΩ
10nF
R9
0
C10
1nF
C13
C14
0
0
I
R7
51.1Ω
C2
0.1µF
C16
1nF
AD607
C4
Q
C9
1nF
47pF
R2
316Ω
RF
R6
51.1Ω
R5
JUMPER
R4
IF
COM2
GAIN
IFLO
332Ω
0
RSSI
C5
1nF
R3
332Ω
C6
C7
1nF
0.1µF
C8
0.1µF
AD607 EVALUATION BOARD
(AS RECEIVED)
VPOS
VPOS
R15
50kΩ
R13
50kΩ
R17
OPEN
R18
OPEN
C18
SHORT
C19
ANYTHING
FDIN
FDIN
FDIN
FDIN
R14
51.1Ω
C20
SHORT
R16
OPEN
C17
10nF
R12
OPEN
R19
RSOURCE
VMID
VMID
MOD FOR DC COUPLED INPUT
MOD FOR LARGE MAGNITUDE
AC COUPLED INPUT
Figure 46. Evaluation Board
–19–
REV. 0
AD607
Figure 47. Evaluation Board Layout
–20–
REV. 0
AD607
The board provides SMA connectors for the RF and LO port
inputs, the demodulated I and Q outputs, the manual gain con-
trol (MGC) input, the PLL input, and the power-up input. In
addition, the IF output is also available at an SMA connector;
this may be connected to the PLL input for carrier recovery to
realize synchronous AM and FM detection via the I and Q de-
modulators, respectively. Table III lists the AD607 Evaluation
Board’s I/O Connectors and their functions.
Table III. AD607 Evaluation Board Input and Output Connections
Reference
Designation
Connector
Type
Approximate
Signal Level
Description
Coupling
Comments
J1
SMA
Frequency
Detector Input
DC
±400 mV
This pin needs to be biased at VMID
and ac coupled when driven by an
external signal generator.
J2
J3
J4
J5
SMA
SMA
SMA
SMA
Power Up
LO Input
RF Input
DC
AC
AC
DC
CMOS Logic
Level Input
–16 dBm
(±50 mV)
–15 dBm max
(±54 mV)
0.4 V to 2.0 V
(3 V Supply)
(GREF = VMID)
Tied to Positive Supply by Jumper J10.
Input is terminated in 50 Ω.
Input is terminated in 50 Ω.
MGC Input
or
RSSI Output
Jumper is set for Manual Gain Control
Input; See Table I for Control Voltage
Values.
J6
J7
J8
J9
SMA
SMA
SMA
Jumper
IF Output
Q Output
I Output
AC
AC
AC
NA
NA
NA
NA
NA
This signal level depends on the
AD607’s gain setting.
This signal level depends on the
AD607’s gain setting.
This signal level depends on the
AD607’s gain setting.
Ties GREF
to VMID
Sets gain-control Scale Factor (SF);
SF = 75/VMID in dB/V, where
VMID = VPOS/2.
J10
T1
T2
Jumper
Ties Power-Up
to Positive
Supply
NA
DC
DC
NA
DC
0 V
Remove to test Power Up/Down.
Terminal Pin
Terminal Pin
Power Supply
Positive Input
(VPS1, VPS2)
2.7 V to 5.5 V
Draws 8.5 mA at
midgain connection.
Power Supply
Return (GND)
REV. 0
–21–
AD607
In operation (Figure 48), the AD607 evaluation board draws
about 8.5 mA at midgain (59 dB). Use high impedance probes
to monitor signals from the demodulated I and Q outputs and
the IF output. The MGC voltage should be set such that the
signal level at DMIP does not exceed ±150 mV; signal levels
above this will overload the I and Q demodulators. The inser-
tion loss between IFOP and DMIP is typically 3 dB if a simple
low-pass filter (R8 and C2) is used and higher if a reverse-
terminated bandpass filter is used.
If the AD607’s internal AGC detector is used, then the GAIN/
RSSI (Pin 12) becomes an output and the RSSI voltage appears
across C12, which serves as an integrating capacitor. This volt-
age must be monitored by a high impedance (100 kΩ minimum)
probe. The internal AGC loop holds the IF voltage at IFOP
(Pin 14) at ±300 mV; in this application, about 6 dB of attenua-
tion is needed between pins IFOP and DMIP to avoid overload-
ing the I and Q demodulators.
HP 3326
HP 6632A
SYNTHESIZED
PROGRAMMABLE
POWER SUPPLY
2.7V–6V
SIGNAL GENERATOR
10.710 MHz
FLUKE 6082A
SYNTHESIZED
SIGNAL GENERATOR
240 MHz
FDIN
VPOS
AD607
EVALUATION
BOARD
I OUTPUT
TEKTRONIX
11402A
OSCILLOSCOPE
WITH 11A32
PLUGIN
RF
MCL
ZFSC–2–1
COMBINER
Σ
Q OUTPUT
HP 8656A
SYNTHESIZED
LO
MGC
SIGNAL GENERATOR
240.02 MHz
HP 9920
IEEE CONTROLLER
HP9121
HP 8656A
DATA PRECISION
SYNTHESIZED
SIGNAL GENERATOR
229.3 MHz
DVC8200
PROGRAMMABLE
VOLTAGE SOURCE
DISK DRIVE
IEEE –488 BUS
Figure 48. Evaluation Board Test Setup
–22–
REV. 0
AD607
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
20-Pin Plastic SSOP (RS-20)
20
11
0.212 (5.38)
0.205 (5.207)
0.311 (7.9)
0.301 (7.64)
PIN 1
10
1
0.07 (1.78)
0.295 (7.50)
0.271 (6.90)
0.066 (1.67)
0.037 (0.94)
8°
0°
0.022 (0.559)
0.008 (0.203)
0.002 (0.050)
0.0256 (0.65)
BSC
0.009 (0.229)
0.005 (0.127)
1. LEAD NO. 1 IDENTIFIED BY A DOT.
2. LEADS WILL BE EITHER TIN PLATED OR SOLDER DIPPED
IN ACCORDANCE WITH MIL-M-38510 REQUIREMENTS
REV. 0
–23–
–24–
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