AD608ARZ [ADI]
Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem; 低功率混频器/限制器/ RSSI 3 V接收器IF子系统
| 型号： | AD608ARZ |
| 厂家： | 
ADI |
| 描述： | Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem |
| 文件： | 总16页 (文件大小：326K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power Mixer/Limiter/RSSI
3 V Receiver IF Subsystem
AD608
The RF and local oscillator (LO) bandwidths both exceed
500 MHz. In a typical IF application, the AD608 can accept the
output of a 240 MHz surface acoustic wave (SAW) filter and down-
convert it to a nominal 10.7 MHz IF with a conversion gain of
24 dB (ZIF = 165 Ω). The AD608 logarithmic/limiting amplifier
section handles any IF from low frequency (LF) up to 30 MHz.
FEATURES
Mixer
−15 dBm, 1 dB compression point
−5 dBm IP3
24 dB conversion gain
>500 MHz input bandwidth
Logarithmic/limiting amplifier
80 dB RSSI range
3ꢀ phase stability over 80 dB range
Low power
The mixer is a doubly balanced gilbert-cell mixer and operates
linearly for RF inputs spanning −95 dBm to −15 dBm. It has a
nominal −5 dBm third-order intercept. An on-board LO pre-
amplifier requires only −16 dBm of LO drive. The current output
of the mixer drives a reverse-terminated, industry-standard
10.7 MHz, 330 Ω filter.
21 mW at 3 V power consumption
CMOS-compatible power-down to 300 μW typical
200 ns enable/disable time
The nominal logarithmic scaling is such that the output is +0.2 V
for a sinusoidal input to the IF amplifier of −75 dBm and +1.8 V
at an input of +5 dBm; over this range, the logarithmic confor-
mance is typically 1 dB. The logarithmic slope is proportional
to the supply voltage. A feedback loop automatically nulls the
input offset of the first stage down to the submicrovolt level.
APPLICATIONS
PHS, GSM, TDMA, FM, or PM receivers
Battery-powered instrumentation
Base station RSSI measurements
The AD608 limiter output provides a hard-limited signal output
at 400 mV p-p. The voltage gain of the limiting amplifier to this
output is more than 100 dB. Transition times are 11 ns and the
phase is stable to within 3ꢀ at 10.7 MHz for signals from −75 dBm
to +5 dBm.
GENERAL DESCRIPTION
The AD608 provides a low power, low distortion, low noise mixer
as well as a complete, monolithic logarithmic/limiting amplifier
that uses a successive-detection technique. In addition, the AD608
provides both a high speed received signal strength indicator
(RSSI) output with 80 dB dynamic range and a hard-limited
output. The RSSI output is from a two-pole postdemodulation
low-pass filter and provides a loadable output voltage of 0.2 V to
1.8 V. The AD608 operates from a single 2.7 V to 5.5 V supply
at a typical power level of 21 mW at 3 V.
The AD608 is enabled by a CMOS logic-level voltage input,
with a response time of 200 ns. When disabled, the standby
power is reduced to 300 μW within 400 ns.
The AD608 is specified for the industrial temperature range of
−25ꢀC to +85ꢀC for 2.7 V to 5.5 V supplies and −40ꢀC to +85ꢀC for
3.0 V to 5.5 V supplies. This device comes in a 16-lead plastic SOIC.
FUNCTIONAL BLOCK DIAGRAM
3dB NOMINAL
INSERTION LOSS
110dB LIMITER GAIN
90dB RSSI
24dB MIXER GAIN
RSSI OUTPUT
20mV/dB
RSSI
7 FULL-WAVE
IF INPUT
11
12
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
RECTIFIER CELLS
–75dBm TO
0.2V TO 1.8V
2
+15dBm
2MHz
LPF
5
6
RFHI
COM3
VPS2
MIXER
10.7MHz
BAND-PASS
FILTER
IFHI
RF INPUT
MXOP
–95dBm TO
7
8
9
14 +2.7V TO 5.5V
1
–15dBm
BPF
DRIVER
LMOP
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
330Ω
15 LIMITER
OUTPUT
400mV p-p
330Ω
RFLO
10nF
LO
PREAMP
VMID
FINAL
LIMITER
10
13
+
IFLO
100nF
100Ω
MIDSUPPLY
IF BIAS
FDBK
18nF
±50µA
BIAS
AD608
VPS1 COM1
LOHI COM2
4
PRUP
1
2
3
16
2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
1
–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.
39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.
2
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©1996–2009 Analog Devices, Inc. All rights reserved.
AD608
TABLE OF CONTENTS
Features .............................................................................................. 1
Mixer...............................................................................................9
Mixer Gain .....................................................................................9
IF Filter Terminations................................................................ 10
The Logarithmic IF Amplifier.................................................. 10
Offset Feedback Loop................................................................ 10
RSSI Output ................................................................................ 11
Digitizing the RSSI..................................................................... 11
Power Consumption .................................................................. 11
Troubleshooting.......................................................................... 11
Applications Information.............................................................. 12
Outline Dimensions....................................................................... 13
Ordering Guide .......................................................................... 13
Applications....................................................................................... 1
General Description......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 4
Thermal Resistance ...................................................................... 4
ESD Caution.................................................................................. 4
Pin Configuration and Function Descriptions............................. 5
Typical Performance Characteristics ............................................. 6
Test Circuits....................................................................................... 8
Theory of Operation ........................................................................ 9
REVISION HISTORY
2/09—Rev. B to Rev. C
Updated Format..................................................................Universal
Reorganized Layout............................................................Universal
Change to General Description Section........................................ 1
Changes to DC Level Parameter, Operating Range Parameter,
and TMIN to TMAX Parameter, Table 1 .......................................... 3
Added Typical Performance Characteristics Heading ................ 6
Added Test Circuits Heading.......................................................... 8
Changes to Figure 17 and Figure 19............................................... 8
Change to Figure 22 ......................................................................... 9
Changes to Table 5............................................................................ 9
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 13
Rev. C | Page 2 of 16
AD608
SPECIFICATIONS
TA = 25ꢀC, supply = 3 V, dBm is referred to 50 Ω, unless otherwise noted.
Table 1.
Parameter
Conditions1
Min
Typ
Max
Unit
MIXER PERFORMANCE
RF and LO Frequency Range
LO Power
Conversion Gain
Noise Figure
500
−16
24
MHz
dBm
dB
Input terminated in 50 Ω
Driving doubly terminated 330 Ω IF filter, ZIF = 165 Ω
Matched input, fRF = 100 MHz
19
28
11
dB
Matched input, fRF = 240 MHz
16
dB
1 dB Compression Point
Third-Order Intercept
Input Resistance
Input Capacitance
LIMITER PERFORMANCE
Gain
Input terminated in 50 Ω
fRF = 240 MHz and 240.02 MHz, fLO = 229.3 MHz
fRF = 100 MHz (see Table 5)
−15
−5
1.9
3
dBm
dBm
kΩ
fRF = 100 MHz (see Table 5)
pF
Full temperature and supply range
3° rms phase jitter at 10.7 MHz
280 kHz IF bandwidth
110
−75
dB
dBm
Limiting Threshold
Input Resistance
Input Capacitance
Phase Variation
DC Level
Output Level
10
3
3
kΩ
pF
Degrees
V
mV p-p
ns
Ω
−75 dBm to +5 dBm IF input signal at 10.7 MHz
Center of output swing (VPOS – 1 V)
Limiter output driving 5 kΩ load
Driving a 5 pF load
2
400
11
200
Rise and Fall Times
Output Impedance
RSSI PERFORMANCE
Nominal Slope
Nominal Intercept
Minimum RSSI Voltage
Maximum RSSI Voltage
RSSI Voltage Intercept
Logarithmic Linearity Error
RSSI Response Time
Output Impedance
POWER-DOWN INTERFACE
Logic Threshold
At 10.7 MHz
At VPOS = 3 V; proportional to VPOS
17.27
1.57
20
23.27
1.82
mV/dB
dBm
V
V
V
dB
ns
Ω
−85
0.2
1.8
−75 dBm input signal
+5 dBm input signal
0 dBm input signal
−75 dBm to +5 dBm input signal at IFHI
90% RF to 50% RSSI
1
200
250
At midscale
System active on logic high
For logic high
Active limiter output
To 200 μA supply current
1.5
75
200
400
100
V
Input Current
mA
ns
ns
μA
Power-Up Response Time
Power-Down Response Time
Power-Down Current
POWER SUPPLY
Operating Range
−25°C to +85°C
−40°C to +85°C
VPOS = 3 V
2.7
3.0
5.5
5.5
V
V
mA
Powered Up Current
OPERATING TEMPERATURE
TMIN to TMAX
7.3
VPOS = 2.7 V to 5.5 V
VPOS = 3.0 V to 5.5 V
−25
−40
+85
+85
°C
°C
1 VPOS is used to refer collectively to the VPS1 and VPS2 pins.
Rev. C | Page 3 of 16
AD608
ABSOLUTE MAXIMUM RATINGS
Table 2.
THERMAL RESISTANCE
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Parameter
Rating
Supply Voltages VPS1, VPS2
Internal Power Dissipation
Temperature Range
Storage Temperature Range
Lead Temperature (Soldering 60 sec)
+6 V
600 mW
−40°C to +85°C
−65°C to +150°C
300°C
Table 3.
Package Type
θJA
Unit
16-Lead SOIC
110
°C/W
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. C | Page 4 of 16
AD608
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PRUP
VPS1
COM1
LOHI
1
2
3
4
5
6
7
8
16
15 LMOP
VPS2
14
AD608
COM2
RFHI
13 FDBK
12 COM3
11 RSSI
10 IFLO
TOP VIEW
(Not to Scale)
RFLO
MXOP
VMID
9
IFHI
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
Mnemonic
VPS11
COM1
LOHI
COM2
RFHI
Description
1
2
3
4
5
6
Positive Supply Input
Common
Local Oscillator Input Connection
Common
RF Input, Noninverting
RF Input, Inverting
RFLO
7
8
9
10
11
12
13
14
15
16
MXOP
VMID
IFHI
IFLO
RSSI
COM3
FDBK
VPS21
LMOP
PRUP
Mixer Output
Midpoint Supply Bias Output
IF Input, Noninverting
IF Input, Inverting
Received Signal Strength Indicator Output
Output Common
Offset-Null Feedback Loop Output
Limiter Positive Supply Input
Limiter Output
Power-Up
1 VPOS is used to refer collectively to the VPS1 and VPS2 pins in this data sheet.
Rev. C | Page 5 of 16
AD608
TYPICAL PERFORMANCE CHARACTERISTICS
25.0
3.0
2.5
2.0
1.5
1.0
0.5
0
+85°C
+25°C
–25°C
24.5
24.0
23.5
23.0
22.5
22.0
0
50
100 150 200 250 300 350 400 450 500
RF FREQUENCY (MHz)
–80
–70
–60
–50
–40
–30
–20
–10
0
10
INPUT POWER (dBm)
Figure 6. IF RSSI Output vs. Input Power and Temperature,
3 V Supply (See Figure 15)
Figure 3. Mixer Conversion Gain vs. RF Frequency
4
3
2
0
–1
–2
–3
–4
–5
–6
–7
–8
1
3V
0
5V
–1
–2
–3
–4
–80
–70
–60
–50
–40
–30
–20
–10
0
10
0
10
20
30
40
50
60
70
80
INPUT POWER (dBm)
IF FREQUENCY (MHz)
Figure 7. RSSI Error vs. Input Power
(See Figure 15)
Figure 4. Mixer IF Port Bandwidth
3.0
2.5
2.0
1.5
1.0
0.5
0
800mV/DIV
100ns/DIV
5V
1V/DIV
3V
100ns/DIV
–80
–70
–60
–50
–40
–30
–20
–10
0
10
INPUT POWER AT IFHI (dBm)
Figure 5. IF RSSI Output vs. Input Power at IFHI and Supply Voltage,
Ambient Temperature (See Figure 15)
Figure 8. RSSI Power-Up Response
(See Figure 19)
Rev. C | Page 6 of 16
AD608
5
4
200mV/DIV
3
2
1
0
–1
–2
–3
–4
–5
800mV/DIV
50ns/DIV
–80
–70
–60
–50
–40
–30
–20
–10
0
10
INPUT POWER AT IFHI (dBm)
Figure 9. RSSI Pulse Response/RSSI Rise Time
(See Figure 16)
Figure 12. Limiter Phase Performance vs. Input Power at IFHI
(See Figure 21)
10
9
8
7
6
5
4
3
2
1
0
60mV/DIV
20ns/DIV
–80
–70
–60
–50
–40
–30
–20
–10
0
10
INPUT POWER AT IFHI (dBm)
Figure 10. Limiter Rise and Fall Times
(See Figure 20)
Figure 13. Limiter RMS Jitter Performance vs. Input Power at IFHI
(See Figure 21)
100ns/DIV
220mV/DIV
1V/DIV
100ns/DIV
Figure 11. Limiter Power-Up Response Time
(See Figure 17)
Rev. C | Page 7 of 16
AD608
TEST CIRCUITS
PRUP INPUT
U1A
TRIGGER
U1B
47k
Ω
4.7kΩ
1
2
3
4
5
6
7
8
16
VPS1
PRUP
0.1µF
VPOS
47kΩ
COM1
LMOP 15
NC
1nF
1nF
18nF
18nF
14
13
12
LO INPUT
LOHI
COM2
RFHI
VPS2
FDBK
COM3
1
2
3
4
5
6
7
8
VPS1
PRUP
16
15
14
13
0.1µF
0.1µF
VPOS
51.1Ω
LMOP OUTPUT
RSSI OUTPUT
COM1
LMOP
VPS2
FDBK
COM3
RSSI
IFLO
IFHI
0.1µF
LOHI
100
Ω
RF INPUT
51.1Ω
51.1Ω
RFLO
MXOP
VMID
RSSI 11
NC
COM2
RFHI
10nF
1nF
1nF
18nF
IFLO
10
9
12
11
10
9
100Ω
1nF
51.1Ω
IFHI
RFLO
MXOP
VMID
10nF
AD608
332
Ω
332Ω
332
Ω
0.1µF
0.1µF
0.1µF
AD608
301
Ω
301Ω
IF OUTPUT
332Ω
IF INPUT
54.9
Ω
0.1µF
54.9Ω
NC = NO CONNECT
U1 – 74HC00
Figure 14. IF Test Board Schematic
Figure 18. Mixer Test Board Schematic
AGILENT
HP54120A
DIGITAL
OSCILLOSCOPE
TEKRONIX
P6201
FLUKE 6082A
SYNTHESIZER
IF TEST BOARD
DIGITAL
MULTIMETER
(DMM)
IF TEST BOARD
FLUKE 6082A
SYNTHESIZER
FET
PROBE
IFHI
RSSI
CH 1
CH 2
10.7MHz
0dBm
IFHI
RSSI
VPOS
DMM
PRUP
VPOS
10.7MHz
AGILENT
HP34401A
DC POWER
SUPPLY
(DCPS)
DCPS
3V
DCPS 3V
AGILENT
HP3366A
AGILENT
HP3366A
Figure 15. Test Circuit for IF RSSI Output vs. Input Power at IFHI and Supply
Voltage, Ambient Temperature (Figure 5); IF RSSI Output vs. Input Power and
Temperature, 3 V Supply (Figure 6); and RSSI Error vs. Input Power (Figure 7)
Figure 19. Test Circuit for RSSI Power-Up Response (Figure 8)
AGILENT
HP54120A
TEKRONIX
P6201
FLUKE 6082A
SYNTHESIZER
IF TEST BOARD
IFHI LMOP
VPOS
CH 1
TEKRONIX
P6201
FLUKE 6082A
SYNTHESIZER
IF TEST BOARD
IFHI RSSI
FET
PROBE
DIGITAL
OSCILLOSCOPE
FET
PROBE
CH 2
COUPLER
10.7MHz
0dBm
10.7MHz
0dBm
MCL
ZDC-20-1
VPOS
AGILENT
HP54120A
DCPS 3V
DCPS 3V
DIGITAL
AGILENT
HP3366A
AGILENT
HP3366A
OSCILLOSCOPE
Figure 16. Test Circuit for RSSI Pulse Response/RSSI Rise Time (Figure 9)
Figure 20. Test Circuit for Limiter Rise and Fall Times (Figure 10)
TEKTRONIX
AGILENT
HP54120A
FLUKE 6082A
MCL
P6201
IF TEST BOARD
IFHI RSSI
SYNTHESIZER ZDC-20-1
TEKRONIX
P6201
DIGITAL
FLUKE 6082A
SYNTHESIZER
FET
PROBE
IF TEST BOARD
COUPLER
10.7MHz
OSCILLOSCOPE
AGILENT
HP8447A
FET
PROBE
IFHI
LMOP
CH 1
CH 2
AGILENT
HP8494A
HP8495A
10.7MHz
0dBm
DCPS
3V
BPF
CH 1
TRIG
PRUP
280kHz BW
10.7MHz CF
AGILENT
HP3366A
VPOS
DCPS 3V
TOKO SK107MK1-A0-10
AGILENT
HP54120A
AGILENT
HP3366A
DIGITAL
OSCILLOSCOPE
Figure 17. Test Circuit for Limiter Power-Up Response Time (Figure 11)
Figure 21. Test Circuit for Limiter Phase Performance vs. Input Power at IFHI
(Figure 12) and Limiter RMS Jitter Performance vs. Input Power at IFHI (Figure 13)
Rev. C | Page 8 of 16
AD608
THEORY OF OPERATION
The AD608 consists of a mixer followed by a logarithmic IF
strip with RSSI and hard-limited outputs (see Figure 22).
MIXER GAIN
The conversion gain of the mixer is the product of its trans-
conductance and the impedance seen at Pin MXOP. For a 330 Ω
parallel-terminated filter at 10.7 MHz, the load impedance is
165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV (or
891 mV) centered on the midpoint of the supply voltage. For
other load impedances, the expression for the gain in decibels is
MIXER
The mixer is a doubly balanced, modified gilbert-cell mixer. Its
maximum input level for linear operation is either 56.2 mV,
regardless of the impedance across the mixer inputs, or −15 dBm
for a 50 Ω input termination. The input impedance of the mixer
can be modeled as a simple parallel RC network; the resistance
and capacitance values vs. frequency are listed in Table 5. The
bandwidth from the RF input to the IF output at the MXOP pin
is −1 dB at 30 MHz and then rapidly decreases as frequency
increases (see Figure 4).
G
dB = 20 log10(0.0961 RL)
where:
G
dB is the gain in decibels.
RL is the load impedance at Pin MXOP.
The gain of the mixer can be increased or decreased by changing
RL. The limitations on the gain are the 6 mA maximum output
current at MXOP and the maximum allowable voltage swing at
Pin MXOP, which is 1.0 V for a 3 V supply or 5 V supply.
3dB NOMINAL
110dB LIMITER GAIN
90dB RSSI
24dB MIXER GAIN
INSERTION LOSS
RSSI OUTPUT
20mV/dB
RSSI
7 FULL-WAVE
IF INPUT
11
12
±6mA MAX OUTPUT
RECTIFIER CELLS
–75dBm TO
(±890mV INTO 165Ω)
0.2V TO 1.8V
2
+15dBm
2MHz
LPF
5
6
RFHI
COM3
VPS2
MIXER
10.7MHz
BAND-PASS
FILTER
IFHI
RF INPUT
MXOP
–95dBm TO
7
8
9
14 2.7V TO 5.5V
1
–15dBm
BPF
DRIVER
LMOP
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
330Ω
15 LIMITER
OUTPUT
330Ω
RFLO
10nF
LO
PREAMP
VMID
400mV p-p
FINAL
LIMITER
10
13
+
IFLO
100nF
100Ω
MIDSUPPLY
IF BIAS
FDBK
18nF
±50µA
BIAS
AD608
LOHI
VPS1 COM1
COM2
4
PRUP
1
2
3
16
2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
1
–15dBm = ±56mV MAXIMUM FOR LINEAR OPERATION.
39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI ACCURACY.
2
Figure 22. Functional Block Diagram
Table 5. Mixer Input Impedance vs. Frequency
Frequency (MHz)
Resistance (Ω)
Capacitance (pF)
45
70
2800
2600
1900
1200
760
3.1
3.1
3.0
3.1
3.2
3.4
3.6
100
200
300
400
500
520
330
Rev. C | Page 9 of 16
AD608
limiter output drive is 200 mV (400 mV p-p) into a 5 kΩ load.
In the absence of an input signal, the limiter output limits noise
fluctuations, producing an output that continues to swing
400 mV p-p, but with random zero crossings.
IF FILTER TERMINATIONS
The AD608 was designed to drive a parallel-terminated 10.7 MHz
band-pass filter (BPF) with a 330 Ω impedance. With a 330 Ω
parallel-terminated filter, Pin MXOP sees a 165 Ω termination,
and the gain is nominally 24 dB. Other filter impedances and
gains can be accommodated by either accepting an increase or
decrease in gain in proportion to the filter impedance or by
keeping the impedance seen by MXOP at a nominal 165 Ω (by
using resistive dividers or matching networks). Figure 23 shows a
simple resistive voltage divider for matching an assortment of
filter impedances, and Table 6 lists component values.
OFFSET FEEDBACK LOOP
Because the logarithmic amplifier is dc-coupled and has more
than 110 dB of gain from the input to the limiter output, a dc
offset at its input of even a few microvolts causes the output to
saturate. Therefore, the AD608 uses a low frequency feedback
loop to null the input offset. Referring to Figure 23, the loop
consists of a current source driven by the limiter, which sends
50 μA current pulses to Pin FDBK. The pulses are low-pass filtered
by a π-network consisting of C1, R4, and C5. The smoothed dc
voltage that results is subtracted from the input to the IF amplifier
at Pin IFLO. Because this is a high gain amplifier with a feedback
loop, care should be taken in layout and component values to
prevent oscillation. Recommended values for the common IFs
of 450 kHz, 455 kHz, 6.5 MHz, and 10.7 MHz are listed in Table 6.
THE LOGARITHMIC IF AMPLIFIER
The logarithmic IF amplifier consists of five amplifier stages
of 16 dB gain each, plus a final limiter. The IF bandwidth is
30 MHz (−1 dB), and the limiting gain is 110 dB. The phase
skew is 3ꢀ from −75 dBm to +5 dBm (approximately 111 μV p-p
to 1.1 V p-p). The limiter output impedance is 200 Ω, and the
12dB NOMINAL
110dB LIMITER GAIN
90dB RSSI
24dB MIXER GAIN
INSERTION LOSS
(ASSUMES 6dB IN FILTER)
7 FULL-WAVE
RECTIFIER CELLS
2MHz
BAND-PASS
FILTER
11
RSSI
5
6
RFHI
COM3
VPS2
LPF
12
14
R2
MIXER
IFHI
MXOP
7
8
9
BPF
DRIVER
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
R3
15 LMOP
R1
RFLO
C5
R4
LO
VMID
FINAL
LIMITER
10
13
PREAMP
+
IFLO
100nF
MIDSUPPLY
IF BIAS
C1
FDBK
±50µA
BIAS
AD608
VPS1 COM1
LOHI COM2
4 16
PRUP
1
2
3
5V
47kΩ
C1
1µF
C2
100pF
LO INPUT
–16dBm
CMOS LOGIC
INPUT
Figure 23. Applications Diagram for Common IFs and Filter Impedances
Table 6. AD608 Filter Termination and Offset-Null Feedback Loop Resistor and Capacitor Values for Common IFs
Filter Termination Resistor
Offset-Null
Feedback Loop Values
Values1 for 24 dB of Mixer Gain
IF
Filter Impedance
1500 Ω
1500 Ω
1000 Ω
330 Ω
R1
R2
R3
R4
C1
C5
450 kHz2
455 kHz
6.5 MHz
10.7 MHz
174 Ω
174 Ω
178 Ω
330 Ω
1330 Ω
1330 Ω
825 Ω
0 Ω
1500 Ω
1500 Ω
1000 Ω
330 Ω
1000 Ω
1000 Ω
100 Ω
100 Ω
200 nF
200 nF
18 nF
18 nF
100 nF
100 nF
10 nF
10 nF
1 Resistor values were calculated so that R1 + R2 = ZFILTER and R1||(R2 + ZFILTER) = 165 Ω.
2 Operation at IFs of 450 kHz and 455 kHz requires use of an external low-pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple at 900 kHz).
Rev. C | Page 10 of 16
AD608
supply as a reference, but also causes the RSSI output and the
ADC output to track over power supply variations, reducing
system errors and component costs.
RSSI OUTPUT
The logarithmic amplifier uses a successive-detection architecture.
Each of the five stages has a full-wave detector; two additional
high level detectors are driven by attenuators at the input to the
limiting amplifiers, for a total of seven detector stages. Because
each detector is a full-wave rectifier, the ripple component in
the resulting dc is at twice the IF. The AD608 low-pass filter has
a 2 MHz cutoff frequency, which is one decade below the 21.4 MHz
ripple that results from a 10.7 MHz IF.
POWER CONSUMPTION
The total power supply current of the AD608 is a nominal
7.3 mA. The power is signal dependent, partly because the RSSI
output increases (the current is increased by 200 μA at an RSSI
output of +1.8 V), but mostly due to the IF consumption of the
band-pass filter when driven to 891 mV, assuming a 4 dB loss
in this filter and a peak input of +5 dBm to the log-IF amp. In
addition, the power is temperature dependent because the
biasing system used in the AD608 is proportional to the
absolute temperature (PTAT).
For operation at lower IFs, such as 450 kHz or 455 kHz, the
AD608 requires an external low-pass filter with a single pole
located at 90 kHz, a decade below the 900 kHz ripple frequency
for these IFs. The RSSI range is from the noise level at approx-
imately −80 dBm to overload at +15 dBm and is specified for
1 dB accuracy from −75 dBm to +5 dBm. The +15 dBm
maximum IF input is provided to accommodate band-pass
filters of lower insertion loss than the nominal 4 dB for
10.7 MHz ceramic filters.
TROUBLESHOOTING
The most common causes of problems with the AD608 are
incorrect component values for the offset feedback loop, poor
board layout, and pickup of radio frequency interference (RFI),
which all cause the AD608 to lose the low end (typically below
−65 dBm) of its RSSI output and cause the limiter to swing
randomly. Both poor board layout and incorrect component
values in the offset feedback loop can cause low level oscillations.
Pickup of RFI can be caused by improper layout and shielding
of the circuit.
DIGITIZING THE RSSI
In typical cellular radio applications, the RSSI output of the
AD608 is digitized by an analog-to-digital converter (ADC).
The RSSI output of the AD608 is proportional to the power
supply voltage, which not only allows the ADC to use the
Rev. C | Page 11 of 16
AD608
APPLICATIONS INFORMATION
Figure 24 shows the AD608 configured for operation in a digital
system at a 10.7 MHz IF. The input and output impedance of the
filter are parallel terminated using 330 Ω resistors, and the
conversion gain is 24 dB. The RF port is terminated in 50 Ω; in
a typical application, the input is matched to a SAW filter using
the impedance data provided in Table 5.
Figure 25 shows the AD608 configured for narrow-band FM
operation at a 450 kHz or 455 kHz with an external discriminator.
The IF filter has 1500 Ω input and output impedances—the
input is matched via a resistive divider, and the output is
terminated in 1500 Ω. The discriminator requires a 1 V p-p
drive from a 1 kΩ source impedance, which in Figure 25 is
provided by a Class A amplifier with a gain of 2.5.
VPOS
SUPPLY
2.7V TO 5.5V
C1
1µF
1
2
3
4
5
6
7
VPS1
PRUP 16
R4
POWER-UP
3V CMOS
47kΩ
LO INPUT
–16dBm
C2
COM1
LOHI
LMOP 15
VPS2 14
FDBK 13
COM3 12
RSSI 11
IFLO 10
100pF
LIMO
LIMITER
OUTPUT
VPOS –1V
±200mV
R5
51.1Ω
COM2
RFHI
+
C7
R3
18nF
100Ω
C3
100pF
RF INPUT
RFLO
MXOP
–95dBm
TO
RSSI OUTPUT
+0.2V TO +1.8V
(20mV/dB)
C4
100pF
R6
–15dBm
51.1Ω
8
VMID
IFHI
9
+
C6
10nF
AD608
10.7MHz BPF Z = 330Ω
BIAS POINT
AT VPOS/2
OFFSET-CONTROL
LOOP FILTER
R2
330Ω
R1
330Ω
+
C5
0.1µF
BPF REVERSE
TERMINATION
BPF
TEMINATION
IF BIAS POINT
DECOUPLING
Figure 24. Application at 10.7 MHz (the Band-Pass Filter Can Be a Toko SK107 or Murata SFE10.7)
JUMPER
PRUP
R16
+5V
GND
R13
47kΩ
R14
402Ω
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VPS1
PRUP
LMOP
8.66kΩ
C1
C5 0.1µF
R10
3.3kΩ
F2
0.1µF
COM1
Q1
LOHI
AUDIO
C8 0.1µF
R1
C2
LOHI
COM2
RFHI
VPS2
FDBK
COM3
RSSI
IFLO
IFHI
R8
R12
1kΩ
C11
0.1µF
R15
24.9kΩ
51.1Ω
1nF
CR1
CR2
1kΩ
R11
3.3kΩ
C10
0.01µF
C9
0.2µF
R9
1kΩ
R6
1kΩ
RFHI
R5
200Ω
R2
51.1Ω
C3
1nF
RFLO
MXOP
VMID
RSSI
C6 0.1µF
C4
1nF
R3
374Ω
AD608
F1: TOKO HCFM2–455B
F2: MURATA CFY455S
CR1, CR2: 1N60
R7
1130Ω
R4
1.5kΩ
F1
Q1: 2N3906
C7
0.1µF
Figure 25. Narrow-Band FM Application at 450 kHz or 455 kHz
Rev. C | Page 12 of 16
AD608
OUTLINE DIMENSIONS
10.00 (0.3937)
9.80 (0.3858)
9
8
16
1
6.20 (0.2441)
5.80 (0.2283)
4.00 (0.1575)
3.80 (0.1496)
1.27 (0.0500)
BSC
0.50 (0.0197)
0.25 (0.0098)
45°
1.75 (0.0689)
1.35 (0.0531)
0.25 (0.0098)
0.10 (0.0039)
8°
0°
COPLANARITY
0.10
SEATING
PLANE
1.27 (0.0500)
0.40 (0.0157)
0.51 (0.0201)
0.31 (0.0122)
0.25 (0.0098)
0.17 (0.0067)
COMPLIANT TO JEDEC STANDARDS MS-012-AC
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 26. 16-Lead Standard Small Outline Package [SOIC_N]
Narrow Body
(R-16)
Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
AD608AR
AD608AR-REEL
AD608ARZ1
AD608ARZ-RL1
EVAL-AD608EBZ1
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
16-Lead Standard Small Outline Package [SOIC_N]
Evaluation Board
R-16
R-16
R-16
R-16
1 Z = RoHS Compliant Part.
Rev. C | Page 13 of 16
AD608
NOTES
Rev. C | Page 14 of 16
AD608
NOTES
Rev. C | Page 15 of 16
AD608
NOTES
©1996–2009 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07886-0-2/09(C)
Rev. C | Page 16 of 16
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