AD608AR [ADI]
Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem; 低功率混频器/限制器/ RSSI 3 V接收器IF子系统
| 型号： | AD608AR |
| 厂家： | 
ADI |
| 描述： | Low Power Mixer/Limiter/RSSI 3 V Receiver IF Subsystem |
| 文件： | 总12页 (文件大小：199K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power Mixer/Limiter/RSSI
3 V Receiver IF Subsystem
a
AD608
T he RF and LO bandwidths both exceed 500 MHz. In a typical
IF application, the AD608 will accept the output of a 240 MHz
SAW filter and downconvert it to a nominal 10.7 MHz IF with
a conversion gain of 24 dB (ZIF = 165 Ω). T he AD608’s loga-
rithmic/limiting amplifier section handles any IF from LF to as
high as 30 MHz.
FEATURES
Mixer
–15 dBm 1 dB Com pression Point
–5 dBm IP3
24 dB Conversion Gain
>500 MHz Input Bandw idth
Logarithm ic/ Lim iting Am plifier
80 dB RSSI Range
؎3؇ Phase Stability over 80 dB Range
Low Pow er
21 m W at 3 V Pow er Consum ption
CMOS-Com patible Pow er-Dow n to 300 W typ
200 ns Enable/ Disable Tim e
T he mixer is a doubly-balanced “Gilbert-Cell” type and oper-
ates linearly for RF inputs spanning –95 dBm to –15 dBm. It
has a nominal –5 dBm third-order intercept. An onboard LO
preamplifier requires only –16 dBm of LO drive. T he mixer’s
current output drives a reverse-terminated, industry-standard
10.7 MHz 330 Ω filter.
T he nominal logarithmic scaling is such that the output is
+0.2 V for a sinusoidal input to the IF amplifier of –75 dBm
and +1.8 V at an input of +5 dBm; over this range the logarith-
mic conformance is typically ±1 dB. T he logarithmic slope is
proportional to the supply voltage. A feedback loop automati-
cally nulls the input offset of the first stage down to the sub-
microvolt level.
APPLICATIONS
PHS, GSM, TDMA, FM, or PM Receivers
Battery-Pow ered Instrum entation
Base Station RSSI Measurem ent
T he AD608’s limiter output provides a hard-limited signal out-
put at 400 mV p-p. T he voltage gain of the limiting amplifier to
this output is more than 100 dB. T ransition times are 11 ns and
the phase is stable to within ±3° at 10.7 MHz for signals from
–75 dBm to +5 dBm.
GENERAL D ESCRIP TIO N
T he AD608 provides both a low power, low distortion, low
noise mixer and a complete, monolithic logarithmic/limiting
amplifier using a “successive-detection” technique. It provides
both a high speed RSSI (Received Signal Strength Indicator)
output with 80 dB dynamic range and a hard-limited output.
T he RSSI output is from a two-pole post-demodulation low-
pass filter and provides a loadable output voltage of +0.2 V to
+1.8 V. T he AD608 operates from a single 2.7 V to 5.5 V sup-
ply at a typical power level of 21 mW at 3 V.
T he AD608 is enabled by a CMOS logic-level voltage input,
with a response time of 200 ns. When disabled, the standby
power is reduced to 300 µW within 400 ns.
T he AD608 is specified for the industrial temperature range of
–25°C to +85°C for 2.7 V to 5.5 V supplies and –40°C to +85°C
for 4.5 V to 5.5 V supplies. It comes in a 16-pin plastic SOIC.
FUNCTIO NAL BLO CK D IAGRAM
110dB LIMITER GAIN
90dB RSSI
24dB MIXER GAIN
3dB NOMINAL
INSERTION LOSS
RSSI OUTPUT
20mV/dB
0.2V TO 1.8V
RSSI
IF INPUT
7 FULL-WAVE
RECTIFIER CELLS
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
11
12
14
15
–75dBm TO
≈
2
+15dBm
RFHI
5
6
2MHz
LPF
COM3
VPS2
MIXER
10.7MHz
BANDPASS
FILTER
IFHI
RF INPUT
–95 TO
MXOP
7
8
+2.7V TO 5.5V
9
≈
1
–15dBm
BPF
DRIVER
LMOP
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
330Ω
LIMITER
OUTPUT
400mVp-p
330Ω
RFLO
10nF
LO
PREAMP
VMID
FINAL
LIMITER
10
13
IFLO
100nF
100Ω
MID-SUPPLY
IF BIAS
LOHI
FDBK
18nF
±50µA
BIAS
AD608
COM2
VPS1 COM1
PRUP
16
1
2
4
3
1
NOTES:
–15dBm = ±56mV MAX FOR LINEAR OPERATION
+2.7V TO
5.5V
LO INPUT
–16dBm
CMOS LOGIC
INPUT
2
39.76µV RMS TO 397.6mV RMS FOR ±1dB RSSI
ACCURACY
REV. B
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1996
One Technology Way, P.O. Box 9106, Norw ood, MA 02062-9106, U.S.A.
Tel: 617/ 329-4700 Fax: 617/ 326-8703
(@ T = + 25؇C, Supply = 3 V, dBm is referred to 50 ⍀, unless otherwise noted)
AD608–SPECIFICATIONS
A
Model
AD 608
Conditions
Min
Typ
Max
Units
MIXER PERFORMANCE
RF and LO Frequency Range
LO Power
Conversion Gain
Noise Figure
500
–16
24
MHz
dBm
dB
Input T erminated in 50 Ω
Driving Doubly-Terminated 330 Ω IF Filter, ZIF = 165 Ω
Matched Input, fRF = 100 MHz
19
28
11
dB
Matched Input, fRF = 240 MHz
16
dB
1 dB Compression Point
T hird-Order Intercept
Input Resistance
Input T erminated in 50 Ω
fRF = 240 MHz and 240.02 MHz, fLO = 229.3 MHz
fRF = 100 MHz (See T able I)
–15
–5
1.9
3
dBm
dBm
kΩ
Input Capacitance
fRF = 100 MHz (See T able I)
pF
LIMIT ER PERFORMANCE
Gain
Limiting T hreshold
Full T emperature and Supply Range
3° rms Phase Jitter at 10.7 MHz
280 kHz IF Bandwidth
110
–75
dB
dBm
Input Resistance
Input Capacitance
Phase Variation
DC Level
Output Level
Rise and Fall T imes
Output Impedance
10
3
±3
2
400
11
200
kΩ
pF
Degree
V
mV p-p
ns
–75 dBm to +5 dBm IF Input Signal at 10.7 MHz
Center of Output Swing (VPOS-1)
Limiter Output Driving 5 kΩ Load
Driving a 5 pF Load
Ω
RSSI PERFORMANCE
Nominal Slope
Nominal Intercept
Minimum RSSI Voltage
Maximum RSSI Voltage
RSSI Voltage Intercept
Logarithmic Linearity Error
RSSI Response T ime
Output Impedance
At 10.7 MHz
At VPOS = 3 V; Proportional to VPOS
17.27
1.57
20
23.27
1.82
mV/dB
dBm
V
V
V
dB
ns
Ω
–85
0.2
1.8
–75 dBm Input Signal
+5 dBm Input Signal
0 dBm Input Signal
–75 dBm to +5 dBm Input Signal at IFHI
90% RF to 50% RSSI
At Midscale
±1
200
250
POWER-DOWN INT ERFACE
Logical T hreshold
Input Current
Power-Up Response T ime
Power-Down Response T ime
Power-Down Current
System Active on Logical High
For Logical High
Active Limiter Output
T o 200 µA Supply Current
1.5
75
200
400
100
V
µA
ns
ns
µA
POWER SUPPLY
Operating Range
–25°C to +85°C
–40°C to +85°C
VPOS = 3 V
2.7
4.5
5.5
5.5
V
V
mA
Powered Up Current
7.3
OPERAT ING T EMPERAT URE
TMIN to TMAX
TMIN to TMAX
VPOS = 2.7 V to 5.5 V
VPOS = 4.5 V to 5.5 V
–25
–40
+85
+85
°C
°C
Specifications subject to change without notice.
–2–
REV. B
AD608
ABSO LUTE MAXIMUM RATINGS1
P IN D ESCRIP TIO NS
Supply Voltage VPS1, VPS2 . . . . . . . . . . . . . . . . . . . . . . +6 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW
T emperature Range . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage T emperature Range . . . . . . . . . . . . . –65°C to +150°C
Lead T emperature (Soldering 60 sec) . . . . . . . . . . . . . +300°C
P in
Mnem onic
D escription
1
2
3
4
5
6
7
8
VPS1
Positive Supply Input
Common
COM1
LOHI
COM2
RFHI
Local Oscillator Input Connection
Common
NOT ES
1Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. T his is a stress rating only, and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended rating conditions for extended periods
may affect device reliability.
RF Input, Noninverting
RF Input, Inverting
Mixer Output
RFLO
MXOP
VMID
2T hermal Characteristics:
16-Pin SOIC Package: θJA = 110°C/W.
Midpoint Supply Bias
Output
O RD ERING GUID E
9
IFHI
IFLO
RSSI
IF Input, Noninverting
IF Input, Inverting
10
11
Tem perature
Range
P ackage
O ption
Received Signal Strength Indicator
Output
Model
AD608AR
–25°C to +85°C,
2.7 V to 5.5 V Supplies;
–40°C to +85°C,
R-16A*
12
13
14
15
16
COM3
FDBK
VPS2
Output Common
Offset-Null Feedback Loop Output
Limiter Positive Supply Input
Limiter Output
4.5 V to 5.5 V Supplies
LMOP
PRUP
*R = Small Outline IC (SOIC).
Power-Up
TERMINAL D IAGRAM
VPS1
COM1
LOHI
1
2
3
4
5
6
7
8
16 PRUP
15 LMOP
14 VPS2
13 FDBK
12 COM3
11 RSSI
10 IFLO
AD608
TOP VIEW
COM2
RFHI
(Not to Scale)
RFLO
MXOP
VMID
9
IFHI
CAUTIO N
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD608 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. T herefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
–3–
AD608
PRUP IN
U1A
U1B
TRIGGER
47kΩ
4.7k
1
2
3
4
5
6
7
8
16
15
14
13
12
VPS1
PRUP
LMOP
VPOS
LO IN
0.1µF
COM1
47kΩ
NC
18nF
18nF
1nF
LOHI
VPS2
FDBK
COM3
1
2
3
4
5
6
7
8
VPS1
PRUP
LMOP
VPS2
FDBK
COM3
RSSI
IFLO
16
15
14
13
51.1Ω
0.1µF
0.1µF
VPOS
COM2
RFHI
COM1
1nF
LMOP OUT
0.1µF
LOHI
100Ω
RF IN
51.1Ω
RFLO
MXOP
VMID
RSSI 11
NC
51.1Ω
10nF
COM2
RFHI
1nF
1nF
IFLO
10
9
18nF
100Ω
12
11
10
9
1nF
IFHI
51.1Ω
RFLO
MXOP
VMID
RSSI OUTPUT
AD608
10nF
332Ω
0.1µF
332Ω
332Ω
0.1µF
IFHI
301Ω
0.1µF
AD608
301Ω
IF OUT
332Ω
54.9Ω
NC = NO CONNECT
0.1µF
IF INPUT
54.9Ω
U1 – 74HC00
Figure 2. Mixer Test Board Schem atic
Figure 1. IF Test Board Schem atic
3.0
2.5
0
25.0
24.5
24.0
23.5
23.0
22.5
22.0
–1
–2
–3
–4
–5
–6
–7
–8
2.0
5V
1.5
1.0
3V
0.5
0
–80 –70 –60 –50 –40 –30 –20 –10
0
10
0
10
20
30
40
50
60
70 80
0
50 100 150 200 250 300 350 400 450 500
RF FREQUENCY – MHz
INPUT POWER AT IFHI – dBm
IF FREQUENCY – MHz
Figure 3. Mixer Conversion Gain vs.
Frequency
Figure 4. Mixer IF Port Bandwidth
Figure 5. IF RSSI Output vs. Supply
Voltage (Am bient Tem perature)
4.0
3.0
2.0
3.0
+85
2.5
+25
IF TEST BOARD
FLUKE 6082A
SYNTHESIZER
–25
2.0
1.0
3V
IFHI
RSSI
VPOS
DMM
0
1.5
1.0
0.5
0
HP34401A
10.7 MHz
5V
–1.0
DCPS 3V
HP3366A
–2.0
–3.0
–4.0
Figure 7. Test Circuit for IF RSSI Out-
put vs. Supply Voltage (Am bient Tem -
perature) (Figure 5) and IF RSSI
Output vs. Tem perature (3 V Supply)
(Figure 6) and RSSI Error vs. Input
Power (Figure 8)
–80 –70 –60 –50 –40 –30 –20 –10
INPUT POWER – dBm
0
10
–80 –70 –60 –50 –40 –30 –20 –10
INPUT POWER – dBm
0
10
Figure 8. RSSI Error vs. Input Power
Figure 6. IF RSSI Output vs.
Tem perature (3 V Supply)
–4–
REV. B
AD608
60mV/DIV
800mV/DIV
100ns/DIV
1V /DIV
100ns/DIV
20ns/DIV
Figure 9. RSSI Power-Up Response
Figure 13. Lim iter Rise and Fall Tim es
HP54120A
DIGITAL
OSCILLOSCOPE
FLUKE 6082A
SYNTHESIZER
IF TEST BOARD
IFHI RSSI
FLUKE 6082A
SYNTHESIZER
TEK P6201
IF TEST BOARD
IFHI LMOP
VPOS
HP54120A
TEK P6201
FET
PROBE
CH 1
CH 2
FET
PROBE
DIGITAL
OSCILLOSCOPE
10.7 MHz
0dBm
PRUP TRIGGER
VPOS
10.7 MHz
0dBm
DCPS 3V
HP3366A
DCPS 3V
HP3366A
Figure 10. Test Circuit for RSSI Power-Up Response
(Figure 9)
Figure 14. Test Circuit for Lim iter Rise and Fall Tim es
(Figure 13)
200mV/DIV
100ns/DIV
220mV/DIV
1V/DIV
800mV/DIV
50ns/DIV
100ns/DIV
Figure 11. RSSI Pulse Response/RSSI Rise Tim e
Figure 15. Lim iter Power-Up Response Tim e
HP54120A
DIGITAL
OSCILLOSCOPE
FLUKE 6082A
SYNTHESIZER
CH 1
CH 2
FLUKE 6082A
SYNTHESIZER
IF TEST BOARD
IFHI LMOP
IF TEST BOARD
IFHI RSSI
TEK P6201
TEK P6201
FET
PROBE
FET
PROBE
CH 1
CH 2
COUPLER
MCL
ZDC-20-1
10.7 MHz
0dBm
PRUP TRIGGER
VPOS
10.7 MHz
0dBm
VPOS
HP54120A
DIGITAL
OSCILLOSCOPE
DCPS 3V
HP3366A
DCPS
3V
HP6633A
Figure 12. Test Circuit for RSSI Pulse Response/RSSI Rise
Tim e (Figure 11)
Figure 16. Test Circuit for Lim iter Power-Up Response
Tim e (Figure 15)
REV. B
–5–
AD608
5
4
10
9
3
8
2
7
1
6
0
5
–1
–2
–3
4
3
2
1
0
–4
–5
–80 –70 –60 –50 –40 –30 –20 –10
INPUT POWER AT IFHI – dBm
0
10
–80 –70 –60 –50 –40 –30 –20 –10
INPUT POWER – dBm
0
10
Figure 17. Lim iter Phase Perform ance vs.
Input Power at IFHI
Figure 19. Lim iter J itter Perform ance vs.
Input Power at IFHI
FLUKE 6082A
SYNTHESIZER ZDC-20-1
MCL
IF TEST BOARD TEK P6201
FET
COUPLER
IFHI RSSI
PROBE
HP8447A
10.7 MHz
HP8494A
HP8495A
DCPS
BPF
CH 1
TRIG
3V
280kHz BW
10.7MHz CF
HP3366A
TOKO SK107MK1-A0-10
HP54120A
DIGITAL
OSCILLOSCOPE
Figure 18. Test Circuit for Lim iter Phase Perform ance vs.
Input Power at IFHI (Figure 17) and Lim iter J itter Perfor-
m ance vs. Input Power at IFHI (Figure 19)
–6–
REV. B
AD608
TH EO RY O F O P ERATIO N
Mixer Gain
T he AD608 (Figure 20) consists of a mixer followed by a loga-
rithmic IF strip with RSSI and hard limited outputs. Each sec-
tion will be described below.
T he mixer’s conversion gain is the product of its transcon-
ductance and the impedance seen at pin MXOP. For a 330 Ω
parallel-terminated filter at 10.7 MHz, the load impedance is
165 Ω, the gain is 24 dB, and the output is 15.85 × 56.2 mV, or
±891 mV, centered on the midpoint of the supply voltage. For
other load impedances, the expression for the gain in dB is
Mixer
T he mixer is a doubly-balanced modified Gilbert cell mixer. Its
maximum input level for linear operation is ±56.2 mV regard-
less of the impedance across the mixer’s inputs, or –15 dBm for
a 50 Ω input termination. T he input impedance of the mixer
can be modeled as a simple parallel RC network; the values ver-
sus frequency are listed in T able I. T he bandwidth from the RF
input to the IF output at MXOP pin is –1 dB at 30 MHz and
then falls off rapidly (Figure 4).
GdB = 20 log10 0.0961 R
(
)
L
T he mixer’s gain can be increased or decreased by changing RL,
the load impedance at pin MXOP. T he limitations on the
mixer’s gain are the ±6 mA maximum output current at MXOP
and the maximum allowable voltage swing at pin MXOP, which
is ±1.0 V for a 3 V supply or 5 V supply.
3dB NOMINAL
INSERTION LOSS
24dB MIXER GAIN
110dB LIMITER GAIN
90dB RSSI
RSSI OUTPUT
20mV/dB
0.2V TO 1.8V
RSSI
IF INPUT
–75dBm TO
+15dBm 2.
7 FULL-WAVE
RECTIFIER CELLS
±6mA MAX OUTPUT
(±890mV INTO 165Ω)
11
≈
5
6
RFHI
COM3 12
IFHI
10.7MHz
BANDPASS
FILTER
RF INPUT
–95 TO
–15dBm 1.
MIXER
MXOP
VPS2
14
7
8
9
+2.7V TO 5.5V
≈
BPF
DRIVER
LMOP
15
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
LIMITER
OUTPUT
400mVp-p
330Ω
330Ω
10nF
RFLO
LO
PREAMP
VMID
FINAL
LIMITER
10
IFLO
100nF
100Ω
MID-SUPPLY
IF BIAS
13
LOIP
18nF
FDBK
±50µA
BIAS
AD608
COM2
VPS1 COM1
PRUP
1
2
3
4
16
1. –15dBm = ±56mV MAX FOR LINEAR OPERATION
NOTES:
+2.7V TO 5.5V LO INPUT
–16dBm
CMOS LOGIC
INPUT
2. 39.76mV RMS TO 396.6mV RMS FOR ±1 dB
RSSI ACCURACY
Figure 20. Functional Block Diagram
Table I. Mixer Input Im pedance vs. Frequency
Frequency
(MH z)
Resistance
(O hm s)
Capacitance
(pF)
45
70
2800
2600
1800
1200
760
3.1
3.1
3.1
3.1
3.2
3.4
3.6
100
200
300
400
500
520
330
REV. B
–7–
AD608
5 kΩ load. In the absence of an input signal, the limiter’s output
will limit on noise fluctuations, which produces an output that
continues to swing 400 mV p-p but with random zero crossings.
IF Filter Ter m inations
T he AD608 was designed to drive a parallel-terminated 10.7 MHz
bandpass filter with a 330 Ω impedance. With a 330 Ω parallel-
terminated filter, pin MXOP sees a 165 Ω termination and the
gain is nominally 24 dB. Other filter impedances and gains can
be accommodated by either accepting an increase or decrease in
gain in proportion to the filter impedance or by keeping the im-
pedance seen by MXOP a nominal 165 Ω (by using resistive di-
viders or matching networks). Figure 21 shows a simple resistive
voltage divider for matching an assortment of filter impedances,
and T able II lists component values.
O ffset Feedback Loop
Because the logarithmic amplifier is dc coupled and has more
than 110 dB of gain from the input to the limiter output, a dc
offset at its input of even a few µV would cause the output to
saturate. T hus, the AD608 uses a low frequency feedback loop
to null out the input offset. Referring to Figure 21, the loop
consists of a current source driven by the limiter, which sends
50 µA current pulses to pin FDBK. T he pulses are low pass
filtered by a π-network consisting of C1, R4, and C5. T he
smoothed dc voltage that results is subtracted from the input to
the IF amplifier at pin IFLO. Because this is a high gain ampli-
fier with a feedback loop, care should be taken in layout and
component values to prevent oscillation. Recommended values
for the common IFs of 450 kH z, 455 kH z, 6.5 MH z, and
10.7 MHz are listed in T able II.
The Logar ithm ic IF Am plifier
T he logarithmic IF amplifier consists of five amplifier stages
of 16 dB gain each, plus a final limiter. T he IF bandwidth is
30 MHz (–1 dB) and the limiting gain is 110 dB. T he phase
skew is ±3° from –75 dBm to +5 dBm (approximately 111 µV
p-p to 1.1 V p-p). T he limiter output impedance is 200 Ω
and the limiter’s output drive is ±200 mV (400 mV p-p) into a
110dB LIMITER GAIN
90dB RSSI
12dB NOMINAL
INSERTION LOSS
24dB MIXER GAIN
(ASSUMES 6dB IN FILTER)
7 FULL-WAVE
RECTIFIER CELLS
BANDPASS
FILTER
11
12
14
15
RSSI
≈
5
6
RFHI
2M Hz
LPF
COM3
VPS2
LMOP
IFHI
MIXER
R2
MXOP
BPF
7
8
9
≈
5-STAGE IF AMPLIFIER
(16dB PER STAGE)
DRIVER
R1
R3
RFLO
C5
LO
PREAMP
VM ID
FINAL
10
13
LIMITER
IFLO
100nF
R4
MID-SUPPLY
IF BIAS
LOHI
C1
FDBK
±50µA
BIAS
AD608
COM2
VPS1 COM1
PRUP
1
2
3
4
16
+5V
47kΩ
C2
100pF
C1
1µF
CMOS
LOGIC
INPUT
LO INPUT
–16dBm
Figure 21. Applications Diagram for Com m on IFs and Filter Im pedances
Table II. AD 608 Filter Term ination and O ffset-Null Feedback Loop Resistor and Capacitor Values for Com m on IFs
Filter
Im pedance
Filter Term ination Resistor
O ffset Null
Feedback Loop Values
IF
Values1 for 24 dB of Mixer Gain
R1
R2
R3
R4
C1
C5
450 kHz2
455 kHz
6.5 MHz
10.7 MHz
1500 Ω
1500 Ω
1000 Ω
330 Ω
174 Ω
174 Ω
178 Ω
330 Ω
1330 Ω
1330 Ω
825 Ω
0 Ω
1500 Ω
1500 Ω
1000 Ω
330 Ω
1000 Ω
1000 Ω
100 Ω
200 nF
200 nF
18 nF
100 nF
100 nF
10 nF
100 Ω
18 nF
10 nF
NOT ES
1Resistor values were calculated so that R1 + R2 = Z FILT ER and R1ʈ(R2+ZFILT ER) = 165 Ω.
2Operation at IFs of 450 kHz and 455 kHz requires an external low pass filter with at least one pole at a cutoff frequency of 90 kHz (a decade below the ripple
at 900 kHz).
–8–
REV. B
AD608
P ower Consum ption
RSSI O utput
T he total power-supply current of the AD608 is a nominal
7.3 mA. T he power is signal-dependent, partly as the RSSI
output increases (the current is increased by 200 µA at an RSSI
output of +1.8 V) but mostly due to the IF BPF consumption
when being driven to ±891 mV assuming a 4 dB loss in this
filter and a peak input of +5 dBm to the log-IF amp, and tem-
perature dependent, as the biasing system used in the AD608 is
proportional to absolute temperature (PT AT ).
T he logarithmic amplifier uses a successive detection architec-
ture. Each of the five stages has a full-wave detector; two addi-
tional high level detectors are driven through attenuators at the
input to the limiting amplifiers, for a total of seven detector
stages. Because each detector is a full-wave rectifier, the ripple
component in the resulting dc is at twice the IF. T he AD608’s
low-pass filter has a 2 MHz cutoff frequency, which is one
decade below the 21.4 MHz ripple that results from a 10.7 MHz
IF.
Tr oubleshooting
T he most common causes of problems with the AD608 are
incorrect component values for the offset feedback loop, poor
board layout, and pickup of RFI, which all cause the AD608 to
“lose” the low end (typically below –65 dBm) of its RSSI output
and cause the limiter to swing randomly. Both poor board lay-
out and incorrect component values in the offset feedback loop
can cause low level oscillations. Pickup of RFI can be caused by
improper layout and shielding of the circuit.
For operation at lower IFs such as 450 kHz or 455 kHz, the
AD608 requires an external low-pass filter with a single pole lo-
cated at 90 kHz, a decade below the 900 kHz ripple frequency
for these IFs. T he RSSI range is from the noise level at approxi-
mately –80 dBm to overload at +15 dBm and is specified for
±1 dB accuracy from –75 dBm to +5 dBm. T he +15 dBm
maximum IF input is provided to accommodate bandpass filters
of lower insertion loss than the nominal 4 dB for 10.7 MHz
ceramic filters.
D igitizing the RSSI
In typical cellular radio applications, the RSSI output of the
AD608 will be digitized by an A/D converter. T he AD608’s
RSSI output is proportional to the power-supply voltage, which
not only allows the A/D converter to use the supply as a refer-
ence but also causes the RSSI output and the A/D converter’s
output to track over power supply variations, reducing system
errors and component costs.
REV. B
–9–
AD608
Applications
Figure 23 shows the AD608 configured for narrowband FM op-
eration at a 450 kHz or 455 kHz with an external discriminator.
T he IF filter has 1500 Ω input and output impedances— the
input is matched via a resistive divider and the output is termi-
nated in 1500 Ω. T he discriminator requires 1 V p-p drive from
a 1 kΩ source impedance, here provided by a gain-of-2.5 Class
A amplifier.
Figure 22 shows the AD608 configured for operation in a digital
system at a 10.7 MHz IF. T he filter’s input and output imped-
ance are parallel terminated using 330 Ω resistors and the con-
version gain is 24 dB. T he RF port is terminated in 50 Ω; in a
typical application the input would be matched to a SAW filter
using the impedance data shown previously in T able I.
VPOS
C1
1µF
SUPPLY
2.7V TO 5.5V
1
VPS1
PRUP
16
R4
47kΩ
POWER-UP
3V CMOS
C2
100pF
LO INPUT
–16dBm
2
3
COM1
LOHI
LMOP 15
VPS2 14
LIMO
LIMITER
OUTPUT
VPOS –1V
±200mV
R5
51.1Ω
4
5
6
7
8
COM2
RFHI
FDBK 13
COM3 12
C7
18nF
R3
100Ω
C3
100pF
RF INPUT
–95dBm
TO
RFLO
RSSI 11
RSSI OUTPUT
+0.2V TO +1.8V
(20mV/dB)
C4
100pF
R6
51.1Ω
–15dBm
MXOP
VMID
IFLO
10
IFHI
9
C6
10nF
AD608
10.7MHz BPF Z = 330Ω
BIAS POINT
AT VPOS/2
OFFSET-CONTROL
LOOP FILTER
R1
330Ω
R2
330Ω
C5
0.1µF
BPF REVERSE
TERMINATION
BPF
TERMINATION
IF BIAS POINT
DECOUPLING
Figure 22. Application at 10.7 MHz. The Bandpass Filter
Can Be a Toko Type SK107 or Murata Type SFE10.7
JUMPER
PRUP
R16
47kΩ
+5V
GND
R13
402
R14
8.66k
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VPS1
PRUP
LMOP
C11
0.1µF
Q1
C5 0.1µF
C8 0.1µF
C1 0.1µF
R10
3.3kΩ
F2
COM1
LOHI
AUDIO
R1
51.1Ω
C2
1nF
R15
24.9k
LOHI
VPS2
FDBK
COM3
RSSI
IFLO
R8
1k
R12
1k
CR1
CR2
R11
3.3k
COM2
RFHI
C10
0.01µF
C9
0.2µF
R9
1k
R6
1kΩ
RFHI
R5 200Ω
RSSI
C3
1nF
R2
51.1Ω
RFLO
MXOP
VMID
C6 0.1µF
C4
1nF
R3
374Ω
IFHI
AD608
F1: TOKO HCFM2–455B
F2: MURATA CFY455S
CR1, CR2: 1N60
R7
1130Ω
R4
1.5kΩ
F1
Q1: 2N3906
C7
0.1µF
Figure 23. Narrowband FM Application at 450 kHz or 455 kHz
–10–
REV. B
AD608
O UTLINE D IMENSIO NS
D imensions shown in inches and (mm).
16-Lead SO IC
(R-16A)
16
1
9
0.1574 (4.00)
0.1497 (3.80)
PIN 1
0.2440 (6.20)
0.2284 (5.80)
8
0.3937 (10.00)
0.3859 (9.80)
0.0196 (0.50)
0.0099 (0.25)
x 45°
0.0688 (1.75)
0.0532 (1.35)
8°
0°
0.0098 (0.25)
0.0040 (0.10)
0.0500 (1.27)
0.0160 (0.41)
0.0500
(1.27)
BSC
0.0192 (0.49)
0.0138 (0.35)
0.0099 (0.25)
0.0075 (0.19)
REV. B
–11–
–12–
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