AD607ARSZ-REEL [ADI]
Low Power Mixer/AGC/RSSI 3V Receiver IF Subsystem;
| 型号： | AD607ARSZ-REEL |
| 厂家： | 
ADI |
| 描述： | Low Power Mixer/AGC/RSSI 3V Receiver IF Subsystem 电信 光电二极管 电信集成电路 |
| 文件： | 总25页 (文件大小：621K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Low Power Mixer
3 V Receiver IF Subsystem
a
AD607
PIN CONFIGURATION
FEATURES
Complete Receiver-on-a-Chip: Monoceiver® Mixer
–15 dBm 1 dB Compression Point
–8 dBm Input Third Order Intercept
500 MHz RF and LO Bandwidths
Linear IF Amplifier
20-Lead SSOP
(RS Suffix)
1
2
20
19
18
17
16
15
14
13
12
11
Linear-in-dB Gain Control
Manual Gain Control
Quadrature Demodulator
On-Board Phase-Locked Quadrature Oscillator
Demodulates IFs from 400 kHz to 12 MHz
Can Also Demodulate AM, CW, SSB
Low Power
VPS1
FLTR
IOUT
QOUT
VPS2
DMIP
IFOP
COM2
GAIN
IFLO
FDIN
COM1
PRUP
LOIP
3
4
5
RFLO
RFHI
AD607
TOP VIEW
(Not to Scale)
6
7
GREF
MXOP
VMID
IFHI
25 mW at 3 V
8
CMOS Compatible Power-Down
Interfaces to AD7013 and AD7015 Baseband Converters
9
10
APPLICATIONS
GSM, CDMA, TDMA, and TETRA Receivers
Satellite Terminals
Battery-Powered Communications Receivers
GENERAL DESCRIPTION
The I and Q demodulators provide in-phase and quadrature
baseband outputs to interface with Analog Devices’ AD7013
(IS54, TETRA, MSAT) and AD7015 (GSM) baseband con-
verters. A quadrature VCO phase-locked to the IF drives the I
and Q demodulators. The I and Q demodulators can also
demodulate AM; when the AD607’s quadrature VCO is phase-
locked to the received signal, the in-phase demodulator becomes
a synchronous product detector for AM. The VCO can also be
phase-locked to an external beat-frequency oscillator (BFO),
and the demodulator serves as a product detector for CW or
SSB reception. Finally, the AD607 can be used to demodulate
BPSK using an external Costas Loop for carrier recovery.
The AD607 is a 3 V low power receiver IF subsystem for opera-
tion at input frequencies as high as 500 MHz and IFs from
400 kHz to 12 MHz. It consists of a mixer, IF amplifiers, I and
Q demodulators, a phase-locked quadrature oscillator, and a
biasing system with external power-down.
The AD607’s low noise, high intercept mixer is a doubly
balanced Gilbert cell type. It has a nominal –15 dBm input
referred 1 dB compression point and a –8 dBm input referred
third order intercept. The mixer section of the AD607 also
includes a local oscillator (LO) preamplifier, which lowers the
required LO drive to –16 dBm.
In MGC operation, the AD607 accepts an external gain-control
voltage input from an external AGC detector or a DAC.
Monoceiver is a registered trademark of Analog Devices, Inc.
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, norforanyinfringementsofpatentsorotherrightsofthirdpartiesthat
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
www.analog.com
© Analog Devices, Inc., 2002
AD607* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
• AD607 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
EVALUATION KITS
• AD607 Evaluation Board
DOCUMENTATION
Application Notes
DISCUSSIONS
View all AD607 EngineerZone Discussions.
• AN-778: Using the PRUP Pin on the AD607 and AD61009
Data Sheet
SAMPLE AND BUY
• AD607: Low Power Mixer 3 V Receiver IF Subsystem Data
Visit the product page to see pricing options.
Sheet
• AD61009: Low Power Mixer 3 V Receiver IF Subsystem
Data Sheet
TECHNICAL SUPPORT
Submit a technical question or find your regional support
number.
Product Highlight
• IS-54/IS-136 IF Baseband CHIPSET
DOCUMENT FEEDBACK
TOOLS AND SIMULATIONS
• ADIsimPLL™
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• ADIsimRF
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AD607–SPECIFICATIONS (@ TA = 25؇C, Supply = 3.0 V, IF = 10.7 MHz, unless otherwise noted.)
AD607ARS
Typ
Model
Conditions
Min
Max
Unit
DYNAMIC PERFORMANCE
MIXER
Maximum RF and LO Frequency Range
Maximum Mixer Input Voltage
Input 1 dB Compression Point
Input Third-Order Intercept
Noise Figure
For Conversion Gain > 20 dB
500
54
–15
–5
14
12
1.3
45
–16
1
MHz
mV
dBm
dBm
dB
For Linear Operation; Between RFHI and RFLO
RF Input Terminated in 50 Ω
RF Input Terminated in 50 Ω
Matched Input, Max Gain, f = 83 MHz, IF = 10.7 MHz
Matched Input, Max Gain, f = 144 MHz, IF = 10.7 MHz
dB
V
Maximum Output Voltage at MXOP
Mixer Output Bandwidth at MXOP
LO Drive Level
LO Input Impedance
Isolation, RF to IF
Isolation, LO to IF
Isolation, LO to RF
Isolation, IF to RF
Z
IF = 165 Ω, at Input Compression
–3 dB, ZIF = 165 Ω
MHz
dBm
kΩ
dB
dB
Mixer LO Input Terminated in 50 Ω
LOIP to VMID
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
RF = 240 MHz, IF = 10.7 MHz, LO = 229.3 MHz
30
20
40
70
dB
dB
IF AMPLIFIERS
Noise Figure
Max Gain, f = 10.7 MHz
IF = 10.7 MHz
IF = 10.7 MHz
ZIF = 600 Ω
From IFOP to VMID
–3 dB at IFOP, Max Gain
17
–15
18
560
15
45
dB
Input 1 dB Compression Point
Output Third-Order Intercept
Maximum IF Output Voltage at IFOP
Output Resistance at IFOP
Bandwidth
dBm
dBm
mV
Ω
MHz
GAIN CONTROL
Gain Control Range
Gain Scaling
(See Figures 23 and 24)
Mixer + IF Section, GREF to 1.5 V
GREF to 1.5 V
GREF to General Reference Voltage VR
GREF to 1.5 V, 80 dB Span
90
20
75/VR
1
5
dB
mV/dB
dB/V
dB
Gain Scaling Accuracy
Bias Current at GAIN
Bias Current at GREF
Input Resistance at GAIN, GREF
µA
1
1
µA
MΩ
I AND Q DEMODULATORS
Required DC Bias at DMIP
Input Resistance at DMIP
Input Bias Current at DMIP
Maximum Input Voltage
VPOS/2
50
2
150
75
0.2
–1.2
–100
18
1.23
+10
1.5
V dc
kΩ
From DMIP to VMID
µA
IF > 3 MHz
IF ≤ 3 MHz
mV
mV
dB
Degrees
dBc/Hz
dB
V
mV
Amplitude Balance
Quadrature Error
IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz
IF = 10.7 MHz, Outputs at 600 mV p-p, F = 100 kHz
IF = 10.7 MHz, F = 10 kHz
Phase Noise in Degrees
Demodulation Gain
Maximum Output Voltage
Output Offset Voltage
Output Bandwidth
Sine Wave Input, Baseband Output
RL ≥ 20 kΩ
Measured from IOUT, QOUT to VMID
Sine Wave Input, Baseband Output
–150
+150
MHz
PLL
Required DC Bias at FDIN
Input Resistance at FDIN
Input Bias Current at FDIN
Frequency Range
Required Input Drive Level
Acquisition Time to 3°
VPOS/2
50
200
0.4 to 12
400
16.5
V dc
kΩ
From FDIN to VMID
nA
MHz
mV
µs
Sine Wave Input at Pin 1
IF = 10.7 MHz
POWER-DOWN INTERFACE
Logical Threshold
Input Current for Logical High
Turn-On Response Time
Standby Current
For Power Up on Logical High
To PLL Locked
2
75
16.5
550
V dc
µA
µs
µA
POWER SUPPLY
Supply Range
2.92
5.5
V
Supply Current
Midgain, IF = 10.7 MHz
8.5
mA
OPERATING TEMPERATURE
TMIN to TMAX
Operation to 2.92 V Minimum Supply Voltage
Operation to 4.5 V Minimum Supply Voltage
–25
–40
+85
+85
°C
°C
Specifications subject to change without notice.
REV. C
–2–
AD607
ABSOLUTE MAXIMUM RATINGS1
ORDERING GUIDE
Supply Voltage VPS1, VPS2 to COM1, COM2 . . . . . . . 5.5 V
Internal Power Dissipation2 . . . . . . . . . . . . . . . . . . . . 600 mW
2.92 V to 5.5 V Operating Temperature Range
Temperature
Range
Package
Description
Package
Option
Model
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –25°C to +85°C
4.5 V to 5.5 V Operating Temperature Range
AD607ARS –25°C to +85°C
20-Lead Plastic RS-20
for 2.92 V to 5.5 V SSOP
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Lead Temperature Range (Soldering 60 sec) . . . . . . . . . 300°C
Operation; –40°C
to +85°C for 4.5 V
to 5.5 V Operation
NOTES
1 Stresses above those listed under Absolute Maximum Rating may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2 Thermal Characteristics: 20-lead SSOP Package: θJA = 126°C/W.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD607 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
–3–
REV. C
AD607
PIN FUNCTION DESCRIPTIONS
Function
Pin Mnemonic
Reads
1
FDIN
Frequency Detector Input
PLL Input for I/Q Demodulator Quadrature Oscillator, 400 mV
Drive Required from External Oscillator. Must be biased at VP/2.
2
3
COM1
PRUP
Common #1
Power-Up Input
Supply Common for RF Front End and Main Bias
3 V/5 V CMOS compatible power-up control; logical high =
powered-up; max input level = VPS1 = VPS2.
4
LOIP
Local Oscillator Input
LO input, ac-coupled 54 mV LO input is required (–16 dBm for
50 Ω input termination).
5
6
7
8
RFLO
RFHI
GREF
MXOP
RF “Low” Input
RF “High” Input
Gain Reference Input
Mixer Output
Usually Connected to AC Ground
AC-Coupled, 56 mV, Max RF Input for Linear Operation
High Impedance Input, typically 1.5 V, sets gain scaling.
High Impedance, Single-Sided Current Output, 1.3 V Max
Voltage Output ( 6 mA Max Current Output)
9
VMID
IFHI
IFLO
GAIN
Midsupply Bias Voltage
IF “High” Input
IF “Low” Input
Output of the Midsupply Bias Generator (VMID = VPOS/2)
AC-Coupled IF Input, 56 mV Max Input for Linear Operation
Reference Node for IF Input; Auto-Offset Null
High Impedance Input, 0 V–2 V Using 3 V Supply, Max Gain at
V = 0
10
11
12
Gain Control Input
13
14
COM2
IFOP
Common #2
IF Output
Supply Common for IF Stages and Demodulator
Low Impedance, Single-Sided Voltage Output, 5 dBm
( 560 mV) Max
15
DMIP
Demodulator Input
Signal input to I and Q demodulators has a 150 mV max input
at IF > 3 MHz for linear operation; 75 mV max input at IF < 3 MHz
for linear operation. Must be biased at VP/2.
16
17
VPS2
QOUT
VPOS Supply #2
Quadrature Output
Supply to High Level IF, PLL, and Demodulators
Low Impedance Q Baseband Output; 1.23 V Full Scale in 20 kΩ
Min Load; AC-Coupled
18
IOUT
In-Phase Output
Low Impedance I Baseband Output; 1.23 V Full Scale in 20 kΩ
Min Load; AC-Coupled
19
20
FLTR
VPS1
PLL Loop Filter
VPOS Supply #1
Series RC PLL Loop Filter, Connected to Ground
Supply to Mixer, Low Level IF, PLL, and Gain Control
PIN CONNECTION
20-Lead SSOP (RS-20)
1
2
20
19
18
17
16
15
14
13
12
11
VPS1
FLTR
IOUT
QOUT
VPS2
DMIP
IFOP
COM2
GAIN
IFLO
FDIN
COM1
PRUP
LOIP
3
4
5
RFLO
RFHI
AD607
TOP VIEW
(Not to Scale)
6
7
GREF
MXOP
VMID
IFHI
8
9
10
–4–
REV. C
AD607
HP8764B
0
50⍀
HP8656B
IEEE
RF_OUT
1
0
SYNTHESIZER
HP8656B
S0
S1
V
HP8764B
0
50⍀
CHARACTERIZATION
BOARD
RF_OUT
IEEE
1
50⍀
SYNTHESIZER
1
0
S0
S1
V
RFHI
MXOP
X
R
L
1
HP8656B
50⍀
LOIP
IFHI
RF_OUT
IEEE
SYNTHESIZER
HP6633A
P6205
TEK1105
OUT1
IFOP
X10
OUT IN1
HP8765B
VPOS
0
1
FET PROBE
HP8594E
VNEG
SPOS
SNEG
C
IEEE
IN2
OUT2
PROBE
SUPPLY
IEEE
RF_IN
SPEC
S0
V
S1
DMIP
FDIN
IOUT
AN
DCPS
PLL
HP34401A
QOUT
HI
LO
I
CPIB
IEEE
VPOS
PRUP
GAIN
BIAS
DMM
R5
DP8200
1k⍀
VPOS
VNEG
SPOS
HP8765B
0
1
SNEG
C
V
REF
S0
V
S1
Figure 1. Mixer/Amplifier Test Set
HP8720C
PORT_1
PORT_2
NETWORK AN
IEEE_488
CHARACTERIZATION
BOARD
HP8765B
HP8765B
50⍀
0
1
0
HP346B
NOISE
HP8970A
28V_OUT
NOISE FIGURE METER
1
C
RFHI
C
MXOP
X
RF_IN
28V
R
S0
V
S1
S0
S1
V
L
NOISE SOURCE
HP8656B
RF_OUT
IEEE
SYNTHESIZER
LOIP
IFHI
IFOP
IOUT
DMIP
FDIN
PLL
QOUT
HP6633A
VPOS
PRUP
GAIN
VPOS
BIAS
VNEG
SPOS
SNEG
IEEE
IEEE
DCPS
DP8200
VPOS
VNEG
SPOS
SNEG
V
REF
Figure 2. Mixer Noise Figure Test Set
REV. C
–5–
AD607
CHARACTERIZATION
BOARD
RFHI
MXOP
X
R
L
LOIP
IFHI
HP346B
NOISE
NOISE SOURCE
HP8970A
28V_OUT
NOISE FIGURE METER
P6205
TEK1103
OUT1
X10
IFOP
OUT IN1
28V
RF_IN
PROBE
FET
IN2
OUT2
PROBE SUPPLY
DMIP
FDIN
IOUT
PLL
QOUT
HP6633A
VPOS
PRUP
GAIN
VPOS
BIAS
VNEG
SPOS
SNEG
IEEE
IEEE
DCPS
DP8200
VPOS
VNEG
SPOS
SNEG
V
REF
Figure 3. IF Amp Noise Figure Test Set
CHARACTERIZATION
BOARD
HP8764B
50⍀
50⍀
MXOP
RFHI
LOIP
IFHI
0
X
R
HP8656B
L
IEEE
SYNTHESIZER
1
0
RF_OUT
S0
S1
V
1
IFOP
HP3326A
OUTPUT_1
OUTPUT_2
1103
OUT1
P6205
OUT
DCFM
IEEE
DMIP
FDIN
IOUT
IN1
X10
HP8694E
RF_IN
FET PROBE
HP8765B
HP8765B
PLL
0
1
DUAL SYNTHESIZER
0
1
IEEE
QOUT
P6205
C
C
SPEC AN
OUT IN2
PROBE
SUPPLY
OUT2
X10
HP6633A
VPOS
S0
S1
S0
V
V
S1
VPOS
PRUP
GAIN
FET PROBE
BIAS
VNEG
IEEE
HP54120
SPOS
CH1
CH2
CH3
CH4
TRIG
SNEG
DCPS
DP8200
VPOS
IEEE_488
DIGITAL
VNEG
IEEE
OSCILLOSCOPE
SPOS
SNEG
V
REF
Figure 4. PLL/Demodulator Test Set
–6–
REV. C
AD607
CHARACTERIZATION
BOARD
RFHI
MXOP
R
X
L
LOIP
IFHI
HP6633A
VPOS
VNEG
SPOS
SNEG
IFOP
IEEE
DCPS
DP8200
IOUT
DMIP
FDIN
VPOS
PLL
VNEG
SPOS
SNEG
IEEE
GPIB
QOUT
VPOS
PRUP
GAIN
V
REF
BIAS
R1
499k
⍀
HP34401A
HI
LO
I
DMM
Figure 5. GAIN Pin Bias Test Set
CHARACTERIZATION
BOARD
MXOP
RFHI
R
X
L
LOIP
IFHI
HP6633A
VPOS
IFOP
VNEG
SPOS
SNEG
IEEE
DCPS
DP8200
DMIP
FDIN
IOUT
VPOS
PLL
VNEG
SPOS
SNEG
IEEE
GPIB
QOUT
VPOS
PRUP
GAIN
V
REF
BIAS
R1
499k⍀
HP34401A
HI
LO
I
DMM
Figure 6. Demodulator Bias Test Set
CHARACTERIZATION
BOARD
HP3325B
MXOP
RFHI
RF_OUT
IEEE
SYNTHESIZER
R
X
L
LOIP
IFHI
HP6633A
VPOS
VNEG
SPOS
SNEG
HP8594E
IFOP
IEEE
RF_IN
SPEC AN
IEEE
DCPS
HP6633A
DMIP
FDIN
IOUT
VPOS
VNEG
SPOS
SNEG
PLL
IEEE
GPIB
QOUT
VPOS
PRUP
GAIN
DCPS
R1
10k⍀
BIAS
HP34401A
HI
LO
I
DMM
Figure 7. Power-Up Threshold Test Set
–7–
REV. C
AD607
CHARACTERIZATION
BOARD
MXOP
RFHI
R
X
L
LOIP
IFHI
P6205
1103
HP54120
IFOP
X10
OUT IN1
OUT1
OUT2
CH1
CH2
CH3
CH4
TRIG
FET PROBE
P6205
50⍀
OUT
IN2
X10
PROBE SUPPLY
FET PROBE
FL6082A
RF_OUT
MOD_OUT
IOUT
DMIP
FDIN
IEEE_488
DIGITAL
OSCILLOSCOPE
IEEE
IEEE
PLL
QOUT
HP6633A
NOTE: MUST BE 3 RESISTOR POWER DIVIDER
VPOS
PRUP
GAIN
VPOS
VNEG
SPOS
SNEG
BIAS
DCPS
DP8200
VPOS
VNEG
SPOS
IEEE
IEEE
SNEG
V
REF
HP8112
PULSE_OUT
PULSE GENERATOR
Figure 8. Power-Up Test Set
CHARACTERIZATION
BOARD
RFHI
MXOP
R
X
L
LOIP
IFHI
HP8656B
RF_OUT
SYNTHESIZER
HP8594E
1103
P6205
IFOP
X10
IEEE
OUT IN1
OUT1
RF_IN
IEEE
FET PROBE
R1
1k⍀
SPEC AN
IN2
OUT2
PROBE SUPPLY
IOUT
DMIP
FDIN
PLL
QOUT
HP6633A
DCPS
VPOS
PRUP
GAIN
VPOS
VNEG
SPOS
BIAS
IEEE
SNEG
Figure 9. IF Output Impedance Test Set
–8–
REV. C
AD607
CHARACTERIZATION
BOARD
RFHI
MXOP
R
X
L
LOIP
IFHI
IFOP
20⍀
dB
HP54120
P6205
1103
FL6082A
RF_OUT
MOD_OUT
DMIP
FDIN
IOUT
OUT IN1
OUT1
X10
CH1
CH2
CH3
CH4
TRIG
IEEE
IEEE
FET PROBE
P6205
PLL
QOUT
OUT IN2
OUT2
X10
HP6633A
VPOS
PRUP
IEEE_488
DIGITAL
FET PROBE PROBE SUPPLY
VPOS
VNEG
SPOS
SNEG
BIAS
OSCILLOSCOPE
GAIN
DCPS
DP8200
VPOS
VNEG
SPOS
SNEG
IEEE
V
REF
Figure 10. PLL Settling Time Test Set
CHARACTERIZATION
BOARD
MXOP
RFHI
R
X
L
HP3325B
LOIP
IFHI
IEEE
RF_OUT
IFOP
SYNTHESIZER
HP3326
OUTPUT_1
OUTPUT_2
P6205
1103
DCFM
IEEE
DMIP
FDIN
IOUT
OUT IN1
OUT1
X10
HP8765B
FET PROBE
P6205
DUAL SYNTHESIZER
0
1
PLL
HP8694E
RF_IN
QOUT
C
OUT IN2
OUT2
X10
IEEE
HP6633A
VPOS
S0
S1
V
SPEC AN
VPOS
PRUP
GAIN
FET PROBE PROBE SUPPLY
BIAS
VNEG
IEEE
SPOS
SNEG
DCPS
DP8200
VPOS
VNEG
IEEE
SPOS
SNEG
V
REF
Figure 11. Quadrature Accuracy Test Set
–9–
REV. C
AD607
VPOS
GND
C15
0.1F
4.99k⍀
R10
C11
10nF
0.1F
C13
0.1F
C1
FDIN
R8
51.1⍀
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
FDIN
VPS1
FLTR
IOUT
QOUT
VPS2
DMIP
IFOP
0⍀
R12
COM1
PRUP
LOIP
C3
10nF
R1
C10
1nF
1k⍀
PRUP
LOIP
IOUT
0.1F
C2
C16
1nF
*
AD607
R7
RFLO
51.1⍀
QOUT
*
RFHI
C9
1nF
R2
316⍀
GREF
RFHI
R6
MXOP
VMID
IFOP
*
COM2
GAIN
IFLO
51.1⍀
R13
301⍀
C5
1nF
GAIN
*
10 IFHI
MXOP
*
R9
51.1⍀
R14
54.9⍀
R5
332⍀
C6
0.1F
C7
1nF
DMIP
*
C8
0.1F
IFHI
0.1F
*CONNECTIONS ARE DC-COUPLED.
Figure 12. Characterization Board
–10–
REV. C
Typical Performance Characteristics–AD607
30
20
19
18
V
= 0.3V
25
20
GAIN
17
16
15
14
13
12
11
10
V
= 0.6V
GAIN
15
10
5
VPOS = 5V, IF = 20MHz
VPOS = 3V, IF = 20MHz
V
= 1.2V
= 1.8V
GAIN
V
GAIN
0
V
= 2.4V
GAIN
–5
–10
VPOS = 5V, IF = 10MHz
VPOS = 3V, IF = 10MHz
50
70
90
110 130 150 170 190 210 230 250
RF FREQUENCY – MHz
0.1
1
10
100
INTERMEDIATE FREQUENCY – MHz
TPC 1. Mixer Noise Figure vs. Frequency
TPC 4. Mixer Conversion Gain vs. IF, T = 25°C,
VPOS = 3 V, VREF = 1.5 V
4500
4.0
3.5
3.0
2.5
80
4000
3500
3000
70
CUBIC FIT OF IF_GAIN (TEMP)
60
IF AMP GAIN
C SHUNT COMPONENT
50
40
30
2500
2000
1500
1000
500
2.0
1.5
20
CUBIC FIT OF CONV_GAIN (TEMP)
10
MIXER CG
R SHUNT COMPONENT
1.0
0.5
0
0
–10
–20
0
0
50
100 150 200 250 300 350 400 450 500
FREQUENCY – MHz
–50 –40 –30 –20–10
0
10 20 30 40 50 60 70 80 90 100 110 120 130
TEMPERATURE – ؇C
TPC 2. Mixer Input Impedance vs. Frequency,
VPOS = 3 V, V GAIN = 0.8 V
TPC 5. Mixer Conversion Gain and IF Amplifier Gain vs.
Temperature, VPOS = 3 V, VGAIN = 0.3 V, VREF = 1.5 V, IF =
10.7 MHz, RF = 250 MHz
30
80
70
25
20
15
10
5
V
= 0.00V
GAIN
V
= 0.54V
= 1.62V
GAIN
CUBIC FIT OF IF_GAIN (V
POS
)
IF AMP GAIN
60
50
V
= 1.08V
GAIN
V
GAIN
40
30
20
10
0
–5
–10
CUBIC FIT OF CONV_GAIN (V
)
POS
V
= 2.16V
GAIN
–15
–20
MIXER CG
2.4 2.6 2.8 3.2 3.4 3.6 3.8
SUPPLY – V
3
4
4.2 4.4 4.6 4.8
5 5.2 5.4 5.6 5.8 6
0
50 100 150 200 250 300 350 400 450 500 550 600
RADIO FREQUENCY – MHz
TPC 6. Mixer Conversion Gain and IF Amplifier Gain vs.
Supply Voltage, T = 25°C, VGAIN = 0.3 V, VREF = 1.5 V, IF =
10.7 MHz, RF = 250 MHz
TPC 3. Mixer Conversion Gain vs. Frequency,
T = 25°C, VPOS = 2.92 V, VREF = 1.35 V, IF = 10.7 MHz
–11–
REV. C
AD607
80
–90.00
V
= 0.3V
GAIN
70
60
50
40
30
20
10
0
–100.00
V
V
= 0.6V
= 1.2V
GAIN
–110.00
–120.00
–130.00
–140.00
–150.00
GAIN
V
= 1.8V
= 2.4V
GAIN
V
GAIN
–10
0.1
1
10
100
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
INTERMEDIATE FREQUENCY – MHz
CARRIER FREQUENCY OFFSET, f(fm) – Hz
TPC 7. IF Amplifier Gain vs. Frequency,
TPC 10. PLL Phase Noise L (F) vs. Frequency,
T = 25°C, VPOS = 3 V, VREF = 1.5 V
VPOS = 3 V, C3 = 0.1 µF, IF = 10.7 MHz
2.5
10
8
6
IF AMP
4
2
2
0
–2
–4
–6
–8
–10
MIXER
1.5
0.1
1
10
100
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
2.2 2.4 2.6 2.8 3
PLL FREQUENCY – MHz
GAIN VOLTAGE – V
TPC 8. Gain Error vs. Gain Control Voltage,
Representative Part
TPC 11. PLL Loop Voltage at FLTR (KVCO) vs. Frequency
8
7
6
5
4
3
2
1
0
996.200s
1.00870ms
2.5s/DIV
1.02120ms
TIMEBASE
MEMORY 1
TIMEBASE
MEMORY 2
TIMEBASE
DELTA T
=
DELAY
OFFSET
DELAY
OFFSET
DELAY
=
=
=
=
=
1.00870ms
127.3mV
=
=
=
=
=
=
100.0mV/DIV
2.50s/DIV
20.00mV/DIV
2.50s/DIV
16.5199s
1.00870ms
155.2mV
85
86
87
88
89
90
91
92
93
94
95
1.00870ms
QUADRATURE ANGLE – Degrees
START
1.00048ms
STOP
=
1.01700ms
TRIGGER ON EXTERNAL AT POS. EDGE AT 134.0mV
TPC 12. Demodulator Quadrature Angle, Histogram,
T = 25°C, VPOS = 3 V, IF = 10.7 MHz
TPC 9. PLL Acquisition Time
–12–
REV. C
AD607
30
25
20
20
19
I_GAIN_CORR
18
17
16
15
14
13
12
11
10
CUBIC FIT OF I_GAIN_CORR (TEMP)
15
10
5
0
–2
–1
0
1
2
2.5
3
3.5
4
4.5
5
5.5
6
IQ GAIN BALANCE – dB
SUPPLY – V
TPC 13. Demodulator Gain Balance, Histogram,
TPC 16. Demodulator Gain vs. Supply Voltage
T = 25°C, VPOS = 3 V, IF = 10.7 MHz
20
19
40
35
30
25
20
15
10
5
18
17
I_GAIN_CORR
16
15
QUADRATIC FIT OF I_GAIN_CORR (IFF)
14
13
12
11
10
0
0
0.2
0.4 0.6 0.8
1.0
1.2 1.4 1.6
1.8 2.0
17
17.2 17.4 17.6 17.8
18
18.2 18.4 18.6 18.8
BASEBAND FREQUENCY – MHz
DEMODULATOR GAIN – dB
TPC 14. Demodulator Gain vs. Frequency
TPC 17. Demodulator Gain Histogram,
T = 25°C, VPOS = 3 V, IF = 10.7 MHz
20
I_GAIN_CORR
19
18
17
CUBIC FIT OF I_GAIN_CORR (TEMP)
16
15
14
13
12
11
10
–50 –40 –30 –20 –10
0
10 20 30 40 50 60 70 80 90 100110 120 130
TEMPERATURE – ؇C
TPC 15. Demodulator Gain vs. Temperature
–13–
REV. C
AD607
PRODUCT OVERVIEW
The AD607 provides most of the active circuitry required to
realize a complete low power, single-conversion superhetero-
dyne receiver, or most of a double-conversion receiver, at input
frequencies up to 500 MHz, and an IF from 400 kHz to 12 MHz.
The internal I/Q demodulators and their associated phase-
locked loop, which can provide carrier recovery from the IF,
support a wide variety of modulation modes, including
n-PSK, n-QAM, and AM. A single positive supply voltage of 3 V
is required (2.92 V minimum, 5.5 V maximum) at a typical
supply current of 8.5 mA at midgain. In the following discus-
sion, VP will be used to denote the power supply voltage, which
will be assumed to be 3 V.
40.2127ms
40.2377ms
500s/DIV
40.2627ms
40.2377ms
154.0mV
TIMEBASE
MEMORY 1
TIMEBASE
MEMORY 2
TIMEBASE
DELTA T
=
DELAY
OFFSET
DELAY
OFFSET
DELAY
=
=
=
=
=
=
=
=
=
=
=
100.0mV/DIV
5.00s/DIV
60.00mV/DIV
5.00s/DIV
15.7990s
40.2377ms
209.0mV
Figure 13 shows the main sections of the AD607. It consists of a
variable gain UHF mixer and linear four-stage IF strip, which
together provide a voltage controlled gain range of more than
90 dB; dual demodulators, each comprising a multiplier fol-
lowed by a two-pole, 2 MHz low-pass filter; and a phase-locked
loop providing the inphase and quadrature clocks. A biasing
system with CMOS compatible power-down completes the
AD607.
40.2377ms
START
40.2327ms
STOP
=
40.2485ms
TRIGGER ON EXTERNAL AT POS. EDGE AT 40.0mV
TPC 18. Power-Up Response Time to PLL Stable
15
Mixer
The UHF mixer is an improved Gilbert cell design, and can
operate from low frequencies (it is internally dc-coupled) up to
an RF input of 500 MHz. The dynamic range at the input of the
mixer is determined at the upper end by the maximum input
signal level of 56 mV between RFHI and RFLO up to which the
mixer remains linear, and at the lower end by the noise level. It is
customary to define the linearity of a mixer in terms of the 1 dB
gain-compression point and third order intercept, which for the
AD607 are –15 dBm and –8 dBm, respectively, in a 50 Ω system.
10
5
0
0.5
1
1.5
2
2.5
GAIN VOLTAGE – V
TPC 19. Power Supply Current vs. Gain Control Voltage,
GREF = 1.5 V
LOIP
RFHI
VMID
IOUT
IFHI
MXOP
VMID
BPF
FDIN
DMIP
IFOP
BPF OR
LPF
VQFO
RFLO
FLTR
IFLO
QOUT
MIDPOINT
BIAS
GENERATOR
GAIN
VPS1
VPS2
PRUP
GREF
BIAS
GENERATOR
PTAT
VOLTAGE
AD607
COM1 COM2
Figure 13. Functional Block Diagram
–14–
REV. C
AD607
The mixer’s RF input port is differential, that is, pin RFLO is
functionally identical to RFHI, and these nodes are internally
biased; we will generally assume that RFLO is decoupled to ac
ground. The RF port can be modeled as a parallel RC circuit as
shown in Figure 14.
Table I. Filter Termination Resistor Values for
Common IFs
Filter
Filter Termination Resistor
Values for 24 dB of Mixer Gain
*
IF
Impedance
R1
R2
R3
450 kHz
455 kHz
6.5 MHz
1500 Ω
1500 Ω
1000 Ω
174 Ω
174 Ω
215 Ω
330 Ω
1330 Ω
1330 Ω
787 Ω
0 Ω
1500 Ω
1500 Ω
1000 Ω
330 Ω
AD607
C1
C2
RFHI
10.7 MHz 330 Ω
R
IN
C
IN
L1
RFLO
*Resistor values were calculated such that R1+ R2 = ZFILTER and
R1ʈ (R2 + ZFILTER) = 165 Ω.
C3
The maximum permissible signal level at MXOP is determined
by both voltage and current limitations. Using a 3 V supply and
VMID at 1.5 V, the maximum swing is about 1.3 V. To attain
a voltage swing of 1 V in the standard IF filter load of 165 Ω
requires a peak drive current of about 6 mA, which is well
within the linear capability of the mixer. However, these upper
limits for voltage and current should not be confused with issues
related to the mixer gain, already discussed. In an operational
system, the AGC voltage will determine the mixer gain, and
hence the signal level at the IF input Pin IFHI; it will always be
less than 56 mV (–15 dBm into 50 Ω), which is the limit of the
IF amplifier’s linear range.
C1, C2, L1: OPTIONAL MATCHING CIRCUIT
C3: COUPLES RFLO TO AC GROUND
Figure 14. Mixer Port Modeled as a Parallel RC Network;
an Optional Matching Network Is also Shown
The local oscillator (LO) input is internally biased at VP/2 via a
nominal 1000 Ω resistor internally connected from pin LOIP to
VMID. The LO interface includes a preamplifier that minimizes
the drive requirements, thus simplifying the oscillator design
and reducing LO leakage from the RF port. Internally, this
single-sided input is actually differential; the noninverting input
is referenced to Pin VMID. The LO requires a single-sided
drive of 50 mV, or –16 dBm in a 50 Ω system.
IF Amplifier
Most of the gain in the AD607 arises in the IF amplifier strip,
which comprises four stages. The first three are fully differential
and each has a gain span of 25 dB for the nominal AGC voltage
range. Thus, in conjunction with the mixer’s variable gain, the
total gain exceeds 90 dB. The final IF stage has a fixed gain of
20 dB, and it also provides differential to single-ended conversion.
The mixer’s output passes through both a low-pass filter and a
buffer, which provides an internal differential to single-ended
signal conversion with a bandwidth of approximately 45 MHz.
Its output at Pin MXOP is in the form of a single-ended cur-
rent. This approach eliminates the 6 dB voltage loss of the usual
series termination by replacing it with shunt terminations at
both the input and the output of the filter. The nominal conver-
sion gain is specified for operation into a total IF band-pass
filter (BPF) load of 165 Ω, that is, a 330 Ω filter doubly-termi-
nated as shown in Figure 14. Note that these loads are con-
nected to bias point VMID, which is always at the midpoint of
the supply (that is, VP/2).
The IF input is differential, at IFHI (noninverting relative to the
output IFOP) and IFLO (inverting). Figure 16 shows a simpli-
fied schematic of the IF interface. The offset voltage of this
stage would cause a large dc output error at high gain, so it is
nulled by a low pass feedback path from the IF output, also
shown in TPC 13. Unlike the mixer output, the signal at IFOP
is a low-impedance single-sided voltage, centered at VP/2 by the
dc feedback loop. It may be loaded by a resistance as low as
50 Ω, which will normally be connected to VMID.
The conversion gain is measured between the mixer input and
the input of this filter, and varies between 1.5 dB and 26.5 dB
for a 165 Ω load impedance. Using filters of higher impedance,
the conversion gain can always be maintained at its specified
value or made even higher; for filters of lower impedance, of say
ZO, the conversion gain will be lowered by 10 log10(165/ZO).
Thus, the use of a 50 Ω filter will result in a conversion gain that
is 5.2 dB lower. Figure 15 shows filter matching networks and
Table I lists resistor values.
AD607
10k⍀
IFHI
VMID
IFOP
IFLO
10k⍀
OFFSET FEEDBACK
LOOP
1nF
R2
BPF
MXOP
VMID
8
9
10 IFHI
11 IFLO
Figure 16. Simplified Schematic of the IF Interface
R3
R1
100nF
100nF
Figure 15. Suggested IF Filter Matching Network. The
Values of R1 and R2 Are Selected to Keep the Impedance
at Pin MXOP at 165 Ω
–15–
REV. C
AD607
The IF’s small-signal bandwidth is approximately 45 MHz from
IFHI and IFLO through IFOP. The peak output at IFOP is
560 mV at VP = 3 V and 400 mV at the minimum VP of
2.92 V. This allows some headroom at the demodulator inputs
(Pin DMIP), which accept a maximum input of 150 mV for
IFs > 3 MHz and 75 mV for IFs ≤ 3 MHz (at IFs ≤ 3 MHz,
the drive to the demodulators must be reduced to avoid saturat-
ing the output amplifiers with higher order mixing products that
are no longer removed by the on-board low pass filters).
Table II lists gain control voltages and scale factors for power
supply voltages from 2.92 V to 5.5 V
Alternatively, Pin GREF can be tied to an external voltage
reference (VR) from, for example, an AD1582 (2.5 V) or
AD1580 (1.21 V) voltage reference, to provide supply-
independent gain scaling of VR/75 (volts per dB). When using
the Analog Devices’ AD7013 and AD7015 baseband converters,
the external reference may also be provided by the reference
output of the baseband converter (Figure 18). For example, the
AD7015 baseband converter provides a VR of 1.23 V; when
connected to GREF, the gain scaling is 16.4 mV/dB (60 dB/V).
An auxiliary DAC in the AD7015 can be used to generate the
MGC voltage. Since it uses the same reference voltage, the
numerical input to this DAC provides an accurate RSSI value
in digital form, no longer requiring the reference voltage to have
high absolute accuracy.
Since there is no band-limiting in the IF strip, the output-
referred noise can be quite high; in a typical application and
at a gain of 75 dB, it is about 100 mV rms, making post-IF filtering
desirable. IFOP may be also used as an IF output for driving
an A/D converter, external demodulator, or external AGC
detector. Figure 17 shows methods of matching the optional
second IF filter.
VPOS
AD7013 OR
AD607
AD7015
R
AD607
2R
T
IOUT
QOUT
VMID
IADC
R
T
C
R
IFOP
DMIP
BPF
QADC
2R
C
T
IADC
QADC
GREF
GAIN
(AD7015)
(AD7013)
REFOUT
BYPASS
10nF
AUX DAC
a. Biasing DMIP from Power Supply (Assumes BPF
AC-Coupled Internally)
1nF
Figure 18. Interfacing the AD607 to the AD7013 or AD7015
Baseband Converters
AD607
R
T
IFOP
DMIP
VMID
BPF
I/Q Demodulators
Both demodulators (I and Q) receive their inputs at Pin DMIP.
Internally, this single-sided input is actually differential; the
noninverting input is referenced to Pin VMID. Each demodula-
tor comprises a full-wave synchronous detector followed by a
2 MHz, two-pole low-pass filter, producing single-sided outputs
at pins IOUT and QOUT. Using the I and Q demodulators for
IFs above 12 MHz is precluded by the 400 kHz to 12 MHz
response of the PLL used in the demodulator section. Pin DMIP
requires an external bias source at VP/2; Figure 19 shows
suggested methods.
R
T
C
BYPASS
b. Biasing DMIP from VMID (Assumes BPF AC-Coupled
Internally)
Figure 17. Input and Output Matching of the Optional
Second IF Filter
Outputs IOUT and QOUT are centered at VP/2 and can swing
up to 1.23 V even at the low supply voltage of 2.92 V. They can
therefore directly drive the RX ADCs in the AD7015 baseband
converter, which require an amplitude of 1.23 V to fully load
them when driven by a single-sided signal. The conversion gain of
the I and Q demodulators is 18 dB (X8), requiring a maxi-
mum input amplitude at DMIP of 150 mV for IFs > 3 MHz.
Gain Scaling and RSSI
The AD607’s overall gain, expressed in decibels, is linear-in-dB
with respect to the AGC voltage VG at Pin GAIN. The gain of
all sections is maximum when VG is zero, and reduces progres-
sively up to VG = 2.2 V (for VP = 3 V; in general, up to a limit
VP – 0.8 V). The gain of all stages changes in parallel. The AD607
features temperature compensation of the gain scaling. The gain
control scaling is proportional to the reference voltage applied to
the Pin GREF. When this pin is tied to the midpoint of the
supply (VMID), the scale is nominally 20 mV/dB (50 dB/V) for
VP = 3 V. Under these conditions, the lower 80 dB of gain range
(mixer plus IF) corresponds to a control voltage of 0.4 V ≤
VG ≤ 2.0 V. The final centering of this 1.6 V range depends on
the insertion losses of the IF filters used. More generally, the gain
scaling using these connections is VP/150 (volts per dB), so scale
becomes 33.3 mV/dB (30 dB/V) using a 5 V supply, with a
proportional change in the AGC range, to 0.33 V ≤ VG ≤ 3 V.
–16–
REV. C
AD607
VPOS
2R
are generated at IOUT and QOUT, respectively. The quadra-
ture accuracy of this VFQO is typically –1.2°C at 10.7 MHz. The
PLL uses a sequential-phase detector that comprises low power
emitter-coupled logic and a charge pump (Figure 20).
AD607
T
R
T
IFOP
BPF
2R
T
DMIP
I
U
~
40A
V
F
I-CLOCK
a. Biasing DMIP from Power Supply (Assumes BPF
AC-Coupled Internally)
VARIABLE-
FREQUENCY
QUADRATURE
OSCILLATOR
F
U
D
SEQUENTIAL
PHASE
DETECTOR
90؇
R
C
AD607
R
T
Q-CLOCK
(ECL OUTPUTS)
R
IFOP
BPF
I ~
D
40A
REFERENCE CARRIER
(FDIN AFTER LIMITING)
DMIP
VMID
R
T
Figure 20. Simplified Schematic of the PLL and
Quadrature VCO
C
BYPASS
The reference signal may be provided from an external source
in the form of a high level clock, typically a low level signal
( 400 mV) since there is an input amplifier between FDIN and
the loop’s phase detector. For example, the IF output itself can
be used by connecting DMIP to FDIN, which will then provide
automatic carrier recover for synchronous AM detection and
take advantage of any post-IF filtering. Pin FDIN must be
biased at VP/2; Figure 22 shows suggested methods.
b. Biasing DMIP from VMID (Assumes BPF
AC-Coupled Internally)
Figure 19. Suggested Methods for Biasing Pin DMIP
at VP/2
For IFs < 3 MHz, the on-chip low-pass filters (2 MHz cutoff)
do not attenuate the IF or feedthrough products. Thus, the
maximum input voltage at DMIP must be limited to 75 mV
to allow sufficient headroom at the I and Q outputs for not only
the desired baseband signal, but also the unattenuated higher-
order demodulation products. These products can be removed
by an external low-pass filter. In the case of IS54 applications
using a 455 kHz IF and the AD7013 baseband converter, a simple
one-pole RC filter with its corner above the modulation band-
width is sufficient to attenuate undesired outputs.
The VFQO operates from 400 kHz to 12 MHz and is controlled
by the voltage between VPOS and FLTR. In normal operation,
a series RC network forming the PLL loop filter is connected
from FLTR to ground. The use of an integral sample-hold
system ensures that the frequency-control voltage on Pin FLTR
remains held during power-down, so reacquisition of the carrier
typically occurs in 16.5 µs.
In practice, the probability of a phase mismatch at power-up is
high, so the worst-case linear settling period to full lock needs
to be considered in making filter choices. This is typically 16.5 µs
at an IF of 10.7 MHz for a 100 mV signal at DMIP and FDIN.
Phase-Locked Loop
The demodulators are driven by quadrature signals that are
provided by a variable frequency quadrature oscillator (VFQO),
phase-locked to a reference signal applied to Pin FDIN. When
this signal is at the IF, in-phase and quadrature baseband outputs
Table II. AD607 Gain and Manual Gain Control Voltage vs. Power Supply Voltage
Power Supply
Voltage
(V)
GREF
(= VMID)
(V)
Gain Control
Voltage Input Range
(V)
Scale Factor
(dB/V)
Scale Factor
(mV/dB)
3.0
3.5
4.0
4.5
5.0
5.5
1.5
1.75
2.0
2.25
2.5
2.75
50.00
42.86
37.50
33.33
30.00
27.27
20.00
23.33
26.67
30.00
33.33
36.67
0.400–2.000
0.467–2.333
0.533–2.667
0.600–3.000
0.667–3.333
0.733–3.667
Maximum gain occurs for gain control voltage = 0 V.
–17–
REV. C
AD607
Bias System
USING THE AD607
The AD607 operates from a single supply, VP, usually of 3 V, at
a typical supply current of 8.5 mA at midgain and T = 27°C,
corresponding to a power consumption of 25 mW. Any voltage
from 2.92 V to 5.5 V may be used.
In this section, we will focus on a few areas of special impor-
tance and include a few general application tips. As is true of
any wideband high gain component, great care is needed in PC
board layout. The location of the particular grounding points
must be considered with due regard to the possibility of unwanted
signal coupling, particularly from IFOP to RFHI or IFHI or both.
The bias system includes a fast-acting active-high CMOS-
compatible power-up switch, allowing the part to idle at 550 µA
when disabled. Biasing is proportional-to-absolute temperature
(PTAT) to ensure stable gain with temperature.
The high sensitivity of the AD607 leads to the possibility that
unwanted local EM signals may have an effect on the perfor-
mance. During system development, carefully-shielded test
assemblies should be used. The best solution is to use a fully-
enclosed box enclosing all components, with the minimum
number of needed signal connectors (RF, LO, I, and Q outputs)
in miniature coax form.
An independent regulator generates a voltage at the midpoint
of the supply (VP/2) that appears at the VMID pin at a low
impedance. This voltage does not shut down, ensuring that the
major signal interfaces (e.g., mixer-to-IF and IF-to-demodulators)
remain biased at all times, thus minimizing transient disturbances
at power-up and allowing the use of substantial decoupling
capacitors on this node. The quiescent consumption of this
regulator is included in the idling current.
The I and Q output leads can include small series resistors
(about 100 Ω) inside the shielded box without significant loss
of performance, provided the external loading during testing
is light (that is, a resistive load of more than 20 kΩ and capaci-
tances of a few picofarads). These help to keep unwanted RF
emanations out of the interior.
VPOS
AD607
50k⍀
The power supply should be connected via a through-hole
capacitor with a ferrite bead on both inside and outside leads.
Close to the IC pins, two capacitors of different value should be
used to decouple the main supply (VP) and the midpoint supply
pin, VMID. Guidance on these matters is also generally included
in applications schematics.
FDIN
EXTERNAL
FREQUENCY
REFERENCE
50k⍀
a. Biasing FDIN from Supply when Using
External Frequency Reference
Gain Distribution
As in all receivers, the most critical decisions in effectively using
the AD607 relate to the partitioning of gain between the various
subsections (Mixer, IF Amplifier, Demodulators) and the place-
ment of filters so as to achieve the highest overall signal-to-noise
ratio and lowest intermodulation distortion.
AD607
FDIN
EXTERNAL
FREQUENCY
50k⍀
REFERENCE
VMID
Figure 22 shows the main RF/IF signal path at maximum and
minimum signal levels.
C
BYPASS
b. Biasing FDIN from VMID when Using
External Frequency Reference
Figure 21. Suggested Methods for Biasing Pin FDIN at VP/2
I
؎1.23V
MAX OUTPUT
؎54mV
MAX INPUT
؎1.3V
؎54mV
؎560mV
؎154mV
IOUT
MAX OUTPUT MAX INPUT
MAX OUTPUT MAX INPUT
IFOP DMIP
MXOP IFHI
RFHI
QOUT
IF BPF
IF BPF
Q
LOIP
(VMID)
330⍀ 330⍀
CONSTANT
–16dBm
(؎50mV)
(TYPICAL
IMPEDANCE)
(LOCATION OF OPTIONAL
SECOND IF FILTER)
Figure 22. Signal Levels for Minimum and Maximum Gain
–18–
REV. C
AD607
As noted earlier, the gain in dB is reduced linearly with the voltage
VG on the GAIN pin. Figure 23 shows how the mixer and IF strip
gains vary with VG when GREF is connected to VMID (1.5 V) and
a supply voltage of 3 V is used. Figure 24 shows how these vary
when GREF is connected to a 1.23 V reference.
Fortunately, there is a very simple solution to the fast PRUP
problem. If the PRUP signal (Pin 3) is slowed down so that
the rise time of the signal edge is greater than 35 µs, the
anomalous behavior will not occur. This can be realized by a
simple RC circuit connected to the PRUP pin, where R = 4.7 kΩ
and C = 1.5 nF. This circuit is shown in Figure 25.
90dB
80dB
FROM PRUP
CONTROL SIGNAL
70dB
(67.5dB)
AD607
60dB
4.7k⍀
PRUP
50dB
40dB
30dB
20dB
10dB
0dB
IF GAIN
1.5nF
(21.5dB)
Figure 25. Proper Configuration of AD607 PRUP Signal
MIXER GAIN
All designs incorporating the AD607 should include this circuitry.
(7.5dB)
(1.5dB)
Note that connecting the PRUP pin to the supply voltage will
not eliminate the problem, since the supply voltage may have a
rise time faster than 35 µs. With this configuration, the 4.7 kΩ
series R and 1.5 nF shunt C should be placed between the
supply and the PRUP pin as shown in Figure 25.
2.2V
0.4V
1.8V
0
1V
NORMAL OPERATING RANGE
2V
V
G
Figure 23. Gain Distribution for GREF = 1.5 V
90dB
AD607 EVALUATION BOARD
80dB
70dB
60dB
50dB
40dB
30dB
20dB
10dB
0dB
The AD607 evaluation board (Figures 26 and 27) consists of an
AD607, ground plane, I/O connectors, and a 10.7 MHz band-
pass filter. The RF and LO ports are terminated in 50 Ω to
provide a broadband match to external signal generators to
allow a choice of RF and LO input frequencies. The IF filter is
at 10.7 MHz and has 330 Ω input and output terminations; the
board is laid out to allow the user to substitute other filters for
other IFs.
(67.5dB)
IF GAIN
(21.5dB)
The board provides SMA connectors for the RF and LO port
inputs, the demodulated I and Q outputs, the manual gain con-
trol (MGC) input, the PLL input, and the power-up input. In
addition, the IF output is also available at an SMA connector;
this may be connected to the PLL input for carrier recovery to
realize synchronous AM and FM detection via the I and Q
demodulators, respectively. Table III lists the AD607 Evalua-
tion Board’s I/O Connectors and their functions.
MIXER GAIN
1V
(7.5dB)
(1.5dB)
0.328V
1.64V
0
2V
V
G
NORMAL OPERATING RANGE
Figure 24. Gain Distribution for GREF = 1.23 V
Using the AD607 with a Fast PRUP Control Signal
If the AD607 is used in a system in which the PRUP signal
(Pin 3) is applied with a rise time less than 35 µs, anomalous
behavior occasionally occurs. The problem is intermittent, so it
will not occur every time the part is powered up under these
conditions. It does not occur for any other normal operating condi-
tions when the PRUP signal has a rise time slower than 35 µs.
Symptoms of operation with too fast a PRUP signal include low
gain, oscillations at the I or Q outputs of the device, or no valid
data occurring at the output of the AD607. The problem causes
no permanent damage to the AD607, so it will often operate
normally when reset.
–19–
REV. C
AD607
VPOS
GND
C15
0.1F
JUMPER
R10
4.99k⍀
R11
OPEN
C11
10nF
C12
C1
0.1F
FDIN
0.1F
R8
51.1⍀
FDIN
COM1
VPS1
FLTR
C3 10nF
R12
4.7k⍀
R1
1k⍀
PRUP
PRUP
C10
1nF
IOUT
QOUT
VPS2
DMIP
C17
1.5nF
I
C13
C14
0
0
LOIP
LO
RF
C2 0.1F
R7
C4
AD607
C16
1nF
Q
51.1⍀
C9
1nF
RFLO
47pF
RFHI
R2
R6
51.1⍀
316⍀
IFOP
COM2
GAIN
IFLO
GREF
R5
JUMPER
IF
MXOP
R4
OPEN
332⍀
VMID
IFHI
GAIN
C5
1nF
R3
C6
332⍀
C7
1nF
0.1F
C8
0.1F
AD607 EVALUATION BOARD
(AS RECEIVED)
VPOS
VPOS
R15
50k⍀
R17
OPEN
R18
OPEN
R13
50k⍀
C18
SHORT
C19
ANYTHING
FDIN
FDIN
FDIN
R14
FDIN
C20
SHORT
R16
OPEN
C17
10nF
R12
51.1⍀
R19
RSOURCE
OPEN
VMID
VMID
MOD FOR DC-COUPLED INPUT
MOD FOR LARGE MAGNITUDE
AC-COUPLED INPUT
Figure 26. Evaluation Board
Figure 27a. Evaluation Board Layout, Topside
–20–
REV. C
AD607
Figure 27b. Evaluation Board Layout, Bottom Side
Table III. AD607 Evaluation Board Input and Output Connections
Approximate
Reference
Designation
Connector
Type
Description
Coupling
Signal Level
Comments
J1
SMA
Frequency
Detector Input
DC
400 mV
This pin needs to be biased at VMID
and ac-coupled when driven by an
external signal generator.
J2
J3
J4
J5
SMA
SMA
SMA
SMA
Power-Up
LO Input
RF Input
DC
AC
AC
DC
CMOS Logic
Level Input
–16 dBm
( 50 mV)
–15 dBm max
( 54 mV)
0.4 V to 2.0 V
(3 V Supply)
(GREF = VMID)
NA
Tied to Positive Supply by Jumper J10
Input is terminated in 50 Ω.
Input is terminated in 50 Ω.
MGC Input
Jumper is set for manual gain control
input; see Table I for control voltage
values.
This signal level depends on the
AD607’s gain setting.
This signal level depends on the
AD607’s gain setting.
This signal level depends on the
AD607’s gain setting.
J6
J7
J8
J9
SMA
SMA
SMA
Jumper
IF Output
Q Output
I Output
AC
AC
AC
NA
NA
NA
NA
Ties GREF
to VMID
Sets gain-control scale factor (SF);
SF = 75/VMID in dB/V, where
VMID = VPOS/2.
J10
T1
Jumper
Ties Power-Up
to Positive
Supply
Power Supply
Positive Input
(VPS1, VPS2)
NA
DC
DC
NA
DC
0 V
Remove to test power-up/-down.
Terminal Pin
Terminal Pin
2.92 V to 5.5 V
Draws 8.5 mA at midgain connection.
T2
Power Supply
Return (GND)
–21–
REV. C
AD607
In operation (Figure 28), the AD607 evaluation board draws
about 8.5 mA at midgain (59 dB). Use high impedance probes
to monitor signals from the demodulated I and Q outputs and
the IF output. The MGC voltage should be set such that the
signal level at DMIP does not exceed 150 mV; signal levels
above this will overload the I and Q demodulators. The insertion
loss between IFOP and DMIP is typically 3 dB if a simple low-pass
filter (R8 and C2) is used, and higher if a reverse-terminated
band-pass filter is used.
HP 3326
SYNTHESIZED
SIGNAL GENERATOR
10.710MHz
HP 6632A
PROGRAMMABLE
POWER SUPPLY
2.92V–6V
FLUKE 6082A
SYNTHESIZED
SIGNAL GENERATOR
240MHz
VPOS
FDIN
I OUTPUT
TEKTRONIX
11402A
MCL
RF
AD607
EVALUATION
BOARD
ZFSC–2–1
COMBINER
OSCILLOSCOPE
WITH 11A32
PLUGIN
Q OUTPUT
HP 8656A
SYNTHESIZED
LO
MGC
SIGNAL GENERATOR
240.02MHz
HP 9920
HP 8656A
DATA PRECISION
IEEE CONTROLLER
HP9121
SYNTHESIZED
DVC8200
SIGNAL GENERATOR
229.3MHz
PROGRAMMABLE
VOLTAGE SOURCE
DISK DRIVE
IEEE–488 BUS
Figure 28. Evaluation Board Test Setup
–22–
REV. C
AD607
OUTLINE DIMENSIONS
20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
7.50
7.20
6.90
20
11
10
8.20
7.80
7.40
5.60
5.30
5.00
1
1.85
1.75
1.65
2.00 MAX
0.25
0.09
8؇
4؇
0؇
0.65
BSC
0.95
0.75
0.55
0.38
0.22 SEATING
PLANE
0.05 MIN
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-150AE
–23–
REV. C
AD607
Revision History
Location
Page
11/02—Data Sheet changed from REV. B to REV. C.
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Changes to TPC 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Edits to PRODUCT OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Edits to IF Amplifier section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Edits to Gain Scaling and RSSI section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Edits to I/Q Demodulators section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Edits to Table II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Edits to Bias System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Edits to Table III . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Edits to Figure 28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
OUTLINE DIMENSIONS Updated . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
–24–
REV. C
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