AD5440YRUZ-REEL [ADI]
Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface; 双8位/ 10位/ 12位，高带宽，乘法DAC ，并行接口
| 型号： | AD5440YRUZ-REEL |
| 厂家： | 
ADI |
| 描述： | Dual 8-/10-/12-Bit, High Bandwidth, Multiplying DACs with Parallel Interface |
| 文件： | 总32页 (文件大小：717K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Dual 8-/10-/12-Bit, High Bandwidth,
Multiplying DACs with Parallel Interface
AD5428/AD5440/AD5447
Data Sheet
FEATURES
GENERAL DESCRIPTION
10 MHz multiplying bandwidth
INL of 0.2ꢀ LSB ꢁ 8 bits
20-lead and 24-lead TSSOP packages
2.ꢀ V to ꢀ.ꢀ V supply operation
10 V reference input
The AD5428/AD5440/AD54471 are CMOS, 8-, 10-, and 12-bit,
dual-channel, current output digital-to-analog converters (DACs),
respectively. These devices operate from a 2.5 V to 5.5 V power
supply, making them suited to battery-powered and other
applications.
21.3 MSPS update rate
As a result of being manufactured on a CMOS submicron process,
they offer excellent 4-quadrant multiplication characteristics,
with large signal multiplying bandwidths of up to 10 MHz.
Extended temperature range: −40°C to +12ꢀ°C
4-quadrant multiplication
Power-on reset
0.ꢀ μA typical current consumption
Guaranteed monotonic
Readback function
AD7ꢀ28 upgrade (ADꢀ428)
AD7ꢀ47 upgrade (ADꢀ447)
The DACs use data readback, allowing the user to read the
contents of the DAC register via the DB pins. On power-up, the
internal register and latches are filled with 0s, and the DAC
outputs are at zero scale.
The applied external reference input voltage (VREF) determines
the full-scale output current. An integrated feedback resistor (RFB)
provides temperature tracking and full-scale voltage output when
combined with an external I-to-V precision amplifier.
APPLICATIONS
Portable battery-powered applications
Waveform generators
Analog processing
The AD5428 is available in a small 20-lead TSSOP package, and
the AD5440/AD5447 DACs are available in small 24-lead TSSOP
packages.
Instrumentation applications
Programmable amplifiers and attenuators
Digitally controlled calibration
Programmable filters and oscillators
Composite video
1 U.S. Patent Number 5,689,257.
Ultrasound
Gain, offset, and voltage trimming
FUNCTIONAL BLOCK DIAGRAM
V
A
REF
AD5428/AD5440/AD5447
R
V
R
A
DD
FB
DB0
DATA
INPUTS
I
A
OUT
INPUT
BUFFER
8-/10-/12-BIT
R-2R DAC A
LATCH
DB7
DB9
DB11
AGND
DAC A/B
R
R
I
B
CONTROL
LOGIC
FB
CS
B
R/W
OUT
8-/10-/12-BIT
R-2R DAC B
LATCH
DGND
POWER-ON
RESET
V
B
REF
Figure 1. AD5428/AD5440/AD5447
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights ofthird parties that may result fromits use. Specifications subject to change without notice. No
licenseis granted byimplication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 ©2004–2011 Analog Devices, Inc. All rights reserved.
AD5428/AD5440/AD5447
Data Sheet
TABLE OF CONTENTS
Specifications..................................................................................... 3
Divider or Programmable Gain Element................................ 20
Reference Selection .................................................................... 20
Amplifier Selection .................................................................... 20
Parallel Interface......................................................................... 22
Microprocessor Interfacing....................................................... 22
PCB Layout and Power Supply Decoupling ........................... 23
Evaluation Board for the AD5447............................................ 23
Power Supplies for the Evaluation Board................................ 23
Bill of Materials............................................................................... 27
Overview of AD54xx Devices....................................................... 28
Outline Dimensions....................................................................... 29
Ordering Guide .......................................................................... 29
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configurations and Function Descriptions ........................... 7
Typical Performance Characteristics ........................................... 10
Terminology .................................................................................... 15
General Description....................................................................... 16
DAC Section................................................................................ 16
Circuit Operation ....................................................................... 16
Single-Supply Applications ....................................................... 19
Adding Gain................................................................................ 19
REVISION HISTORY
Changes to General Description Section .................................... 16
Changes to Figure 37...................................................................... 16
Changes to Single-Supply Applications Section......................... 19
Changes to Figure 40 Through Figure 42.................................... 19
Changes to Divider or Programmable Gain Element Section.... 20
Changes to Figure 43...................................................................... 20
Changes to Table 9 Through Table 11 ......................................... 21
Changes to Microprocessor Interfacing Section ........................ 22
Added Figure 44 Through Figure 46 ........................................... 22
Added 8xC51-to-AD5428/AD5440/AD5447
8/11—Rev. B to Rev. C
CS
Changes to
Pin Description, Table 6........................................ 9
3/11—Rev. A to Rev. B
Changes to Evaluation Board For the AD5447 Section ............ 23
Changes to Figure 47 Caption....................................................... 24
Changes to Figure 49...................................................................... 25
Change to U1 Description in Table 12......................................... 27
Change to Ordering Guide............................................................ 29
7/05—Rev. 0 to Rev. A
Changed Pin DAC A/B to DAC /B................................Universal
Interface Section........................................................................ 22
Added ADSP-BF5xx-to-AD5428/AD5440/AD5447
A
Changes to Features List.................................................................. 1
Changes to Specifications................................................................ 3
Changes to Timing Characteristics................................................ 5
Change to Figure 2 ........................................................................... 5
Change to Absolute Maximum Ratings Section........................... 6
Change to Figure 13, Figure 14, and Figure 18........................... 11
Change to Figure 32 Through Figure 34 ..................................... 14
Interface Section........................................................................ 22
Changes to Power Supplies for the Evaluation Board Section.... 23
Changes to Table 13 ....................................................................... 28
Updated Outline Dimensions....................................................... 29
Changes to Ordering Guide.......................................................... 29
7/04—Revision 0: Initial Version
Rev. C | Page 2 of 32
Data Sheet
AD5428/AD5440/AD5447
SPECIFICATIONS1
VDD = 2.5 V to 5.5 V, VREF = 10 V, IOUT2 = 0 V. Temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless
otherwise noted. DC performance is measured with OP177, and ac performance is measured with AD8038, unless otherwise noted.
Table 1.
Parameter
Min
Typ
Max
Unit
Conditions
STATIC PERFORMANCE
AD5428
Resolution
8
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD544±
±±.25
±ꢀ
Guaranteed monotonic
Guaranteed monotonic
Guaranteed monotonic
Resolution
ꢀ±
±±.5
±ꢀ
Bits
LSB
LSB
Relative Accuracy
Differential Nonlinearity
AD5447
Resolution
ꢀ2
±ꢀ
–ꢀ/+2
±25
Bits
LSB
LSB
mV
Relative Accuracy
Differential Nonlinearity
Gain Error
Gain Error Temperature Coefficient
Output Leakage Current
±5
ppm FSR/°C
nA
nA
±5
±ꢀ5
Data = ±x±±±±, TA = 25°C
Data = ±x±±±±
REFERENCE INPUT
Reference Input Range
VREFA, VREFB Input Resistance
VREFA-to-VREFB Input
Resistance Mismatch
±ꢀ±
ꢀ±
ꢀ.6
V
kΩ
%
8
ꢀ3
2.5
Input resistance TC = –5± ppm/°C
Typ = 25°C, max = ꢀ25°C
Input Capacitance
Code ±
Code 4±95
3.5
3.5
pF
pF
DIGITAL INPUTS/OUTPUT
Input High Voltage, VIH
ꢀ.7
ꢀ.7
V
V
VDD = 3.6 V to 5.5 V
VDD = 2.5 V to 3.6 V
Input Low Voltage, VIL
Output High Voltage, VOH
Output Low Voltage, VOL
±.8
±.7
V
V
V
V
V
V
μA
pF
VDD = 2.7 V to 5.5 V
VDD = 2.5 V to 2.7 V
VDD = 4.5 V to 5.5 V, ISOURCE = 2±± μA
VDD = 2.5 V to 3.6 V, ISOURCE = 2±± μA
VDD = 4.5 V to 5.5 V, ISINK = 2±± μA
VDD = 2.5 V to 3.6 V, ISINK = 2±± μA
VDD − ꢀ
VDD − ±.5
±.4
±.4
ꢀ
Input Leakage Current, IIL
Input Capacitance
4
ꢀ±
DYNAMIC PERFORMANCE
Reference-Multiplying BW
Output Voltage Settling Time
ꢀ±
MHz
VREF = ±3.5 V p-p, DAC loaded all ꢀs
RLOAD = ꢀ±± Ω, CLOAD = ꢀ5 pF, VREF = ꢀ± V
DAC latch alternately loaded with ±s and ꢀs
Measured to ±ꢀ mV of FS
Measured to ±4 mV of FS
Measured to ±ꢀ6 mV of FS
Digital Delay
ꢀ±% to 9±% Settling Time
Digital-to-Analog Glitch Impulse
8±
35
3±
2±
ꢀ5
3
ꢀ2±
7±
6±
4±
3±
ns
ns
ns
ns
ns
nV-sec
Interface delay time
Rise and fall times, VREF = ꢀ± V, RLOAD = ꢀ±± Ω
ꢀ LSB change around major carry, VREF = ± V
Rev. C | Page 3 of 32
AD5428/AD5440/AD5447
Data Sheet
Parameter
Min
Typ
Max
Unit
Conditions
Multiplying Feedthrough Error
DAC latches loaded with all ±s, VREF = ±3.5 V
ꢀ MHz
ꢀ± MHz
DAC latches loaded with all ±s
DAC latches loaded with all ꢀs
Feedthrough to DAC output with CS high and
alternate loading of all ±s and all ꢀs
@ ꢀ kHz
7±
48
ꢀ7
3±
dB
dB
pF
pF
Output Capacitance
Digital Feedthrough
ꢀ2
25
ꢀ
nV-sec
Output Noise Spectral Density
Analog THD
Digital THD
25
8ꢀ
nV/√Hz
dB
VREF = 3.5 V p-p, all ꢀs loaded, f = ꢀ±± kHz
Clock = ꢀ± MHz, VREF = 3.5 V
ꢀ±± kHz fOUT
5± kHz fOUT
6ꢀ
66
dB
dB
SFDR Performance (Wide Band)
Clock = ꢀ± MHz
5±± kHz fOUT
AD5447, 65k codes, VREF = 3.5 V
55
63
65
dB
dB
dB
ꢀ±± kHz fOUT
5± kHz fOUT
Clock = 25 MHz
5±± kHz fOUT
ꢀ±± kHz fOUT
5±
6±
62
dB
dB
dB
5± kHz fOUT
SFDR Performance (Narrow Band)
Clock = ꢀ± MHz
5±± kHz fOUT
AD5447, 65k codes, VREF = 3.5 V
73
8±
87
dB
dB
dB
ꢀ±± kHz fOUT
5±k Hz fOUT
Clock = 25 MHz
5±± kHz fOUT
ꢀ±± kHz fOUT
7±
75
8±
dB
dB
dB
5± kHz fOUT
Intermodulation Distortion
fꢀ = 4± kHz, f2 = 5± kHz
fꢀ = 4± kHz, f2 = 5± kHz
POWER REQUIREMENTS
Power Supply Range
IDD
AD5447, 65k codes, VREF = 3.5 V
Clock = ꢀ± MHz
Clock = 25 MHz
72
65
dB
dB
2.5
5.5
±.7
ꢀ±
±.±±ꢀ
V
μA
μA
%/%
TA = 25°C, logic inputs = ± V or VDD
TA = −4±°C to +ꢀ25°C, logic inputs = ± V or VDD
∆VDD = ±5%
±.5
Power Supply Sensitivity
ꢀ Guaranteed by design, not subject to production test.
Rev. C | Page 4 of 32
Data Sheet
AD5428/AD5440/AD5447
TIMING CHARACTERISTICS
All input signals are specified with tr = tf = 1 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. VDD = 2.5 V to 5.5 V,
REF = 10 V, IOUT2 = 0 V, temperature range for Y version: −40°C to +125°C. All specifications TMIN to TMAX, unless otherwise noted.
V
Table 2.
Parameter1
Limit at TMIN, TMAX
Unit
Conditions/Comments
Write Mode
R/W to CS setup time
R/W to CS hold time
CS low time
tꢀ
±
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
t2
±
t3
ꢀ±
ꢀ±
±
6
±
t4
t5
t6
t7
Address setup time
Address hold time
Data setup time
Data hold time
R/W high to CS low
CS min high time
t8
5
t9
7
Data Readback Mode
tꢀ±
tꢀꢀ
tꢀ2
±
±
5
25
5
ns typ
ns typ
ns typ
ns max
ns typ
ns max
MSPS
Address setup time
Address hold time
Data access time
tꢀ3
Bus relinquish time
ꢀ±
2ꢀ.3
Update Rate
Consists of CS min high time, CS low time, and output
voltage settling time
ꢀ Guaranteed by design and characterization, not subject to production test.
t1
t2
t8
t2
R/W
t9
t3
CS
t5
t4
t10
t11
DACA/DACB
t8
t12
t13
t7
DATA VALID
DATA VALID
DATA
Figure 2. Timing Diagram
200μA
I
OL
V
+ V
2
OH (MIN)
OL (MAX)
TO OUTPUT
PIN
C
L
50pF
200μA
I
OH
Figure 3. Load Circuit for Data Output Timing Specifications
Rev. C | Page 5 of 32
AD5428/AD5440/AD5447
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Transient currents of up to 100 mA do not cause SCR latch-up.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VDD to GND
VREFA, VREFB, RFBA, RFBB to DGND
IOUTꢀ, IOUT2 to DGND
Logic Inputs and Outputꢀ
Operating Temperature Range
Automotive (Y Version)
Storage Temperature Range
Junction Temperature
Stresses above those listed in Absolute Maximum Ratings may
cause permanent damage to the device. This is a stress rating
only; functional operation of the device at these or any other
conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device
reliability. Only one absolute maximum rating may be applied
at any one time.
Rating
–±.3 V to +7 V
–ꢀ2 V to +ꢀ2 V
–±.3 V to +7 V
–±.3 V to VDD + ±.3 V
–4±°C to +ꢀ25°C
–65°C to +ꢀ5±°C
ꢀ5±°C
ꢀ43°C/W
ꢀ28°C/W
ESD CAUTION
2±-lead TSSOP θJA Thermal Impedance
24-lead TSSOP θJA Thermal Impedance
Lead Temperature, Soldering (ꢀ± sec)
IR Reflow, Peak Temperature (<2± sec)
ꢀ
3±±°C
235°C
CS
W
Overvoltages at DBx, , and R/ are clamped by internal diodes.
Rev. C | Page 6 of 32
Data Sheet
AD5428/AD5440/AD5447
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
20
19
18
17
16
15
14
13
12
11
AGND
I
B
B
OUT
I
A
A
A
R
FB
OUT
3
R
V
V
B
FB
REF
DD
AD5428
TOP VIEW
(Not to Scale)
4
V
REF
5
DGND
DAC A/B
DB7
R/W
CS
6
7
DB0 (LSB)
DB1
8
DB6
9
DB5
DB2
10
DB4
DB3
Figure 4. Pin Configuration 20-Lead TSSOP (RU-20)
Table 4. AD5428 Pin Function Descriptions
Pin No.
Mnemonic
Description
ꢀ
AGND
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
2, 2±
3, ꢀ9
IOUTA, IOUT
RFBA, RFBB
B
DAC Current Outputs.
DAC Feedback Resistor Pins. These pins establish voltage output for the DAC by connecting to an external
amplifier output.
4, ꢀ8
5
VREFA, VREF
DGND
B
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
6
DAC A/B
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 toꢀ4
ꢀ5
DB7 to DB±
CS
Parallel Data Bits 7 Through ±.
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.
ꢀ6
ꢀ7
R/W
VDD
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction
with CS to read back contents of the DAC register.
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 7 of 32
AD5428/AD5440/AD5447
Data Sheet
1
2
24
23
22
21
20
19
18
17
16
15
14
13
AGND
I
B
B
OUT
I
A
A
A
R
FB
OUT
3
R
V
V
B
FB
REF
DD
4
V
REF
AD5440
TOP VIEW
(Not to Scale)
5
R/W
CS
DGND
DAC A/B
DB9
6
7
NC
NC
8
DB8
9
DB7
DB0 (LSB)
DB1
10
DB6
DB5 11
12
DB2
DB4
DB3
NC = NO CONNECT
Figure 5. Pin Configuration 24-Lead TSSOP (RU-24)
Table 5. AD5440 Pin Function Descriptions
Pin No. Mnemonic
Function
AGND
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
ꢀ
2, 24
3, 23
IOUTA, IOUT
B
DAC Current Outputs.
DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier
output.
RFBA, RFBB
4, 22
5
VREFA, VREF
DGND
B
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
DAC A/B
6
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 toꢀ6
DB9 to DB±
Parallel Data Bits 9 Through ±.
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.
CS
ꢀ9
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
CS to read back contents of the DAC register.
R/W
VDD
2±
2ꢀ
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 8 of 32
Data Sheet
AD5428/AD5440/AD5447
1
2
24
23
22
21
20
19
18
17
16
15
14
13
AGND
I
B
B
OUT
I
A
A
A
R
FB
OUT
3
R
V
V
B
FB
REF
DD
4
V
REF
AD5447
TOP VIEW
(Not to Scale)
5
DGND
DAC A/B
DB11
R/W
CS
6
7
DB0 (LSB)
DB1
8
DB10
9
DB9
DB2
10
DB8
DB3
DB7 11
12
DB4
DB6
DB5
Figure 6. Pin Configuration 24-Lead TSSOP (RU-24)
Table 6. AD5447 Pin Function Descriptions
Pin No. Mnemonic
Description
ꢀ
AGND
DAC Ground Pin. This pin should typically be tied to the analog ground of the system, but can be biased to
achieve single-supply operation.
2, 24
3, 23
IOUTA, IOUT
RFBA, RFBB
B
DAC Current Outputs.
DAC Feedback Resistor Pins. Establish voltage output for the DAC by connecting to an external amplifier
output.
4, 22
5
VREFA, VREF
DGND
B
DAC Reference Voltage Input Terminals.
Digital Ground Pin.
6
DAC A/B
Selects DAC A or DAC B. Low selects DAC A; high selects DAC B.
7 to ꢀ8
ꢀ9
DBꢀꢀ to DB±
CS
Parallel Data Bits ꢀꢀ Through ±.
Chip Select Input. Active low. Used in conjunction with R/W to load parallel data to the input latch or to read
data from the DAC register.
2±
2ꢀ
R/W
VDD
Read/Write. When low, used in conjunction with CS to load parallel data. When high, used in conjunction with
CS to read back the contents of the DAC register. When CS and R/W are held low, the latches are transparent.
Any changes on the data lines are reflected in the relevant DAC output.
Positive Power Supply Input. This part can be operated from a supply of 2.5 V to 5.5 V.
Rev. C | Page 9 of 32
AD5428/AD5440/AD5447
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0.20
0.20
0.15
0.10
0.05
0
T
= 25°C
T
= 25°C
A
A
V
V
= 10V
V
V
= 10V
REF
= 5V
REF
= 5V
0.15
0.10
0.05
0
DD
DD
–0.05
–0.10
–0.15
–0.20
–0.05
–0.10
–0.15
–0.20
0
50
100
150
200
250
0
50
100
150
200
250
CODE
CODE
Figure 7. INL vs. Code (8-Bit DAC)
Figure 10. DNL vs. Code (8-Bit DAC)
0.5
0.4
0.5
0.4
T
V
V
= 25°C
T
V
V
= 25°C
A
A
= 10V
= 10V
REF
= 5V
REF
= 5V
DD
DD
0.3
0.3
0.2
0.2
0.1
0.1
0
0
–0.1
–0.2
–0.3
–0.4
–0.5
–0.1
–0.2
–0.3
–0.4
–0.5
0
200
400
600
800
1000
0
200
400
600
800
1000
CODE
CODE
Figure 8. INL vs. Code (10-Bit DAC)
Figure 11. DNL vs. Code (10-Bit DAC)
1.0
0.8
1.0
0.8
T
V
V
= 25°C
T
V
V
= 25°C
A
A
= 10V
= 10V
REF
= 5V
REF
= 5V
DD
DD
0.6
0.6
0.4
0.4
0.2
0.2
0
0
–0.2
–0.4
–0.6
–0.8
–1.0
–0.2
–0.4
–0.6
–0.8
–1.0
0
500
1000
1500
2000
2500
3000
3500
4000
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
CODE
Figure 9. INL vs. Code (12-Bit DAC)
Figure 12. DNL vs. Code (12-Bit DAC)
Rev. C | Page ꢀ± of 32
Data Sheet
AD5428/AD5440/AD5447
0.6
0.5
0.4
0.3
0.2
0.1
0
8
7
6
5
4
3
2
1
0
T
= 25°C
A
MAX INL
V
= 5V
DD
T
V
= 25°C
= 5V
A
DD
MIN INL
–0.1
–0.2
–0.3
V
= 3V
DD
V
= 2.5V
DD
2
3
4
5
6
7
8
9
10
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0
0.5
1.0
REFERENCE VOLTAGE
INPUT VOLTAGE (V)
Figure 13. INL vs. Reference Voltage
Figure 16. Supply Current vs. Logic Input Voltage
1.6
–0.40
–0.45
–0.50
–0.55
–0.60
–0.65
–0.70
T
V
= 25°C
A
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
= 5V
DD
I
I
1 V = 5V
DD
OUT
OUT
1 V = 3V
DD
MIN DNL
–40
–20
0
20
40
60
80
100
120
2
3
4
5
6
7
8
9
10
TEMPERATURE (°C)
REFERENCE VOLTAGE
Figure 14. DNL vs. Reference Voltage
Figure 17. IOUT1 Leakage Current vs. Temperature
5
4
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
V
= 5V
V
= 5V
DD
DD
3
2
ALL 0s
ALL 1s
1
0
V
= 2.5V
V
= 2.5V
DD
DD
–1
–2
–3
–4
–5
ALL 1s
ALL 0s
V
= 10V
REF
–60 –40 –20
0
20
40
60
80
100 120 140
–60 –40 –20
0
20
40
60
80
100 120 140
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 15. Gain Error vs. Temperature
Figure 18. Supply Current vs. Temperature
Rev. C | Page ꢀꢀ of 32
AD5428/AD5440/AD5447
Data Sheet
14
3
0
T
= 25°C
A
T
= 25°C
A
LOADING ZS TO FS
V
= 5V
DD
12
10
8
V
= 5V
DD
–3
–6
–9
6
V
V
= 3V
DD
DD
4
V
V
V
V
V
= ±2V, AD8038 C 1.47pF
C
= 2.5V
REF
REF
REF
REF
REF
= ±2V, AD8038 C 1pF
C
2
= ±0.15V, AD8038 C 1pF
C
= ±0.15V, AD8038 C 1.47pF
C
= ±3.51V, AD8038 C 1.8pF
C
0
1
10
100
1k
10k
100k
1M
10M
100M
10k
100k
1M
10M
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 22. Reference Multiplying Bandwidth vs. Frequency and
Compensation Capacitor
Figure 19. Supply Current vs. Update Rate
6
0
T
= 25°C
0.045
0.040
0.035
0.030
0.025
0.020
0.015
0.010
0.005
0
ALL ON
DB11
DB10
DB9
DB8
DB7
A
0x7FF TO 0x800
V
LOADING
ZS TO FS
T
V
= 25°C
A
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
–66
–72
–78
–84
–90
–96
–102
= 0V
REF
= 5V
AMP = AD8038
C
DD
= 1.8pF
COMP
DB6
DB5
DB4
DB3
DB2
DB1
DB0
V
= 3V
DD
0x800 TO 0x7FF
= 3V
V
DD
T
V
= 25°C
DD
= ±3.5V
= 1.8pF
A
= 5V
V
REF
C
ALL OFF
COMP
AMP = AD8038
–0.005
–0.010
V
= 5V
DD
1
10
100
1k
10k
100k
1M 10M 100M
0
20
40
60
80
100 120 140 160 180 200
TIME (ns)
FREQUENCY (Hz)
Figure 20. Reference Multiplying Bandwidth vs. Frequency and Code
Figure 23. Midscale Transition, VREF = 0 V
–1.68
–1.69
–1.70
–1.71
–1.72
–1.73
–1.74
–1.75
–1.76
–1.77
0.2
0
T
V
= 25°C
= 3.5V
A
0x7FF TO 0x800
= 5V
REF
AMP = AD8038
= 1.8pF
V
DD
C
COMP
–0.2
–0.4
V
= 3V
DD
V
= 5V
V
DD
= 3V
DD
T
V
V
= 25°C
A
–0.6
–0.8
= 5V
DD
=
±
3.5V
REF
C
= 1.8pF
COMP
0x800 TO 0x7FF
20 40 60
AMP = AD8038
1
10 100
1k
10k
100k
1M
10M
100M
0
80
100 120 140 160 180 200
TIME (ns)
FREQUENCY (Hz)
Figure 21. Reference Multiplying Bandwidth—All 1s Loaded
Figure 24. Midscale Transition, VREF = 3.5 V
Rev. C | Page ꢀ2 of 32
Data Sheet
AD5428/AD5440/AD5447
90
80
70
60
50
40
30
20
10
0
20
T
V
= 25°C
A
= 3V
DD
AMP = AD8038
MCLK = 5MHz
0
–20
MCLK = 10MHz
–40
MCLK = 25MHz
FULL SCALE
ZERO SCALE
–60
–80
T
V
= 25°C
= 3.5V
A
–100
–120
REF
AMP = AD8038
0
100 200 300 400 500 600 700 800 900 1000
fOUT (kHz)
1
100
1k
10k
100k
1M
10M
10
FREQUENCY (Hz)
Figure 25. Power Supply Rejection Ratio vs. Frequency
Figure 28. Wideband SFDR vs. fOUT Frequency
–60
0
T
V
= 25°C
A
T
V
V
= 25°C
A
= 5V
DD
= 3V
DD
–10
–20
–30
–40
–50
–60
–70
–80
–90
AMP = AD8038
65k CODES
= 3.5V p-p
REF
–65
–70
–75
–80
–85
–90
0
2
4
6
8
10
12
1
10
100
1k
10k
100k
1M
FREQUENCY (MHz)
FREQUENCY (Hz)
Figure 26. THD + Noise vs. Frequency
Figure 29. Wideband SFDR, fOUT = 100 kHz, Clock = 25 MHz
100
80
60
40
20
0
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
T
V
= 25°C
A
MCLK = 1MHz
= 5V
DD
AMP = AD8038
65k CODES
MCLK = 200kHz
MCLK = 0.5MHz
T
V
= 25°C
= 3.5V
A
REF
AMP = AD8038
0
20
40
60
80
100 120 140 160 180 200
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
fOUT (kHz)
FREQUENCY (MHz)
Figure 27. Wideband SFDR vs. fOUT Frequency
Figure 30. Wideband SFDR, fOUT = 500 kHz, Clock = 10 MHz
Rev. C | Page ꢀ3 of 32
AD5428/AD5440/AD5447
Data Sheet
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
T
V
= 25°C
T = 25°C
A
DD
AMP = AD8038
65k CODES
A
= 5V
V
= 3V
DD
AMP = AD8038
65k CODES
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
70
75
80
85
90
95
100 105 110 115 120
FREQUENCY (MHz)
FREQUENCY (kHz)
Figure 31. Wideband SFDR, fOUT = 50 kHz, Clock = 10 MHz
Figure 34. Narrow-Band IMD, fOUT = 90 kHz, 100 kHz, Clock = 10 MHz
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
T
V
= 25°C
DD
A
T
V
= 25°C
DD
A
= 3V
= 5V
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
AMP = AD8038
65k CODES
AMP = AD8038
65k CODES
250 300 350 400 450 500 550 600 650 700 750
0
50
100
150
200
250
300
350
400
FREQUENCY (kHz)
FREQUENCY (kHz)
Figure 32. Narrow-Band SFDR, fOUT = 500 kHz, Clock = 25 MHz
Figure 35. Wideband IMD, fOUT = 90 kHz, 100 kHz, Clock = 25 MHz
300
20
T
= 25°C
T
V
= 25°C
DD
A
A
ZERO SCALE LOADED TO DAC
MIDSCALE LOADED TO DAC
FULL SCALE LOADED TO DAC
AMP = AD8038
= 3V
AMP = AD8038
65k CODES
0
–20
250
200
150
100
50
–40
–60
–80
–100
–120
0
100
1k
10k
FREQUENCY (Hz)
100k
50
60
70
80
90
100 110 120 130 140 150
FREQUENCY (kHz)
Figure 36. Output Noise Spectral Density
Figure 33. Narrow-Band SFDR, fOUT = 100 kHz, Clock = 25 MHz
Rev. C | Page ꢀ4 of 32
Data Sheet
AD5428/AD5440/AD5447
TERMINOLOGY
Relative Accuracy (Endpoint Nonlinearity)
A measure of the maximum deviation from a straight line
passing through the endpoints of the DAC transfer function. It
is measured after adjusting for zero and full scale and is
typically expressed in LSBs or as a percentage of the full-scale
reading.
Digital Feedthrough
When the device is not selected, high frequency logic activity
on the device’s digital inputs is capacitively coupled through the
device and produces noise on the IOUT pins and, subsequently,
on the following circuitry. This noise is digital feedthrough.
Multiplying Feedthrough Error
Differential Nonlinearity
The error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
The difference in the measured change and the ideal 1 LSB
change between two adjacent codes. A specified differential
nonlinearity of −1 LSB maximum over the operating
temperature range ensures monotonicity.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower-order harmonics are included,
such as second to fifth harmonics.
Gain Error (Full-Scale Error)
A measure of the output error between an ideal DAC and the
actual device output. For these DACs, ideal maximum output is
V
REF – 1 LSB. The gain error of the DACs is adjustable to zero
2
2
2
2
V2 +V3 +V4 +V5
with an external resistance.
THD = 20 log
V1
Output Leakage Current
The current that flows into the DAC ladder switches when they
are turned off. For the IOUT1 terminal, it can be measured by
loading all 0s to the DAC and measuring the IOUT1 current.
Minimum current flows into the IOUT2 line when the DAC is
loaded with all 1s.
Digital Intermodulation Distortion
Second-order intermodulation distortion (IMD) measurements
are the relative magnitude of the fa and fb tones digitally generated
by the DAC and the second-order products at 2fa − fb and
2fb − fa.
Output Capacitance
Capacitance from IOUT1 or IOUT2 to AGND.
Spurious-Free Dynamic Range (SFDR)
SFDR is the usable dynamic range of a DAC before spurious
noise interferes or distorts the fundamental signal. SFDR is the
measure of difference in amplitude between the fundamental
and the largest harmonic or nonharmonic spur from dc to full
Nyquist bandwidth (half the DAC sampling rate, or fs/2).
Narrow-band SFDR is a measure of SFDR over an arbitrary
window size, in this case 50%, of the fundamental. Digital SFDR
is a measure of the usable dynamic range of the DAC when the
signal is a digitally generated sine wave.
Output Current Settling Time
The amount of time for the output to settle to a specified level
for a full-scale input change. For these devices, it is specified
with a 100 Ω resistor to ground.
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-sec or nV-sec,
depending on whether the glitch is measured as a current or
voltage signal.
Rev. C | Page ꢀ5 of 32
AD5428/AD5440/AD5447
Data Sheet
GENERAL DESCRIPTION
CIRCUIT OPERATION
DAC SECTION
Unipolar Mode
The AD5428/AD5440/AD5447 are CMOS 8-, 10-, and 12-bit,
dual-channel, current output DACs consisting of a standard
inverting R-2R ladder configuration. Figure 37 shows a simplified
diagram for a single channel of the 8-bit AD5428. The feedback
resistor RFBA has a value of R. The value of R is typically 10 kΩ
Using a single op amp, these devices can easily be configured to
provide 2-quadrant multiplying operation or a unipolar output
voltage swing, as shown in Figure 38. When an output amplifier
is connected in unipolar mode, the output voltage is given by
(with a minimum of 8 kΩ and a maximum of 12 kΩ). If IOUT
1
VOUT = −VREF × D/2n
and AGND are kept at the same potential, a constant current
flows into each ladder leg, regardless of digital input code.
Therefore, the input resistance presented at VREFA is always
constant and nominally of value R. The DAC output (IOUT) is
code-dependent, producing various resistances and
capacitances. When choosing an external amplifier, take into
account the variation in impedance generated by the DAC on
the amplifier’s inverting input node.
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (8-bit AD5428)
= 0 to 1023 (10-bit AD5440)
= 0 to 4095 (12-bit AD5447)
n is the resolution of the DAC.
R
R
R
V
REF
Note that the output voltage polarity is opposite to the VREF
polarity for dc reference voltages. These DACs are designed to
operate with either negative or positive reference voltages. The
VDD power pin is only used by the internal digital logic to drive
the on and off states of the DAC switches.
2R
S1
2R
S2
2R
S3
2R
S8
2R
R
R
A
FB
I
A
OUT
AGND
DAC DATA LATCHES
AND DRIVERS
These DACs are also designed to accommodate ac reference
input signals in the range of –10 V to +10 V.
Figure 37. Simplified Ladder
With a fixed 10 V reference, the circuit in Figure 38 gives a
unipolar 0 V to –10 V output voltage swing. When VIN is an ac
signal, the circuit performs 2-quadrant multiplication.
Access is provided to the VREF, RFB, and IOUT terminals of DAC A
and DAC B, making the devices extremely versatile and
allowing them to be configured in several operating modes,
such as unipolar output mode, 4-quadrant multiplication
bipolar mode, or single-supply mode. Note that a matching
switch is used in series with the internal RFBA feedback resistor.
If users attempt to measure RFBA, power must be applied to VDD
to achieve continuity.
Table 7 shows the relationship between digital code and the
expected output voltage for unipolar operation using the 8-bit
AD5428.
Table 7. Unipolar Code
Digital Input
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ±±± ±±±±
±±±± ±±±ꢀ
±±±± ±±±±
Analog Output (V)
–VREF (255/256)
–VREF(ꢀ28/256) = –VREF/2
–VREF (ꢀ/256)
–VREF (±/256) = ±
Rev. C | Page ꢀ6 of 32
Data Sheet
AD5428/AD5440/AD5447
V
A
IN
(±10V)
1
R1
V
A
REF
AD5428/AD5440/AD5447
R
A
1
R2
FB
R
V
DD
2
C1
I
A
OUT
DB0
DATA
8-/10-/12-BIT
R-2R DAC A
INPUT
BUFFER
INPUTS
LATCH
V
A
OUT
DB7
DB9
DB11
AGND
AGND
DAC A/B
R
B
1
FB
R4
R
CONTROL
LOGIC
2
CS
C2
I
B
OUT
R/W
8-/10-/12-BIT
R-2R DAC B
V
B
LATCH
OUT
DGND
AGND
POWER-ON
RESET
V
B
REF
1
R3
V
B
IN
(±10V)
1
2
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
C1, C2 PHASE COMPENSATION (1pF TO 2pF) IS REQUIRED WHEN USING
HIGH SPEED AMPLIFIERS TO PREVENT RINGING OR OSCILLATION.
Figure 38. Unipolar Operation
Rev. C | Page ꢀ7 of 32
AD5428/AD5440/AD5447
Data Sheet
Bipolar Operation
Table 8. Bipolar Code
Digital Input
ꢀꢀꢀꢀ ꢀꢀꢀꢀ
ꢀ±±± ±±±±
±±±± ±±±ꢀ
Analog Output (V)
+VREF (ꢀ27/ꢀ28)
±
–VREF (ꢀ27/ꢀ28)
–VREF (ꢀ28/ꢀ28)
In some applications, it may be necessary to generate full 4-quad-
rant multiplying operation or a bipolar output swing. This can
easily be accomplished by using another external amplifier and
some external resistors, as shown in Figure 39. In this circuit, the
second amplifier, A2, provides a gain of 2. Biasing the external
amplifier with an offset from the reference voltage results in full
4-quadrant multiplying operation. The transfer function of this
circuit shows that both negative and positive output voltages are
±±±± ±±±±
Stability
In the I-to-V configuration, the IOUT of the DAC and the inverting
node of the op amp must be connected as close as possible, and
proper PCB layout techniques must be used. Because every code
change corresponds to a step function, gain peaking may occur
if the op amp has limited gain bandwidth product (GBP) and
there is excessive parasitic capacitance at the inverting node.
This parasitic capacitance introduces a pole into the open-loop
response, which can cause ringing or instability in the closed-
loop applications circuit.
created as the input data (D) is incremented from Code 0 (VOUT
−VREF) to midscale (VOUT = 0 V) to full scale (VOUT = +VREF).
When connected in bipolar mode, the output voltage is given by
=
VOUT
=
(
VREF ×D / 2n−1
− VREF
)
where:
D is the fractional representation of the digital word loaded to
the DAC.
D = 0 to 255 (AD5428)
= 0 to 1023 (AD5440)
= 0 to 4095 (AD5447)
n is the number of bits.
An optional compensation capacitor, C1, can be added in parallel
with RFBA for stability, as shown in Figure 38 and Figure 39. Too
small a value of C1 can produce ringing at the output, whereas
too large a value can adversely affect the settling time. C1 should
be found empirically, but 1 pF to 2 pF is generally adequate for
the compensation.
When VIN is an ac signal, the circuit performs 4-quadrant
multiplication. Table 8 shows the relationship between digital
code and the expected output voltage for bipolar operation
using the 8-bit AD5428.
V
A
IN
(±10V)
R5
20kΩ
1
R1
2
R6
20kΩ
V
A
REF
AD5428/AD5440/AD5447
2
A2
R7
10kΩ
1
R2
V
A
R
R
A
OUT
FB
V
DD
3
C1
R11
5kΩ
I
A
OUT
DATA
INPUTS
DB0
INPUT
BUFFER
8-/10-/12-BIT
R-2R DAC A
A1
LATCH
AGND
DB7
DB9
DB11
AGND
AGND
DAC A/B
R
B
1
FB
R4
R
CONTROL
LOGIC
CS
3
C2
I
B
OUT
R/W
8-/10-/12-BIT
R-2R DAC B
A3
LATCH
R8
20kΩ
2
R9
10kΩ
DGND
AGND
A4
2
R10
POWER-ON
RESET
20kΩ
V
B
OUT
V
B
REF
R12
5kΩ
1
R3
AGND
V
B
IN
(±10V)
1
R1, R2 AND R3, R4 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED. ADJUST R1 FOR V
OUT
A = 0V WITH CODE 10000000 IN DAC A LATCH.
ADJUST R3 FOR V
B = 0V WITH CODE 10000000 IN DAC B LATCH.
OUT
2
3
MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS R6, R7 AND R9, R10.
C1, C2 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED IF A1/A3 IS A HIGH SPEED AMPLIFIER.
Figure 39. Bipolar Operation (4-Quadrant Multiplication)
Rev. C | Page ꢀ8 of 32
Data Sheet
AD5428/AD5440/AD5447
V
= 5V
DD
SINGLE-SUPPLY APPLICATIONS
Voltage-Switching Mode
ADR03
V
V
OUT
IN
GND
Figure 40 shows the DACs operating in voltage-switching
mode. The reference voltage, VIN, is applied to the IOUTA pin,
and the output voltage is available at the VREFA terminal. In this
configuration, a positive reference voltage results in a positive
output voltage, making single-supply operation possible. The
output from the DAC is voltage at constant impedance (the
DAC ladder resistance). Therefore, an op amp is necessary to
buffer the output voltage. The reference input no longer sees
constant input impedance, but one that varies with code.
Therefore, the voltage input should be driven from a low
impedance source.
+5V
–5V
C1
V
R
A
DD
FB
8-/10-/12-BIT
I
A
–2.5V
OUT
V
A
REF
DAC
V
=
AGND
OUT
0V to 2.5V
GND
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 41. Positive Voltage Output with Minimum Components
ADDING GAIN
Note that VIN is limited to low voltages because the switches in
the DAC ladder no longer have the same source-drain drive
voltage. As a result, their on resistance differs and degrades the
integral linearity of the DAC. Also, VIN must not go negative by
more than 0.3 V, or an internal diode turns on, causing the
device to exceed the maximum ratings. In this type of
application, the full range of multiplying capability of the DAC
is lost.
In applications where the output voltage must be greater than
VIN, gain can be added with an additional external amplifier, or
it can be achieved in a single stage. Consider the effect of temper-
ature coefficients of the thin film resistors of the DAC. Simply
placing a resistor in series with the RFB resistor causes mismatches
in the temperature coefficients, resulting in larger gain temper-
ature coefficient errors. Instead, the circuit in Figure 42 shows
the recommended method for increasing the gain of the circuit.
R1, R2, and R3 should have similar temperature coefficients,
but they need not match the temperature coefficients of the
DAC. This approach is recommended in circuits where gains of
greater than 1 are required.
V
DD
R1
R2
R
A V
DD
FB
V
V
OUT
I
A
V
IN
OUT
DD
V
A
REF
AGND
GND
C1
V
R
A
DD
FB
I
A
R1
OUT
8-/10-/12-BIT
V
V
IN
OUT
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
AGND
DAC
V
A
REF
R3
R2
GND
R2 + R3
R2
GAIN =
R2R3
Figure 40. Single-Supply Voltage-Switching Mode
R
=
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
1
R2 R3
+
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Positive Output Voltage
The output voltage polarity is opposite to the VREF polarity for
dc reference voltages. To achieve a positive voltage output, an
applied negative reference to the input of the DAC is preferred
over the output inversion through an inverting amplifier
because of the resistor’s tolerance errors. To generate a negative
reference, the reference can be level-shifted by an op amp such
that the VOUT and GND pins of the reference become the virtual
ground and –2.5 V, respectively, as shown in Figure 41.
Figure 42. Increasing Gain of Current Output DAC
Rev. C | Page ꢀ9 of 32
AD5428/AD5440/AD5447
Data Sheet
REFERENCE SELECTION
DIVIDER OR PROGRAMMABLE GAIN ELEMENT
When selecting a reference for use with the AD54xx series of
current output DACs, pay attention to the reference’s output
voltage temperature coefficient specification. This parameter not
only affects the full-scale error, but can also affect the linearity
(INL and DNL) performance. The reference temperature
coefficient should be consistent with the system accuracy
specifications. For example, an 8-bit system required to hold its
overall specification to within 1 LSB over the temperature range
0° to 50°C dictates that the maximum system drift with temp-
erature should be less than 78 ppm/°C. A 12-bit system with the
same temperature range to overall specification within 2 LSBs
requires a maximum drift of 10 ppm/°C. Choosing a precision
reference with low output temperature coefficient minimizes this
error source. Table 9 lists some references available from Analog
Devices that are suitable for use with these current output DACs.
Current-steering DACs are very flexible and lend themselves to
many applications. If this type of DAC is connected as the
feedback element of an op amp and RFBA is used as the input
resistor, as shown in Figure 43, the output voltage is inversely
proportional to the digital input fraction, D.
For D = 1 − 2−n, the output voltage is
VOUT = −VIN / D = −VIN
/
(
1−2−n
)
V
DD
V
IN
R
A
V
FB
DD
I
A
OUT
V
A
REF
AGND
GND
AMPLIFIER SELECTION
The primary requirement for the current-steering mode is an
amplifier with low input bias currents and low input offset
voltage. Because of the code-dependent output resistance of the
DAC, the input offset voltage of an op amp is multiplied by the
variable gain of the circuit. A change in the noise gain between
two adjacent digital fractions produces a step change in the
output voltage due to the amplifier’s input offset voltage. This
output voltage change is superimposed on the desired change in
output between the two codes and gives rise to a differential
linearity error, which, if large enough, could cause the DAC to
be nonmonotonic. The input offset voltage should be <1/4 LSB
to ensure monotonic behavior when stepping through codes.
V
OUT
NOTES
1. ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 43. Current-Steering DAC Used as a Divider or
Programmable Gain Element
As D is reduced, the output voltage increases. For small values
of the digital fraction D, it is important to ensure that the
amplifier does not saturate and that the required accuracy is
met. For example, an 8-bit DAC driven with the binary code
0x10 (0001 0000)—that is, 16 decimal—in the circuit of
Figure 43 should cause the output voltage to be 16 times VIN.
However, if the DAC has a linearity specification of 0.5 LSB, D
can have a weight in the range of 15.5/256 to 16.5/256 so that the
possible output voltage is in the range of 15.5 VIN to 16.5 VIN—
an error of 3%, even though the DAC itself has a maximum
error of 0.2%.
The input bias current of an op amp also generates an offset at
the voltage output as a result of the bias current flowing in the
feedback resistor, RFB. Most op amps have input bias currents
low enough to prevent significant errors in 12-bit applications.
Common-mode rejection of the op amp is important in voltage-
switching circuits, because it produces a code-dependent error
at the voltage output of the circuit. Most op amps have adequate
common-mode rejection for use at 8-, 10-, and 12-bit resolution.
DAC leakage current is also a potential error source in divider
circuits. The leakage current must be counterbalanced by an
opposite current supplied from the op amp through the DAC.
Because only a fraction, D, of the current into the VREF terminal
is routed to the IOUT1 terminal, the output voltage changes as
follows:
Provided that the DAC switches are driven from true wideband,
low impedance sources (VIN and AGND), they settle quickly.
Consequently, the slew rate and settling time of a voltage-
switching DAC circuit is determined largely by the output op
amp. To obtain minimum settling time in this configuration,
minimize capacitance at the VREF node (the voltage output node
in this application) of the DAC by using low input capacitance
buffer amplifiers and careful board design.
Output Error Voltage Due to DAC Leakage
=
Leakage × R
/D
where R is the DAC resistance at the VREF terminal.
For a DAC leakage current of 10 nA, R = 10 kΩ, and a gain (that
is, 1/D) of 16, the error voltage is 1.6 mV.
Most single-supply circuits include ground as part of the analog
signal range, which in turns requires an amplifier that can handle
rail-to-rail signals. Analog Devices offers a wide variety of single-
supply amplifiers (see Table 10 and Table 11).
Rev. C | Page 2± of 32
Data Sheet
AD5428/AD5440/AD5447
Table 9. Suitable ADI Precision References
Part No. Output Voltage (V)
Initial Tolerance (%)
Temp Drift (ppm/°C)
ISS (mA)
Output Noise (μV p-p) Package
ADR±ꢀ
ADR±ꢀ
ADR±2
ADR±2
ADR±3
ADR±3
ADR±6
ADR±6
ADR43ꢀ
ADR435
ADR39ꢀ
ADR395
ꢀ±
ꢀ±
5
±.±5
±.±5
±.±6
±.±6
±.ꢀ±
±.ꢀ±
±.ꢀ±
±.ꢀ±
±.±4
±.±4
±.ꢀ6
±.ꢀ±
3
9
3
9
3
9
3
9
3
3
9
9
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
±.8
±.8
±.ꢀ2
±.ꢀ2
2±
2±
ꢀ±
ꢀ±
6
SOIC-8
TSOT-23, SC7±
SOIC-8
TSOT-23, SC7±
SOIC-8
TSOT-23, SC7±
SOIC-8
TSOT-23, SC7±
SOIC-8
SOIC-8
TSOT-23
TSOT-23
5
2.5
2.5
3
3
2.5
5
6
ꢀ±
ꢀ±
3.5
8
5
8
2.5
5
Table 10. Suitable ADI Precision Op Amps
0.1 Hz to 10 Hz
Noise (μV p-p)
Part No.
OP97
OPꢀꢀ77
AD855ꢀ
AD86±3
AD8628
Supply Voltage (V)
±2 to ±2±
±2.5 to ±ꢀ5
2.7 to 5
ꢀ.8 to 6
2.7 to 6
VOS (Max) (μV)
IB (Max) (nA)
Supply Current (μA)
Package
25
6±
5
5±
5
±.ꢀ
2
±.±5
±.±±ꢀ
±.ꢀ
±.5
±.4
ꢀ
2.3
±.5
6±±
5±±
975
5±
SOIC-8
MSOP, SOIC-8
MSOP, SOIC-8
TSOT
85±
TSOT, SOIC-8
Table 11. Suitable ADI High Speed Op Amps
Part No.
AD8±65
AD8±2ꢀ
AD8±38
AD963ꢀ
Supply Voltage (V)
BW @ ACL (MHz)
Slew Rate (V/μs)
VOS (Max) (μV) IB (Max) (nA)
Package
5 to 24
±2.5 to ±ꢀ2
3 to ꢀ2
ꢀ45
49±
35±
32±
ꢀ8±
ꢀ2±
425
ꢀ,3±±
ꢀ,5±±
ꢀ,±±±
3,±±±
ꢀ±,±±±
6,±±±
ꢀ±,5±±
75±
SOIC-8, SOT-23, MSOP
SOIC-8, MSOP
SOIC-8, SC7±-5
SOIC-8
±3 to ±6
7,±±±
Rev. C | Page 2ꢀ of 32
AD5428/AD5440/AD5447
Data Sheet
8xC51-to-AD5428/AD5440/AD5447 Interface
PARALLEL INTERFACE
Figure 45 shows the interface between the AD5428/AD5440/
AD5447 and the 8xC51 family of DSPs. To facilitate external
data memory access, the address latch enable (ALE) mode is
enabled. The low byte of the address is latched with this output
pulse during access to the external memory. AD0 to AD7 are
the multiplexed low order addresses and data bus, and they
require strong internal pull-ups when emitting 1s. During
access to external memory, A8 to A15 are the high order
address bytes. Because these ports are open drain, they also
require strong internal pull-ups when emitting 1s.
Data is loaded into the AD5428/AD5440/AD5447 in 8-, 10-, or
12-bit parallel word format. Control lines
and R/ allow
CS
data to be written to or read from the DAC register. A write
event takes place when and R/ are brought low, data
W
CS
available on the data lines fills the shift register, and the rising
edge of latches the data and transfers the latched data-word
W
CS
to the DAC register. The DAC latches are not transparent;
therefore, a write sequence must consist of a falling and rising
edge on
to ensure that data is loaded into the DAC register
CS
and its analog equivalent is reflected on the DAC output.
A8 TO A15
ADDRESS BUS
A read event takes place when R/ is held high and is
W
CS
brought low. Data is loaded from the DAC register, goes back
into the input register, and is output onto the data line, where it
can be read back to the controller for verification or diagnostic
purposes. The input and DAC registers of these devices are not
AD5428/
AD5440/
AD54471
1
8051
ADDRESS
DECODER
CS
transparent; therefore, a falling and rising edge of
is required
CS
WR
R/W
to load each data-word.
DB0 TO DB11
8-BIT
LATCH
ALE
MICROPROCESSOR INTERFACING
ADSP-21xx-to-AD5428/AD5440/AD5447 Interface
AD0 TO AD7
DATA BUS
Figure 44 shows the AD5428/AD5440/AD5447 interfaced to
the ADSP-21xx series of DSPs as a memory-mapped device. A
single wait state may be necessary to interface the AD5428/
AD5440/AD5447 to the ADSP-21xx, depending on the clock
speed of the DSP. The wait state can be programmed via the
data memory wait state control register of the ADSP-21xx (see
the ADSP-21xx family’s user manual for details).
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 45. 8xC51-to-AD5428/AD5440/AD5447 Interface
ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
Figure 46 shows a typical interface between the AD5428/
AD5440/AD5447 and the ADSP-BF5xx family of DSPs. The
asynchronous memory write cycle of the processor drives the
ADDR TO
ADRR
0
ADDRESS BUS
13
digital inputs of the DAC. The
x line is actually four
AMS
memory select lines. Internal ADDR lines are decoded into
3–0, and then these lines are inserted as chip selects. The
AD5428/
AD5440/
AD54471
1
ADSP-21xx
AMS
rest of the interface is a standard handshaking operation.
ADDRESS
DECODER
DMS
WR
CS
ADDR TO
1
ADDRESS BUS
R/W
ADRR
19
DB0 TO DB11
AD5428/
AD5440/
AD54471
1
ADSP-BF5xx
ADDRESS
DECODER
AMSx
DATA 0 TO
DATA 23
CS
DATA BUS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
AWE
R/W
Figure 44. ADSP21xx-to-AD5428/AD5440/AD5447 Interface
DB0 TO DB11
DATA 0 TO
DATA 23
DATA BUS
1
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. ADSP-BF5xx-to-AD5428/AD5440/AD5447 Interface
Rev. C | Page 22 of 32
Data Sheet
AD5428/AD5440/AD5447
microstrip technique is by far the best method, but its use is not
always possible with a double-sided board. In this technique,
the component side of the board is dedicated to the ground
plane, and signal traces are placed on the soldered side.
PCB LAYOUT AND POWER SUPPLY DECOUPLING
In any circuit where accuracy is important, careful
consideration of the power supply and ground return layout
helps to ensure the rated performance. The printed circuit
board on which the AD5428/AD5440/AD5447 is mounted
should be designed so that the analog and digital sections are
separate and confined to certain areas of the board. If the DAC
is in a system where multiple devices require an AGND-to-
DGND connection, the connection should be made at one
point only. The star ground point should be established as close
as possible to the device.
It is good practice to use compact, minimum lead length PCB
layout design. Leads to the input should be as short as possible
to minimize IR drops and stray inductance.
The PCB metal traces between VREF and RFB should also be
matched to minimize gain error. To maximize high frequency
performance, the I-to-V amplifier should be located as close as
possible to the device.
These DACs should have ample supply bypassing of 10 μF in
parallel with 0.1 μF on the supply located as close as possible to
the package, ideally right up against the device. The 0.1 μF
capacitor should have low effective series resistance (ESR) and
low effective series inductance (ESI), like the common ceramic
types of capacitors that provide a low impedance path to ground
at high frequencies, to handle transient currents due to internal
logic switching. Low ESR 1 μF to 10 μF tantalum or electrolytic
capacitors should also be applied at the supplies to minimize
transient disturbance and filter out low frequency ripple.
EVALUATION BOARD FOR THE AD5447
The evaluation board consists of an AD5447 DAC and a
current-to-voltage amplifier, the AD8065. Included on the
evaluation board is a 10 V reference, the ADR01. An external
reference may also be applied via an SMB input.
The evaluation kit consists of a CD-ROM with self-installing
PC software to control the DAC. The software simply allows the
user to write a code to the device.
POWER SUPPLIES FOR THE EVALUATION BOARD
Components, such as clocks, that produce fast-switching signals
should be shielded with digital ground to avoid radiating noise
to other parts of the board, and they should never be run near
the reference inputs.
The board requires 12 V and +5 V supplies. The +12 V VDD
and −12 V VSS are used to power the output amplifier; the +5 V
is used to power the DAC (VDD1) and transceivers (VCC).
Both supplies are decoupled to their respective ground plane
with 10 ꢀF tantalum and 0.1 ꢀF ceramic capacitors.
Avoid crossover of digital and analog signals. Traces on
opposite sides of the board should run at right angles to each
other. This reduces the effects of feedthrough on the board. A
Rev. C | Page 23 of 32
AD5428/AD5440/AD5447
Data Sheet
Figure 47. Schematic of AD5447 Evaluation Board
Rev. C | Page 24 of 32
Data Sheet
AD5428/AD5440/AD5447
Figure 48. Component-Side Artwork
Figure 49. Silkscreen—Component-Side View (Top Layer)
Rev. C | Page 25 of 32
AD5428/AD5440/AD5447
Data Sheet
Figure 50. Solder-Side Artwork
Rev. C | Page 26 of 32
Data Sheet
AD5428/AD5440/AD5447
BILL OF MATERIALS
Table 12.
Name/Position Part Description
Value
Tolerance (%)
Stock Code
Cꢀ
X7R ceramic capacitor
±.ꢀ ꢁF
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
ꢀ±
FEC 499-675
FEC 499-675
FEC ꢀ97-427
FEC 499-675
FEC ꢀ97-ꢀ3±
FEC 499-675
FEC 72ꢀ-876
FEC 499-675
FEC ꢀ97-427
FEC 499-675
FEC ꢀ97-427
FEC 499-675
FEC 499-675
FEC ꢀ97-427
FEC 499-675
FEC ꢀ97-427
FEC 499-675
FEC ꢀ97-427
FEC 499-675
FEC ꢀ97-427
FEC 499-675
FEC 72ꢀ-876
FEC ꢀ97-427
FEC 499-675
FEC ꢀ97-427
FEC 499-675
FEC 24±-345 (Pack)
FEC 3ꢀ±-682
FEC 3ꢀ±-682
FEC 3ꢀ±-682
FEC 3ꢀ±-682
FEC 3ꢀ±-682
FEC 3ꢀ±-682
FEC 5ꢀꢀ-79ꢀ and FEC 528-456
FEC ꢀ47-753
FEC ꢀ5ꢀ-792
FEC 24±-345 (Pack)
FEC 24±-345 (Pack)
AD5447YRU
C2
X7R ceramic capacitor
±.ꢀ ꢁF
C3
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF 2± V
±.ꢀ ꢁF
C4
C5
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF ꢀ± V
±.ꢀ ꢁF
C6
C7
NPO ceramic capacitor
ꢀ.8 pF
C8
X7R ceramic capacitor
±.ꢀ ꢁF
C9
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF 2± V
±.ꢀ ꢁF
Cꢀ±
Cꢀꢀ
Cꢀ2
Cꢀ3
Cꢀ4
Cꢀ5
Cꢀ6
Cꢀ7
Cꢀ8
Cꢀ9
C2±
C2ꢀ
C22
C23
C24
C25
C26
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF 2± V
±.ꢀ ꢁF
X7R ceramic capacitor
±.ꢀ ꢁF
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF 2± V
±.ꢀ ꢁF
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF 2± V
±.ꢀ ꢁF
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF 2± V
±.ꢀ ꢁF
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF 2± V
±.ꢀ ꢁF
NPO ceramic capacitor
ꢀ.8 pF
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF 2± V
±.ꢀ ꢁF
Tantalum capacitor—Taj series
X7R ceramic capacitor
ꢀ± ꢁF 2± V
±.ꢀ ꢁF
CS, DB± to DBꢀꢀ Red testpoint
Jꢀ to J6
SMB socket
J2
SMB socket
J3
SMB socket
J4
SMB socket
J5
SMB socket
J6
SMB socket
LKꢀ
3-pin header (2 × 2)
36-pin Centronics connector
6-pin terminal block
Red testpoint
Red testpoint
AD5447
Pꢀ
P2
RW
TPꢀ to TP4
Uꢀ
U2
ADR±ꢀ
ADR±ꢀAR
U3
AD8±65
AD8±65AR
U4, U5
U6
74ABT543
Fairchild 74ABT543CMTC
CD74HCTꢀ39M
AD8±65AR
74ꢀ39
U7
AD8±65
Each Corner
Rubber stick-on feet
FEC ꢀ48-922
Rev. C | Page 27 of 32
AD5428/AD5440/AD5447
Data Sheet
OVERVIEW OF AD54xx DEVICES
Table 13.
Part No.
AD5424
AD5426
AD5428
AD5429
AD545±
AD5432
AD5433
AD5439
AD544±
AD5451
AD5443
AD5444
AD5415
AD54±5
AD5445
AD5447
AD5449
AD5452
AD5446
AD5453
AD5553
AD5556
AD5555
AD5557
AD5543
AD5546
AD5545
AD5547
Resolution
No. DACs
INL (LSB)
±±.25
±±.25
±±.25
±±.25
±±.25
±±.5
±±.5
±±.5
±±.5
±±.25
±1
Interface
Parallel
Serial
Parallel
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Serial
Serial
Serial
Parallel
Parallel
Parallel
Serial
Serial
Serial
Serial
Serial
Parallel
Serial
Parallel
Serial
Parallel
Serial
Parallel
Package1
RU-16, CP-2±
RM-1±
RU-2±
Features
8
1
1
2
2
1
1
1
2
2
1
1
1
2
2
2
2
2
1
1
1
1
1
2
2
1
1
2
2
1± MHz BW, 17 ns CS pulse width
1± MHz BW, 5± MHz serial
1± MHz BW, 17 ns CS pulse width
1± MHz BW, 5± MHz serial
1± MHz BW, 5± MHz serial
1± MHz BW, 5± MHz serial
1± MHz BW, 17 ns CS pulse width
1± MHz BW, 5± MHz serial
1± MHz BW, 17 ns CS pulse width
1± MHz BW, 5± MHz serial
1± MHz BW, 5± MHz serial
1± MHz BW, 5± MHz serial
8
8
8
8
RU-1±
UJ-8
RM-1±
RU-2±, CP-2±
RU-16
1±
1±
1±
1±
1±
12
12
12
12
12
12
12
12
14
14
14
14
14
14
16
16
16
16
RU-24
UJ-8
RM-1±
RM-8
RU-24
CP-4±
±±.5
±1
±1
1± MHz BW, 5± MHz serial
1± MHz BW, 17 ns CS pulse width
1± MHz BW, 17 ns CS pulse width
1± MHz BW, 17 ns CS pulse width
1± MHz BW, 5± MHz serial
1± MHz BW, 5± MHz serial
1± MHz BW, 5± MHz serial
±1
RU-2±, CP-2±
RU-24
±1
±1
±±.5
±1
±2
±1
RU-16
UJ-8, RM-8
RM-8
UJ-8, RM-8
RM-8
RU-28
1± MHz BW, 5± MHz serial
4 MHz BW, 5± MHz serial clock
4 MHz BW, 2± ns WR pulse width
4 MHz BW, 5± MHz serial clock
4 MHz BW, 2± ns WR pulse width
4 MHz BW, 5± MHz serial clock
4 MHz BW, 2± ns WR pulse width
4 MHz BW, 5± MHz serial clock
4 MHz BW, 2± ns WR pulse width
±1
±1
±1
RM-8
RU-38
±2
±2
RM-8
RU-28
±2
±2
RU-16
RU-38
1 RU = TSSOP, CP = LFCSP, RM = MSOP, UJ = TSOT.
Rev. C | Page 28 of 32
Data Sheet
AD5428/AD5440/AD5447
OUTLINE DIMENSIONS
7.90
7.80
7.70
6.60
6.50
6.40
24
13
4.50
4.40
20
11
10
4.50
4.40
4.30
4.30
6.40 BSC
12
1
6.40 BSC
1
PIN 1
0.65
1.20
PIN 1
BSC
MAX
0.65
BSC
0.15
0.05
1.20 MAX
0.15
0.05
0.20
0.09
0.75
0.60
0.45
8°
0°
0.75
0.60
0.45
0.30
0.19
0.20
0.09
8°
0°
SEATING
PLANE
0.30
0.19
COPLANARITY
0.10
SEATING
PLANE
0.10 COPLANARITY
COMPLIANT TO JEDEC STANDARDS MO-153-AC
COMPLIANT TO JEDEC STANDARDS MO-153-AD
Figure 51. 20-Lead Thin Shrink Outline Package [TSSOP]
(RU-20)
Figure 52. 24-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-24)
Dimensions shown in millimeters
Dimensions shown in millimeters
ORDERING GUIDE
Model1
Resolution
INL (LSB)
±±.5
±±.5
±±.5
±±.5
±±.5
±±.5
±±.5
±±.5
±±.5
±±.5
±1
Temperature Range
Package Description
2±-Lead TSSOP
2±-Lead TSSOP
2±-Lead TSSOP
2±-Lead TSSOP
2±-Lead TSSOP
2±-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
24-Lead TSSOP
Evaluation Kit
Package Option
RU-2±
RU-2±
RU-2±
RU-2±
AD5428YRU
8
8
8
8
8
8
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
–4± °C to +125°C
AD5428YRU-REEL
AD5428YRU-REEL7
AD5428YRUZ
AD5428YRUZ-REEL
AD5428YRUZ-REEL7
AD544±YRU
AD544±YRU-REEL
AD544±YRU-REEL7
AD544±YRUZ
AD544±YRUZ-REEL
AD544±YRUZ-REEL7
AD5447YRU
AD5447YRU-REEL
AD5447YRUZ
AD5447YRUZ-REEL
AD5447YRUZ-REEL7
EVAL-AD5447EBZ
RU-2±
RU-2±
1±
1±
1±
1±
12
12
12
12
12
12
12
RU-24
RU-24
RU-24
RU-24
RU-24
RU-24
±1
±1
±1
±1
±1
RU-24
RU-24
RU-24
RU-24
±1
RU-24
1 Z = RoHS Compliant Part.
Rev. C | Page 29 of 32
AD5428/AD5440/AD5447
NOTES
Data Sheet
Rev. C | Page 3± of 32
Data Sheet
NOTES
AD5428/AD5440/AD5447
Rev. C | Page 31 of 32
AD5428/AD5440/AD5447
NOTES
Data Sheet
©2004–2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D04462-0-8/11(C)
Rev. C | Page 32 of 32
相关型号：
AD5442ABCPZ-1-RL7
SERIAL INPUT LOADING, 1us SETTLING TIME, 16-BIT DAC, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-220WEED, LFCSP-10
ADI
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