AD5441 [ADI]
12-Bit Serial Input Multiplying DAC; 12位串行输入乘法数模转换器
| 型号： | AD5441 |
| 厂家： | 
ADI |
| 描述： | 12-Bit Serial Input Multiplying DAC |
| 文件： | 总16页 (文件大小：277K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
12-Bit Serial Input
Multiplying DAC
AD5441
Preliminary Technical Data
FEATURES
FUNCTIONAL BLOCK DIAGRAM
3 V to 5 V supply operation
True 12-bit accuracy
5 V operation @ <10 μA
AD5441
V
R
I
DD
FB
V
DAC
REF
OUT
Fast 3-wire serial input
12
Fast 1 μs settling time
LD
DAC REG
2.4 MHz, 4-quadrant multiply BW
Upgrade for DAC8043 and DAC8043A
Standard and rotated pinout
12
GND
CLK
SRI
12-BIT SHIFT
REGISTER
APPLICATIONS
Figure 1.
Ideal for PLC applications in industrial control
Programmable amplifiers and attenuators
Digitally controlled calibration and filters
Motion control systems
GENERAL DESCRIPTION
0.5
0.4
The AD5441 is an improved high accuracy 12-bit multiplying
digital-to-analog converter (DAC) in space-saving 8-lead
packages. Featuring serial input, double buffering, and excellent
analog performance, the AD5441 is ideal for applications where
PC board space is at a premium. Improved linearity and gain
error performance permit reduced part counts through the
elimination of trimming components. Separate input clock and
load DAC control lines allow full user control of data loading
and analog output.
T
= –40°C, +25°C, +85°C
A
V
= +5V
DD
V
= –10V
REF
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
The circuit consists of a 12-bit serial-in/parallel-out shift
register, a 12-bit DAC register, a 12-bit CMOS DAC, and
control logic. Serial data is clocked into the input register on the
rising edge of the CLOCK pulse. When the new data-word is
0
512
1024
1536
2048
2560
3072
3584
4096
CODE
LD
clocked in, it is loaded into the DAC register with the
input
Figure 2. Integral Nonlinearity Error vs. Code
pin. Data in the DAC register is converted to an output current
by the DAC.
Consuming only 10 μA from a single 5 V power supply, the
AD5441 is the ideal low power, small size, high performance
solution to many application problems.
The AD5441 is specified over the extended industrial (−40°C to
+125°C) temperature range. It is available in an 8-lead LFCSP
and an 8-lead MSOP.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registeredtrademarks arethe property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
©2007 Analog Devices, Inc. All rights reserved.
AD5441
Preliminary Technical Data
TABLE OF CONTENTS
Features .............................................................................................. 1
Typical Performance Characteristics ..............................................7
Terminology.................................................................................... 10
Parameter Definitions.................................................................... 11
General Circuit Information..................................................... 11
Output Impedance ..................................................................... 11
Applications Information.......................................................... 11
Unipolar 2-Quadrant Multiplying ........................................... 11
Bipolar 4-Quadrant Multiplying .............................................. 12
Interface Logic Information...................................................... 12
Digital Section ............................................................................ 12
Outline Dimensions....................................................................... 13
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description......................................................................... 1
Table of Contents.............................................................................. 2
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Characteristics............................................................. 3
Absolute Maximum Ratings............................................................ 4
ESD Caution.................................................................................. 4
Pin Configurations and Function Descriptions ........................... 5
REVISION HISTORY
3/07—Revision PrA: Preliminary Version
Rev. PrA | Page 2 of 16
Preliminary Technical Data
AD5441
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
@ VDD = 5 V, VREF = 10 V, −40°C < TA < +125°C, unless otherwise noted.
Table 1.
Parameter
Symbol
Min Typ
Max
Unit
Condition
STATIC PERFORMANCE
Resolution
Relative Accuracy
Differential Nonlinearity
N
12
Bits
LSB
LSB
LSB
ppm/°C
nA
INL
DNL
GFSE
TCGFS
ILKG
±1.ꢀ
±1.ꢀ
±2.ꢀ
±±
All grades monotonic to 12 bits
Data = FFFH
IOUT pin measured
Gain Temperature Coefficient1
Output Leakage Current
±±
Data = ꢀꢀꢀH, IOUT pin measured
±2±
ꢀ.ꢀ3
ꢀ.1±
nA
LSB
LSB
TA = –4ꢀ°C, +12±°C, Data = ꢀꢀꢀH, IOUT pin measured
Data = ꢀꢀꢀH
TA = −4ꢀ°C, +12±°C, Data = ꢀꢀꢀH
Zero-Scale Error
IZSE
REFERENCE INPUT
Input Resistance
Input Capacitance1
ANALOG OUTPUT
Output Capacitance1
RREF
CREF
7
1±
kΩ
pF
Absolute temperature coefficient < ±ꢀ ppm/°C
±
COUT
2±
3ꢀ
pF
pF
Data = ꢀꢀꢀH
Data = FFFH
DIGITAL INPUTS
Digital Input Low
Digital Input High
Input Leakage Current
Input Capacitance1
INTERFACE TIMING1, 2
Data Setup
Data Hold
Clock Width High
Clock Width Low
Load Pulse Width
LD DAC High to MSB CLK High
LSB CLK to LD DAC
AC CHARACTERISTICS1
Output Current Settling Time
DAC Glitch
VIL
VIH
IIL
ꢀ.8
V
V
μA
pF
2.4
1
1ꢀ
VLOGIC = ꢀ V to ± V
VLOGIC = ꢀ V
CIL
tDS
tDH
tCH
tCL
tLD
tLD1
tASB
1ꢀ
±
2±
2±
2±
ꢀ
ns
ns
ns
ns
ns
ns
ns
ꢀ
tS
Q
1
2ꢀ
μs
nVs
To ±ꢀ.ꢀ1ꢁ of full-scale, external op amp OP42
Data = ꢀꢀꢀH to FFFH to ꢀꢀꢀH, VREF = ꢀ V
Digital Feedthrough
Feedthrough (VOUT/VREF
TBD
1
)
FT
mV p-p
dB
nV/√Hz
MHz
V
VREF = 2ꢀ V p-p, data = ꢀꢀꢀH, f = 1ꢀ kHz
VREF = 6 V rms, data = FFFH, f = 1 kHz
1ꢀ Hz to 1ꢀꢀ kHz between RFB and IOUT
−3 dB, VOUT/VREF, VREF = 1ꢀꢀ mV rms, data = FFFH
Total Harmonic Distortion
Output Noise Density
Multiplying Bandwidth
Power Supply Range
Positive Supply Current
Power Dissipation
THD
en
BW
VDD RANGE
IDD
PDISS
PSS
−8±
17
2.4
3
±
1ꢀ
±ꢀ
μA
μW
VLOGIC = ꢀ V or VDD
VLOGIC = ꢀ V or VDD
ΔVDD = ±±ꢁ
Power Supply Sensitivity
ꢀ.ꢀꢀ2 ꢁ/ꢁ
1 These parameters are guaranteed by design and not subject to production testing.
2 All input control signals are specified with tR = tF = 2 ns (1ꢀꢁ to 9ꢀꢁ of ± V) and timed from a voltage level of 1.6 V.
Rev. PrA | Page 3 of 16
AD5441
Preliminary Technical Data
ABSOLUTE MAXIMUM RATINGS
The AD5441 contains 346 transistors. The die size measures
70.3 mm × 57.1 mm = 4014 square mm.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Table 2.
Parameter
Rating
VDD to GND
VREF to GND
−ꢀ.3 V, +8 V
±18 V
RFB to GND
±18 V
Logic Inputs to GND
VIOUT to GND
−ꢀ.3 V, VDD + ꢀ.3 V
−ꢀ.3 V, VDD + ꢀ.3 V
±ꢀ mA
ESD CAUTION
IOUT Short Circuit to GND
Package Power Dissipation
Thermal Resistance
θJA: 8-Lead MSOP
(TJ max − TA)/θJA
142°C/W
7±°C/W
θJA: 8-Lead LFCSP1
θJC: 8-Lead MSOP
θJC: 8-Lead LFCSP1
44°C/W
18°C/W
Maximum Junction Temperature (TJ max)
Operating Temperature Range
Storage Temperature Range
Lead Temperature (Soldering, 1ꢀ sec)
1±ꢀ°C
−4ꢀ°C to +12±°C
−6±°C to +1±ꢀ°C
3ꢀꢀ°C
1 Exposed pad soldered to application board.
Rev. PrA | Page 4 of 16
Preliminary Technical Data
AD5441
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
VREF
RFB
1
2
3
4
8 VDD
7 CLK
5 SRI
5 LD
AD5441
TOP VIEW
(Not to Scale)
VREF
RFB
1
2
3
4
8
7
6
5
VDD
CLK
SRI
LD
IOUT
GND
AD5441
TOP VIEW
(Not to Scale)
IOUT
GND
Figure 4. 8-Lead MSOP Pin Configuration
Figure 3. 8-LeadLFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
Mnemonic Descriptions
1
2
3
4
±
VREF
RFB
IOUT
GND
LD
DAC Reference Input Pin. Establishes DAC full-scale voltage. Constant input resistance vs. code.
Internal Matching Feedback Resistor. Connect to external op amp output.
DAC Current Output, full-scale output 1 LSB less than reference input voltage −VREF
Analog and Digital Ground.
.
Load Strobe, Level-Sensitive Digital Input. Transfers shift-register data to DAC register while active low.
See Table 4 for operation.
6
7
8
SRI
CLK
VDD
12-Bit Serial Register Input, data loads directly into the shift register MSB first. Extra leading bits are ignored.
Clock Input, positive-edge clocks data into shift register.
Positive Power Supply Input. Specified range of operation ± V ± 1ꢀꢁ.
Rev. PrA | Page ± of 16
AD5441
Preliminary Technical Data
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SRI
CLK
tLD1
tASB
LD
DATA LOADED MSB(D11) FIRST
Dxx
DAC REGISTER LOAD
SRI
tDS
tDH
tCL
CLK
LD
tCH
tLD
tS
FS
±1LSB
V
OUT
ERROR BAND
ZS
Figure 5. Timing Diagram
Table 4. Control-Logic Truth Table
CLK
LD
Serial Shift Register Function
DAC Register Function
1
H
Shift-register-data advanced one bit
Latched
↑
H or L
L
L
No effect
No effect
Updated with current shift register contents
Latched all 12 bits
1
↑
1
↑ equals positive logic transition.
Rev. PrA | Page 6 of 16
Preliminary Technical Data
AD5441
TYPICAL PERFORMANCE CHARACTERISTICS
35
10
1
SS = 200 UNITS
V
V
= 5V
= 0V OR V
DD
LOGIC
T
V
= 25°C
= 5V
A
DD
30
25
20
15
10
5
DD
V
= 10V
REF
0.1
0.01
0
0.001
0.5
TOTAL UNADJUSTED ERROR (LSB)
1.0
–1.0
–0.5
0
–55
–35
–15
5
25
45
65
85
105
125
TEMPERATURE (°C)
Figure 6. Total Unadjusted Error Histogram
Figure 9. Supply Current IDD vs. Temperature
3500
3000
2500
2000
1500
1000
500
V
= 5V
= 10V
= 25°C
DD
50
V
REF
SS = 200 UNITS
= –40°C TO +85°C
T
A
T
A
V
V
= 5V
DD
= 10V
40
30
REF
CODE = 0xF55
CODE = 0x800
20
10
0
CODE = 0xFFF
0
1k
10k
100k
1M
10M
100M
0
1
2
FREQUENCY (Hz)
FULL SCALE TEMPCO (ppm/°C)
Figure 10. Supply Current IDD vs. Clock Frequency
Figure 7. Full-Scale Output Temperature Coefficient Histogram
100
80
ΔV = 5V ± 10%
DD
0.5
T
V
= 25°C
A
= 5V
DD
0.4
0.3
0.2
0.1
0
60
40
20
1k
10k
100k
1M
10M
FREQUENCY (Hz)
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
LOGIC INPUT VOLTAGE (V)
Figure 11. Power Supply Rejection Ratio (PSRR) vs. Frequency
Figure 8. Supply Current IDD vs. Logic Input Voltage
Rev. PrA | Page 7 of 16
AD5441
Preliminary Technical Data
0.5
V
V
V
T
= 5V
= 5V
DD
DD
5V
= 10V
V
= 10V
REF
0.4
REF
= 25°C
SUPERIMPOSED: T = –40°C, +25°C, +85°C
A
A
CLK
(5V/DIV)
0.3
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
V
OUT
(5V/DIV)
5V
0
512
1024
1536
2048
2560
3072
3584
4096
TIME (1µs/DIV)
CODE (Decimal)
Figure 12. Linearity Error vs. Digital Code
Figure 15. Large Signal Settling Time
4
2
0
ALL BITS ON
V
= 5V
DD
(MSB) B
V
T
= 10V
11
REF
12
24
36
48
60
72
84
96
108
B
= 25°C
10
A
B
B
B
B
B
9
8
7
6
5
4
B
0
–2
–4
B
B
B
3
2
1
0
(LSB) B
ALL BITS OFF
100
1k
10k
100k
1M
10M
–2000
–1000
0
1000
2000
FREQUENCY (Hz)
OP AMP OFFSET V (µV)
OS
Figure 13. Linearity Error vs. External Op Amp Offset VOS
Figure 16. Reference Multiplying Bandwidth vs. Frequency and Code
V
V
= 5V
DD
V
T
= 5V
DD
= 25°C
A
= 10V
REF
0.50
0.25
0
fCLK = 2.5MHz
CODE: 0x7FF TO 0x800
V
OUT
(10mV/DIV)
LD
(5V/DIV)
–0.25
–0.50
20mV
0
5
10
TIME (200ns/DIV)
|V
| (V)
REF
Figure 17. Linearity Error vs. Reference Voltage
Figure 14. Midscale Transition Performance
Rev. PrA | Page 8 of 16
Preliminary Technical Data
AD5441
0.0320
1.2
–70
SAMPLE SIZE = 50
V
= 4V p-p
REF
OUTPUT OP AMP: OP42
1.0
0.8
0.6
0.4
0.0180
–75
–80
CODE = 0xFFF
0.0100
0.0056
0.0032
–85
–90
–95
CODE = 0x000
0.2
0
0.0018
100k
10
100
1k
FREQUENCY (Hz)
10k
0
100
200
300
400
500
600
HOURS OF OPERATION AT 150°C
Figure 18. Long-Term Drift Accelerated by Burn-In
Figure 19. THD vs. Frequency
Rev. PrA | Page 9 of 16
AD5441
Preliminary Technical Data
TERMINOLOGY
Digital Feedthrough
Relative Accuracy
When the device is not selected, high frequency logic activity
on the device’s digital inputs may be capacitively coupled
through the device and produce noise on the IOUT pins. This
noise is coupled from the outputs of the device onto follow-on
circuitry. This noise is digital feedthrough.
Relative accuracy or endpoint nonlinearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero and full scale and is normally expressed in
LSBs or as a percentage of the full-scale reading.
Multiplying Feedthrough Error
Differential Nonlinearity
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT1 terminal when all 0s are
loaded to the DAC.
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of −1 LSB maximum
over the operating temperature range ensures monotonicity.
Total Harmonic Distortion (THD)
The DAC is driven by an ac reference. The ratio of the rms sum
of the harmonics of the DAC output to the fundamental value is
the THD. Usually only the lower order harmonics, such as
second to fifth, are included.
Gain Error
Gain error or full-scale error is a measure of the output error
between an ideal DAC and the actual device output. For these
DACs, ideal maximum output is VREF − 1 LSB. Gain error of the
DACs is adjustable to zero with external resistance.
V22 + V32 + V4 + V52
2
THD = 20log
Zero Scale Error
V
1
Calculated from worst-case RREF
ZSE(LSB) = (RREF × ILKG × 4096)/VREF
Output Leakage Current
:
Compliance Voltage Range
The maximum range of (output) terminal voltage for which the
device will provide the specified characteristics.
I
.
Output leakage current is the current that flows into the DAC
ladder switches when they are turned off. For the IOUT terminal,
it can be measured by loading all 0s to the DAC and measuring
the IOUT current.
Output Noise Spectral Density
Calculation from
en = √4KTRB
where:
Output Capacitance
Capacitance from IOUT1 to AGND.
K = Boltzmann Constant (J/°K)
R = Resistance (Ω)
Digital-to-Analog Glitch Impulse
The amount of charge injected from the digital inputs to the
analog output when the inputs change state. This is normally
specified as the area of the glitch in either pA-s or nV-s,
depending on whether the glitch is measured as a current or
voltage signal.
T = Resistor temperature (°K)
B = 1 Hz bandwidth
Rev. PrA | Page 1ꢀ of 16
Preliminary Technical Data
AD5441
PARAMETER DEFINITIONS
GENERAL CIRCUIT INFORMATION
OUTPUT IMPEDANCE
The AD5441’s output resistance, as in the case of the output
capacitance, varies with the digital input code. This resistance,
looking back into the IOUT terminal, may be between 10 kꢀ, the
feedback resistor alone when all digital inputs are low, and
7.5 kꢀ, the feedback resistor in parallel with approximate 30 kꢀ
of the R-2R ladder network resistance when any single bit logic
is high. Static accuracy and dynamic performance will be
affected by these variations.
The AD5441 is a 12-bit multiplying DAC with a low
temperature coefficient. It contains an R-2R resistor ladder
network, data input and control logic, and two data registers.
The digital circuitry forms an interface in which serial data can
be loaded under microprocessor control into a 12-bit shift
register and then transferred, in parallel, to the 12-bit DAC
register.
The analog portion of the AD5441 contains an inverted R-2R
ladder network consisting of silicon-chrome, highly stable
(50 ppm/°C), thin-film resistors, and 12 pairs of NMOS
current-steering switches, see Figure 20. These switches steer
binarily weighted currents into either IOUT or GND; this yields a
constant current in each ladder leg, regardless of digital input
code. This constant current results in a constant input resistance
at VREF equal to R. The VREF input may be driven by any
reference voltage or current, ac or dc that is within the limits
stated in the Absolute Maximum Ratings.
APPLICATIONS INFORMATION
In most applications, linearity depends upon the potential of
the IOUT and GND pins being at the same voltage potential. The
DAC is connected to an external precision op amp inverting
input. The external amplifiers noninverting input should be tied
directly to ground without the usual bias current compensating
resistor (see Figure 21 and Figure 22). The selected amplifier
should have a low input bias current and low drift over
temperature. The amplifiers input offset voltage should be
nulled to less than 200 mV (less than 10% of 1 LSB). All
grounded pins should tie to a single common ground point to
avoid ground loops. The VDD power supply should have a low
noise level with adequate bypassing. It is best to operate the
AD5441 from the analog power supply and grounds.
10kΩ
20kΩ
S1
10kΩ
20kΩ
S2
10kΩ
20kΩ
S3
V
REF
20kΩ
20kΩ
S12
*
GND
UNIPOLAR 2-QUADRANT MULTIPLYING
I
OUT
10kΩ
R
The most straightforward application of the AD5441 is in the
2-quadrant multiplying configuration shown in Figure 21.
If the reference input signal is replaced with a fixed dc voltage
reference, the DAC output will provide a proportional dc
voltage output according to the transfer equation
FEEDBACK
*
BIT 1 (MSB)
BIT 2
BIT 3
BIT 12 (LSB)
DIGITAL INPUTS
*THESE SWITCHES PERMANENTLY ON.
NOTES
1. SWITCHES SHOWN FOR DIGITAL INPUTS HIGH.
Figure 20. Simplified DAC Circuit
V
OUT = −D/4096 × VREF
where:
The 12 output current steering NMOS FET switches are in
series with each R-2R resistor.
D is the decimal data loaded into the DAC register.
To further ensure accuracy across the full temperature range,
permanently on MOS switches were included in series with the
feedback resistor and the R-2R ladder’s terminating resistor.
Figure 20 shows the location of the series switches. During any
testing of the resistor ladder or RFEEDBACK (such as incoming
inspection), VDD must be present to turn on these series
switches.
V
REF is the externally applied reference voltage source.
V
DD
R2
C1
V
R
DD
FB
I
1
OUT
V
REF
V
REF
A1
AD5441
R1
GND
V
= 0 TO –V
REF
OUT
LD CLK SRI
AGND
μCONTROLLER
NOTES
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
2. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1 IS A HIGH SPEED AMPLIFIER.
Figure 21. Unipolar (2-Quadrant) Operation
Rev. PrA | Page 11 of 16
AD5441
Preliminary Technical Data
BIPOLAR 4-QUADRANT MULTIPLYING
INTERFACE LOGIC INFORMATION
Figure 22 shows a suggested circuit to achieve 4-quadrant
multiplying operation. The summing amplifier multiplies VOUT1
by 2 and offsets the output with the reference voltage so that a
midscale digital input code of 2048 places VOUT2 at 0 V. The
negative full-scale voltage will be VREF when the DAC is loaded
with all zeros. The positive full-scale output will be −(VREF − 1
LSB) when the DAC is loaded with all ones. Therefore, the
digital coding is offset binary. The voltage output transfer
equation for various input data and reference (or signal) values
follows
The AD5441 has been designed for ease of operation. The
timing diagram in Figure 5 illustrates the input register loading
sequence. Note that the most significant bit (MSB) is loaded
first. Once the 12-bit input register is full, the data is transferred
LD
to the DAC register by taking
momentarily low.
DIGITAL SECTION
LD
The AD5441’s digital inputs, SRI,
, and CLK, are TTL
compatible. The input voltage levels affect the amount of
current drawn from the supply; peak supply current occurs as
the digital input (VIN) passes through the transition region. See
Figure 8 for the supply current vs. logic input voltage graph.
Maintaining the digital input voltage levels as close as possible
to the supplies, VDD and GND, minimizes supply current
consumption. The AD5441’s digital inputs have been designed
with ESD resistance incorporated through careful layout and
the inclusion of input protection circuitry. Figure 23 shows the
input protection diodes and series resistor; this input structure
is duplicated on each digital input. High voltage static charges
applied to the inputs are shunted to the supply and ground rails
through forward-biased diodes. These protection diodes were
designed to clamp the inputs to well below dangerous levels
during static discharge conditions.
V
OUT2 = (D/2048 − 1) − VREF
where:
D is the decimal data loaded into the DAC register.
V
REF is the externally applied reference voltage source.
R3
20kΩ
V
DD
DD
R5
20kΩ
R2
C1
V
R
FB
R4
10kΩ
I
1
OUT
V
±10V
REF
V
REF
A1
AD5441
R1
GND
A2
V
=
–V
REF
TO +V
REF
OUT
LD
CLK SRI
AGND
μCONTROLLER
NOTES
V
DD
1. R1 AND R2 USED ONLY IF GAIN ADJUSTMENT IS REQUIRED.
ADJUST R1 FOR V = 0V WITH CODE 10000000 LOADED TO DAC.
OUT
2. MATCHING AND TRACKING IS ESSENTIAL FOR RESISTOR PAIRS
R3 AND R4.
3. C1 PHASE COMPENSATION (1pF TO 2pF) MAY BE REQUIRED
IF A1/A2 IS A HIGH SPEED AMPLIFIER.
5kΩ
LD, CLK, SRI
Figure 22. Bipolar (4-Quadrant) Operation
GND
Figure 23. Digital Input Protection
Rev. PrA | Page 12 of 16
Preliminary Technical Data
OUTLINE DIMENSIONS
AD5441
1.89
1.74
1.59
3.25
3.00
2.75
0.25
0.20
0.15
0.55
0.40
0.30
5
8
2.25
2.00
1.75
1.95
1.75
1.55
EXPOSEDPAD
BOTTOM VIEW
TOP VIEW
0.60
0.45
0.30
0.15
0.10
0.05
4
1
PIN 1
2.95
2.75
2.55
INDICATOR
0.50 BSC
12° MAX
0.80 MAX
0.65 TYP
1.00
0.85
0.80
0.05 MAX
0.02 NOM
0.30
0.23
0.18
SEATING
PLANE
0.20 REF
Figure 24. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD]
(CP-8-1)
Dimensions are shown in millimeters
3.20
3.00
2.80
8
1
5
4
5.15
4.90
4.65
3.20
3.00
2.80
PIN 1
0.65 BSC
0.95
0.85
0.75
1.10 MAX
0.80
0.60
0.40
8°
0°
0.15
0.00
0.38
0.22
0.23
0.08
SEATING
PLANE
COPLANARITY
0.10
COMPLIANT TO JEDEC STANDARDS MO-187-AA
Figure 25. 8-Lead Mini Small Outline Package [MINI_SO]
(RM-8)
Dimensions are shown in millimeters
Rev. PrA | Page 13 of 16
AD5441
NOTES
Preliminary Technical Data
Rev. PrA | Page 14 of 16
Preliminary Technical Data
NOTES
AD5441
Rev. PrA | Page 1± of 16
AD5441
NOTES
Preliminary Technical Data
©2007 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
PR06492-0-3/07(PrA)
Rev. PrA | Page 16 of 16
相关型号：
AD5442ABCPZ-1-RL7
SERIAL INPUT LOADING, 1us SETTLING TIME, 16-BIT DAC, PDSO10, 3 X 3 MM, ROHS COMPLIANT, MO-220WEED, LFCSP-10
ADI
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