MH88634CV-K [ZARLINK]
Central Office Interface Circuit; 中部连接CE接口电路
| 型号： | MH88634CV-K |
| 厂家： | 
ZARLINK SEMICONDUCTOR INC |
| 描述： | Central Office Interface Circuit |
| 文件： | 总13页 (文件大小：439K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MH88634CV-K
Central Office Interface Circuit
Data Sheet
September 2003
Ordering Information
Features
•
•
•
•
Loop Start Trunk Interface
600Ω
2-4 Wire Conversion
Line state Detection Outputs:
MH88634CV-K 21 Pin SIL Package
•
•
•
•
Forward Loop
Reverse Loop
Ringing Voltage
Switch Hook
0°C to 70°C
•
•
Digital Loop Carrier
Optical Multiplexer
•
•
•
•
One Relay Driver
On-Hook Reception
Small footprint area
Description
The Zarlink MH88634CV-K Central Office Interface
Circuit trunk provides a complete analog and signalling
Meets FCC Part 68 Leakage Current
link between audio switching equipment and
telephone line.
a
Requirements
Applications
Interface to Central Office for:
The device is fabricated as a thick film hybrid
incorporating various technologies for optimum circuit
design and very high reliability.
•
•
•
•
•
PABX
The component design has been changed to improve
the general performance of the part. It is also now
capable of operating at a 24V battery and on hook
reception.
Key Telephone Systems
Channel Bank
Voice Mail
Terminal Equipment
The main difference between the MH88634BV-2 and
MH88634CV-K is that SHK is active high on the CV-K.
VCC
VEE
AGND
XLD
RL SHK XLA XLB XLC
RV
FL
Status
Detection
Receive
Gain
RX
TX
TIP
2 - 4 Wire
Hybrid
Line
Dummy
Ringer
Termination
Transmit
Gain
RING
LRC
LRD
Loop Relay
Impedance
Matching
Network
Balance
Driver
VRLY
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2003, 2001 Zarlink Semiconductor Inc. All Rights Reserved.
MH88634CV-K
Data Sheet
1
TIP
RING
XLA
XLD
XLB
XLC
IC
2
3
4
5
6
7
IC
8
9
IC
10
11
12
13
14
15
16
17
18
SHK
RX
VEE
TX
RV
FL
RL
VCC
AGND
LRC
19
20
21
VRLY
LRD
Figure 2 - Pin Connections
Pin Description
Pin # Name
Description
1
2
3
TIP
Tip Lead. Connects to the "Tip" lead of a Telephone Line.
RING Ring Lead. Connects to the "Ring" lead of a Telephone Line.
XLA
XLD
XLB
XLC
Loop Relay Contact A. Connects to XLB through the Loop relay (K1) contacts when the
relay is activated.
4
5
6
Loop Relay Contact D. Connects to XLC through the loop relay (K1) contacts, when the
relay is activated.
Loop Relay Contact B. Connects to XLA through the loop relay (K1) contacts, when the
relay is activated.
Loop Relay Contact C. Connects to XLD through the loop relay (K1) contacts, when the
relay is activated.
7-9
10
IC
Internal Connection. No connection should be made to this pin.
SHK
Switch Hook (Output). A logic 0 indicates the presence of forward or reverse battery voltage
when LRC is logic 0 and the presence of forward or reverse loop current when LRC is logic 1.
11
12
13
14
RX
VEE
TX
Receive (Input). 4-Wire ground (AGND) referenced analog input.
Negative Supply Voltage. -5V DC
Transmit (Output). 4-Wire ground (AGND) referenced analog output.
RV
Ringing Voltage Detect (Output). A logic low indicates that ringing voltage is across the Tip
and Ring leads.
15
FL
Forward Loop Detect (Output). In the on-hook state, a logic 0 output indicates that forward
loop battery is present. In the off-hook state, a logic 0 indicates that forward loop current is
present.
2
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
Pin Description (continued)
Pin # Name
Description
16
RL
Reverse Loop Detect (Output). In the on-hook state, a logic 0 output indicates that reverse
loop battery is present. In the off-hook state, a logic 0 output indicates that reverse loop
current is present.
17
18
19
20
21
VCC
Positive Supply Voltage. +5V DC
AGND Analog Ground. 4-wire ground (AGND). Normally connected to system ground.
LRC Loop Relay Control (Input). A logic 1 activates the Loop Relay Driver output (LRD).
VRLY Relay Positive Supply Voltage. Typically +5V. Connects to the relay supply voltage.
LRD
Loop Relay Drive (Output). Connects to the Loop Relay Coil. When LRC is at a logic 1 an
open collector output at LRD sinks current and energizes the relay.
Functional Description
The MH88634CV-K is a Central Office Interface Circuit (COIC). It is used to correctly terminate a Central Office 2-
wire telephone line. The device provides a signalling link and a 2-4 Wire line interface between the Telephone Line
and subscriber equipment. The subscriber equipment can include Private Branch Exchanges (PBXs), Key
Telephone Systems, Terminal Equipment, Digital Loop Carriers and Wireless Local Loops.
All descriptions assume that the device is connected as in the application circuit shown in Figure 3.
Isolation Barrier
The MH88634CV-K provides an isolation barrier which is designed to meet FCC Part 68 (November 1987) Leakage
Current Requirements.
External Protection Circuit
An external Protection Circuit Device assists in preventing damage to the device and the subscriber’s equipment,
due to over-voltage conditions. The type of protection required is dependant upon the application and regulatory
standards. Further details should be obtained from the specific country’s regulatory body. Typically you will need
TM
lightening protection supplied by resettable fuses or PTC and mains crossover protection via a foldover diode.
Suitable Markets
The MH88634CV-K has fixed 600Ω line and network balance impedance for use in North America and Asia.
Line Termination
When LRC is at a logic 1, LRD will sink current which energizes the Loop Relay (K1), connecting XLA to XLB and
XLC to XLD. This places a line termination across Tip and Ring. The device can be considered to be in an off-hook
state and DC loop current will flow. The line termination consists of a DC resistance and an AC impedance. When
LRC is at a logic 0, the line termination is removed from across Tip and Ring.
An internal Dummy Ringer is permanently connected across Tip and Ring which is a series AC load of
(17kΩ+330nF). This represents a mechanical telephone ringer and allows ringing voltages to be sensed. This load
can be considered negligible when the line has been terminated.
Depending on the Network Protocol being used the Line Termination can terminate an incoming call, seize the line
for an outgoing call, or if applied and disconnected at the correct rate can be used to generate dial pulse signals.
3
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
The DC line termination circuitry provides the line with an active DC load termination which is equivalent to a DC
resistance of 280Ω at 20mA.
Ringing Equivalent Number
The Ringing Equivalent Number (REN) is application specific. See the governing regulatory body specification for
details.
Input Impedance
The input impedance (Zin) is the AC impedance that the MH88634CV-K places across Tip and Ring to terminate
the Telephone line. This is fixed at 600Ω.
Network Balance Impedance
The MH88634CV-K Network Balance Impedance is fixed at 600Ω.
2-4 Wire Conversion
The device converts the balanced 2-Wire input, presented by the line at Tip and Ring, to a ground referenced signal
at TX. This circuit operates with or without loop current; signal reception with no loop current is required for on-hook
reception enabling the detection of Caller Line Identification (CLI) signals.
Conversely, the device converts the ground referenced signal input at RX, to a balanced 2-Wire signal across Tip
and Ring.
The 4-Wire side (TX and RX) can be interfaced to a filter/codec, such as the Zarlink MT896X, for use in digital voice
switched systems.
During full duplex transmission, the signal at Tip and Ring consists of both the signal from the device to the line and
the signal from the line to the device. The signal input at RX, being sent to the line, must not appear at the output
TX. In order to prevent this, the device has an internal cancellation circuit. The measure of attenuation is
Transhybrid Loss (THL).
Transmit and Receive Gain
The Transmit Gain of the device is the gain from the balanced signal across Tip and Ring to the ground referenced
signal at TX. It is set at 0dB.
The Receive Gain of the device is the gain from the ground referenced signal at RX to the balanced signal across
Tip and Ring. It is set at -2dB.
Supervision Features
Line Status Detection Outputs
The MH88634CV-K supervisory circuitry provides the signalling status outputs which are monitored by the system
controller. The supervisory circuitry is capable of detecting: Ringing Voltage; Forward and Reverse loop battery;
Forward and Reverse loop current; and Switch Hook.
Ringing Voltage Detect Output (RV)
The RV output provides a logic 0 when ringing voltage is detected across Tip and Ring. This detector includes a
filter which ensures that the output toggles at the ringing cadence and not at the ringing frequency. Typically this
4
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
output switches to a logic 0 after 50ms of applied ringing voltage and remains at a logic 0 for 50ms after ringing
voltage is removed.
RV shall not toggle during ringing.
Forward Loop and Reverse Loop Detect Outputs (FL & RL)
The FL output provides a logic 0 when either forward loop battery or forward loop current is detected, that is the
Ring pin voltage is more negative than the Tip pin voltage.
The RL output provides a logic 0 when either reverse loop battery or reverse loop current is detected, that is the Tip
pin voltage is more negative than the Ring pin voltage.
Switch Hook (SHK)
The SHK output is active if either forward loop or reverse loop current is detected, or if forward or reverse battery
voltage is detected.
Control Input
The MH88634CV-K accepts a control signal from the system controller at the Loop Relay Control input (LRC). This
energizes the relay drive output Loop Relay Drive (LRD). The output is active low and has an internal clamp diode
to VRLY.
The intended use of this relay driver is to add and remove the Line Termination from across Tip and Ring, as shown
in Figure 3.
If this Control input and the Supervisory Features are used as indicated in Figure 3, Loop-Start Signalling can be
implemented.
Mechanical Data
See Figure 9 for details of the mechanical specification.
5
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
MH88634
+5V
1
2
Tip
C1
TIP
17
VCC
Protection
Circuit
Ring
RING
+5V
13
11
Analog Out
TX
RX
21
K1
LRD
VRLY
LRC
Analog In
20
19
Loop Relay Control
14
15
RV
Ringing Detect
Forward Loop
Reverse Loop
Switch Hook
K1
K1
5
3
XLB
XLA
FL
RL
16
10
6
4
XLC
XLD
SHK
AGND
18
VEE
12
C2
NOTES:
1) K1 Electro Mechanical 2 Form A
2) C1 and C2 are decoupling capacitors
-5V
Figure 3 - Typical LS Application Circuit
Absolute Maximum Ratings*
Parameters
Sym
Min
Max
Units
Comments
1
DC Supply Voltages
VCC
-0.3
7
V
VEE
0.3
-7
V
2
3
4
DC Ring Relay Voltage
Storage Temperature
Ring Trip Current
VRLY
S
ITRIP
-0.3
-55
18
+125
180
V
°C
T
mArms 250ms 10% duty cycle or 500ms single shot
*Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
Recommended Operating Conditions
Parameters
Sym
Min
Typ‡
Max
Units
1
DC Supply Voltages
VCC
4.75
5.0
5.25
V
VEE
-4.75
-5.0
-5.25
V
2
3
DC Ring Relay Voltage
VRLY
TOP
5.0
25
15
70
V
°C
Operating Temperature
0
‡ Typical figures are at 25°C with nominal ±5V supplies and are for design aid only.
6
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
s
DC Electrical Characteristics†
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
Supply Current
ICC
5
13
mA
IEE
2.5
13
mA
2
3
Power Consumption
PC
37.5
137
0.5
mW
VBAT not connected
FL
RL
Low Level Output Voltage
VOL
V
IOL = 4mA
High Level Output Voltage
VOH
2.4
V
IOH = 0.4mA
SHK
RV
4
5
6
LRD
LRC
LRC
Sink Current, Relay to VCC
Clamp Diode Current
IOL
ICD
100
150
mA
mA
VOL = 0.5V not
continuous, LRC=5V
Low Level Input Voltage
VIL
0.8
V
High Level Input Voltage
VIH
3.20
V
High Level Input Current
Low Level Input Current
IIH
IIL
40
40
µA
µA
VIH = 5.0V
† Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C with nominal ±5V supplies and are for design aid only.
Loop Electrical Characteristics†
Characteristics
Sym
Min
Typ‡
Max
Units
Test Conditions
1
2
3
4
5
Ringing Voltage
Operating Loop Current
Off-Hook DC Resistance
Leakage Current (Tip-Ring to AGND)
VR
40
16
90
150
85
280
7
Vrms
mA
Ω
17 to 68Hz
270
@ 20mA
Note 1
mArms @ 1000VAC
SHK & FL Threshold
Tip-Ring (On-hook)
12
21
15
Vdc
mA
LRC = 0V
LRC = 5V
Tip-Ring Current (Off-Hook)
10.5
6
SHK & RL Threshold
Tip-Ring (On-Hook)
12
21
Vdc
mA
LRC = 0V
LRC = 5V
Tip-Ring Current (Off-Hook)
10.5
-15
† Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C with nominal ±5V supplies and are for design aid only.
Note 1: Maximum figure of 282Ω at 0°C
7
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
AC Electrical Characteristics†
Characteristics
Symbol
Min
Typ‡
Max
Units
Test Conditions
1
2
2-wire Input Impedance
Return Loss at 2-wire
Zin
RL
600
Ω
-2 Variant
Test Circuit as Fig 6
20
29
dB
200-3400 Hz
3
Longitudinal to Metallic
Balance
Test Circuit as Fig 7
200Hz
58
55
53
60
60
58
dB
dB
dB
1000Hz
3400Hz
4
5
Transhybrid Loss
Gain, 2 wire to TX
THL
20
27
dB
200-3400Hz
Test Circuit as Fig 4
-0.25
-0.3
0
0
0.25
0.3
dB
dB
1000Hz
Relative Gain
Gain, Rx to 2 wire
200-3400Hz
6
Test Circuit as Fig 5
-2.25
-0.3
-2
0
-1.75
0.3
dB
dB
1000Hz
Relative Gain
200-3400Hz
7
8
9
Input impedance at RX
Output impedance at TX
Signal Overload Level
10
5
kΩ
Ω
% THD < 5% @ 20mA
at 2-wire
at TX
10 Total Harmonic Distortion
at 2-wire
4.0
1.7
dBm
dBm
THD
1.0
1.0
%
%
Input 0.5V, 1kHz @
RX
at TX
Input 0.5V, 1kHz @
Tip-Ring
11 Idle Channel Noise
NC
at 2-Wire
at TX
1 5
15
16.5
16.5
dBrnC
dBrnC
12 Power Supply Rejection Ratio
PSRR
Ripple 0.1V, 1kHz
at 2-wire and TX
VCC
VEE
25
25
48
47
dB
dB
13 On-Hook Gain, 2-Wire to TX
-1
0
1
dB
Input 1000Hz @ 0.5V
Test Circuit as Fig. 8
Relative to Off-Hook Gain
14 Met. to Long. Balance
-2 Variant
60
40
55
40
62
48
62
48
200-1000Hz
1000-3400Hz
200-1000Hz
1000-3400Hz
-4 Variant
15 Common Mode Rejection
Ratio
CMRR
48
55
dB
Test Circuit as Fig. 7
1000Hz, FL = 0V,
ILoop = 25mA
† Electrical Characteristics are over recommended operating conditions unless otherwise stated.
‡ Typical figures are at 25°C with nominal ±5V supplies and are for design aid only.
8
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
-V
+5V
-5V
10H 300Ω
VEE
VCC
XLA
XLB
100uF
+
RING
I = 25mA
XLC
XLD
Vs = 0.5V
600Ω
~
100uF
+
V
TX
RX
tx
TIP
V
AGND
10H 300Ω
Gain = 20 * Log (Vtx/Vs)
Figure 4 - 2-4 Wire Gain Test Circuit
-V
+5V
-5V
10H 300Ω
VEE
VCC
XLA
XLB
100uF
+
RING
I = 25mA
XLC
XLD
VZ
Z = 600Ω
100uF
+
TX
RX
TIP
Vs = 0.5V
AGND
10H 300Ω
~
Gain = 20 * Log (Vz/Vs)
Figure 5 - 4-2 Wire Gain Test Circuit
9
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
-V
+5V
-5V
10H 300Ω
VCC
VEE
XLA
XLB
100uF
+
600Ω
RING
I = 25mA
XLC
XLD
368Ω
368Ω
Vs = 0.5V
V1
~
100uF
+
TX
RX
TIP
AGND
10H 300Ω
Return Loss = 20 * Log (V1\Vs)
Figure 6 - Return Loss Test Circuit
-V
+5V
-5V
10H 300Ω
100uF
VEE
VCC
XLA
XLB
RING
+
I = 25mA
XLC
XLD
368Ω
V1
368Ω
Vs = 0.5V
V
100uF
+
tx
TX
~
VEX
TIP
RX
V
AGND
10H 300Ω
Long to Met Bal. = 20 * Log (V1\Vs)
CMRR = 20 * Log (Vtx\Vs) - ( 2-4W Gain)
Figure 7 - Longitudinal to Metallic Balance and CMRR Test Circuit
10
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
-V
+5V
-5V
10H 300Ω
VEE
VCC
XLA
XLB
100uF
+
RING
I = 25mA
368Ω
XLC
XLD
Vs = 0.5V
~
510Ω
V1
100uF
+
TX
RX
368Ω
TIP
AGND
10H 300Ω
Met to Long Bal. = 20 * Log (V1\Vs)
Figure 8 - Metallic to Longitudinal Balance Test Circuit
0.13 Max
(3.3 Max)
0.14 Max
(3.6 Max)
2.120 Max
(53.85 Max)
0.625 Max
(15.9 Max)
1
0.180 + 0.020
(4.57 + 0.51)
0.020 +0.005
(0.5 +0.13)
*
*
0.010 + 0.002
0.06+0.02
0.100 + 0.010
(0.25 + 0.05)
(1.52+0.05)
(2.54 + 0.25)
Notes:
1) Not to scale
2) Dimensions in inches.(Dimensions in millimetres)
3) Pin tolerances are non-accumulative.
4) Recommended soldering conditions: Wave soldering temperature 260°C for 10 secs.
* Dimensions to centre of pin.
Figure 9 - Mechanical Data
11
Zarlink Semiconductor Inc.
MH88634CV-K
Data Sheet
2.12 Max
(53.85 Max)
0.62 Max
(15.75 Max)
1
0.080 +0.020
(2.03 +0.51)
0.170 Max
(4.32 Max)
0.080 Max
(2.03 Max)
Notes:
1) Not to scale
0.260 +0.015
(6.60 +0.38)
2) Dimensions in inches.
(Dimensions in millimetres)
3) Pin tolerances are non-accumulative.
4) Recommended soldering conditions:
Wave Soldering -
*
0.100 ± 0.010
(2.54 ±0.25)
0.020 +0.005
(0.51 +0.13)
Max temp at pins 260° for 10 secs.
0.250 ± 0.020
(6.35 ± 0.51)
* Dimensions to centre of pin.
Figure 10 - MH88634CV-KT-2 Mechanical Information
12
Zarlink Semiconductor Inc.
For more information about all Zarlink products
visit our Web Site at
www.zarlink.com
Information relating to products and services furnished herein by Zarlink Semiconductor Inc. or its subsidiaries (collectively “Zarlink”) is believed to be reliable.
However, Zarlink assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such
information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or
use. Neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual
property rights owned by Zarlink or licensed from third parties by Zarlink, whatsoever. Purchasers of products are also hereby notified that the use of product in
certain ways or in combination with Zarlink, or non-Zarlink furnished goods or services may infringe patents or other intellectual property rights owned by Zarlink.
This publication is issued to provide information only and (unless agreed by Zarlink in writing) may not be used, applied or reproduced for any purpose nor form part
of any order or contract nor to be regarded as a representation relating to the products or services concerned. The products, their specifications, services and other
information appearing in this publication are subject to change by Zarlink without notice. No warranty or guarantee express or implied is made regarding the
capability, performance or suitability of any product or service. Information concerning possible methods of use is provided as a guide only and does not constitute
any guarantee that such methods of use will be satisfactory in a specific piece of equipment. It is the user’s responsibility to fully determine the performance and
suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. Manufacturing does
not necessarily include testing of all functions or parameters. These products are not suitable for use in any medical products whose failure to perform may result in
significant injury or death to the user. All products and materials are sold and services provided subject to Zarlink’s conditions of sale which are available on request.
Purchase of Zarlink’s I2C components conveys a licence under the Philips I2C Patent rights to use these components in and I2C System, provided that the system
conforms to the I2C Standard Specification as defined by Philips.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright Zarlink Semiconductor Inc. All Rights Reserved.
TECHNICAL DOCUMENTATION - NOT FOR RESALE
相关型号：
©2020 ICPDF网 联系我们和版权申明