MH89625C-6 [MITEL]
OPS/DID PCM SLIC Preliminary Information; OPS / DID PCM SLIC初步信息
| 型号： | MH89625C-6 |
| 厂家： | 
MITEL NETWORKS CORPORATION |
| 描述： | OPS/DID PCM SLIC Preliminary Information |
| 文件： | 总16页 (文件大小：137K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MH89625C
OPS/DID PCM SLIC
Preliminary Information
ISSUE 4
May 1995
Features
Ordering Information
•
Input impedance variants:
- 600Ω
- 200Ω + 680Ω // 0.1µF
- 200Ω + 560Ω // 0.1µF
Operates with a wide range of battery voltages
MH89625C
MH89625C- 5
MH89625C- 6
600Ω
200Ω + 680Ω // 0.1µF
200Ω + 560Ω // 0.1µF
•
•
Constant current battery feed with constant
voltage fallback for long loop drive capabilities
Overvoltage and short circuit protection
Off-hook detection and LED indicator drive
Dial pulse detection
Ring trip filter with auto ring trip
Ring relay driver plus three more uncommitted
relay drivers
40 Pin DIL Package
•
•
•
•
•
Description
The Mitel MH89625C SLIC (Subscriber Line
Interface Circuit) provides a complete interface
between an off-premise telephone line and a digital
switching system. All BORSCHT functions of Battery
Feed, Overvoltage Protection, Ringing Feed, Line
Supervision, Codec, 2-4 Wire Hybrid and Test are
provided requiring only a few external components.
The input impedance conforms with Chinese
standard requirements. The device is fabricated
using thick film hybrid technology which incorporates
various technologies for high voltage capability,
optimum circuit design and very high reliability.
•
•
•
•
•
Transformerless 2W to 4W conversion
A/D and D/A conversion
Conforms to A-Law PCM
Analog and digital loopback
Conforms to CCITT k.20 overvoltage surge
requirements with external primary protection
circuitry
Applications
•
•
•
Off premise digital PBX line cards
DID (Direct Inward Dial) line cards
PABX, Key Systems, Central Office Equipment
VBat
LGND
LCA
GS
VREF
VREF
CA
VX
VR
DSTi
CA
Gain
Adjust
Tip
Drive
DSTo
DSTi
TIP
DSTo
CSTi
CSTi
F1i
CODEC
SD0 SD1 SD2
2w/4w
hybrid
Current
F1i
CS
SD3
Constant
Current &
Voltage
Control
& Voltage
Sensing
C2i
Impedance
Matching
Ring
Drive
RING
Ring
Trip
RF2
RF1
Filter
Relay
Driver 4
Relay
Driver 1
Relay
Driver 2
Relay
Driver 3
Line
Supervision
LED
RD2
RD3
RD4
SHK
RD1
Figure 1 - Functional Block Diagram
2-269
MH89625C
Preliminary Information
TIP
RING
IC
1
2
3
40
39
38
IC
IC
IC
IC
IC
VBAT
LGND
GS
VAC
IC
LCA
VDD
AGND
IC
IC
IC
IC
IC
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
37
36
RF1
RF2
IC
VEE
SHK
LED
CSTi
DSTi
C2i
DSTo
F1i
CA
RGND
RD2
RD1
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
VREF
VRLY
RD4
RD3
Figure 2 - Pin Connections
Pin Description
Pin #
Name
Description
1
2
3
4
5
6
TIP
RING
IC
Tip Lead. Connects to the “Tip” lead of the telephone line.
Ring Lead. Connects to the “Ring” lead of the telephone line.
Internal Connection: This pin is internally connected.
Internal Connection: This pin is internally connected.
Internal Connection: This pin is internally connected.
IC
IC
RF1
Ring Feed 1: For OPS operation, connects to the external battery backed ringing
generator, see Figure 2.
7
RF2
Ring Feed 2: For OPS operation, connects to RING through a normally closed relay
contact (K1), see Figure 2.
8
9
IC
Internal Connection. This pin is internally connected.
Negative Supply Voltage: (-5V)
VEE
SHK
LED
10
11
Switch Hook Detect (Output): A logic low indicates an off-hook condition.
LED Drive (Output): Drives an LED directly through an internal 2.2kΩ resistor. A logic
low indicates an off-hook condition.
12
CSTi
Control ST-BUS in (Input): A TTL compatible digital input used to control the function
of the filter/codec. Three modes of operation may be affected by applying to this input
logic high, logic low or an 8-bit serial word, depending on the logic states of CA and F1i.
Functions controlled are: power down, filter gain adjust, loopback, chip testing, and the
SD outputs which control the relay drivers, ring trip circuitry and impedance selection.
13
DSTi
Data ST-BUS in (Input): A TTL compatible digital input which accepts the 8-bit PCM
word from the incoming PCM bus.
14
15
C2i
Clock Input (Input): A TTL compatible digital input which accepts the 2048 kHz clock.
DSTo
Data ST-BUS Out (Output). A three stage TTL compatible digital output which drives
the 8-bit PCM word to the outgoing PCM bus.
16
F1i
Synchronization Input (Input): A TTL compatible active low digital input enabling (in
conjunction with CA) the PCM input, PCM output and digital control input. It is internally
sampled on every positive edge of the clock, C2i, and provides frame and channel
synchronization.
2-270
Preliminary Information
MH89625C
Pin Description (Continued)
Pin #
Name
Description
17
CA
Control Address (Input): A three-level digital input which enables PCM input and
output, and determines into which control register (A or B) the serial data, presented to
CSTi, is stored.
18
19
RGND
RD2
Relay Ground: Return path for relay supply voltage.
Relay Driver 2: Connects to a user provided external relay coil. A logic high at the SD1
output of the internal MT8967 codec activates this driver. An internal clamp diode from
VRLY to RD2 is provided. This relay is typically used for DID reversals.
20
21
22
23
RD1
RD3
RD4
VRLY
Relay Driver 1. Connects to a user provided external relay coil. A logic high at the SD0
output of the internal MT8967 codec activates this driver. An internal clamp diode from
VRLY to RD1 is provided. This relay is typically used for ringing.
Relay Driver 3. Connects to a user provided external relay coil. A logic high at the SD2
output of the internal MT8967 codec activates this driver. An internal clamp diode from
VRLY to RD3 is provided. This relay is typically used for in-test.
Relay Driver 4: Connects to a user provided external relay coil. A logic high at the SD3
output of the internal MT8967 codec activates this driver. An internal clamp diode from
VRLY to RD4 is provided. This relay is typically used for out-test.
Relay Positive Supply Voltage: Normally +5V. Connects to the relay coil and the relay
supply voltage.
24
25
26
27
28
29
30
31
32
VRef
IC
Voltage Reference (Input): +2.50V for the internal codec.
Internal Connection: This pin is internally connected.
Internal Connection: This pin is internally connected
Internal Connection: This pin is internally connected
Internal Connection: This pin is internally connected
Internal Connection: This pin is internally connected
Analog Ground. Analog and Digital Ground. Connects to System Ground.
Positive Supply Voltage (+5V)
IC
IC
IC
IC
AGND
VDD
LCA
Loop Current Adjust (Input). The maximum constant loop current is a function of the
resistance connected from this pin to VEE. Normally left open
33
34
IC
Internal Connection. This pin is internally connected.
VAC
Battery AC Component (Input). AC noise present in the VBAT supply, isolated from the
DC component, can be applied to this pin to reduce longitudinal noise on TIP and RING.
To implement this feature, connect a 0.1µF 100V capacitor from VBAT to VAC, and a 1kΩ
resistor from VAC to AGND. This pin must be tied to AGND when not used.
35
36
GS
Gain Setting (Input). A logic low at this input adds an additional -0.5dB gain in the
receive direction (DSTi to Tip-Ring). This gain is in addition to the gain set by the Codec.
A logic high adds 0dB gain.
LGND
Loop Ground. Return path for the battery (VBAT) supply voltage. Connects to System
Ground.
37
38
39
40
VBat
IC
Battery Supply Voltage. Normally -48V.
Internal Connection: This pin is internally connected
Internal Connection: This pin is internally connected
Internal Connection: This pin is internally connected
IC
IC
2-271
MH89625C
Preliminary Information
Functional Description
Ringing
The ringing insertion circuit has the capability to
provide ringing voltage to a telephone set by simply
adding an external relay, ring generator and a
transient protector. The internal relay driver switches
ringing voltage onto the line via the external ring
relay. A clamp diode is included which suppresses
voltage transients during relay switching caused by
the relay coil. The serial data input at CSTi controls
the internal Codec’s SDo output which activates the
ring driver. Refer to Table 1 for control of SLIC
functions.
The Mitel MH89625C OPS SLIC (Off-Premise
Subscriber Line Interface Circuit) provides
a
complete interface between an off-premise
telephone line and an digital switching system. All
BORSCHT functions are provided requiring only a
few external components. The input impedance
conforms with Chinese standard requirements.
All functions of the SLIC are controlled by the system
Drive (SD) outputs of the internal Mitel A-Law Codec
MT8967. The SD outputs are controlled by the serial
data input stream at CSTi.
Supervision
The BORSCHT Functions
The loop detection circuit determines whether a low
enough resistance is across Tip and Ring to be
recognized as an off-hook condition. When an
off-hook condition occurs, the SHK and LED (the
LED output can drive an LED directly) outputs toggle
to a low level. These outputs also toggle with
incoming dial pulses.
The MH89625C performs all of the BORSCHT
functions of Battery Feed, Overvoltage Protection,
Ringing, Supervision, Codec, Hybrid and Test.
Battery Feed
During applied ringing (ring relay driver activated),
the loop detection circuit engages a ringing filter.
This filter prevents false off-hook detection due to
the current associated with the AC ringing voltage as
well as current transients that occur when the ringing
voltage is switched in and out. The ring trip detection
circuitry deactivates the ring relay driver after an
off-hook condition is detected.
The MH89625C powers the telephone set with
constant DC loop current for short lines and
automatically reverts to constant voltage for long
lines. The constant loop current is a function of the
resistance connected from the LCA pin to VEE.
147.2 -ILoop
R =
(0.0001176 X ILoop) -0.002586
Codec
Where ILoop is the desired constant loop current in mA,
and R is the resistance from pin LCA to pin VEE in
ohms.
The Codec function of the SLIC is implemented
using the Mitel MT8967 A-Law Codec. This device
provides the conversion interface between the
voiceband analog signals of a telephone subscriber
loop and the digital signals required in a digital PCM
(pulse code modulation) system. Eight-bit PCM
encoded digital data enters and leaves the chip
serially on DSTi and DSTo pins, respectively.
R (kΩ)
open
22.0
348k 200k
25.0 27.1 34.0 40.2 49.7
80k
50k
30k
I
Loop
(mA)
Overvoltage Protection
For detailed information on the CODEC portion of
the MH89625C, refer to the MT8967 integrated PCM
Filer/Codec data sheet (Microelectronics Digital
Communications Handbook, Mitel Semiconductor
Issue 9).
The MH89625C is protected from short term (20ms)
transients (+250V) between TIP and RING, TIP and
ground, and RING and ground. However, additional
protection circuitry may be needed depending on the
requirements which must be met. Normally simple
external shunt protection as shown in Figure 4 is all
that is required.
2-272
Preliminary Information
MH89625C
.
Absolute Maximum Ratings* - All voltages are with respect to AGND unless otherwise specified.
Parameter
Symbol
Min
Max
Units
1
DC Supply Voltage
VDD
VEE
-0.3
0.3
7
-7
V
2
3
4
5
6
DC Battery Voltage ①
VBAT
VRLY
VREF
0.3
-0.3
-0.3
-65
7
V
V
DC Ring Relay Voltage
DC Reference Voltage
AC Ring Generator Voltage
DC Digital Input Voltage
VDD
150
VDD
V
VRMS
V
GS, CSTi
DSTi, C2i
F1i
-0.3
7
8
DC Digital (3-level) Input voltage
Storage Temperature
CA
TS
VEE
-40
VDD
V
+125
°C
* Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied.
① LGND is connected to AGND
Recommended Operating Conditions
‡
Parameters
Sym
Min
Typ
Max
Units
Test Conditions
1
DC Supply Voltages
VDD
VEE
4.75
-4.75
5.0
-5.0
5.25
-5.25
V
V
2
3
DC Battery Voltage ①
VBAT
VRLY
-39.8
-48
5.0
-60
7
V
V
DC Ring Relay Voltage
4
5
DC Reference Voltage ②
VREF
2.488
22
2.500
2.512
V
AC Ringing Generator
Voltage
90
25
130
28
VRMS
Hz
Ringing Generator
Frequency
6
Operating Temperature
TOP
0
25
70
°C
① LGND is connected to AGND.
② Temperature coefficient of V
should be better than 100ppm/C.
REF
‡ Typical figures are at 25°C and are for design aid only: not guaranteed and not subject to production testing.
2-273
MH89625C
Preliminary Information
DC Electrical Characteristics†
‡
Characteristics
Sym
Min
Typ
Max Units
Test Conditions
1
2
Supply and Battery Current ①
LCA = Open
IDD
IEE
IBAT
IBAT
8.7
8.4
23.5
1.5
15
15
28
2
mA
mA
mA
mA
Short Loop
Open Loop
RLoop = 0Ω
RLoop = Open
Power Consumption ①
PC
LCA = Open
RLoop =Open
On-Hook (VBAT
Powerdown (VDD and VEE
Off-Hook (VDD,VEE,VBAT
)
)
)
100
150
1500
mW
mW
mW
RLoop = 0Ω
3
4
5
6
REF DC Reference Voltage
2
µA
Mean Current
SHK Low Level Output Voltage
High level Output Voltage
VOL
VOH
-0.3
3.7
0.5
5.25
V
V
IOL = 2mA
IOH = 2mA
LED Low Level Output Voltage ②
VOL
VOH
3.0
V
V
IOL = 1.1mA
IOH = 0.7mA
High Level Output Voltage
2.0
RD1 Sink Current, Relay to VDD
RD2 Clamp Diode Current
IOL
ICD
65
100
mA
mA
VOL = 1.0V
RD3
RD4
7
8
9
GS
Low Level Input Voltage
High Level Input Voltage
VIL
VIH
0.8
V
V
2.0
Low Level Input Current
High Level Input Current
IIL
IIH
1
1
µΑ
µΑ
VIL = 0V
VIH = 5.0V
Low Level Input Voltage
Intermediate Input Voltage
High Level Input Voltage
VIL
VIM
VIH
-3.5
0.8
V
V
V
0.0
2.4
CA
RD
10
Low Level Input Current
High Level Input Current
High Level Input Current
IIL
IIM
IIH
10
10
10
µA
µA
VIL = 5.0V
VIM = 0.5V
VIH = 5.0V
11 DSTo Low Level Output Voltage
High Level Input Voltage
VOL
VOH
IOZ
0.4
V
V
mA
IOL = 1.6mA
IOH = 0.1mA
4.0
2.4
Tri-State Leakage Current
0.1
12
13
CSTi Low Level Input Voltage
DSTi High Level Input Voltage
VIL
VIH
0.8
V
V
C2i
Low Level Input Current
F1i
IIL
IIH
10
10
µA
µA
VIL = 0V
VIH = 5.0V
High Level Input Current
† DC Electrical Characteristics are over Recommended Operating Conditions with VDD at +5.0V ± 5% and VEE at -5.0V ±5% unless otherwise
stated.
‡ Typical figures are at 25°C with nominal ± 5V supplies and are for design aid only.
① Supply current and power consumption characteristics are over Recommended Operating Conditions with VDD at 5.0V, VEE at -5.0V
and VBAT at -48.0V
② The LED output consists of a 2.2kΩ resistor in series with the SHK HCT output.
NOTE 1: Powerdown mode is activated through the CSTi input data stream. Refer to Table 2.
2-274
Preliminary Information
MH89625C
Loop Electrical Characteristics† -
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
Maximum AC Ringing ①
33
mA
25Hz, VBAT = -48V
Current Rejection
2
3
Ring Trip Detect Time ②
100
ms
Hook Switch Detect Time:
Off-Hook to On-Hook
On-Hook to Off-Hook
20
20
ms
ms
4
5
6
Operating Loop Currents
Maximum Operating Loop Current
IIP
RIP
ISH
18
22
50
26
1850
mA
LCA= Open
LCA= 30k to VEE
Operating Loop Resistance
0
0
Ω
Ω
VBAT= -40V
VBAT=-48V
2300
13
Loop Current at Off-Hook ③
7
10
mA
Detect Threshold
† Loop Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.
‡ Typical figures are at 25°C with nominal ±5V supplies and are for design aid only.
① The SLIC can be loaded with an AC impedance as low as 4000Ω without generating a false SHK output. Since each REN
represents 8kΩ, the SLIC can drive a REN of 2 without generating a false SHK output.
② This parameter is over Recommended Operating Conditions as well as the specified Operating Loop Resistance.
③Off-Hook Detect (SHK) will be detected for loop lengths of 2900Ω or less.
AC Electrical Characteristics†
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1020 Hz
1
2
2-wire Input Impedance ①
Zin
600R
560 Network
680 Network
600
720
813
Ω
Ω
Ω
(Magnitude)
(Magnitude)
Return Loss at 2-Wire ②
14
18
14
23
24
35
dB
dB
dB
300 Hz
500-2000 Hz
3400 Hz
3
4
Longitudinal to Metallic
Balance
40
46
54
51
dB
dB
300-600 Hz
600-3400 Hz
Transhybrid Loss ➁
16
20
16
52
41
52
dB
dB
dB
300 Hz
500-2500 Hz
3400 Hz
5
Power Supply Rejection Ratio
at 2-Wire and DSTo:
PSRR
Ripple 50mV
1020 Hz
VDD
VEE
VBAT
40
30
40
20
20
20
dB
dB
dB
† AC Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.
‡ Typical figures are at 25°C and are for design aid only.
① Three impedance selections of Z = 600Ω, Z =200Ω + 560 // 0.1µF, and Z =200Ω + 680 // 0.1µF are available.
in in in
② Values apply for all three impedances selections; in all three cases Z = Reference Impedance.
in
Note 1: All of the above test conditions use 200Hz to 3400 Hz unless otherwise stated.
Note 2: The transmit codec gain is set to 0dB, the receive codec gain is set to 0dB, and the receive gain adjustment is set to 0dB
(GS=5V), unless otherwise specified.
Note 3: With the transmit and receive gains set to 0dB; 0dBmO at the DSTi input will appear as 0dBm at the Tip-Ring output; 0dBm at
the Tip-Ring input will appear as 0dBmO at the DSTo output.
Note 4 All dBm is referenced to 600Ω.
2-275
MH89625C
Preliminary Information
AC Electrical Characteristics† - Transmit (A/D) Path
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
Input -6dBm
1
Absolute Gain
-0.5
0
0.5
dB
Default (Codec 0dB)
1020 Hz
2
3
Gain Programmable Range ①
0
7
dB
1020 Hz
Loss Distortion with Frequency
(relative to level at 1020Hz
with codec at 0dB)
0.0
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-
-
dB
dB
dB
dB
dB
dB
dB
0-200 Hz
200-300 Hz
300-400 Hz
400-600 Hz
600-2400 Hz
2400-3000 Hz
3000-3400 Hz
1.0
0.75
0.35
0.55
1.5
4
Gain Variation with Input Level
(relative to gain at 1020Hz with
-6dBm input)
Input 1020 Hz
0 to + 3dBm
-40 to 0dBm
-50 to -40dBm
-55 to-50dBm
-0.25
-0.25
-0.5
0.25
0.25
0.5
dB
dB
dB
dB
-1.5
1.5
5%
THD <
Input 1020 Hz
5
6
7
Signal input Overload Level at
2-Wire
3.14
dBm
Signal Output Overload Level at
DSTo
3.14
dBm0
THD < 5%
Input 1020 Hz
Signal to Total Distortion Ratio at
DSTo
Input at 2-Wire
0 to -10dBm
-20dBm
-30dBm
-40dBm
35
dB
dB
dB
dB
dB
33.8
28.8
19.5
14.5
-50dBm
8
9
Out-of-Band Discrimination at
DSTo:
Signals in 4.6 -72 kHz band
Signals in 300 -3400 Hz band
other than 1020Hz
Input at 2-Wire
-50
-40
dBm0
dBm0
-25dBm, 4.6 -72kHz
0dB, 1020 Hz
Signals in 4.6 -72 kHz band
-25
-41
dBm0
dB
0dBm, 300-3400 Hz
Harmonic Distortion
(2nd or 3rd Harmonic) at DSTo
10 Idle Channel Noise at DSTo
-72
-64
dBm0p
† AC Gain Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.
‡ Typical figures are at 25°C with nominal ± 5V supplies and are for design aid only.
① Codec provides adjustment in 1 dB steps.
Note 1: With the transmit gain set to 0dB; 0dBm at the Tip-Ring input will appear as 0dBmO at the DSTo output.
Note 2: The transmit codec gain is set to 0dB unless otherwise specified.
Note 3: All dBm is referenced to 600Ω.
Note 4: Refer to table 2 for control of SLIC gain.
Note 5: Loss Distortion with Frequency is equivalent to the negative of Frequency Response Gain.
2-276
Preliminary Information
MH89625C
AC Electrical Characteristics† - Receive (D/A) Path
‡
Characteristics
Sym
Min
Typ
Max
Units
Test Conditions
1
2
3
Absolute Gain
Default 1 (Codec 0dB, GS = 5V)
Default 2 (Codec 0dB, GS =oV)
Input -10dBm0
1020 Hz
1020 Hz
-0.5
-1.0
0.0
-0.5
0.5
0.0
dB
dB
Gain Programmable Range
GS = 5V ①
GS = 0V ①
Input -10dBm0
1020 Hz
1020 Hz
-7
-7.5
-0
-0.5
dB
dB
Loss Distortion with Frequency
(relative to level at 1020 Hz)
with Codec at 0dB and GS =5V)
Input -10dBm0
0-200 Hz
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-
-
dB
dB
dB
dB
dB
dB
dB
200-300 Hz
300-400 Hz
400-600 Hz
600-2400 Hz
2400-3000 Hz
3000-3400 Hz
1.0
0.75
0.35
0.55
1.5
4
Gain Variation with Input Level
(relative to gain to 1020 Hz with
-10dBm0 input)
Input 1020 Hz
0 to +3dBm
-40 to 0dBm
-50 to -40dBm
-55 to -50dBm
-0.25
-0.25
-0.5
0.25
0.25
0.5
dB
dB
dB
dB
-1.5
1.5
5%
5
6
7
Signal Input Overload Level at DSTi
3.14
dBm
THD <
Input 1020 Hz
Signal Output Overload Level at
2-Wire
3.14
dBm0 THD < 5%
Input 1020 Hz
Signal Output to Total
Distortion Ratio at 2-Wire
Input at 2-Wire
0 to -20dBm
-30dBm
-40dBm
-50dBm
35
dB
dB
dB
dB
32.9
24.9
19.9
8
Out-of-Band Discrimination at
2-wire
Input at DSTi
Signals in 4.6 -72kHz band
-50
-40
dBm
dBm
-25dBm0, 4.6 -72 kHz
0dBm0, 1020 Hz
Signals in 300-3400 Hz band
other than 1020 Hz
Signals in 4.6 -72 kHz band
-25
-41
dBm
dB
0dBm0, 300 -3400 Hz
9
Harmonic Distortion
(2nd or 3rd Harmonic) at 2-Wire
10 Idle Channel Noise at
2-Wire
Gain Setting:
dBmp -3.5dB
dBmp -7dB
-73
-73
-67
-67
† AC Gain Electrical Characteristics are over Recommended Operating Conditions unless otherwise stated.
‡ Typical figures are at 25°C with nominal ± 5V supplies and are for design aid only.
① Codec provides adjustment in 1 dB steps
Note 1: With the transmit gain set it 0dB; 0dBm0 at the DSTi input will appear as 0dBm at the Tip-Ring output.
Note 2: The receive codec gain is set to 0dB; and the receive gain adjustment is set to 0dB (GS =5V), unless otherwise specified.
Note 3: All dBm is referenced to 600Ω
Note 4: Refer to Table 2 for control of SLIC gain.
Note 5: Loss Distortion with Frequency is equivalent to the negative of Frequency Response Gain.
2-277
MH89625C
Preliminary Information
Table 1- Control of SLIC Functions through Codec 8 bit Register B
Codec Name
Bit
Description
(SLIC Name)
7, 6
CODEC
TESTING
CONTROL
Codec Testing Controls. Set bits to 0 for normal operation. For details of testing
functions, see the MT8967 integrated PCM Filter/Codec data sheet.
3
2
1
SD3
(RD4)
When logic ‘0’, SD3 goes to the open state which deactivates the internal relay
driver 4, RD4 output goes to the open state.
SD2
(RD3)
When logic ‘0’ SD2 goes to AGND which deactivates the internal relay driver 3,
RD3 output goes to the open state.
SD1
(RD2)
A logic ‘0’, SD1 goes to AGND which deactivates the internal relay driver 2, RD2
output goes to the open state.
A logic ‘1’, SD1 goes to VDD which activates the internal relay driver 2, RD2 output
goes to RGND.
0
SD0
(RD1)
A logic ‘0’, SD0 goes to AGND which deactivates the internal relay driver 1, RD1
output goes to the open state.
A logic ‘1’, SD0 goes to VDD which activates the internal driver 1, RD1 output goes
to RGND.
Table 2 - Modified Analog Gain* - Which when combined with CODEC gives 0dBm
Transmit (A/D)
Path
Receive (D/A)
Variant
Input Impedance
600R
Units
Path
MH89625C
MH89625C-5
MH89625C-6
4.02
2.72
3.26
-4.02
-2.72
-3.26
dB
dB
dB
200R + 680R // 0.1µF
200R + 560R // 0.1µF
* All with GS = High and A-Law CODEC (Mitel)
2-278
Preliminary Information
MH89625C
Table 3- Control of SLIC Functions through GS and Codec 8 Bit Register A
Bit 7
Bit 6
Special Function Control
0
0
1
1
0
1
0
1
Normal Operation
Digital Loopback
Analog Loopback
Powerdown
Receive (D/A) Gain (dB)
Bit 5
Bit 4
Bit 3
With GS =0
With GA = 1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
-0.5
-1.5
-2.5
-3.5
-4.5
-5.5
-6.5
-7.5
-1
-2
-3
-4
-5
-6
-7
Bit 2
Bit 1
Bit 0
Transmit (A/D) Gain (dB)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
+1
+2
+3
+4
+5
+6
+7
Note: A transmit gain of 0dB indicates that an analog input signal of 0dBm at Tip-Ring will appear as 0dBmO at the DSTo output. A
receive gain of 0dB indicates that an input signal of 0dBmO will appear as 0dBm at the Tip-Ring output.
2-279
MH89625C
Preliminary Information
Hybrid
Transmit Gain
The 2-4 Wire hybrid circuit separate the 2-wire
balanced full duplex signal at Tip and Ring of the
telephone line into 4-wire receive and transmit
ground referenced analog signals internal to the
SLIC. These analog signals are internally connected
to the MT8967 Filter/Codec which translates the
analog signals to digital PCM. The hybrid also
includes cancellation circuitry which prevents the
input PCM signal at DSTi from appearing at DSTo.
The degree to which the Hybrid minimizes the
contribution of the input signal at DSTi from
appearing at the DSTo output is specified as
transhybrid loss. See the Network Balance section
for maximizing transhybrid loss.
Transmit Gain (Tip-Ring to DSTo) and Receive Gain
(DSTi to Tip-Ring) are programmed in 1dB steps by
writing to the Codec’s Control Register A via the
CSTi serial data stream. In addition, a Receive Gain
adjustment is provided which when activated
provides an additional -0.5dB gain. Refer to control
of SLIC gain.
Short Circuit Protection
The MH89625C is protected from long term (infinite)
short circuit conditions occurring between Tip and
Ring, Tip and AGND, and Ring and AGND.
Protection Circuit Design
Return Loss
The high voltage protection circuit is the MH80625C
which can be used in conjunction with the
MH89625C to meet the CCITT K.20 specification.
See Figures 3 and 4. The protection circuit consists
of 1 MOSFET Transistor (BUZ 22) per 16 lines and 4
voltage clamping diodes (IN4004) per line circuit.
This protection circuit will dissipate the lightning and
AC power energy to protect the line circuit. The
Energy Dump Ground (EDG) is tied to the chassis of
the system ground. The PCB E.D.G. track to the
MOSFET must be run separately. The width of the
ground track should be greater than 0.050 thou and
the resistance should be kept as low as possible,
less than 1 ohm. The MOSFET requires a heat sink
of 9°C/W to dissipate the heat generated by the
overvoltages
To maximize return loss, the impedance at Tip-Ring
should match the SLIC’s input impedance (Zin).
Network Balance
Transhybrid loss is maximized when the line
termination impedance and the SLIC’s network
balance are matched. The MH89625C’s network
balance impedance is automatically internally set to
match the SLIC’s input impedance (Zin). Therefore,
the SLIC’s transhybrid loss is maximized when the
line termination impedance and the SLIC’s input
impedance (Zin) are matched.
Tip-Ring Drive Circuit
Mechanical Data
The PCM input ground referenced signal at DSTi is
converted to a balanced output signal at Tip and
Ring. The Tip-Ring Drive Circuit is optimized for
good 2-wire longitudinal balance.
See Figure 6.
Tip-Ring Receive Gain
The differential audio signal at Tip and Ring is
converted to a ground referenced PCM signal at the
DSTo output.
2-280
Preliminary Information
MH89625C
MH89625C
MH80625C
K1A
K2A
D1
D3
17
TOUT
Tip
CA
5
1
Test
In
Test
Out
12
CSTi
16
F1i
8
2
24
Ring
ROUT
VREF
6
D4
D2
Tip
TIN
RIN
K2B
R1
K1B
14
C2i
K4A
K3A
C1
15
Q1
to other
circuit
DSTo
R2
13
9oC/W
-48V
Heat sink
DSTi
3
RF2
RF1
7
35
GS
Ring
K3B
K4B
8
11
LED
10
SHK
22
34
RD4
RD1
VAC
K4 RELAY
K1 RELAY
20
19
36
LGND
-5V
90VRMS25Hz
RD2
K2 RELAY
K3 RELAY
37
32
-48V
V
Bat
21
PTC
-48V
RD3
LCA
23
VRLY
Components
D1,D2,D3,D4 IN4004
VDD VEE
AGND RGND
18
31
30
9
Q1 = FET BUZ 22 or equivalent
R1 = 10k Ω +5% 1/4W
R2 = 1k Ω + 5% 1/4W
C1 = 0.01µF + 10% 100V
PTC = 55Ω, 50mA
290V
TISP
+5V
-5V
Figure 3 - Typical Line Card Application
2-281
MH89625C
Preliminary Information
Energy Dump Ground (E.D.G)
MH80625C
TIP1
MH89625C
IN4004
MH80625C
MH89625C
IN4004
1
TIP 16
5
5
1
8
TOUT
ROUT
8
TIP
TIP
TOUT
6
LINE 1
6
LINE 16
RING
ROUT
3
RING
3
2
2
RING1
RING 16
IN4004
IN4004
10K
S
10nF/100V
G
D
Heat Sink
9oC/w
1K
E.D.G
-48V
Figure 4 - 16 Lines Circuit Configuration
MH80625C
Protection Circuit
F1
R1
Tip
Tip
To Tip and Ring
of
To Tip and Ring
of
Telephone Line
SLIC Circuitry
R2
F2
Ring
Ring
Notes
1) F1, 2 1/ W 250V Slow Blow Fuse (Littlefuse 229.250 or 230.250).
4
2) R1, 2 5ohm 5% 1W Carbon Composition Resistor.
3) This protection circuit is available as a hybrid circuit with Mitel part number MH80625C.
Figure 5 - Solid State External Protection Application Circuit
2-282
Preliminary Information
MH89625C
2.0
(50.8)
0.180 (4.5)
0.08
(2.0)
0.020 + 0.005
(0.51 + 0.13)
0.10 + 0.01
(2.5 + 0.2)
0.20 + 0.01
(5.0 + 0.2)
1.30 +0.03
(33.0+0.8)
MH89625C
Note 1
0.30 +0.02
(7.8 +0.5)
0.020 + 0.002
(0.51 + 0.051)
Notes:
1) Row pitch is to the centre of the pins.
2) All dimensions are typical and in inches (mm).
3) Not to scale.
Figure 6 - Mechanical Data
2-283
MH89625C
Preliminary Information
Notes:
2-284
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