XC17S05XLVO8I [XILINX]
Spartan Family of One-Time Programmable Configuration PROMs; Spartan系列一次性可编程配置PROM
| 型号： | XC17S05XLVO8I |
| 厂家： | 
XILINX, INC |
| 描述： | Spartan Family of One-Time Programmable Configuration PROMs |
| 文件： | 总9页 (文件大小：110K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
Spartan Family of One-Time
Programmable Configuration
PROMs (XC17S00)
R
0
5
DS030 (v1.8) October 10, 2001
Product Specification
Introduction
The Spartan™ family of PROMs provides an easy-to-use,
cost-effective method for storing Spartan device configura-
tion bitstreams.
Spartan PROM Features
•
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan, Spartan-XL, and Spartan-II FPGA devices
•
•
Simple interface to the Spartan device requires only
one user I/O pin
When the Spartan device is in Master Serial mode, it gener-
ates a configuration clock that drives the Spartan PROM. A
short access time after the rising clock edge, data appears
on the PROM DATA output pin that is connected to the Spar-
tan device DIN pin. The Spartan device generates the
appropriate number of clock pulses to complete the config-
uration. Once configured, it disables the PROM. When a
Spartan device is in Slave Serial mode, the PROM and the
Spartan device must both be clocked by an incoming signal.
Programmable reset polarity (active High or active
Low)
•
•
•
Low-power CMOS floating gate process
Available in 5V and 3.3V versions
Available in compact plastic 8-pin DIP, 8-pin VOIC, or
20-pin SOIC packages.
•
•
•
Programming support by leading programmer
manufacturers.
For device programming, either the Xilinx Alliance or the
Foundation series development systems compiles the Spar-
tan device design file into a standard HEX format which is
then transferred to most commercial PROM programmers.
Design support using the Xilinx Alliance and
Foundation series software packages.
Guaranteed 20 year life data retention
Spartan FPGA
XCS05
Configuration Bits
53,984
Compatible Spartan PROM
XC17S05
XCS05XL
XCS10
54,544
XC17S05XL
XC17S10
95,008
XCS10XL
XCS20
95,752
XC17S10XL
XC17S20
178,144
179,160
247,968
249,168
329,312
330,696
559,232
781,248
1,040,128
XCS20XL
XCS30
XC17S20XL
XC17S30
XCS30XL
XCS40
XC17S30XL
XC17S40
XCS40XL
XC2S50
XC2S100
XC2S150
XC17S40XL
XC17S50XL
XC17S100XL
XC17S150XL
© 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS030 (v1.8) October 10, 2001
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1
Product Specification
1-800-255-7778
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
Pin Description
Table 1: Spartan PROM Pinouts
8-pin
20-pin
PDIP and
Pin Name
VOIC
SOIC
Pin Description
DATA
1
1
Data output, High-Z state when either CE or OE are inactive. During programming,
the DATA pin is I/O. Note that OE can be programmed to be either active High or
active Low.
CLK
2
3
3
8
Each rising edge on the CLK input increments the internal address counter, if both
CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and puts the DATA output in
a high-impedance state. The polarity of this input pin is programmable as either
RESET/OE or OE/RESET. To avoid confusion, this document describes the pin as
RESET/OE, although the opposite polarity is possible on all devices. When RESET
is active, the address counter is held at zero, and the DATA output is in a
high-impedance state. The polarity of this input is programmable. The default is
active High RESET, but the preferred option is active Low RESET, because it can
be driven by the FPGAs INIT pin.
(OE/RESET)
The polarity of this pin is controlled in the programmer interface. This input pin is
easily inverted using the Xilinx HW-130 programmer software. Third-party
programmers have different methods to invert this pin.
CE
4
10
11
When High, this pin disables the internal address counter, puts the DATA output in
a high-impedance state, and forces the device into low-ICC standby mode.
GND
VCC
5
GND is the ground connection.
7, 8
18, 20 The VCC pins are to be connected to the positive voltage supply.
Notes:
1. Pins not listed in the table are reserved and must not be externally connected.
High during user operation. CE can also be
permanently tied Low, but this keeps the DATA output
active and causes an unnecessary supply current of
10 mA maximum.
Controlling PROMs
Connecting the Spartan device with the PROM:
•
The DATA output of the PROM drives the DIN input of
the lead Spartan device.
FPGA Master Serial Mode Summary
•
•
The Master Spartan device CCLK output drives the
CLK input of the PROM.
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device MODE pin. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The Spar-
tan PROM has been designed for compatibility with the
Master Serial mode.
The RESET/OE input of the PROM is driven by the
INIT output of the Spartan device. This connection
assures that the PROM address counter is reset before
the start of any (re)configuration, even when a
reconfiguration is initiated by a VCC glitch. Other
methods—such as driving RESET/OE from LDC or
system reset—assume that the PROM internal
power-on-reset is always in step with the FPGAs
internal power-on-reset, which may not be a safe
assumption.
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the MODE pin is Low.
Data is read from the PROM sequentially on a single data
line. Synchronization is provided by the rising edge of the
temporary signal CCLK, which is generated during configu-
ration.
•
The CE input of the PROM is driven by the DONE
output of the Spartan device, provided that DONE is
not permanently grounded. Otherwise, LDC can be
used to drive CE, but must then be unconditionally
2
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DS030 (v1.8) October 10, 2001
Product Specification
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
Master Serial mode provides a simple configuration inter-
face (Figure 1). Only a serial data line and two control lines
are required to configure the Spartan device. Data from the
PROM is read sequentially, accessed via the internal
address and bit counters which are incremented on every
valid rising edge of CCLK.
unchanged after configuration is complete. Therefore, to
reprogram the FPGA with another program, the DONE line
is pulled Low and configuration begins at the last value of
the address counters.
This method fails if a user applies RESET during the Spar-
tan device configuration process. The Spartan device
aborts the configuration and then restarts a new configura-
tion, as intended, but the PROM does not reset its address
counter, since it never saw a High level on its OE input. The
new configuration, therefore, reads the remaining data in
the PROM and interprets it as preamble, length count etc.
Since the Spartan device is the Master, it issues the neces-
sary number of CCLK pulses, up to 16 million (224) and
DONE goes High. However, the Spartan device configura-
tion will be completely wrong, with potential contentions
inside the Spartan device and on its output pins. This
method must, therefore, never be used when there is any
chance of external reset during configuration.
If the user-programmable, dual-function DIN pin on the
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The Spar-
tan family takes care of this automatically with an on-chip
default pull-up resistor.
Programming the FPGA With Counters
Unchanged Upon Completion
When multiple-configurations for a single Spartan device
are stored in a PROM, the OE pin should be tied Low. Upon
power-up, the internal address counters are reset and con-
figuration begins with the first program stored in memory.
Since the OE pin is held Low, the address counters are left
Spartan
Master Serial
3.3V
V
V
CC
MODE
4.7K
V
CC
CC
DATA
CLK
DIN
CCLK
DONE
INIT
Spartan
PROM
CE
OE/RESET
(Low Resets the Address Pointer)
CCLK
(Output)
DIN
DOUT
(Output)
DS030_01_101001
Figure 1: Master Serial Mode. The one-time-programmable Spartan PROM supports automatic loading of configuration programs.
An early DONE inhibits the PROM data output one CCLK cycle before the Spartan FPGA I/Os become active.
DS030 (v1.8) October 10, 2001
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3
Product Specification
1-800-255-7778
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming the Spartan Family
PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
V
CC
GND
RESET/
CE
OE
or
OE/
RESET
Address Counter
CLK
TC
EPROM
Cell
OE
Output
DATA
Matrix
DS030_02_011300
Figure 2: Simplified Block Diagram (does not show programming circuit)
Important: Always tie the two VCC pins together in your application.
Table 2: Truth Table for XC17S00 Control Inputs
Control Inputs
Outputs
RESET(1)
CE
Internal Address(2)
DATA
ICC
Inactive
Low
If address < TC: increment
Active
Active
If address > TC: don’t change
High-Z
Reduced
Active
Inactive
Active
Low
High
High
Held reset
Not changing
Held reset
High-Z
High-Z
High-Z
Active
Standby
Standby
Notes:
1. The XC17S00 RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
4
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DS030 (v1.8) October 10, 2001
Product Specification
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
XC17S05, XC17S10, XC17S20, XC17S30, XC17S40
(1)
Absolute Maximum Ratings
Symbol
VCC
Description
Supply voltage relative to GND
Value
–0.5 to +7.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to +150
+260
Units
V
V
V
C
C
VIN
Input voltage relative to GND
VTS
Voltage applied to High-Z output
Storage temperature (ambient)
TSTG
TSOL
Notes:
Maximum soldering temperature (10s @ 1/16 in.)
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
(1)
Operating Conditions
Symbol
Description
Commercial
Industrial
Conditions
Min
4.75
4.50
Max
5.25
5.50
Units
VCC
Supply voltage relative to GND (TA = 0 C to +70 C)
Supply voltage relative to GND (TA = –40 C to +85 C)
V
V
Notes:
1. During normal read operation both VCC pins must be connected together.
DC Characteristics Over Operating Condition
Symbol
VIH
Description
Min
Max
Units
High-level input voltage
Low-level input voltage
2.0
VCC
0.8
-
V
V
VIL
0
VOH
VOL
High-level output voltage (IOH = –4 mA)
Low-level output voltage (IOL = +4 mA)
High-level output voltage (IOH = –4 mA)
Low-level output voltage (IOL = +4 mA)
Commercial
Industrial
3.86
V
-
0.32
-
V
VOH
VOL
3.76
V
-
-
-
0.37
10
V
ICCA
ICCS
Supply current, active mode (at maximum frequency)
mA
A
Supply current, standby mode
XC17S05, XC17S10,
50
XC17S20, XC17S30
XC17S40
-
100
10
A
A
IL
Input or output leakage current
–10
CIN
Input Capacitance (VIN = GND, f = 1.0 MHz)
Output Capacitance (VIN = GND, f = 1.0 MHz)
-
-
10
pF
pF
COUT
10
DS030 (v1.8) October 10, 2001
Product Specification
www.xilinx.com
1-800-255-7778
5
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
XC17S05XL, XC17S10XL, XC17S20XL, XC17S30XL, XC17S40XL, XC17S50XL,
XC17S100XL, XC17S150XL
(1)
Absolute Maximum Ratings
Symbol
VCC
Description
Supply voltage relative to GND
Value
–0.5 to +4.0
–0.5 to VCC +0.5
–0.5 to VCC +0.5
–65 to +150
+260
Units
V
V
V
C
C
VIN
Input voltage with respect to GND
Voltage applied to High-Z output
VTS
TSTG
TSOL
Notes:
Storage temperature (ambient)
Maximum soldering temperature (10s @ 1/16 in.)
1. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability.
(1)
Operating Conditions
Symbol
Description
Commercial
Industrial
Min
3.0
3.0
Max
3.6
Units
VCC
Supply voltage relative to GND (TA = 0 C to +70 C)
V
V
Supply voltage relative to GND (TA = –40 C to +85 C)
3.6
Notes:
1. During normal read operation both VCC pins must be connected together.
DC Characteristics Over Operating Condition
Symbol
VIH
Description
Min
Max
VCC
0.8
-
Units
V
High-level input voltage
Low-level input voltage
2.0
VIL
0
V
VOH
VOL
ICCA
ICCS
IL
High-level output voltage (IOH = –3 mA)
Low-level output voltage (IOL = +3 mA)
Supply current, active mode (at maximum frequency)
Supply current, standby mode
2.4
V
-
0.4
5
V
-
mA
A
-
50
10
10
10
Input or output leakage current
–10
A
CIN
Input Capacitance (VIN = GND, f = 1.0 MHz)
Output Capacitance (VIN = GND, f = 1.0 MHz)
-
-
pF
pF
COUT
6
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DS030 (v1.8) October 10, 2001
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Product Specification
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
(1)
AC Characteristics Over Operating Condition
CE
T
T
T
HCE
SCE
SCE
RESET/OE
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS0306_03_011300
Symbol
TOE
Description
Min
-
Max
Units
RESET/OE to Data Delay
CE to Data Delay
45
60
80
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCE
TCAC
TOH
-
CLK to Data Delay
-
Data Hold From CE, RESET/OE, or CLK(2)
CE or RESET/OE to Data Float Delay(2,3)
Clock Periods
0
TDF
-
50
-
TCYC
TLC
100
50
50
25
0
CLK Low Time(2)
-
THC
CLK High Time(2)
-
TSCE
THCE
THOE
Notes:
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLK (to guarantee proper counting)
RESET/OE Hold Time (guarantees counters are reset)
-
-
25
-
1. AC test load = 50 pF
2. Guaranteed by design, not tested.
3. Float delays are measured with 5 pF AC loads. Transition is measured at ±200 mV from steady state active levels.
4. All AC parameters are measured with VIL = 0.0V and VIH = 3.0V.
DS030 (v1.8) October 10, 2001
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7
Product Specification
1-800-255-7778
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
Ordering Information
XC17S20XL VO8 C
Operating Range/Processing
C = Commercial (TA = 0 C to +70 C)
= Industrial (TA = –40 C to +85 C)
Device Number
XC17S05
XC17S05XL
XC17S10
I
XC17S10XL
XC17S20
Package Type
PD8
VO8
=
=
8-pin Plastic DIP
8-pin Plastic Small-Outline Thin Package
XC17S20XL
XC17S30
SO20 = 20-pin Plastic Small-Outline Package
XC17S30XL
XC17S40
XC17S40XL
XC17S50XL
XC17S100XL
XC17S150XL
Spartan 5V Valid Ordering Combinations (XC17S00)
XC17S05PD8C
XC17S05VO8C
XC17S05PD8I
XC17S05VO8I
XC17S10PD8C
XC17S10VO8C
XC17S10PD8I
XC17S10VO8I
XC17S20PD8C
XC17S20VO8C
XC17S20PD8I
XC17S20VO8I
XC17S30PD8C
XC17S30VO8C
XC17S30PD8I
XC17S30VO8I
XC17S40PD8C
XC17S40SO20C
XC17S40PD8I
XC17S40SO20I
Spartan 3.3V Valid Ordering Combinations (XC17S00XL)
XC17S05XLPD8C
XC17S05XLVO8C
XC17S05XLPD8I
XC17S05XLVO8I
XC17S10XLPD8C
XC17S10XLVO8C
XC17S10XLPD8I
XC17S10XLVO8I
XC17S100XLPD8C
XC17S20XLPD8C
XC17S40XLPD8C
XC17S100XLSO20C XC17S20XLVO8C
XC17S40XLSO20C
XC17S40XLPD8I
XC17S40XLSO20I
XC17S50XLPD8C
XC17S50XLSO20C
XC17S50XLPD8I
XC17S50XLSO20I
XC17S100XLPD8I
XC17S100XLSO20I
XC17S150XLPD8C
XC17S20XLPD8I
XC17S20XLVO8I
XC17S30XLPD8C
XC17S150XLSO20C XC17S30XLVO8C
XC17S150XLPD8I
XC17S150XLSO20I
XC17S30XLPD8I
XC17S30XLVO8I
Marking Information
Due to the small size of the PROM package, the complete ordering part number cannot be marked on the package. The XC
8
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DS030 (v1.8) October 10, 2001
1-800-255-7778
Product Specification
R
Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)
prefix is deleted and the package code is simplified. Device marking is as follows.
17S20L V C
Operating Range/Processing
Device Number
C = Commercial (TA = 0 C to +70 C)
17S05
I
= Industrial (TA = –40 C to +85 C)
17S05L
17S10
17S10L
17S20
Package Mark
P
V
S
=
=
=
8-pin Plastic DIP
8-pin Plastic Small-Outline Thin Package
20-pin Plastic Small-Outline Package
17S20L
17S30
17S30L
17S40
17S40L
17S50L
17S100L
17S150L
Note: When marking the device number on the XL parts, an L is used in place of an XL.
Revision History
The following table shows the revision history for this document.
Date
Revision
1.1
Revision
07/14/98
09/08/98
Cosmetic edits for pages 1, 2, and 3.
1.2
Clarified the SPARTAN FPGA and PROM interface by removing references to CEO pin. Removed
the ESD notation in Absolute Maximum table since it is now included in Xilinx’s Reliability Monitor
Report.
01/20/00
02/18/00
04/04/00
08/06/00
04/07/01
10/10/01
1.3
1.4
1.5
1.6
1.7
1.8
Added additional Spartan-XL parts, changed SPROM to PROM.
Changed device ordering numbers, added 4.7K resistor to OE/RESET in Figure 1.
Added XC17S200XL PROM for Spartan XC2S200.
Updated format.
Added to features: “Guaranteed 20 year life data retention.”
Added a note to Table 1. Changed VPP to VCC on Figure 1.
DS030 (v1.8) October 10, 2001
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9
Product Specification
1-800-255-7778
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