XC17S100ASO20C [XILINX]
Spartan-II/Spartan-IIE Family OTP Configuration PROMs; 的Spartan- II /的Spartan -IIE系列OTP配置PROM
| 型号： | XC17S100ASO20C |
| 厂家： | 
XILINX, INC |
| 描述： | Spartan-II/Spartan-IIE Family OTP Configuration PROMs |
| 文件： | 总9页 (文件大小：93K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
0
Spartan-II/Spartan-IIE Family
OTP Configuration PROMs
(XC17S00A)
R
0
5
DS078 (v1.8) November 18, 2002
Advance Product Specification
Features
•
Configuration one-time programmable (OTP) read-only
memory designed to store configuration bitstreams for
Spartan-II/Spartan-IIE FPGA devices
•
•
•
•
Available in compact plastic 8-pin DIP, 8-pin VOIC,
20-pin SOIC, or 44-pin VQFP packages.
Programming support by leading programmer
manufacturers.
•
•
Simple interface to the Spartan device
Programmable reset polarity (active High or active
Low)
Design support using the Xilinx Alliance and
Foundation series software packages.
•
•
Low-power CMOS floating gate process
3.3V PROM
Guaranteed 20-year life data retention
Introduction
The XC17S00A family of PROMs provide an easy-to-use,
cost-effective method for storing Spartan-II/Spartan-IIE
device configuration bitstreams.
configuration. Once configured, it disables the PROM.
When a Spartan device is in Slave Serial mode, the PROM
and the Spartan device must both be clocked by an
incoming signal.
When the Spartan device is in Master Serial mode, it
generates a configuration clock that drives the Spartan
PROM. A short access time after the rising clock edge, data
appears on the PROM DATA output pin that is connected to
For device programming, either the Xilinx Alliance or the
Spartan device design file into a standard HEX format
which is then transferred to most commercial PROM
programmers.
the Spartan device D pin. The Spartan device generates
IN
the appropriate number of clock pulses to complete the
Spartan-II/IIE FPGA
Configuration Bits
197,696
Compatible Spartan-II/IIE PROM
XC17S15A
XC2S15
XC2S30
336,768
559,200
XC17S30A
XC2S50
XC17S50A
XC2S100
XC2S150
XC2S200
XC2S50E
XC2S100E
781,216
XC17S100A
1,040,096
1,335,840
630,048
XC17S150A
XC17S200A
XC17S50A
863,840
XC17S100A
(1)
XC2S150E
XC2S200E
XC2S300E
XC2S400E
XC2S600E
1,134,496
1,442,016
1,875,648
2,693,440
3,961,632
XC17S200A
XC17S200A
XC17S300A
(2)
XC17V04
(2)
XC17V04
Notes:
1. Due to the higher configuration bit requirements of the XC2S150E device, an XC17S200A PROM is required to configure this FPGA.
2. See XC17V00 series configuration PROMs data sheet at: http://direct.xilinx.com/bvdocs/publications/ds073.pdf
© 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All other
trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
require for your implementation. Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of the implementation, including but not limited to any warranties
or representations that this implementation is free from claims of infringement and any implied warranties of merchantability or fitness for a particular purpose.
DS078 (v1.8) November 18, 2002
www.xilinx.com
1
Advance Product Specification
1-800-255-7778
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Pin Description
Pins not listed are "no connects."
Table 1: XC17S00A PROM Pinouts
8-pin
PDIP (PD8)
and
VOIC/TSOP
(VO8)
20-pin
SOIC
(SO20)
44-pin
VQFP
(VQ44)
Pin Name
Pin Description
DATA
1
1
40
Data output, High-Z state when either CE or OE are inactive.
During programming, the DATA pin is I/O. Note that OE can be
programmed to be either active High or active Low.
CLK
2
3
3
8
43
13
Each rising edge on the CLK input increments the internal
address counter, if both CE and OE are active.
RESET/OE
When High, this input holds the address counter reset and puts
the DATA output in a high-impedance state. The polarity of this
input pin is programmable as either RESET/OE or OE/RESET. To
avoid confusion, this document describes the pin as RESET/OE,
although the opposite polarity is possible on all devices. When
RESET is active, the address counter is held at zero, and the
DATA output is in a high-impedance state. The polarity of this input
is programmable. The default is active High RESET, but the
preferred option is active Low RESET, because it can be
connected to the FPGAs INIT pin and a pull-up resistor.
(OE/RESET)
The polarity of this pin is controlled in the programmer interface.
This input pin is easily inverted using the Xilinx HW-130
programmer software. Third-party programmers have different
methods to invert this pin.
CE
4
10
15
When High, this pin resets the internal address counter, puts the
DATA output in a high-impedance state, and forces the device into
low-I standby mode.
CC
GND
5
11
18, 41
38, 35
GND is the ground connection.
V
7, 8
18, 20
The V pins are to be connected to the positive voltage supply.
CC
CC
2
www.xilinx.com
DS078 (v1.8) November 18, 2002
1-800-255-7778
Advance Product Specification
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Pinout Diagrams
Controlling PROMs
Connecting the Spartan device with the PROM:
•
The DATA output of the PROM drives the D input of
IN
1
2
3
4
the lead Spartan device.
DATA (D0)
CLK
VCC
VCC
NC
8
7
6
5
•
•
The Master Spartan device CCLK output drives the
CLK input of the PROM.
PD8/
VO8
Top View
The RESET/OE input of the PROM is connected to the
INIT pin of the Spartan device and a pull-up resistor.
This connection assures that the PROM address
counter is reset before the start of any
OE/RESET
CE
GND
(re)configuration, even when a reconfiguration is
DS078_04_111502
initiated by a V glitch.
CC
•
The CE input of the PROM is connected to the DONE
pin of the Spartan device and a pull-up resistor. CE can
also be permanently tied Low, but this keeps the DATA
output active and causes an unnecessary supply
current of 10 mA maximum.
DATA(D0)
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
VCC
NC
VCC
NC
NC
NC
NC
NC
NC
GND
NC
CLK
NC
NC
NC
FPGA Master Serial Mode Summary
The I/O and logic functions of the Configurable Logic Block
(CLB) and their associated interconnections are established
by a configuration program. The program is loaded either
automatically upon power up, or on command, depending
on the state of the Spartan device mode pins. In Master
Serial mode, the Spartan device automatically loads the
configuration program from an external memory. The
XC17S00A PROM has been designed for compatibility with
the Master Serial mode.
SO20
Top View
NC
OE/RESET
NC
CE
10
DS078_05_111502
Upon power-up or reconfiguration, the Spartan device
enters the Master Serial mode when the mode pins are set
to Master Serial mode. Data is read from the PROM
sequentially on a single data line. Synchronization is pro-
vided by the rising edge of the temporary signal CCLK,
which is generated during configuration.
Master Serial mode provides a simple configuration inter-
face (Figure 1). Only a serial data line, two control lines, and
a clock line are required to configure the Spartan device.
Data from the PROM is read sequentially, accessed via the
internal address and bit counters which are incremented on
every valid rising edge of CCLK.
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
2
3
4
5
6
7
8
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
33
32
31
30
29
28
27
26
25
24
23
If the user-programmable, dual-function D pin on the
VQ44
Top View
IN
Spartan device is used only for configuration, it must still be
held at a defined level during normal operation. The
Spartan-II/Spartan-IIE family takes care of this
automatically with an on-chip pull-up/down resistor or
keeper circuit.
9
10
11
DS073_06_101002
DS078 (v1.8) November 18, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
3
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Spartan-II/
Spartan-IIE
Master Serial
3.3V
V
V
CC
3.3V
M0
M1
M2
3.3K
3.3K
CC
DATA
CLK
DIN
CCLK
DONE
INIT
XC17S00A
PROM
CE
OE/RESET
Notes:
1. If the DriveDone configuration option is not active, pull up DONE with a 3.3kΩ resistor.
(Low Resets the Address Pointer)
CCLK
(Output)
DIN
DOUT
(Output)
DS078_01_110601
Figure 1: Master Serial Mode
The one-time-programmable XC17S00A PROM in Figure 1
supports automatic loading of configuration programs. An
early DONE inhibits the PROM data output one CCLK cycle
before the Spartan FPGA I/Os become active.
4
www.xilinx.com
1-800-255-7778
DS078 (v1.8) November 18, 2002
Advance Product Specification
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Standby Mode
The PROM enters a low-power standby mode whenever CE
is asserted High. The output remains in a high-impedance
state regardless of the state of the OE input.
Programming Spartan-II/Spartan-IIE
Family PROMs
The devices can be programmed on programmers supplied
by Xilinx or qualified third-party vendors. The user must
ensure that the appropriate programming algorithm and the
latest version of the programmer software are used. The
wrong choice can permanently damage the device.
V
CC
GND
RESET/
CE
OE
or
OE/
RESET
Address Counter
CLK
TC
EPROM
Cell
OE
Output
DATA
Matrix
DS030_02_011300
Figure 2: Simplified Block Diagram (does not show programming circuit)
Important: Always tie the two V pins together in your application.
CC
Table 2: Truth Table for XC17S00A Control Inputs
Control Inputs
Outputs
(1)
(2)
RESET
CE
Internal Address
DATA
I
CC
Inactive
Low
If address < TC: increment
Active
Active
If address > TC: don’t change
High-Z
Reduced
Active
Inactive
Active
Low
High
High
Held reset
Not changing
Held reset
High-Z
High-Z
High-Z
Active
Standby
Standby
Notes:
1. The XC17S00A RESET input has programmable polarity
2. TC = Terminal Count = highest address value. TC + 1 = address 0.
DS078 (v1.8) November 18, 2002
Advance Product Specification
www.xilinx.com
1-800-255-7778
5
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
XC17S15A, XC17S30A, XC17S50A, XC17S100A, XC17S150A, XC17S200A, and
XC17S300A
Absolute Maximum Ratings(1)
Symbol
Description
Supply voltage relative to GND
Value
Units
V
V
–0.5 to +4.0
CC
V
Input voltage with respect to GND
Voltage applied to High-Z output
–0.5 to V +0.5
V
IN
CC
V
–0.5 to V +0.5
V
TS
CC
T
T
Storage temperature (ambient)
–65 to +150
°C
°C
STG
Maximum soldering temperature (10s @ 1/16 in.)
+260
SOL
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress
ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions
is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
Operating Conditions(1)
Symbol
Description
Commercial
Industrial
Min
3.0
3.0
1.0
Max
3.6
3.6
50
Units
V
V
Supply voltage relative to GND (T = 0°C to +70°C)
CC
A
Supply voltage relative to GND (T = –40°C to +85°C)
V
A
T
V
rise time from 0V to nominal voltage
CC
ms
VCC
Notes:
1. During normal read operation, both V pins must be connected together.
CC
2. At power-up, the device requires the V power supply to monotonically rise from 0V to nominal voltage within the specified V rise
CC
CC
time. If the power supply cannot meet this requirement, then the device may not perform a power-on-reset properly.
DC Characteristics Over Operating Condition
Symbol
Description
Min
Max
Units
V
V
High-level input voltage
Low-level input voltage
2.0
V
CC
IH
V
0
0.8
-
V
IL
V
High-level output voltage (I = –3 mA)
2.4
V
OH
OH
V
Low-level output voltage (I = +3 mA)
-
0.4
15
1
V
OL
OL
I
Supply current, active mode (at maximum frequency)
Supply current, standby mode
-
mA
mΑ
µA
pF
pF
CCA
CCS
I
-
I
Input or output leakage current
–10
10
10
10
L
C
Input Capacitance (V = GND, f = 1.0 MHz)
-
-
IN
IN
C
Output Capacitance (V = GND, f = 1.0 MHz)
IN
OUT
6
www.xilinx.com
1-800-255-7778
DS078 (v1.8) November 18, 2002
Advance Product Specification
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
AC Characteristics Over Operating Condition(1)
T
CEH
CE
T
T
T
HCE
SCE
SCE
ESET/OE
CLK
T
HOE
T
T
HC
LC
T
CYC
T
T
DF
OE
T
T
CAC
OH
T
CE
DATA
T
OH
DS030_03_111502
Symbol
Description
Min
-
Max
Units
ns
T
T
T
T
T
T
T
T
T
T
T
T
RESET/OE to Data Delay
CE to Data Delay
45
60
80
-
OE
-
ns
CE
CLK to Data Delay
-
ns
CAC
OH
(2)
Data Hold From CE, RESET/OE, or CLK
0
ns
(2,3)
CE or RESET/OE to Data Float Delay
Clock Periods
-
50
-
ns
DF
100
50
50
25
0
ns
CYC
LC
(2)
CLK Low Time
-
ns
(2)
CLK High Time
-
ns
HC
CE Setup Time to CLK (to guarantee proper counting)
CE Hold Time to CLK (to guarantee proper counting)
RESET/OE Hold Time (guarantees counters are reset)
CE High time (guarantees counters are reset)
-
ns
SCE
HCE
HOE
CEH
-
ns
25
20
-
ns
-
ns
Notes:
1. AC test load = 50 pF
2. Guaranteed by design, not tested.
3. Float delays are measured with 5 pF AC loads. Transition is measured at 200 mV from steady state active levels.
4. All AC parameters are measured with V = 0.0V and V = 3.0V.
IL
IH
5. If T
6. If T
High < 2µs, T = 2 µs.
CEH
HOE
CE
High < 2µs, T = 2 µs.
CE
DS078 (v1.8) November 18, 2002
www.xilinx.com
7
Advance Product Specification
1-800-255-7778
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Ordering Information
XC17S15A VO8 C
Device Number
Operating Range/Processing
C = Commercial (TA = 0°C to +70°C)
XC17S15A
XC17S30A
XC17S50A
XC17S100A
I
= Industrial (TA = –40°C to +85°C)
Package Type
XC17S150A
PD8
VO8
=
=
8-pin Plastic DIP
8-pin Plastic Small-Outline Thin Package
XC17S200A
XC17S300A
SO20 = 20-pin Plastic Small-Outline Package
VQ44 = 44-pin Plastic Quad Flat Package
Spartan-II 3.3V Valid Ordering Combinations
XC17S15APD8C
XC17S15AVO8C
XC17S15ASO20C
XC17S15APD8I
XC17S15AVO8I
XC17S15ASO20I
XC17S30APD8C
XC17S30AVO8C
XC17S30ASO20C
XC17S30APD8I
XC17S30AVO8I
XC17S30ASO20I
XC17S50APD8C
XC17S50AVO8C
XC17S50ASO20C
XC17S50APD8I
XC17S50AVO8I
XC17S150APD8C
XC17S150AVO8C
XC17S150ASO20C
XC17S150APD8I
XC17S150AVO8I
XC17S150ASO20I
XC17S200APD8C
XC17S200AVO8C
XC17S200AVQ44C
XC17S200APD8I
XC17S200AVO8I
XC17S200AVQ44I
XC17S300AVQ44C
XC17S300AVQ44I
XC17S50ASO20I
XC17S100APD8C
XC17S100AVO8C
XC17S100ASO20C
XC17S100APD8I
XC17S100AVO8I
XC17S100ASO20I
8
www.xilinx.com
1-800-255-7778
DS078 (v1.8) November 18, 2002
Advance Product Specification
R
Spartan-II/Spartan-IIE Family OTP Configuration PROMs (XC17S00A)
Marking Information
Due to the small size of the PROM package, the complete
ordering part number cannot be marked on the package.
The XC prefix is deleted and the package code is simplified.
Device marking is as follows.
17S15A V C
Operating Range/Processing
Device Marking
C = Commercial (TA = 0°C to +70°C)
17S15A
17S30A
17S50A
17S100A
I
= Industrial (TA = –40°C to +85°C)
Package Mark
17S150A
P
V
S
VQ
=
=
=
=
8-pin Plastic DIP
17S200A
17S300A
8-pin Plastic Small-Outline Thin Package
20-pin Plastic Small-Outline Package
44-pin Plastic Quad Flat Package
Revision History
The following table shows the revision history for this document.
Date
Revision
1.0
Revision
09/14/00
11/13/00
04/07/01
Initial Xilinx release.
1.1
Updated configuration bits.
1.2
Added to features: “Guaranteed 20 year life data retention”, removed “Programming the FPGA
with counters” and related text.
06/20/01
10/09/01
1.3
1.4
Revised Figure 1 resistor values to match Spartan-II data sheet.
Added note for unlisted pins, changed I
and note regarding power-on reset.
and I
, and added power-on supply requirements
CCA
CCS
11/15/01
06/25/02
10/15/02
11/18/02
1.5
1.6
1.7
1.8
Updated for Spartan-IIE FPGA family.
Changed Table 1.
Changed Table 1. Added Pinout Diagrams, page 3.
Added XC2S400E and XC2S600E to Compatible FPGAS table. Modified document title.
DS078 (v1.8) November 18, 2002
www.xilinx.com
9
Advance Product Specification
1-800-255-7778
相关型号：
©2020 ICPDF网 联系我们和版权申明